Semiconductor fuse resistor, method of manufacture and circuit protection device

Abstract

The application discloses a semiconductor fuse resistor, a preparation method and a circuit protection device. The resistor comprises a substrate, a doped semiconductor layer arranged on the surface of the substrate, a first electrode and a second electrode arranged on the doped semiconductor layer, and the first electrode and the second electrode form ohmic contact with the doped semiconductor layer. The region of the doped semiconductor layer between the first electrode and the second electrode forms a resistor body for current conduction. When the current flowing through the resistor body is higher than a set protection current, the Joule heat generated by the resistor body can form a high resistance region in the local region where the resistor body is located, so as to disconnect the electrical connection between the first electrode and the second electrode. The semiconductor fuse resistor can form a high resistance region in a microsecond order without a complex detection and control circuit, completely cut off the circuit, greatly improve the response speed and system safety under an extreme overcurrent condition, and reduce the complexity and occupied area of the system protection circuit.

Description

Technical Field

[0001] This invention relates to the field of fuse technology, and in particular to a semiconductor fusible resistor, its preparation method, and a circuit protection device. Background Technology

[0002] With the rapid development of power electronics technology, communication equipment, and consumer electronics towards higher frequencies, smaller sizes, and higher integration, the performance requirements for circuit protection components are constantly increasing. As one of the most critical overcurrent protection components in a circuit, the response speed, size, and threshold accuracy of fuses (or fusible resistors) directly affect the reliability and safety of the entire electronic system.

[0003] Currently, the commonly used overcurrent protection components in the industry mainly include the following types: First, there are traditional metal fuses and ceramic / glass tube fuses. These devices use the thermal effect of current to melt the internal metal conductor (fuse) and thus break the circuit. However, these traditional fuses are generally large and cannot meet the miniaturization requirements of modern electronic devices, especially semiconductor chips, let alone achieve monolithic integration with semiconductor power devices. In addition, their fusing current is determined by the inherent melting point and cross-sectional area of ​​the metal material, with a fixed threshold that cannot be flexibly and precisely adjusted according to specific application requirements. Furthermore, their fusing response speed is slow (usually in the millisecond to second range), and they are prone to arcing under high current surges, posing a physical safety hazard.

[0004] Secondly, there are polymer positive temperature coefficient (PPTC) devices. These devices utilize the thermal expansion effect of conductive particles in the polymer matrix, causing a sharp increase in resistance during overcurrent to achieve protection. However, PPTC devices have a slower response time (typically on the order of seconds) and exhibit significant resistance drift after recovery, which can easily affect the long-term stability of the circuit. Furthermore, their voltage withstand capability is limited, making them unsuitable for high-voltage power electronics applications.

[0005] Secondly, there are active overcurrent protection circuits using semiconductors. With the development of semiconductor technology, active protection circuits are now commonly constructed using current sensing chips in conjunction with power switching transistors. While this approach offers relatively precise protection, it requires the design of complex logic control circuits. This not only significantly increases the system's manufacturing cost and chip footprint but also necessitates an additional drive power supply. More importantly, active detection and control inherently involve signal processing delays (microseconds to milliseconds), which may lead to protection failure under extreme sudden overcurrent conditions due to insufficient system response.

[0006] In conclusion, a new type of purely passive fusible resistor is needed. Summary of the Invention

[0007] The purpose of this invention is to provide a compact semiconductor fusible resistor, a method for its fabrication, and a circuit protection device that allows for precise configuration of the overcurrent protection current and a fast response speed.

[0008] To achieve the above objectives, the present invention provides a semiconductor fusible resistor, comprising: Substrate; A doped semiconductor layer is disposed on the surface of the substrate; The first electrode and the second electrode are disposed at a distance on the doped semiconductor layer, and both the first electrode and the second electrode form an ohmic contact with the doped semiconductor layer. The doped semiconductor layer region located between the first electrode and the second electrode forms a resistive body for current conduction; When the current flowing through the resistor is higher than the set protection current, the Joule heat generated by the resistor can form a high-resistance region in its local area, thereby disconnecting the electrical connection between the first electrode and the second electrode.

[0009] Preferably, the planar geometry of the resistor, the thickness of the doped semiconductor layer, and the doping concentration are configured according to the protection current.

[0010] Preferably, the substrate is any one of sapphire, silicon, or silicon carbide; the material of the doped semiconductor layer is any one of N-type doped gallium nitride, polycrystalline silicon, tantan nitride, amorphous silicon, or silicon-chromium.

[0011] Preferably, when the material of the doped semiconductor layer is N-type doped gallium nitride, the thickness of the doped semiconductor layer is 0.5 to 5 μm, and the doping concentration is 1×10^16 to 1×10^19 cm^-3; The planar geometry of the resistive element includes a width and a length, wherein the width is 5–100 μm and the length is 50–500 μm.

[0012] Preferably, the resistor comprises a plurality of spaced and insulated resistor cells, the two ends of which are electrically connected to a common first electrode and a second electrode, respectively, to form a parallel-connected resistor array.

[0013] Preferably, the spacing between two adjacent resistor cells is 10 to 100 μm; The relationship between the resistive element and the protective current satisfies the following equation: Ifuse = N×Isingle×K; Wherein, Ifuse is the protection current, N is the number of resistors connected in parallel, Isingle is the fusing current of the resistor in a local high-resistance region, and K is the mutual thermal coupling coefficient determined based on the spacing between two adjacent resistors.

[0014] Preferably, the materials of the first electrode and the second electrode are composed of a metal stack, wherein the metal stack is selected from any one of Ti / Al / Ni / Au stack, Ti / Al / Ti / TiN stack or Cr / Al / Ti / Pt / Ti / Pt / Ti / Pt / Au stack, and the total thickness of the first electrode and the second electrode is 0.5 to 1.5 μm.

[0015] Preferably, it further includes a passivation layer covering the exposed surface of the doped semiconductor layer and covering a portion of the first electrode and the second electrode.

[0016] Preferably, the high-resistivity region is a physical breakpoint that blocks current transmission when the temperature of the local area where the doped semiconductor layer is located reaches a critical value due to the Joule heat accumulation, resulting in thermal decomposition or thermal oxidation.

[0017] The present invention also provides a method for fabricating a semiconductor fusible resistor, comprising: A substrate is provided, and a doped semiconductor layer is epitaxially grown on the surface of the substrate; A metal layer is deposited on the doped semiconductor layer to form a first electrode and a second electrode at intervals, and the first electrode and the second electrode form an ohmic contact with the doped semiconductor layer, and a resistive body is formed in the region of the doped semiconductor layer between the first electrode and the second electrode as a current conduction element. The performance parameters of the resistor are configured according to a preset protection current so that when the current flowing through the resistor is higher than the protection current, the Joule heat generated by the resistor can form a high-resistance region in its local area, thereby disconnecting the electrical connection between the first electrode and the second electrode.

[0018] Preferably, the performance parameters include the planar geometry of the resistor, the thickness of the doped semiconductor layer, and the doping concentration.

[0019] Preferably, multiple segmentation regions are etched in parallel in the doped semiconductor layer region located between the first electrode and the second electrode by patterned etching to form multiple spaced resistor units; The number of resistors connected in parallel and the spacing between two adjacent resistors are configured according to the protection current.

[0020] Preferably, after forming the first electrode and the second electrode, a passivation layer is also deposited on the exposed surface of the doped semiconductor layer and on a portion of the first electrode and the second electrode. The passivation layer is etched to create openings, exposing the contact areas of the first and second electrodes used as external connections.

[0021] The present invention also provides a circuit protection device, which includes a power supply circuit and a semiconductor fusible resistor as described above disposed on the power supply circuit.

[0022] Compared to existing technologies, the semiconductor fusible resistor provided by the above-mentioned technical solution breaks away from the conventional mindset of avoiding thermal runaway in current semiconductor design, transforming the Joule thermal destruction effect of the doped semiconductor bulk material into a usable and precise protection mechanism. Compared to traditional bulky metal fuses or active protection circuits requiring complex control logic, this solution uses a purely passive bulk material structure, which not only eliminates the need for complex barrier layer processes, significantly reducing manufacturing costs, but also perfectly supports standard semiconductor manufacturing processes, making it extremely easy to achieve high-density monolithic integration at the chip level. Furthermore, by utilizing a purely physical thermal accumulation mechanism, it eliminates the signal detection feedback delay of traditional active circuits, enabling the rapid formation of a high-resistance region within microseconds, completely cutting off the circuit and greatly improving response speed and system safety under extreme overcurrent conditions. Attached Figure Description

[0023] Figure 1 This is a planar structural diagram of a semiconductor fusible resistor in one embodiment of the present invention.

[0024] Figure 2 For along Figure 1 Longitudinal section view along the AA direction.

[0025] Figure 3 This is a planar structural diagram of a semiconductor fusible resistor in another embodiment of the present invention.

[0026] Figure 4 This is an IR curve diagram of the resistive blue film test in an embodiment of the present invention.

[0027] Figure 5 This is a flowchart illustrating the fabrication process of the resistor in an embodiment of the present invention. Detailed Implementation

[0028] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0029] This embodiment discloses a semiconductor fusible resistor, which is mainly used in overcurrent protection scenarios in power electronic systems such as power adapters, fast chargers, and motor drivers.

[0030] First, it should be noted that third-generation semiconductor materials (such as gallium nitride GaN, silicon carbide SiC, etc.) or semiconductor materials with specific doping concentrations have been widely used in power electronics due to their excellent characteristics such as wide bandgap and high breakdown field strength. However, in existing semiconductor device design concepts, the thermal runaway or thermal decomposition of semiconductor materials caused by Joule heating generated by high current is generally regarded by the industry as a device failure mechanism or reliability problem that must be avoided at all costs. The semiconductor fusible resistor of this invention takes the opposite approach, transforming the Joule thermal destruction effect of semiconductor bulk materials into an usable and precise circuit protection mechanism.

[0031] like Figure 1 and Figure 2 The basic architecture of the semiconductor fusible resistor includes: a substrate 10, a doped semiconductor layer 13 disposed on the surface of the substrate 10, and a first electrode 11 and a second electrode 12 disposed at intervals on the doped semiconductor layer 13.

[0032] In this configuration, both the first electrode 11 and the second electrode 12 form ohmic contacts with the doped semiconductor layer 13. The region of the doped semiconductor layer 13 located between the first electrode 11 and the second electrode 12 constitutes a resistive element R for current conduction.

[0033] This semiconductor fusible resistor utilizes the Joule thermal melting mechanism of semiconductor materials under overcurrent conditions, as detailed below: Under normal operating conditions, current flows stably through the doped semiconductor layer 13 between the first electrode 11 and the second electrode 12, and the device (semiconductor fusible resistor) exhibits a fixed resistance value. When the current flowing through the resistive element R exceeds the set protection current, the Joule heating effect causes the temperature of the resistive element R to rise rapidly, and the generated heat power is proportional to the square of the current and the resistance value.

[0034] Due to the physical limits of thermal conductivity of the semiconductor material and the bottom substrate 10, heat cannot be completely dissipated instantly, resulting in severe heat accumulation in the resistive body R region. As the temperature continues to rise and exceeds the material's tolerance limit, structural damage or phase transition will occur in the local area where the resistive body R is located, forming a high-resistivity region. Ultimately, the electrical connection between the first electrode 11 and the second electrode 12 is completely severed within microseconds to milliseconds, achieving rapid and irreversible overcurrent cut-off protection.

[0035] This embodiment combines the current-conducting resistive element R with the Joule thermally induced high-resistivity region mechanism of the material body, enabling the device to rapidly form a high-resistivity region within microseconds without the need for complex detection and control circuits. This allows for a one-time complete circuit cutoff, greatly improving the response speed and system safety under extreme overcurrent conditions, while also reducing the complexity and footprint of the system protection circuit.

[0036] In another embodiment, to meet the differentiated requirements for the fusing threshold in different application scenarios, during the device design phase, the planar geometry of the resistive element R (including its length along the current flow direction and its width perpendicular to the current flow direction), the thickness of the doped semiconductor layer 13, and the internal doping concentration can be precisely configured according to the target protection current. This allows for a wide range of precise programmable fusing currents. For example, with the same geometry, reducing the doping concentration will increase the material resistivity, thereby generating sufficient Joule heating to trigger the formation of a high-resistivity region at a lower current. Conversely, by increasing the thickness or width of the doped semiconductor layer 13, the current conduction cross-section can be expanded, enabling the device to carry a larger steady-state current.

[0037] In addition, the substrate 10 can be selected from sapphire, silicon, or silicon carbide, depending on the heat dissipation requirements and epitaxial lattice matching. For example, the sapphire substrate 10 has a relatively low thermal conductivity (about 35 W / m·K). This low thermal conductivity helps to concentrate heat in the resistive body R region during overcurrent, accelerating heat accumulation and the formation of a high-resistivity region.

[0038] The doped semiconductor layer 13, which serves as a conductive channel, can be made of any one of N-type doped gallium nitride (N-GaN), polycrystalline silicon, tantalum nitride, amorphous silicon, or silicon-chromium.

[0039] Those skilled in the art should understand that different materials will result in different physical boundary conditions. Taking N-type doped gallium nitride as an example, as a wide bandgap semiconductor material, it not only has a high breakdown field strength, but also, compared with the traditional AlGaN / GaN heterojunction structure, the N-GaN material structure does not require the growth of a complex barrier layer. This not only makes the epitaxial structure simpler and significantly reduces the fabrication cost, but also allows it to maintain more stable physical properties at high temperatures until a specific thermal decomposition critical point is reached before melting is triggered.

[0040] To achieve highly consistent microsecond to millisecond-level fuse response, when the material of the doped semiconductor layer 13 is N-type doped gallium nitride, the thickness of the N-GaN layer is preferably 0.5 to 5 μm, and the doping concentration is controlled between 1×10^16 and 1×10^19 cm^-3; at the same time, in the planar geometry of the resistor R, the width is set to 5 to 100 μm and the length is set to 50 to 500 μm.

[0041] In a specific application scenario, the N-GaN layer is 1.5 μm thick, and silicon doping is used to achieve a concentration of 2 × 10^17 cm^-3. At this thickness, the resistivity of the N-GaN is approximately 0.055 Ω·cm. Combined with a geometry of 20 μm width and 218 μm length, the resistance R of this resistor under normal conditions is approximately 400 Ω. Under isolated testing conditions (such as when attached to a blue film with limited heat dissipation), such as... Figure 4 The measured fusing current can be accurately stabilized at about 70 mA, which proves the effectiveness of the above parameter range in controlling the thermal runaway boundary.

[0042] In another embodiment, to address high-power, high-current overcurrent protection scenarios, simply scaling up the size of a single resistor R proportionally can easily lead to uneven heat distribution within the semiconductor layer due to microscopic defects, thereby affecting the accuracy of the fusing threshold. Therefore, this embodiment modifies the topology of the resistor R, designing it to include multiple spaced, insulated resistor units R', such as... Figure 3 .

[0043] Multiple resistor cells R' are arranged in an array in physical space, and their two ends are electrically connected to a common first electrode 11 and a second electrode 12, respectively. Through this structure, a large current is divided into zero and distributed to each resistor cell R', forming a parallel resistor array, which not only greatly improves the overall current carrying capacity, but also ensures a high degree of consistency in local thermal triggering characteristics.

[0044] Furthermore, when using a parallel array of multiple resistor cells R', the thermal coupling effect between adjacent resistor cells R' has a decisive influence on the overall fusing characteristics. Therefore, in this embodiment, the spacing between two adjacent resistor cells R' is 10–100 μm.

[0045] Based on the above structure, the overall protection current (Ifuse) and the individual unit characteristics follow the following quantitative relationship: Ifuse = N×Isingle×K; Where N is the number of resistor cells R' connected in parallel, Isingle is the fusing current of a single resistor cell R' forming a high-resistance region under isolated reference conditions, and K is the mutual thermal coupling coefficient determined based on the spacing between two adjacent resistor cells R' (usually between 0.7 and 1.0).

[0046] Taking a scenario with a target protection current of 1.5A as an example: under the conditions that the single-unit fusing current is 70mA and the unit spacing is set to 10μm (corresponding to a calculated K value of 0.85), the required number of parallel connections N, derived from the above formula, is approximately 25.2. In actual design, N=24 is used. At this time, the overall device size is only 762μm×400μm.

[0047] The fusible resistors with the above structure were batch-produced and tested, and the test data is shown in Table 1 below: Table 1

[0048] Therefore, the average fusing current of this array structure is 1510mA, with a deviation from the design target of only +0.7%, and a very small standard deviation. By adjusting the value of N, this design system can strictly control the design error of the actual fusing current within ±5% over a very wide range of 0.5A to 5.0A (e.g., N can be 8 to 84).

[0049] In addition, taking a resistor R' with a width of 20μm, a length of 218μm, and an N-GaN layer thickness of 1.5μm as an example, the protection current corresponding to different numbers (N) of parallel resistor R's was actually tested, and the test data is shown in Table 2 below: Table 2

[0050] The test results show that by precisely designing the number of parallel resistors R', the protection current can be accurately programmed within the range of 0.5 A to 5 A, with the design error controlled within ±5%.

[0051] Furthermore, the contact quality of the electrodes directly affects the insertion loss during normal device operation. Therefore, in this embodiment, the first electrode 11 and the second electrode 12 are composed of multiple metal stacks, selected from any one of Ti / Al / Ni / Au stacks, Ti / Al / Ti / TiN stacks, or Cr / Al / Ti / Pt / Ti / Pt / Ti / Pt / Au stacks, and the total metal thickness is controlled between 0.5 and 1.5 μm.

[0052] In specific process execution, for example, a composite stacked structure of Cr / Al / Ti / Pt with a total thickness of approximately 4000 nm is used. After deposition using electron beam evaporation technology, it is rapidly thermally annealed at a specific temperature (such as 200°C in a nitrogen atmosphere) for about 10 minutes. This annealing process promotes an alloying reaction at the metal-semiconductor interface, forming an ohmic contact with extremely low contact resistance. This ensures that before the protection action occurs, most of the device heat is concentrated on the resistive element R rather than the electrode contact surface, preventing premature electrode burn-out.

[0053] In another embodiment, to improve the long-term reliability of the device under complex electrical and environmental conditions, the semiconductor fusible resistor further includes a passivation layer 14. The passivation layer 14 covers the exposed surface of the doped semiconductor layer 13 and extends to cover a portion of the edge of the first electrode 11 and the second electrode 12.

[0054] The passivation layer 14 can be made of SiN or SiO2 grown by plasma-enhanced chemical vapor deposition (PECVD), with a thickness of, for example, 100 nm. This passivation layer 14 not only isolates the semiconductor surface from external moisture and impurities, but also provides a stable thermal boundary condition above the resistor R, preventing uneven heat dissipation caused by local airflow disturbances, and further improving the accuracy of the melting threshold.

[0055] Furthermore, the microscopic formation mechanism of the high-resistivity region is as follows: During the thermal accumulation stage under overcurrent conditions, when the local temperature of the doped semiconductor layer 13 rises and reaches a specific critical value (e.g., 600–800°C for GaN materials), the semiconductor lattice cannot maintain stability and spontaneously undergoes a violent thermal decomposition reaction, or a thermal oxidation reaction occurs at the passivation layer 14 / interface.

[0056] This material-level phase transition and disintegration directly creates a physical breakpoint that blocks carrier transport. Macroscopically, this manifests as follows: before melting, the device maintains a low impedance of several hundred ohms, but after a high-resistance region at the microsecond level is formed, the resistance between the first electrode 11 and the second electrode 12 abruptly jumps to a maximum value, completely and physically cutting off the circuit.

[0057] In another preferred embodiment of the present invention, a method for fabricating a semiconductor fusible resistor is also disclosed, such as... Figures 1 to 3 and Figure 5 It includes the following steps: S1. Provide a substrate 10 and form a doped semiconductor layer 13 on the surface of the substrate 10. When GaN material is used, an N-type doped gallium nitride layer is epitaxially grown on its surface by MOCVD. For non-GaN material systems, sputtering, chemical vapor deposition, low-pressure chemical vapor deposition, evaporation deposition, or other processes suitable for forming the desired thin film resistive layer can also be used.

[0058] S2. Perform patterned isolation to define the chip boundary and the resistor R region. The active region of the device and the chip boundary can be defined first using photolithography, and then an etching process can be used to form mesa isolation or partitioned regions. For a single resistor R structure, a continuous conductive region of a doped semiconductor layer 13 is retained between the two electrodes; for a parallel array structure, multiple partitioned regions are etched in parallel between the two electrodes, so that the remaining conductive strips form multiple resistor units.

[0059] S3. Form a first electrode 11 and a second electrode 12 on the doped semiconductor layer 13. A metal layer can be deposited first, and then the first electrode 11 and the second electrode 12, which are spaced apart from each other, can be formed by photolithography and lift-off or etching processes. After this step, the region of the doped semiconductor layer 13 located between the two electrodes constitutes a resistive body R as a current conduction path.

[0060] S4. Configure the performance parameters of resistor R according to the target current. During the layout design phase, the width, length, thickness, material resistivity, and number of parallel resistors R can be selected based on the target fusing current.

[0061] S5. Forming the passivation layer 14 and creating openings. After the first electrode 11 and the second electrode 12 are formed, a passivation layer 14 can be deposited on the exposed surface of the doped semiconductor layer 13 and on the electrode portion. The passivation layer 14 can be made of SiN or SiO2, and its thickness can be selected according to insulation requirements and stress levels. Then, openings are formed on the passivation layer 14 using photolithography and etching to expose the electrode contact areas required for external connections. For applications requiring improved environmental reliability, the passivation coverage can be appropriately expanded; for pad areas requiring high-current soldering or bonding, the opening size must meet the packaging process requirements.

[0062] When fabricated using the above method, the structural, material, and thermal parameters of the resistor R can all be predefined through the front-end process, thus the device's fusing threshold has good designability. Furthermore, this method does not rely on complex current detection and active shutdown circuits, has a short process path, and is suitable for on-chip integration and mass production.

[0063] In summary, the semiconductor fusible resistor and its fabrication method provided by this invention overcome the bottlenecks in size, response speed, and integration density of traditional metal fuses, ceramic tubes, or PPTC devices. Especially in wide-bandgap semiconductor systems represented by N-GaN, it cleverly transforms thermal runaway, typically considered a device failure mode, into a controlled and precisely programmable overcurrent protection mechanism. The solution of this invention features extremely small footprint and ultra-fast response time. Furthermore, the deposition, photolithography, and annealing steps involved in this invention have high compatibility with standard transistor (such as GaN HEMT) process platforms, demonstrating significant commercial value and technological superiority.

[0064] The present invention discloses a circuit protection device, which includes a power supply circuit and a semiconductor fusible resistor as described in the above embodiment disposed on the power supply circuit (such as a power bus), so that the circuit protection device automatically disconnects in the event of overcurrent to prevent other important components from burning out.

[0065] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A semiconductor fusible resistor, characterized in that, include: Substrate; A doped semiconductor layer is disposed on the surface of the substrate; The first electrode and the second electrode are disposed at a distance on the doped semiconductor layer, and both the first electrode and the second electrode form an ohmic contact with the doped semiconductor layer. The doped semiconductor layer region located between the first electrode and the second electrode forms a resistive body for current conduction; When the current flowing through the resistor is higher than the set protection current, the Joule heat generated by the resistor can form a high-resistance region in its local area, thereby disconnecting the electrical connection between the first electrode and the second electrode.

2. The semiconductor fusible resistor according to claim 1, characterized in that, The planar geometry of the resistor, the thickness of the doped semiconductor layer, and the doping concentration are configured according to the protection current.

3. The semiconductor fusible resistor according to claim 1, characterized in that, The substrate is any one of sapphire, silicon, or silicon carbide; the material of the doped semiconductor layer is any one of N-type doped gallium nitride, polycrystalline silicon, tantan nitride, amorphous silicon, or silicon-chromium.

4. The semiconductor fusible resistor according to claim 3, characterized in that, When the material of the doped semiconductor layer is N-type doped gallium nitride, the thickness of the doped semiconductor layer is 0.5 to 5 μm, and the doping concentration is 1×10^16 to 1×10^19 cm^-3; The planar geometry of the resistive element includes a width and a length, wherein the width is 5–100 μm and the length is 50–500 μm.

5. The semiconductor fusible resistor according to claim 1, characterized in that, The resistor comprises a plurality of spaced and insulated resistor cells, the two ends of which are electrically connected to a common first electrode and a second electrode, respectively, to form a parallel-connected resistor array.

6. The semiconductor fusible resistor according to claim 5, characterized in that, The spacing between two adjacent resistor cells is 10–100 μm; The relationship between the resistive element and the protective current satisfies the following equation: Ifuse = N×Isingle×K; Wherein, Ifuse is the protection current, N is the number of resistors connected in parallel, Isingle is the fusing current of the resistor in a local high-resistance region, and K is the mutual thermal coupling coefficient determined based on the spacing between two adjacent resistors.

7. The semiconductor fusible resistor according to claim 1, characterized in that, The first electrode and the second electrode are made of a metal stack, which is selected from any one of Ti / Al / Ni / Au stack, Ti / Al / Ti / TiN stack or Cr / Al / Ti / Pt / Ti / Pt / Ti / Pt / Au stack, and the total thickness of the first electrode and the second electrode is 0.5 to 1.5 μm.

8. The semiconductor fusible resistor according to claim 1, characterized in that, It also includes a passivation layer covering the exposed surface of the doped semiconductor layer and covering a portion of the first electrode and the second electrode.

9. The semiconductor fusible resistor according to claim 1, characterized in that, The high-resistivity region is a physical break in the current transmission caused by thermal decomposition or thermal oxidation when the temperature of the local area where the doped semiconductor layer is located reaches a critical value due to the Joule heat accumulation.

10. A method for fabricating a semiconductor fusible resistor, characterized in that, include: A substrate is provided, and a doped semiconductor layer is epitaxially grown on the surface of the substrate; A metal layer is deposited on the doped semiconductor layer to form a first electrode and a second electrode at intervals, and the first electrode and the second electrode form an ohmic contact with the doped semiconductor layer, and a resistive body is formed in the region of the doped semiconductor layer between the first electrode and the second electrode as a current conduction element. The performance parameters of the resistor are configured according to a preset protection current so that when the current flowing through the resistor is higher than the protection current, the Joule heat generated by the resistor can form a high-resistance region in its local area, thereby disconnecting the electrical connection between the first electrode and the second electrode.

11. The preparation method according to claim 10, characterized in that, The performance parameters include the planar geometry of the resistor, the thickness of the doped semiconductor layer, and the doping concentration.

12. The preparation method according to claim 10, characterized in that, By patterning etching, multiple segmentation regions are etched in parallel in the doped semiconductor layer region located between the first electrode and the second electrode to form multiple spaced resistor units. The number of resistors connected in parallel and the spacing between two adjacent resistors are configured according to the protection current.

13. The preparation method according to claim 10, characterized in that, After the first electrode and the second electrode are formed, a passivation layer is also deposited on the exposed surface of the doped semiconductor layer and on a portion of the first electrode and the second electrode. The passivation layer is etched to create openings, exposing the contact areas of the first and second electrodes used as external connections.

14. A circuit protection device, characterized in that, It includes a power supply circuit and a semiconductor fusible resistor as described in any one of claims 1 to 9 disposed on the power supply circuit.

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