A bonded silicon bridge, package structure and method of fabrication thereof

Abstract

The application provides a bonded silicon bridge, a packaging structure and a preparation method thereof, and belongs to the field of advanced packaging technology. The bonded silicon bridge comprises a first silicon bridge and a second silicon bridge which are connected by face-to-face bonding. Stress adjustment through silicon vias are arranged in the first silicon bridge and / or the second silicon bridge. Meanwhile, the preparation method of the bonded silicon bridge, the packaging structure comprising the bonded silicon bridge and the preparation method of the packaging structure are disclosed. According to the warping trend of the bonded silicon bridge and the packaging structure, the stress adjustment through silicon vias are arranged in the first silicon bridge or the second silicon bridge. The bonded silicon bridge and the packaging structure can respectively adjust the stress distribution in the overall bonded silicon bridge and the overall packaging structure by arranging the bonded silicon bridge with the stress adjustment through silicon vias, so as to relieve the warping of the bonded silicon bridge and the packaging structure.

Description

Technical Field

[0001] This application relates to the field of advanced semiconductor packaging technology, and in particular to a bonding silicon bridge, a packaging structure and a method for fabricating the same. Background Technology

[0002] As Moore's Law approaches its physical limits, advanced packaging technology has become a key path for continuing to improve semiconductor performance. 2.5D packaging integrates multiple functional chips into a single package with high density through silicon interposers or embedded silicon bridges, achieving heterogeneous interconnection of logic, memory, and switching chips within a limited space, thereby building complete system-level functionality. Compared to traditional 2.5D solutions that use a monolithic silicon interposer, embedded silicon bridge technology only embeds silicon bridge dies in the chip interconnect area, while retaining the organic packaging substrate structure in the remaining areas. This architecture significantly reduces silicon material usage and overall manufacturing costs while effectively increasing package size and wiring flexibility, making large-scale multi-chip integration possible. Currently, embedded silicon bridge solutions have been widely used in high-performance computing, artificial intelligence accelerators, and network switching, achieving high-bandwidth, low-latency communication between chips through fine silicon bridge traces, driving the continuous evolution of packaging technology towards higher integration and larger sizes.

[0003] However, with the continuous increase in package size and the growing number of embedded functional modules, stress management within the package structure has become a core challenge restricting manufacturing yield and long-term reliability. How to balance stress and suppress warpage within the package structure has become a critical technical bottleneck that urgently needs to be addressed in advanced packaging processes. Summary of the Invention

[0004] The problem to be solved by this application is to provide a bonded silicon bridge, a packaging structure and a method for fabricating the same, so as to solve the problem of internal stress imbalance or warping of existing packaging structures.

[0005] To address the aforementioned problems, this application provides a bonding silicon bridge, comprising a first silicon bridge and a second silicon bridge. At least one through-silicon via (TSV) is provided in each of the first and second silicon bridges. The TSVs of the first and second silicon bridges are connected to each other. Stress-adjusting TSVs are provided in the first and / or second silicon bridges. When stress-adjusting TSVs are provided in both the first and second silicon bridges, the number of stress-adjusting TSVs in the first and second silicon bridges is not equal to the number of stress-adjusting TSVs in the second silicon bridge, resulting in either a greater tensile stress in the first silicon bridge or a greater tensile stress in the second silicon bridge than in the first silicon bridge.

[0006] In an optional embodiment, both the first silicon bridge and the second silicon bridge include a first surface and a second surface disposed opposite to each other. The first surface of the first silicon bridge and the second silicon bridge are respectively provided with a passivation layer. Each passivation layer has at least one hybrid bonding pad corresponding to and connected to the through silicon via. The hybrid bonding pad of the first silicon bridge is bonded to the hybrid bonding pad of the second silicon bridge. The passivation layer of the first surface of the first silicon bridge is bonded to the passivation layer of the first surface of the second silicon bridge, so that the first silicon bridge and the second silicon bridge are bonded face to face.

[0007] The stress-adjustable silicon via is in contact with the passivation layer.

[0008] In an optional embodiment, the stress-adjustable silicon via is a blind via structure or a through-hole structure.

[0009] In an optional embodiment, the stress-adjustable silicon vias within the first silicon bridge or the second silicon bridge include a plurality of vias, and the spacing between adjacent stress-adjustable silicon vias is 25 micrometers to 75 micrometers.

[0010] In an optional embodiment, the stress-adjustable silicon vias within the first silicon bridge or the second silicon bridge include a plurality of vias, and the plurality of stress-adjustable silicon vias are arranged in a rectangular array, a circular array, or a ring array.

[0011] In an optional embodiment, an active trace is provided within the first silicon bridge, and the active trace is located on the side of the first silicon bridge away from the second silicon bridge.

[0012] This application also provides a method for preparing a bonded silicon bridge, comprising the following steps: A first silicon bridge and a second silicon bridge are provided. At least one through-silicon via is provided in the first silicon bridge and the second silicon bridge respectively. Stress-adjustable through-silicon vias are provided in the first silicon bridge and / or the second silicon bridge. When stress-adjustable through-silicon vias are provided in the first silicon bridge and the second silicon bridge respectively, the number of stress-adjustable through-silicon vias in the first silicon bridge is not equal to the number of stress-adjustable through-silicon vias in the second silicon bridge, so that the tensile stress of the first silicon bridge is greater than that of the second silicon bridge, or the tensile stress of the second silicon bridge is greater than that of the first silicon bridge. The first silicon bridge and the second silicon bridge are bonded together, and the through silicon vias of the first silicon bridge are connected to the through silicon vias of the second silicon bridge.

[0013] In an optional embodiment, the first silicon bridge and the second silicon bridge respectively have a first surface and a second surface disposed opposite to each other. The first surface of the first silicon bridge and the first surface of the second silicon bridge are respectively provided with a passivation layer. Each passivation layer has a hybrid bonding pad that is connected to each of the through silicon vias. The stress-adjusting through silicon vias in the first silicon bridge are in contact with the passivation layer of the first surface of the first silicon bridge, and the stress-adjusting through silicon vias in the second silicon bridge are in contact with the passivation layer of the first surface of the second silicon bridge. The steps of bonding the first silicon bridge to the second silicon bridge include: The passivation layer on the first surface of the first silicon bridge is bonded to the passivation layer on the first surface of the second silicon bridge, so that the hybrid bonding pad of the first silicon bridge is bonded to the hybrid bonding pad of the second silicon bridge. The contact surface of the two passivation layers is the bonding surface. When stress-adjustable silicon vias are provided in both the first silicon bridge and the second silicon bridge, the stress-adjustable silicon vias in the first silicon bridge and the stress-adjustable silicon vias in the second silicon bridge are asymmetrically arranged with respect to the bonding surface.

[0014] In an optional embodiment, the stress-adjustable silicon via is not provided within the first silicon bridge, and the steps for forming the first silicon bridge include: A first bonding substrate and a first silicon bridge initial wafer are provided. The first silicon bridge initial wafer is disposed on the surface of the first bonding substrate. The first silicon bridge initial wafer includes at least one through-silicon via (TSV). One end of the TSV is exposed on the surface of the first silicon bridge initial wafer that contacts the first bonding substrate. The first silicon bridge initial wafer is thinned so that the other end of the through silicon via is exposed on the side of the first silicon bridge initial wafer away from the first bonding substrate. A passivation layer is formed on the surface of the first silicon bridge initial wafer on the side away from the first bonding substrate, the passivation layer including hybrid bonding pads disposed corresponding to the through silicon vias.

[0015] In an optional embodiment, after the first silicon bridge and the second silicon bridge are bonded, the first bonding carrier is removed, and a silicon bridge connecting post is formed on the surface of the through silicon via on the side of the initial wafer of the first silicon bridge away from the passivation layer.

[0016] In an optional embodiment, the stress-adjustable silicon via is disposed within the second silicon bridge, and the formation step of the second silicon bridge includes: A second bonding substrate and a second silicon bridge initial wafer are provided. The second silicon bridge initial wafer is disposed on the surface of the second bonding substrate. The second silicon bridge initial wafer includes at least one through-silicon via and at least one stress-adjustable through-silicon via. The surface of the second silicon bridge initial wafer that contacts the second bonding substrate exposes one end of the through-silicon via and one end of the stress-adjustable through-silicon via. The second silicon bridge initial wafer is thinned so that the other end of the through silicon via and the other end of the stress-adjusting through silicon via are exposed on the side of the second silicon bridge initial wafer away from the second bonding substrate. A passivation layer is formed on the surface of the second silicon bridge initial wafer on the side away from the second bonding substrate, the passivation layer including hybrid bonding pads disposed corresponding to the through silicon vias.

[0017] In an optional embodiment, the stress-adjustable silicon via is disposed within the second silicon bridge, and the formation step of the second silicon bridge includes: A second bonding substrate and a second silicon bridge initial wafer are provided. The second silicon bridge initial wafer is disposed on the surface of the second bonding substrate. The second silicon bridge initial wafer includes at least one through-silicon via (TSV) and at least one stress-adjustable TSV. The surface of the second silicon bridge initial wafer that contacts the second bonding substrate exposes one end of the TSV and one end of the stress-adjustable TSV. The height of the stress-adjustable TSV is lower than the height of the TSV. The second silicon bridge initial wafer is thinned so that the other end of the through silicon via is exposed on the side of the second silicon bridge initial wafer away from the second bonding substrate, but the other end of the stress-adjusting through silicon via is not exposed. A third bonding substrate is provided, and the second silicon bridge initial wafer is transferred to the surface of the third bonding substrate, wherein the side surface of the second silicon bridge initial wafer away from the second bonding substrate is in contact with the surface of the third bonding substrate; The second bonding substrate is removed, and a passivation layer is formed on one side surface of the second silicon bridge initial wafer that exposes the other end of the through-silicon via and the other end of the stress-adjustable through-silicon via. The passivation layer includes a hybrid bonding pad disposed corresponding to the through-silicon via.

[0018] This application also provides a packaging structure, including a packaging substrate and a bonding silicon bridge; The bonding silicon bridge is embedded in the packaging substrate. The bonding silicon bridge includes the bonding silicon bridge described above, or a bonding silicon bridge prepared by the method described above.

[0019] In an optional embodiment, the stress-adjustable through-silicon via is located within the first silicon bridge to suppress warping of the package structure downward in the middle and upward at the edges; Alternatively, stress-adjustable through-silicon vias are provided in the first silicon bridge and the second silicon bridge, respectively, and the number of stress-adjustable through-silicon vias in the first silicon bridge is greater than the number of stress-adjustable through-silicon vias in the second silicon bridge, so as to suppress the downward warping of the middle and upward warping of the packaging structure.

[0020] In an optional embodiment, the stress-adjustable through-silicon via (TSV) is located within the first silicon bridge, and there are multiple stress-adjustable TSVs. The first silicon bridge is provided with multiple through-silicon vias, and the multiple stress-adjustable TSVs and the multiple through-silicon vias are distributed alternately at intervals.

[0021] In an optional embodiment, the stress-adjustable silicon via is located within the second silicon bridge to suppress warping of the package structure upward in the middle and downward at the edges; Alternatively, stress-adjustable through-silicon vias are provided in the first silicon bridge and the second silicon bridge, respectively, and the number of stress-adjustable through-silicon vias in the first silicon bridge is less than the number of stress-adjustable through-silicon vias in the second silicon bridge, so as to suppress the warping of the package structure upward in the middle and downward at the edges.

[0022] In an optional embodiment, the stress-adjustable through-silicon via (TSV) is located within the second silicon bridge, and there are multiple stress-adjustable TSVs. The second silicon bridge has multiple through-silicon vias, and the multiple stress-adjustable TSVs and the multiple through-silicon vias are distributed alternately at intervals.

[0023] In an optional embodiment, it further includes a chip interconnect layer and a substrate interconnect layer; The packaging substrate has a third surface and a fourth surface disposed opposite to each other. The first silicon bridge of the bonding silicon bridge is disposed close to the third surface and away from the fourth surface. The chip interconnect layer is located on the third surface of the packaging substrate and connected to the first silicon bridge. The substrate interconnect layer is located on the fourth surface of the packaging substrate and connected to the second silicon bridge.

[0024] In an optional embodiment, a chip structure is further included, which is disposed on the side surface of the chip interconnect layer away from the packaging substrate and connected to the chip interconnect layer via chip interconnect bumps.

[0025] In an optional embodiment, the chip structure includes at least two, and the at least two chip structures are connected by the bonding silicon bridge.

[0026] In an optional embodiment, the packaging substrate further includes an embedded chip located within the packaging substrate, and the upper and lower surfaces of the embedded chip, which are disposed opposite to each other, are connected to the chip interconnect layer and the substrate interconnect layer, respectively.

[0027] In an optional embodiment, the packaging structure further includes conductive connection pillars disposed within the packaging substrate, with both ends of the conductive connection pillars connected to the chip connection layer and the substrate connection layer, respectively.

[0028] In an optional embodiment, a silicon bridge connection post is further included. The silicon bridge connection post is disposed on the surface of the first silicon bridge away from the second silicon bridge and is connected to a through-silicon via in the first silicon bridge. The first silicon bridge is connected to the chip interconnection layer through the silicon bridge connection post.

[0029] In an optional embodiment, the chip interconnect layer includes a chip redistribution layer, which is electrically connected to a through-silicon via within the first silicon bridge.

[0030] In an optional embodiment, a chip connection bump is further included, the chip connection bump being disposed on the side surface of the chip redistribution layer away from the package substrate.

[0031] In an optional embodiment, the substrate interconnect layer includes a substrate redistribution layer, which is electrically connected to a through-silicon via within the second silicon bridge.

[0032] In an optional embodiment, the substrate connection layer further includes substrate connection bumps disposed on the side surface of the substrate redistribution layer away from the package substrate.

[0033] This application also provides a method for preparing a packaging structure, including the following steps: Provide a bonded silicon bridge, the bonded silicon bridge including the bonded silicon bridge described above, or a bonded silicon bridge prepared by the method described above; A molding compound is filled around the bonded silicon bridge to form a packaging substrate.

[0034] In an optional embodiment, the packaging substrate has a third surface and a fourth surface disposed opposite to each other, and further includes: A chip interconnect layer is formed on the third surface of the packaging substrate, and the chip interconnect layer is connected to the first silicon bridge; A substrate connection layer is formed on the fourth surface of the packaging substrate, and the substrate connection layer is connected to the second silicon bridge.

[0035] In an optional embodiment, the chip interconnect layer includes a chip redistribution layer, and the substrate interconnect layer includes a substrate redistribution layer; It also includes the steps of forming chip connection bumps on the side surface of the chip redistribution layer away from the packaging substrate, and forming substrate connection bumps on the side surface of the substrate redistribution layer away from the packaging substrate.

[0036] In an optional embodiment, a chip structure is further mounted on the surface of the chip interconnect layer away from the packaging substrate.

[0037] In an optional embodiment, the formation of the packaging substrate includes the following steps: Provide carrier board; The bonding silicon bridge is provided, the bonding silicon bridge is mounted on the surface of the carrier plate, the second silicon bridge of the bonding silicon bridge is located on the side close to the carrier plate, and the outer peripheral side of the bonding silicon bridge is filled with molding compound to form a packaging substrate. The through silicon via of the bonding silicon bridge is exposed on the side of the packaging substrate away from the carrier plate. Remove the carrier plate.

[0038] In an optional embodiment, an embedded chip is disposed on the surface of the carrier board, the embedded chip being spaced apart from the bonding silicon bridge.

[0039] In an optional embodiment, a chip interconnect layer is formed on the surface of the packaging substrate away from the carrier before the carrier is removed; After removing the carrier board, a substrate connection layer is formed on the surface of the packaging substrate away from the chip connection layer.

[0040] In an optional embodiment, before forming the chip interconnect layer, a conductive interconnect post is further formed in the packaging substrate; or, before filling the outer periphery of the bonding silicon bridge with molding compound, a conductive interconnect post is further formed on the surface of the carrier board, wherein the conductive interconnect post is spaced apart from the bonding silicon bridge.

[0041] The advantages of the technical solution in this application are: This application embodiment provides bonding silicon bridges, which are connected face-to-face to a second silicon bridge via a first silicon bridge. Stress-adjustable vias are selectively and specifically formed within the first and / or second silicon bridges to adjust the stress distribution of the entire package structure. In practice, the stress distribution characteristics of the stress-adjustable vias within the silicon bridges are: compressive stress near the via and tensile stress between adjacent stress-adjustable vias. When stress-adjustable vias (SIVs) are located within the first silicon bridge, or when the number of SIVs within the first silicon bridge exceeds that of the second silicon bridge, the tensile stress of the first silicon bridge is greater than that of the second silicon bridge. This results in a warping stress (convex warping) in the bonded silicon bridge, causing the ends of the bonded silicon bridge to warp downwards (towards the second silicon bridge) and the middle to warp upwards. This stress generated by the bonded silicon bridge can offset or counteract the stress that causes the package structure to warp downwards in the middle and upwards at the edges (concave warping), thereby suppressing the concave warping of the package structure itself. When stress-adjustable vias (SIVs) are located within the second silicon bridge, or when the number of SIVs within the second silicon bridge exceeds that of the first silicon bridge, the tensile stress of the second silicon bridge is greater than that of the first silicon bridge. This results in a warping stress (concave warping) in the bonded silicon bridge, causing the ends of the bonded silicon bridge to warp upwards (towards the first silicon bridge) and the middle to warp downwards. This stress generated by the bonded silicon bridge can offset or counteract the stress that causes the package structure to warp upwards in the middle and downwards at the edges (convex warping), thereby suppressing the convex warping of the package structure itself. Therefore, the position, structure, and number of stress-adjustable through-silicon vias (TSVs) can be set according to the stress and warpage of the packaging structure itself, combined with the stress distribution characteristics of the TSVs within the silicon bridge. This ensures that the stress generated by the bonding silicon bridge is opposite to the stress that causes the packaging structure to warp, thus creating stress offset and suppressing the warpage of the packaging structure itself.

[0042] Furthermore, in an optional embodiment, the bonding silicon bridge of this application, while ensuring vertical power supply, forms an enhanced bonding silicon bridge structure by mixing and bonding the first silicon bridge and the second silicon bridge face-to-face. A stress-adjusting silicon via with axial compressive stress is provided on the passivation layer side, thereby introducing compressive stress towards the passivation layer to counteract the axial tensile stress of the packaging structure, achieving dynamic stress balance within the packaging structure. Simultaneously, the double-layer silicon bridge structure can improve the structural stiffness and bending resistance of local areas, enhance structural stability, effectively suppress warpage deformation of large-size packages during reflow soldering and molding processes, reduce the risk of solder joint cracking and delamination at the chip interconnect interface, and thus improve packaging manufacturing yield and long-term reliability. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure in one embodiment of the present application where the initial wafer of the first silicon bridge is mounted on the first bonding carrier. Figure 2This is a schematic diagram of the structure of the first silicon bridge after initial wafer thinning in one embodiment of this application; Figure 3 This is a schematic diagram of the structure after a passivation layer is formed on the initial wafer surface of the first silicon bridge in one embodiment of this application; Figure 4 This is a schematic diagram of the structure in one embodiment of the present application where the initial wafer of the second silicon bridge is mounted on the second bonding carrier. Figure 5 This is a schematic diagram of the structure of the second silicon bridge after initial wafer thinning in one embodiment of this application; Figure 6 This is a schematic diagram of the structure in one embodiment of the present application, showing the transfer of the initial wafer of the second silicon bridge to the third bonding carrier. Figure 7 This is a schematic diagram of the structure after transferring the initial wafer of the second silicon bridge to the third bonding substrate and removing the second bonding substrate in one embodiment of this application; Figure 8 This is a schematic diagram of the structure after a passivation layer is formed on the initial wafer surface of the second silicon bridge in one embodiment of this application; Figure 9 This is a schematic diagram of the structure of a bonded silicon bridge formed by the first silicon bridge and the second silicon bridge through a passivation layer in one embodiment of this application; Figure 10 This is a schematic diagram of the structure after removing the third bonding carrier plate in one embodiment of this application; Figure 11 This is a schematic diagram of the structure after the silicon bridge connecting pillars are formed in one embodiment of this application; Figure 12 This is a schematic diagram of the structure formed after bonding the silicon bridge in one embodiment of this application; Figure 13 This is a schematic diagram of the structure of the carrier plate provided in one embodiment of this application; Figure 14 This is a schematic diagram of the structure after bonding silicon bridges and embedded chips are formed on the surface of a carrier board in one embodiment of this application; Figure 15 This is a schematic diagram of the structure after the packaging substrate is formed in one embodiment of this application; Figure 16 This is a schematic diagram of the structure after the chip interconnect layer is formed in one embodiment of this application; Figure 17 This is a schematic diagram of the structure after the chip structure is installed in one embodiment of this application; Figure 18 This is a schematic diagram of the structure after filling the periphery of the chip structure with molding compound in one embodiment of this application; Figure 19 This is a schematic diagram of the structure after forming the substrate interconnect layer (substrate rewiring layer) in one embodiment of this application; Figure 20This is a schematic diagram of the structure after forming the substrate connection layer (substrate connection bump) in one embodiment of this application (the stress-adjustable silicon via is located in the second silicon bridge, and the encapsulation structure has a concave warping tendency). Figure 21 This is a schematic diagram of the structure after forming the substrate connection layer (substrate connection bump) in another embodiment of this application (the stress-adjustable silicon via is located in the first silicon bridge, and the packaging structure has a convex warping tendency). Figure 22 This is a schematic diagram of the encapsulation structure in another embodiment of this application; Figure 23 This is a schematic diagram of the process structure for fabricating a bonded silicon bridge according to an embodiment of this application; Figure 24 This is a schematic diagram of the process structure for fabricating a packaging structure according to an embodiment of this application.

[0044] Explanation of reference numerals in the attached figures: 100. Bonded silicon bridge; 1. First silicon bridge; 11. Stress-adjustable through-silicon via (TSV); 12. Conductive TSV; 13. Passivation layer; 14. Hybrid bonding pad; 151. First bonding carrier; 152. Initial wafer of the first silicon bridge; 153. Active trace; 154. Silicon bridge connecting post; 161. Second bonding carrier; 162. Initial wafer of the second silicon bridge; 163. Third bonding carrier; 2. Second silicon bridge; 200. Packaging structure; 21. Packaging substrate; 22. Conductive connecting post; 23. Chip molding layer; 24. Chip connection layer; 241. Chip connection bump; 25. Substrate connection layer; 251. Substrate connection bump; 26. Embedded chip; 27. Carrier; 271. Adhesive layer; 300. Chip structure; 400. Organic substrate. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] It should be understood that terms such as “first” and “second” used herein to describe various elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. For example, the use of terms such as “first” and “second” herein does not imply order or sequence unless the context clearly indicates otherwise. For ease of description, spatially relative terms such as “upper” and “lower” may be used herein to describe the relationship of one element or feature to other elements or features as shown in the accompanying drawings. It should be understood that spatially relative terms are intended to include not only the orientations shown in the accompanying drawings but also different orientations of the device in use or operation.

[0047] In this application, unless otherwise expressly specified and limited, the terms "connected" and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0048] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples. It should be noted that the terms "comprising" and "having," and their variations, used in this application are intended to cover non-exclusive inclusion.

[0049] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0050] Through experiments, the inventors discovered that the reasons for the internal stress imbalance and package warping in existing packaging structures include: In packaging structures containing embedded silicon bridges, there are significant differences in the coefficients of thermal expansion (CTE) between the silicon bridge die (thermal expansion coefficient of approximately 2.6 ppm / °C), the organic substrate (thermal expansion coefficient of approximately 16–17 ppm / °C), and various functional chips (such as logic chips and memory chips). This leads to uneven expansion and contraction of the components during thermal processes such as temperature cycling or reflow soldering, making the package extremely prone to warping and deformation during heating or cooling.

[0051] To address this issue, this application provides a bonding silicon bridge to alleviate stress imbalance and warpage within the packaging structure. Please refer to [reference needed]. Figure 12 The bonding silicon bridge 100 includes a first silicon bridge 1 and a second silicon bridge 2. At least one through-silicon via 12 is provided in the first silicon bridge 1 and the second silicon bridge 2 respectively. The through-silicon via 12 of the first silicon bridge 1 and the through-silicon via 12 of the second silicon bridge 2 are connected to each other. Stress-adjusting through-silicon via 11 is provided in the first silicon bridge 1 and / or the second silicon bridge 2. When stress-adjusting through-silicon via 11 is provided in the first silicon bridge 1 and the second silicon bridge 2 respectively, the number of stress-adjusting through-silicon via 11 in the first silicon bridge 1 is not equal to the number of stress-adjusting through-silicon via 11 in the second silicon bridge 2, so that the tensile stress of the first silicon bridge 1 is greater than that of the second silicon bridge 2, or the tensile stress of the second silicon bridge 2 is greater than that of the first silicon bridge 1.

[0052] The bonding silicon bridge 100 is connected face-to-face to the second silicon bridge 2 via a first silicon bridge 1, and stress-adjustable silicon vias 11 are selectively and specifically provided within the first silicon bridge 1 and / or the second silicon bridge 2 to adjust the stress condition of the entire package structure. In practice, the stress distribution characteristics of the stress-adjustable silicon vias 11 within the silicon bridge are: compressive stress near the via 11, and tensile stress between adjacent stress-adjustable silicon vias 11. When the stress-adjustable through-silicon via 11 is located within the first silicon bridge 1, or when the number of stress-adjustable through-silicon vias 11 within the first silicon bridge 1 is greater than that within the second silicon bridge 2, the tensile stress of the first silicon bridge 1 is greater than that of the second silicon bridge 2. This means that the bonding silicon bridge 100 will generate a stress that causes warping (convex warping) with both ends pointing downwards (towards the second silicon bridge 2) and the middle pointing upwards. This stress generated by the bonding silicon bridge 100 can offset or counteract the stress that causes warping (concave warping) with the middle pointing downwards and the edges pointing upwards in the package structure, thereby suppressing the concave warping of the package structure itself. When the stress-adjustable through-silicon via 11 is located within the second silicon bridge 2, or when the number of stress-adjustable through-silicon vias 11 within the second silicon bridge 2 is greater than that within the first silicon bridge 1, the tensile stress of the second silicon bridge 2 is greater than that of the first silicon bridge 1. This means that the bonding silicon bridge 100 will generate a stress F (stress F is as follows) that causes warping (concave warping) with both ends pointing upwards (towards the first silicon bridge 1) and the middle pointing downwards in the bonded silicon bridge 100. Figure 12 As shown, the stress generated by the bonding silicon bridge 100 can offset or counteract the stress that causes the package structure to warp upwards in the middle and downwards at the edges (convex warping), thereby suppressing the convex warping of the package structure itself. Accordingly, based on the stress and warping characteristics of the package structure itself, and combined with the stress distribution characteristics of the stress-adjustable through-silicon vias 11 within the silicon bridge, the position, structure, and number of stress-adjustable through-silicon vias 11 can be set so that the stress generated by the bonding silicon bridge 100 is opposite to the stress that causes the package structure to warp, forming stress counteraction, thereby suppressing the warping of the package structure itself.

[0053] Please continue to refer to this. Figure 12 In one embodiment, both the first silicon bridge 1 and the second silicon bridge 2 include a first surface and a second surface disposed opposite to each other. The first surfaces of the first silicon bridge 1 and the second silicon bridge 2 are respectively provided with passivation layers 13. Each passivation layer 13 has at least one hybrid bonding pad 14 corresponding to and connected to the through silicon via 12. The hybrid bonding pad 14 of the first silicon bridge 1 is bonded to the first silicon bridge 1, and the passivation layer 13 of the first surface of the first silicon bridge 1 is bonded to the passivation layer 13 of the first surface of the second silicon bridge 2, so that the first silicon bridge 1 and the second silicon bridge 2 are bonded face to face. The stress-adjustable silicon via 11 is in contact with the passivation layer 13.

[0054] The bonding silicon bridge 100 of this application, while ensuring vertical power supply, forms an enhanced bonding silicon bridge structure by mixing and bonding the first silicon bridge 1 and the second silicon bridge 2 face-to-face. A stress-adjustable silicon via 11 with axial compressive stress is provided on the passivation layer 13 side, thereby introducing compressive stress towards the passivation layer 13 to counteract the axial tensile stress (in the axial direction of the stress-adjustable silicon via 11) of the packaging structure, achieving dynamic stress balance within the packaging structure. Simultaneously, the double-layer silicon bridge structure of the bonding silicon bridge 100 can improve the structural stiffness and bending resistance of local areas, enhance structural stability, effectively suppress warpage deformation of large-size packages during reflow soldering and molding processes, reduce the risk of solder joint cracking and delamination at the chip interconnect interface, and thus improve packaging manufacturing yield and long-term reliability.

[0055] In one embodiment, the stress-adjustable silicon via 11 is a blind via structure or a through-hole structure.

[0056] By configuring the stress-adjustable silicon via 11 as either a blind via or a through-hole structure, the stress distribution pattern can be flexibly selected according to stress adjustment requirements. The compressive stress generated by the through-hole structure along the axial direction of the stress-adjustable silicon via 11 and towards the passivation layer 13 is mainly the resultant force of the axial components of the compressive stress around the via. The blind via structure, due to its closed bottom, can concentrate and amplify the axial compressive stress on the bottom surface, forming stronger local stress and exerting a more significant pre-tightening effect on the passivation layer 13 and the hybrid bonding pad 14; the through-hole structure, on the other hand, allows stress to be uniformly transmitted along the thickness direction of the silicon bridge, improving the overall structural rigidity. Using either or in combination can achieve refined stress adjustment and enhanced reliability.

[0057] In one embodiment, the stress-adjustable silicon vias 11 in the first silicon bridge 1 or the second silicon bridge 2 include a plurality of vias, and the spacing between adjacent stress-adjustable silicon vias 11 is 25 micrometers to 75 micrometers (specifically, it can be 50 micrometers, 60 micrometers or 70 micrometers). This spacing facilitates appropriate tensile stress between the stress-adjustable silicon vias 11.

[0058] In one embodiment, the distance between the stress-adjustable silicon via 11 and the through silicon via 12 can also be maintained at 25 micrometers to 75 micrometers (specifically, it can be 50 micrometers, 60 micrometers or 70 micrometers).

[0059] In actual use, there is also tensile stress between the stress-adjustable silicon via 11 and the conductive silicon via 12. This arrangement can prevent excessive stress concentration in the silicon bridge.

[0060] In one embodiment, the stress-adjustable silicon vias 11 in the first silicon bridge 1 or the second silicon bridge 2 include a plurality of vias, and the plurality of stress-adjustable silicon vias 11 are arranged in a rectangular array, a circular array or a ring array.

[0061] The array arrangement of the stress-adjustable through-silicon vias 11 within the first silicon bridge 1 can uniformly distribute the stress transmission path from the center to the edge of the silicon bridge, avoid stress concentration in the edge and center regions of the first silicon bridge 1 when the convex surface warps, and prevent the passivation layer 13 from cracking or the interconnection between the through-silicon vias 12 and the hybrid bonding pad 14 from breaking.

[0062] In one embodiment, an active trace 153 is provided in the first silicon bridge 1. The active trace 153 is located on the side of the first silicon bridge 1 away from the second silicon bridge 2 and can be disposed closer to the chip interconnect layer 24 to facilitate interconnection with the chip interconnect layer 24.

[0063] In one specific embodiment, the active trace 153 includes wiring metal.

[0064] In one embodiment, a silicon bridge connection post 154 is also included. The silicon bridge connection post 154 is disposed on the surface of the first silicon bridge 1 away from the second silicon bridge 2 and is connected to the through silicon via 12 in the first silicon bridge 1. The first silicon bridge 1 is connected to the chip interconnect layer 24 through the silicon bridge connection post 154.

[0065] This application also provides a method for preparing a bonded silicon bridge, which is used to prepare the aforementioned bonded silicon bridge. Please refer to [reference needed]. Figure 23 The preparation method includes the following steps: Step S100: Provide a first silicon bridge and a second silicon bridge. At least one through-silicon via is provided in the first silicon bridge and the second silicon bridge respectively. Stress-adjustable through-silicon vias are provided in the first silicon bridge and / or the second silicon bridge. When stress-adjustable through-silicon vias are provided in the first silicon bridge and the second silicon bridge respectively, the number of stress-adjustable through-silicon vias in the first silicon bridge is not equal to the number of stress-adjustable through-silicon vias in the second silicon bridge, so that the tensile stress of the first silicon bridge is greater than that of the second silicon bridge, or the tensile stress of the second silicon bridge is greater than that of the first silicon bridge. Step S200: Bond the first silicon bridge to the second silicon bridge, and make the through silicon vias of the first silicon bridge and the through silicon vias of the second silicon bridge correspondingly connected.

[0066] The bonding silicon bridge prepared by the method of this application can ensure vertical power supply while adjusting the bonding stress of the silicon bridge through the asymmetrically arranged stress-adjusting silicon vias 11 in the bonding silicon bridge to adapt to the stress of the packaging structure and avoid warping and cracking of the packaging structure.

[0067] The fabrication method of the aforementioned bonded silicon bridge is described in detail below with reference to the accompanying drawings in some embodiments.

[0068] First, please refer to Figure 23 In conjunction with references Figure 3 and Figure 8 In step S100, a first silicon bridge 1 and a second silicon bridge 2 are provided. At least one through-silicon via 12 is provided in the first silicon bridge 1 and the second silicon bridge 2 respectively. Stress-adjustable through-silicon via 11 is provided in the first silicon bridge 1 and / or the second silicon bridge 2. When stress-adjustable through-silicon via 11 is provided in the first silicon bridge 1 and the second silicon bridge 2 respectively, the number of stress-adjustable through-silicon via 11 in the first silicon bridge 1 is not equal to the number of stress-adjustable through-silicon via 11 in the second silicon bridge 2, so that the tensile stress of the first silicon bridge 1 is greater than that of the second silicon bridge 2, or the tensile stress of the second silicon bridge 2 is greater than that of the first silicon bridge 1.

[0069] In one embodiment, the stress-adjustable silicon via 11 is not provided within the first silicon bridge 1, and the steps for forming the first silicon bridge 1 include: Please refer to Figure 1 A first bonding substrate 151 and a first silicon bridge initial wafer 152 are provided. The first silicon bridge initial wafer 152 is disposed on the surface of the first bonding substrate 151. The first silicon bridge initial wafer 152 includes at least one through silicon via 12. One end of the through silicon via 12 is exposed on the surface of the first silicon bridge initial wafer 152 that is in contact with the first bonding substrate 151. Please refer to Figure 2 The first silicon bridge initial wafer 152 is thinned so that the other end of the through silicon via 12 is exposed on the side of the first silicon bridge initial wafer 152 away from the first bonding substrate 151. Please refer to Figure 3 A passivation layer 13 is formed on the surface of the first silicon bridge initial wafer 152 on the side away from the first bonding carrier 151. The passivation layer 13 includes a hybrid bonding pad 14 disposed corresponding to the through silicon via 12.

[0070] In one specific embodiment, the initial wafer 152 of the first silicon bridge can be thinned by a grinding process.

[0071] In one specific embodiment, when the first silicon bridge initial wafer 152 is disposed on the surface of the first bonding carrier 151, the active traces 153 of the first silicon bridge initial wafer 152 are disposed close to the first bonding carrier 151.

[0072] In one embodiment, the stress-adjustable silicon via 11 is disposed within the second silicon bridge 2, and the formation step of the second silicon bridge 2 includes: Please refer to Figure 4A second bonding carrier 161 and a second silicon bridge initial wafer 162 are provided. The second silicon bridge initial wafer 162 is disposed on the surface of the second bonding carrier 161. The second silicon bridge initial wafer 162 includes at least one through silicon via 12 and at least one stress-adjustable through silicon via 11. One end of the through silicon via 12 and one end of the stress-adjustable through silicon via 11 are exposed on the side surface of the second silicon bridge initial wafer 162 that is in contact with the second bonding carrier 161. The height of the stress-adjustable through silicon via 11 is lower than the height of the through silicon via 12. Please refer to Figure 5 The second silicon bridge initial wafer 162 is thinned so that the other end of the through silicon via 12 is exposed on the side of the second silicon bridge initial wafer 162 away from the second bonding substrate 161, but the other end of the stress-adjusting through silicon via 11 is not exposed (at this time, the stress-adjusting through silicon via 11 is a blind via structure). Please refer to Figure 6 A third bonding substrate 163 is provided, and the second silicon bridge initial wafer 162 is transferred to the surface of the third bonding substrate 163, wherein the side surface of the second silicon bridge initial wafer 162 away from the second bonding substrate 161 is in contact with the surface of the third bonding substrate 163. Please refer to Figure 7 and Figure 8 The second bonding carrier 161 is removed, and a passivation layer 13 is formed on one side surface (first surface) of the second silicon bridge initial wafer 162 that exposes the other end of the through silicon via 12 and the other end of the stress-adjustable through silicon via 11. The stress-adjustable through silicon via 11 in the second silicon bridge initial wafer 162 contacts the passivation layer 13 on the first surface of the second silicon bridge 2. The passivation layer 13 includes a hybrid bonding pad 14 corresponding to the through silicon via 12.

[0073] In one specific embodiment, the initial wafer 162 of the second silicon bridge can be thinned by a grinding process.

[0074] In another embodiment, the stress-adjustable silicon via 11 is disposed within the second silicon bridge 2, and the formation step of the second silicon bridge 2 includes: A second bonding carrier 161 and a second silicon bridge initial wafer 162 are provided. The second silicon bridge initial wafer 162 is disposed on the surface of the second bonding carrier 161. The second silicon bridge initial wafer 162 includes at least one through silicon via 12 and at least one stress-adjustable through silicon via 11. The surface of the second silicon bridge initial wafer 162 that contacts the second bonding carrier 161 exposes one end of the through silicon via 12 and one end of the stress-adjustable through silicon via 11. The second silicon bridge initial wafer 162 is thinned so that the other end of the through silicon via 12 and the other end of the stress-adjustable through silicon via 11 are exposed on the side of the second silicon bridge initial wafer 162 away from the second bonding carrier 161 (at this time, the stress-adjustable through silicon via 11 is a through-hole structure). A passivation layer 13 is formed on the surface (first surface) of the second silicon bridge initial wafer 162 on the side away from the second bonding substrate 161. The passivation layer 13 includes a hybrid bonding pad 14 disposed corresponding to the through silicon via 12.

[0075] In another specific embodiment, after the first silicon bridge 1 and the second silicon bridge 2 are bonded, the second bonding carrier 161 is removed.

[0076] Next, please refer to Figure 23 In conjunction with references Figure 9 In step S200, the first silicon bridge 1 and the second silicon bridge 2 are bonded together, and the through silicon vias 12 of the first silicon bridge 1 and the through silicon vias 12 of the second silicon bridge 2 are connected accordingly.

[0077] Please continue to refer to this. Figure 9 In one embodiment, the step of bonding the first silicon bridge 1 to the second silicon bridge 2 includes: The passivation layer 13 on the first surface of the first silicon bridge 1 is bonded to the passivation layer 13 on the first surface of the second silicon bridge 2, so that the hybrid bonding pad 14 of the first silicon bridge 1 is bonded to the hybrid bonding pad 14 of the second silicon bridge 2.

[0078] In another embodiment, the contact surface of the two passivation layers 13 is a bonding surface, and stress-adjustable silicon vias 11 are provided in both the first silicon bridge 1 and the second silicon bridge 2. The stress-adjustable silicon vias 11 in the first silicon bridge 1 and the stress-adjustable silicon vias 11 in the second silicon bridge 2 are asymmetrically arranged with respect to the bonding surface.

[0079] Please refer to Figure 10 and Figure 11 In one embodiment, after the first silicon bridge 1 and the second silicon bridge 2 are bonded, the first bonding carrier 151 is removed, and a silicon bridge connecting post 154 is formed on the surface of the through silicon via 12 on the side of the first silicon bridge initial wafer 152 away from the passivation layer 13.

[0080] In actual use, the silicon bridge connection post 154 is selected according to the thickness of the bonding silicon bridge 100. When the thickness of the bonding silicon bridge 100 is less than the thickness of the packaging substrate 21, the silicon bridge connection post 154 is provided on the surface of the first silicon bridge 1 to assist the interconnection between the bonding silicon bridge 100 and the chip interconnection layer 24.

[0081] In one embodiment, the silicon bridge connecting post 154 may be formed during the fabrication process of the bonded silicon bridge 100, or it may be formed after the outer periphery of the bonded silicon bridge 100 is filled with molding compound, and then an opening is etched to expose a through silicon via 12, and then the silicon bridge connecting post 154 is formed in the opening.

[0082] Please refer to Figure 12 In one specific embodiment, after the first silicon bridge 1 and the second silicon bridge 2 are bonded, the third bonding carrier 163 is removed.

[0083] Please refer to Figure 20 In conjunction with references Figure 12 In another aspect, this application also provides a packaging structure, including a packaging substrate 21 and a bonding silicon bridge 100; The bonding silicon bridge 100 is embedded in the packaging substrate 21. The bonding silicon bridge 100 includes the bonding silicon bridge described above, or the bonding silicon bridge 100 prepared by the method described above.

[0084] This embodiment of the application provides a bonding silicon bridge 100 with stress-adjustable through-silicon vias 11 within the packaging substrate 21. The stress-adjustable through-silicon vias 11 can be selectively and specifically provided within the first silicon bridge 1 and / or the second silicon bridge 2 to adjust the stress condition of the entire packaging structure 200. Specifically, based on the stress and warpage of the packaging structure 200 itself, and combined with the stress distribution characteristics of the stress-adjustable through-silicon vias 11 within the silicon bridge, the position, structure, and number of stress-adjustable through-silicon vias 11 can be set as needed. This ensures that the stress in the bonding silicon bridge 100 region is opposite to the stress in the packaging structure 200, creating stress offsetting and thereby adjusting the warpage of the packaging structure 200 itself.

[0085] Please continue to refer to this. Figure 20 In one embodiment, it further includes a chip interconnect layer 24 and a substrate interconnect layer 25; The packaging substrate 21 has a third surface and a fourth surface disposed opposite to each other. The first silicon bridge 1 of the bonding silicon bridge 100 is disposed close to the third surface and away from the fourth surface. The chip connection layer 24 is located on the third surface of the packaging substrate 21 and connected to the first silicon bridge 1. The substrate connection layer 25 is located on the fourth surface of the packaging substrate 21 and connected to the second silicon bridge 2.

[0086] Please continue to refer to this. Figure 20 In one embodiment, the stress-adjustable silicon via 11 is located within the second silicon bridge 2 (the bonding silicon bridge 100 is concave or has a tendency to be concave) to suppress the upward warping (convex warping) of the middle and downward warping of the package structure 200.

[0087] When the package structure 200 warps upward in the middle and downward at the edges, the substrate connection layer 25 contracts on one side to generate a bending moment. The stress-adjusting silicon via 11 is located in the second silicon bridge 2 and can introduce tensile stress in the opposite direction to the warping stress from one side of the second silicon bridge 2, thereby suppressing the overall warping of the package structure 200.

[0088] In one embodiment, the stress-adjustable through-silicon via 11 is located within the second silicon bridge 2, and there are multiple stress-adjustable through-silicon vias 11. The second silicon bridge 2 is provided with multiple through-silicon vias 12, and the multiple stress-adjustable through-silicon vias 11 and the multiple through-silicon vias 12 are distributed alternately at intervals.

[0089] The alternating distribution of the stress-adjustable silicon vias 11 and the conductive silicon vias 12 facilitates the uniform distribution of the axial compressive stress generated by the stress-adjustable silicon vias 11 along the bonding surface direction of the bonded silicon bridge 100, avoiding localized cracking of the passivation layer 13 or delamination of the bonding interface caused by stress concentration. This effectively suppresses convex warping while significantly improving the structural stiffness and thermomechanical reliability of the enhanced bonded silicon bridge 100.

[0090] In one embodiment, the through-silicon via 12 is filled with a conductive metal (copper, tungsten, aluminum or polysilicon), and the stress-adjustable through-silicon via 11 is filled with a conductive metal (copper, tungsten, aluminum or polysilicon).

[0091] In one embodiment, the conductive metal filling the stress-adjustable through-silicon via 11 is the same material as the conductive metal filling the through-silicon via 12, in order to reduce warping due to material differences.

[0092] In one embodiment, the first silicon bridge 1 and the second silicon bridge 2 are respectively provided with an unequal number of stress-adjusting silicon vias 11 arranged asymmetrically. The unequal number is used to generate tensile stress on one side of the first silicon bridge 1 or the second silicon bridge 2. The asymmetrical arrangement is to avoid the situation where the axial stress between the two opposing stress-adjusting silicon vias 11 is directly canceled out.

[0093] In another embodiment, stress-adjustable silicon vias 11 are respectively provided in the first silicon bridge 1 and the second silicon bridge 2, and the number of stress-adjustable silicon vias 11 in the first silicon bridge 1 is less than the number of stress-adjustable silicon vias 11 in the second silicon bridge 2 (the bonding silicon bridge 100 is concave or has a concave warping tendency). The stress-adjustable silicon vias 11 in the first silicon bridge 1 and the second silicon bridge 2 are asymmetrically arranged to suppress the warping (convex warping) of the packaging structure 200 with the middle rising and the edges falling.

[0094] When there is horizontal stress between the embedded chip 26 and the packaging substrate 21, the stress-adjusting silicon vias 11 in the first silicon bridge 1 and the second silicon bridge 2 can simultaneously generate tensile stress in the first silicon bridge 1 and the second silicon bridge 2 respectively (the tensile stress of the first silicon bridge 1 and the tensile stress of the second silicon bridge 2 have different position heights relative to the silicon bridge bonding surface), so as to offset the stress between the embedded chip 26 and the packaging substrate 21, so as to avoid edge warping or horizontal delamination between the packaging substrate 21 and the bonding silicon bridge 100 and the embedded chip 26 respectively.

[0095] Please refer to Figure 21 In another embodiment, the stress-adjustable silicon via 11 is located within the first silicon bridge 1 (the bonding silicon bridge 100 is convex or has a tendency to convexly warp) to suppress the downward warping (concave warping) of the middle and upward warping of the package structure 200.

[0096] In another embodiment, the stress-adjustable through-silicon via 11 is located within the first silicon bridge 1, and there are multiple stress-adjustable through-silicon vias 11. The first silicon bridge 1 is provided with multiple through-silicon vias 12, and the multiple stress-adjustable through-silicon vias 11 and the multiple through-silicon vias 12 are distributed alternately at intervals.

[0097] In another embodiment, stress-adjustable silicon vias 11 are respectively provided in the first silicon bridge 1 and the second silicon bridge 2, and the number of stress-adjustable silicon vias 11 in the first silicon bridge 1 is greater than the number of stress-adjustable silicon vias 11 in the second silicon bridge 2 (the bonding silicon bridge 100 is convexly warped or has a convexly warped tendency). The stress-adjustable silicon vias 11 in the first silicon bridge 1 and the second silicon bridge 2 are asymmetrically arranged to suppress the downward warping (concave warping) of the middle and upward warping (concave warping) of the packaging structure 200.

[0098] In actual use, when the middle of the package structure 200 warps downward and the edges upward, the chip interconnect layer 24 shrinks on one side to generate a bending moment. The stress-adjustable silicon via 11 is located in the first silicon bridge 1, or the number of stress-adjustable silicon via 11 in the first silicon bridge 1 is greater than the number of stress-adjustable silicon via 11 in the second silicon bridge 2. This can introduce a tensile stress in the opposite direction to the warping stress of the package structure 200 from one side of the first silicon bridge 1, thereby suppressing the overall warping of the package structure 200.

[0099] Please continue to refer to this. Figure 20 In one embodiment, the package further includes a chip structure 300, which is disposed on the surface of the chip interconnect layer 24 away from the packaging substrate 21 and connected to the chip interconnect layer 24 via chip interconnect bumps 241. In this case, the packaging structure 200 is a chip packaging structure.

[0100] In one embodiment, the chip structure 300 includes at least two, and the at least two chip structures 300 are connected by the bonding silicon bridge 100.

[0101] In one specific embodiment, the chip structure 300 includes electrical chips (heterogeneous accelerator processor chip / general-purpose parallel processor chip xPU, application-specific integrated circuit chip ASIC, high-bandwidth memory chip HBM, input / output control chip or super IO chip).

[0102] In one specific embodiment, the side and bottom surfaces of the chip structure 300 are further covered with molding compound.

[0103] In one embodiment, the packaging substrate 21 further includes an embedded chip 26, which is located within the packaging substrate 21, and the upper and lower surfaces of the embedded chip 26 are respectively connected to the chip connection layer 24 and the substrate connection layer 25.

[0104] Embedded chip 26 can perform signal switching, data processing or function integration, increase interconnect density, shorten signal paths and reduce transmission loss.

[0105] In one embodiment, the packaging substrate 21 is mounted onto the circuit board via the substrate connection layer 25.

[0106] In another embodiment, please refer to Figure 22 The packaging substrate 21 does not include the embedded chip 26. The structural layer where the packaging substrate 21 is located serves as an intermediate structural layer. The substrate connection layer 25 is used to connect the organic substrate 400 (as a packaging substrate). The chip structure 300 is then mounted onto the circuit board (not shown in the figure) through the organic substrate 400.

[0107] In one embodiment, the packaging structure 200 further includes conductive connection pillars 22 disposed in the packaging substrate 21, with both ends of the conductive connection pillars 22 connected to the chip connection layer 24 and the substrate connection layer 25 respectively, thereby further realizing the interconnection between the chip connection layer 24 and the substrate connection layer 25.

[0108] Please continue to refer to this. Figure 20 In one embodiment, it further includes a silicon bridge connection post 154, which is disposed on the surface of the first silicon bridge 1 away from the second silicon bridge 2 and connected to the through silicon via 12 in the first silicon bridge 1. The first silicon bridge 1 is connected to the chip interconnect layer 24 through the silicon bridge connection post 154.

[0109] Please continue to refer to this. Figure 20In one embodiment, the chip interconnect layer 24 includes a chip redistribution layer, which is electrically connected to the through silicon via 12 in the first silicon bridge 1.

[0110] Please continue to refer to this. Figure 20 In one embodiment, a chip connection bump 241 is also included, which is disposed on the side surface of the chip redistribution layer away from the packaging substrate 21.

[0111] Please continue to refer to this. Figure 20 In one embodiment, the substrate connection layer 25 includes a substrate redistribution layer, which is electrically connected to the through silicon via 12 in the second silicon bridge 2.

[0112] Please continue to refer to this. Figure 20 In one embodiment, the substrate connection layer 25 further includes a substrate connection bump 251, which is disposed on the side surface of the substrate redistribution layer away from the package substrate 21.

[0113] This application also provides a method for preparing a packaging structure, which is used to prepare the aforementioned packaging structure. Please refer to [reference needed]. Figure 24 The method for preparing the encapsulation structure includes the following steps: Step S10: Provide a bonded silicon bridge, wherein the bonded silicon bridge includes the bonded silicon bridge described above, or a bonded silicon bridge prepared by the method described above. Step S20: Fill the outer periphery of the bonded silicon bridge with molding compound to form a packaging substrate.

[0114] The preparation method of the aforementioned packaging structure is described in detail below with reference to the accompanying drawings in some embodiments.

[0115] In one embodiment, the method for preparing the packaging structure includes the following specific steps: Please refer to Figure 13 Provide carrier board 27; Please refer to Figure 12 and Figure 14 The bonding silicon bridge 100 is provided and mounted on the surface of the carrier 27. The second silicon bridge 2 of the bonding silicon bridge 100 is located on the side close to the carrier 27, and the outer periphery of the bonding silicon bridge 100 is filled with molding compound (see reference). Figure 15 A packaging substrate 21 is formed, and the through silicon via 12 of the bonding silicon bridge 100 is exposed on the side of the substrate away from the carrier plate 27. Please refer to Figure 18 Remove the carrier plate 27.

[0116] Please refer to Figure 14In one specific embodiment, the bonded silicon bridge 100 is bonded to the surface of the carrier plate 27 by an adhesive layer 271 (including but not limited to epoxy resin adhesive, metal stop layer and other structural layers).

[0117] Please refer to Figure 17 and Figure 18 In one specific embodiment, when removing the carrier board 27, the adhesive layer 271 that bonds the bonding silicon bridge 100 (or embedded chip 26) to the surface of the carrier board 27 is also removed.

[0118] In one embodiment, the substrate has a third surface and a fourth surface disposed opposite to each other, and the method for fabricating the encapsulation structure further includes: Please refer to Figure 16 A chip interconnect layer 24 is formed on the third surface of the substrate, and the chip interconnect layer 24 is connected to the first silicon bridge 1. Please refer to Figure 19 A substrate connection layer 25 is formed on the fourth surface of the substrate, and the substrate connection layer 25 is connected to the second silicon bridge 2.

[0119] In one embodiment, before removing the carrier 27, a chip interconnect layer 24 is first formed on the surface of the substrate away from the carrier 27 (see reference). Figure 16 ); After removing the carrier 27, a substrate interconnect layer 25 is formed on the surface of the substrate away from the chip interconnect layer 24 (see reference). Figure 19 ).

[0120] Please refer to Figure 15 In one embodiment, before forming the chip interconnect layer 24, conductive interconnect pillars 22 are formed in the substrate; or, before filling the outer periphery of the bonding silicon bridge 100 with molding compound, conductive interconnect pillars 22 are formed on the surface of the carrier 27, wherein the conductive interconnect pillars 22 are spaced apart from the bonding silicon bridge 100.

[0121] Please refer to Figure 15 In one embodiment, before filling the outer periphery of the bonding silicon bridge 100 with molding compound, an embedded chip 26 is disposed on the surface of the carrier 27, the embedded chip 26 being disposed at a distance from the bonding silicon bridge 100.

[0122] In one embodiment, the molding compound is filled onto the side surface of the embedded chip 26, and the filling of the molding compound onto the side surface of the embedded chip 26 can be performed in steps.

[0123] Please refer to Figure 16 and Figure 19In one embodiment, the chip interconnect layer 24 includes a chip redistribution layer, and the substrate interconnect layer 25 includes a substrate redistribution layer; It also includes the steps of forming chip connection bumps 241 on the side surface of the chip redistribution layer away from the substrate, and forming substrate connection bumps 251 on the side surface of the substrate redistribution layer away from the substrate.

[0124] Please refer to Figure 17 In one embodiment, a chip structure 300 is mounted on the surface of the chip interconnect layer 24 away from the packaging substrate 21.

[0125] Please refer to Figure 18 In one embodiment, the package structure 200 is further filled with molding compound to form a chip molding layer 23 covering the side and bottom surfaces of the chip structure 300.

[0126] In one embodiment, in the method for preparing the packaging structure, the chip structure 300 can be installed after the substrate interconnect layer 25 is prepared, or the chip structure 300 can be installed after the chip interconnect layer 24 is formed and before the substrate interconnect layer 25 is formed, so as to simplify the process steps and improve the process efficiency.

[0127] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A bonded silicon bridge, characterized in that, The bonding silicon bridge includes a first silicon bridge and a second silicon bridge. At least one through-silicon via is provided in each of the first and second silicon bridges. The through-silicon vias of the first and second silicon bridges are connected to each other. Stress-adjusting through-silicon vias are provided in the first and / or second silicon bridges. When stress-adjusting through-silicon vias are provided in the first and second silicon bridges respectively, the number of stress-adjusting through-silicon vias in the first and second silicon bridges is not equal to the number of stress-adjusting through-silicon vias in the second silicon bridge, so that the tensile stress of the first silicon bridge is greater than that of the second silicon bridge, or the tensile stress of the second silicon bridge is greater than that of the first silicon bridge.

2. A bonding silicon bridge as described in claim 1, characterized in that, Both the first silicon bridge and the second silicon bridge include a first surface and a second surface disposed opposite to each other. The first surface of the first silicon bridge and the second silicon bridge are respectively provided with a passivation layer. Each passivation layer has at least one hybrid bonding pad corresponding to and connected to the through silicon via. The hybrid bonding pad of the first silicon bridge is bonded to the hybrid bonding pad of the second silicon bridge. The passivation layer of the first surface of the first silicon bridge is bonded to the passivation layer of the first surface of the second silicon bridge, so that the first silicon bridge and the second silicon bridge are bonded face to face. The stress-adjustable silicon via is in contact with the passivation layer.

3. A bonding silicon bridge as described in claim 1, characterized in that, The stress-adjustable silicon via can be either a blind via structure or a through-hole structure.

4. A bonding silicon bridge as described in claim 1, characterized in that, The stress-adjustable silicon vias within the first or second silicon bridge comprise a plurality of vias, and the spacing between adjacent stress-adjustable silicon vias is 25 micrometers to 75 micrometers.

5. A bonding silicon bridge as described in claim 1, characterized in that, The stress-adjustable silicon vias within the first silicon bridge or the second silicon bridge comprise a plurality of vias, and the plurality of stress-adjustable silicon vias are arranged in a rectangular array, a circular array, or a ring array.

6. A bonding silicon bridge as described in claim 1, characterized in that, An active trace is provided inside the first silicon bridge, and the active trace is located on the side of the first silicon bridge away from the second silicon bridge.

7. A method for fabricating a bonded silicon bridge, characterized in that, Includes the following steps: A first silicon bridge and a second silicon bridge are provided. At least one through-silicon via is provided in the first silicon bridge and the second silicon bridge respectively. Stress-adjustable through-silicon vias are provided in the first silicon bridge and / or the second silicon bridge. When stress-adjustable through-silicon vias are provided in the first silicon bridge and the second silicon bridge respectively, the number of stress-adjustable through-silicon vias in the first silicon bridge is not equal to the number of stress-adjustable through-silicon vias in the second silicon bridge, so that the tensile stress of the first silicon bridge is greater than that of the second silicon bridge, or the tensile stress of the second silicon bridge is greater than that of the first silicon bridge. The first silicon bridge and the second silicon bridge are bonded together, and the through silicon vias of the first silicon bridge are connected to the through silicon vias of the second silicon bridge.

8. The method for fabricating a bonded silicon bridge as described in claim 7, characterized in that, The first silicon bridge and the second silicon bridge have a first surface and a second surface disposed opposite to each other. The first surface of the first silicon bridge and the first surface of the second silicon bridge are respectively provided with a passivation layer. Each passivation layer has a hybrid bonding pad that is connected to each of the through silicon vias. The stress-adjusting through silicon vias in the first silicon bridge are in contact with the passivation layer of the first surface of the first silicon bridge, and the stress-adjusting through silicon vias in the second silicon bridge are in contact with the passivation layer of the first surface of the second silicon bridge. The steps of bonding the first silicon bridge to the second silicon bridge include: The passivation layer on the first surface of the first silicon bridge is bonded to the passivation layer on the first surface of the second silicon bridge, so that the hybrid bonding pad of the first silicon bridge is bonded to the hybrid bonding pad of the second silicon bridge. The contact surface of the two passivation layers is the bonding surface. When stress-adjustable silicon vias are provided in both the first silicon bridge and the second silicon bridge, the stress-adjustable silicon vias in the first silicon bridge and the stress-adjustable silicon vias in the second silicon bridge are asymmetrically arranged with respect to the bonding surface.

9. The method for fabricating a bonded silicon bridge as described in claim 8, characterized in that, The first silicon bridge does not contain the stress-adjustable silicon via, and the steps for forming the first silicon bridge include: A first bonding substrate and a first silicon bridge initial wafer are provided. The first silicon bridge initial wafer is disposed on the surface of the first bonding substrate. The first silicon bridge initial wafer includes at least one through-silicon via (TSV). One end of the TSV is exposed on the surface of the first silicon bridge initial wafer that contacts the first bonding substrate. The first silicon bridge initial wafer is thinned so that the other end of the through silicon via is exposed on the side of the first silicon bridge initial wafer away from the first bonding substrate. A passivation layer is formed on the surface of the first silicon bridge initial wafer on the side away from the first bonding substrate, the passivation layer including hybrid bonding pads disposed corresponding to the through silicon vias.

10. The method for fabricating a bonded silicon bridge as described in claim 9, characterized in that, After the first silicon bridge and the second silicon bridge are bonded, the process further includes removing the first bonding substrate and forming a silicon bridge connecting post on the surface of the through silicon via on the side of the initial wafer of the first silicon bridge away from the passivation layer.

11. The method for fabricating a bonded silicon bridge as described in claim 8, characterized in that, The stress-adjustable silicon via is disposed within the second silicon bridge, and the formation steps of the second silicon bridge include: A second bonding substrate and a second silicon bridge initial wafer are provided. The second silicon bridge initial wafer is disposed on the surface of the second bonding substrate. The second silicon bridge initial wafer includes at least one through-silicon via and at least one stress-adjustable through-silicon via. The surface of the second silicon bridge initial wafer that contacts the second bonding substrate exposes one end of the through-silicon via and one end of the stress-adjustable through-silicon via. The second silicon bridge initial wafer is thinned so that the other end of the through silicon via and the other end of the stress-adjusting through silicon via are exposed on the side of the second silicon bridge initial wafer away from the second bonding substrate. A passivation layer is formed on the surface of the second silicon bridge initial wafer on the side away from the second bonding substrate, the passivation layer including hybrid bonding pads disposed corresponding to the through silicon vias.

12. The method for fabricating a bonded silicon bridge as described in claim 8, characterized in that, The stress-adjustable silicon via is disposed within the second silicon bridge, and the formation steps of the second silicon bridge include: A second bonding substrate and a second silicon bridge initial wafer are provided. The second silicon bridge initial wafer is disposed on the surface of the second bonding substrate. The second silicon bridge initial wafer includes at least one through-silicon via (TSV) and at least one stress-adjustable TSV. The surface of the second silicon bridge initial wafer that contacts the second bonding substrate exposes one end of the TSV and one end of the stress-adjustable TSV. The height of the stress-adjustable TSV is lower than the height of the TSV. The second silicon bridge initial wafer is thinned so that the other end of the through silicon via is exposed on the side of the second silicon bridge initial wafer away from the second bonding substrate, but the other end of the stress-adjusting through silicon via is not exposed. A third bonding substrate is provided, and the second silicon bridge initial wafer is transferred to the surface of the third bonding substrate, wherein the surface of the second silicon bridge initial wafer away from the second bonding substrate is in contact with the surface of the third bonding substrate; The second bonding substrate is removed, and a passivation layer is formed on one side surface of the second silicon bridge initial wafer that exposes the other end of the through-silicon via and the other end of the stress-adjustable through-silicon via. The passivation layer includes a hybrid bonding pad disposed corresponding to the through-silicon via.

13. A packaging structure, characterized in that, This includes the packaging substrate and the bonding silicon bridge; The bonding silicon bridge is embedded in the packaging substrate. The bonding silicon bridge includes a bonding silicon bridge as described in any one of claims 1 to 6, or a bonding silicon bridge prepared by the method described in any one of claims 7 to 12.

14. The packaging structure as described in claim 13, characterized in that, The stress-adjustable silicon via is located within the first silicon bridge to suppress the downward warping of the middle and upward warping of the packaging structure at the edges. Alternatively, stress-adjustable through-silicon vias are provided in the first silicon bridge and the second silicon bridge, respectively, and the number of stress-adjustable through-silicon vias in the first silicon bridge is greater than the number of stress-adjustable through-silicon vias in the second silicon bridge, so as to suppress the downward warping of the middle and upward warping of the packaging structure.

15. The packaging structure as described in claim 14, characterized in that, The stress-adjustable through-silicon vias are located within the first silicon bridge. There are multiple stress-adjustable through-silicon vias. The first silicon bridge is provided with multiple through-silicon vias. The multiple stress-adjustable through-silicon vias and the multiple through-silicon vias are distributed alternately at intervals.

16. The packaging structure as described in claim 13, characterized in that, The stress-adjustable silicon via is located within the second silicon bridge to suppress the upward warping of the middle and downward warping of the packaging structure at the edges. Alternatively, stress-adjustable through-silicon vias are provided in the first silicon bridge and the second silicon bridge, respectively, and the number of stress-adjustable through-silicon vias in the first silicon bridge is less than the number of stress-adjustable through-silicon vias in the second silicon bridge, so as to suppress the warping of the package structure upward in the middle and downward at the edges.

17. The packaging structure as described in claim 16, characterized in that, The stress-adjustable through-silicon vias are located within the second silicon bridge. There are multiple stress-adjustable through-silicon vias. The second silicon bridge has multiple conductive through-silicon vias. The multiple stress-adjustable through-silicon vias and the multiple conductive through-silicon vias are distributed alternately at intervals.

18. The packaging structure as described in claim 13, characterized in that, It also includes a chip interconnect layer and a substrate interconnect layer; The packaging substrate has a third surface and a fourth surface disposed opposite to each other. The first silicon bridge of the bonding silicon bridge is disposed close to the third surface and away from the fourth surface. The chip interconnect layer is located on the third surface of the packaging substrate and connected to the first silicon bridge. The substrate interconnect layer is located on the fourth surface of the packaging substrate and connected to the second silicon bridge.

19. The packaging structure as described in claim 18, characterized in that, It also includes a chip structure, which is disposed on the side surface of the chip interconnect layer away from the packaging substrate and connected to the chip interconnect layer through chip interconnect bumps.

20. The packaging structure as described in claim 19, characterized in that, The chip structure includes at least two, and the at least two chip structures are connected by the bonding silicon bridge.

21. The packaging structure as described in claim 18, characterized in that, The packaging substrate also includes an embedded chip, which is located within the packaging substrate, and the upper and lower surfaces of the embedded chip are respectively connected to the chip connection layer and the substrate connection layer.

22. The packaging structure as described in claim 18, characterized in that, The packaging structure further includes conductive connection pillars disposed within the packaging substrate, with both ends of the conductive connection pillars connected to the chip connection layer and the substrate connection layer, respectively.

23. The packaging structure as described in claim 18, characterized in that, It also includes silicon bridge connection posts, which are disposed on the surface of the first silicon bridge away from the second silicon bridge and connected to through-silicon vias in the first silicon bridge. The first silicon bridge is connected to the chip interconnect layer through the silicon bridge connection posts.

24. The packaging structure as described in claim 18, characterized in that, The chip interconnect layer includes a chip redistribution layer, which is electrically connected to the through-silicon via in the first silicon bridge.

25. The packaging structure as described in claim 24, characterized in that, It also includes chip connection bumps, which are disposed on the side surface of the chip redistribution layer away from the packaging substrate.

26. The packaging structure as described in claim 19, characterized in that, The substrate interconnect layer includes a substrate redistribution layer, which is electrically connected to the through-silicon via in the second silicon bridge.

27. The packaging structure as described in claim 26, characterized in that, The substrate connection layer further includes substrate connection bumps, which are disposed on the side surface of the substrate redistribution layer away from the package substrate.

28. A method for preparing a packaging structure, characterized in that, Includes the following steps: Provide a bonded silicon bridge, the bonded silicon bridge including a bonded silicon bridge according to any one of claims 1 to 6, or a bonded silicon bridge prepared by the preparation method of a bonded silicon bridge according to any one of claims 7 to 12; A molding compound is filled around the bonded silicon bridge to form a packaging substrate.

29. The method for preparing a packaging structure as described in claim 28, characterized in that, The packaging substrate has a third surface and a fourth surface disposed opposite to each other, and further includes: A chip interconnect layer is formed on the third surface of the packaging substrate, and the chip interconnect layer is connected to the first silicon bridge; A substrate connection layer is formed on the fourth surface of the packaging substrate, and the substrate connection layer is connected to the second silicon bridge.

30. The method for preparing a packaging structure as described in claim 29, characterized in that, The chip interconnect layer includes a chip redistribution layer, and the substrate interconnect layer includes a substrate redistribution layer; It also includes the steps of forming chip connection bumps on the side surface of the chip redistribution layer away from the packaging substrate, and forming substrate connection bumps on the side surface of the substrate redistribution layer away from the packaging substrate.

31. The method for preparing a packaging structure as described in claim 29, characterized in that, It also includes mounting a chip structure on the side of the chip interconnect layer away from the packaging substrate.

32. The method for preparing a packaging structure as described in claim 29, characterized in that, The formation of the packaging substrate includes the following steps: Provide carrier board; The bonding silicon bridge is provided, the bonding silicon bridge is mounted on the surface of the carrier plate, the second silicon bridge of the bonding silicon bridge is located on the side close to the carrier plate, and the outer peripheral side of the bonding silicon bridge is filled with molding compound to form a packaging substrate. The through silicon via of the bonding silicon bridge is exposed on the side of the packaging substrate away from the carrier plate. Remove the carrier plate.

33. The method for preparing a packaging structure as described in claim 32, characterized in that, It also includes an embedded chip disposed on the surface of the carrier board, the embedded chip being spaced apart from the bonding silicon bridge.

34. The method for preparing a packaging structure as described in claim 32, characterized in that, Before removing the carrier board, a chip interconnect layer is formed on the surface of the packaging substrate away from the carrier board; After removing the carrier board, a substrate connection layer is formed on the surface of the packaging substrate away from the chip connection layer.

35. The method for preparing a packaging structure as described in claim 32, characterized in that, Before forming the chip interconnect layer, the method further includes forming conductive interconnect pillars within the packaging substrate, or, before filling the outer periphery of the bonding silicon bridge with molding compound, the method further includes forming conductive interconnect pillars on the surface of the carrier board, wherein the conductive interconnect pillars are spaced apart from the bonding silicon bridge.

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