Improved structure and method of preparation of intermetallic semiconductor thin interlayer-based conductors

Abstract

The application discloses a conductive improvement structure based on an intermetallic semiconductor thin interlayer and a preparation method, belongs to the field of advanced packaging technology of integrated circuits, and aims to solve the problem of the increase of resistivity caused by the size effect of the existing metal interconnection structure. The structure comprises a substrate, a metal-semiconductor thin layer alternately stacked layer and a patterned metal cover layer which are sequentially stacked from bottom to top. The semiconductor thin layer is a two-dimensional / quasi-two-dimensional material. The metal cover layer and the semiconductor thin interlayer edge form a carrier injection channel. The preparation method comprises substrate cleaning, metal-semiconductor alternately stacked layer preparation and patterning, metal cover layer preparation and patterning. The application changes the carrier transmission mechanism, avoids the size effect, considers the conductive performance and mechanical stability, is compatible with the existing micro-nano processing technology, has low cost and is easy to mass produce, can realize the transmission line structure with line width / line spacing not worse than 4 microns, and is suitable for advanced packaging redistribution layers.

Description

Technical Field

[0001] This invention belongs to the field of advanced integrated circuit packaging technology, specifically relating to a conductivity-improved structure and preparation method based on a thin intermetallic semiconductor sandwich layer. Background Technology

[0002] Packaging is the technological foundation for ensuring the proper functioning of integrated circuit devices. In the post-Moore's Law era, introducing advanced packaging is a key path to improve the performance density of semiconductor devices and promote the miniaturization of devices and integrated circuit products. As a hallmark structure within advanced packaging, the redistribution layer in the packaging substrate and interposer breaks the spatial limitations of chip pin (interface) layout by redistributing the electrical connections of the encapsulated wafer, greatly improving the flexibility and wiring density of chip integration. With the rapid evolution of fields such as artificial intelligence and high-performance computing, redistribution layer technology plays a core role in fan-out packaging, 2.5D / 3D packaging, and chiplet advanced packaging architectures, becoming a key link in achieving high-performance signal transmission.

[0003] As packaging integration density continues to increase, the horizontal line dimensions (linewidth / spacing) in redistribution layers are also gradually shrinking towards the micrometer and even submicrometer scale. Against this backdrop, traditional single-metal interconnect structures are constrained by size effects: when the metal interconnect shrinks in at least one dimension (linewidth or thickness) to the same order of magnitude (tens of nanometers) or even smaller than the mean free path of charge carriers in the metal, the contribution of scattering mechanisms such as the metal surface and grain boundaries to charge carrier scattering increases to a non-negligible level. This results in a significant increase in the effective resistivity of such quasi-two-dimensional layers / quasi-one-dimensional lines compared to three-dimensional bulk metals. In applications, this non-linear increase in resistivity caused by size reduction can lead to numerous problems such as increased signal transmission impedance, signal delay, and heat accumulation, seriously threatening the signal transmission characteristics and long-term reliability of the package.

[0004] Existing technologies attempt to reduce interconnect resistivity by optimizing metal deposition processes and improving grain size and orientation. However, these improvements are approaching their physical limits when faced with scattering at extremely small sizes. Additionally, some technologies propose using two-dimensional semi-metallic materials such as graphene as carrier mirror reflective layers on the copper surface to mitigate the reduction of carrier kinetic energy caused by surface scattering. However, this approach does not reduce the scattering effect of grain boundaries on carriers, and the effective resistivity of the transmission line remains highly dependent on the physical properties of the metal. Furthermore, achieving high-quality, large-area fabrication or transfer of two-dimensional materials such as graphene on metal surfaces is extremely difficult and costly. Poor bonding between graphene and metal can easily lead to interlayer slippage and delamination, thereby weakening the mechanical properties of the entire redistribution layer structure.

[0005] Therefore, the advanced packaging field urgently needs a low-cost, mechanically robust, and highly reliable method to improve the conductive structure by fundamentally changing the carrier transport mechanism. This would overcome the key problem of the size effect restricting the conductivity of the redistribution layer circuits, further increase the wiring density in the redistribution layer, and continue to promote the miniaturization and performance density of advanced packaging structures and even integrated circuit products. Summary of the Invention

[0006] The technical problem to be solved by this invention is to overcome the shortcomings of the prior art and provide a conductivity-improving structure and preparation method based on a thin intermetallic semiconductor sandwich layer. This invention introduces one or more extremely thin two-dimensional or quasi-two-dimensional semiconductor material sandwich layers in the middle of the original metal conductive layer, thereby changing the carrier transport mechanism in the horizontal direction: a heterogeneous gold-semi-contact structure is formed between the semiconductor layer and the metal. During signal transmission, the high concentration of carriers in the metal is injected into the semiconductor energy band in large quantities through the edge under the drive of the potential difference, and then transported rapidly in the horizontal direction in this two-dimensional or quasi-two-dimensional semiconductor material with an extremely low scattering rate, thereby improving the macroscopic conductivity of the conductive layer in the horizontal direction.

[0007] The technical solution adopted by this invention to solve the problems existing in the prior art is: An improved conductivity structure based on intermetallic semiconductor thin sandwich layers includes a substrate, alternating metal-semiconductor thin layers, and a patterned metal capping layer stacked sequentially from bottom to top. The alternating stacking of metal-semiconductor thin layers forms the core conductive functional layer of the structure, which is then patterned to form a preset conductive structure pattern. The patterned metal overlay and the edge of the semiconductor thin interlayer form a good electrical connection, creating a carrier injection channel.

[0008] A method for fabricating a conductivity-improved structure based on an intermetallic semiconductor thin sandwich layer includes the following steps: S01: Substrate cleaning process, which uses a multi-step cleaning process to remove oil, impurities and oxide layer from the substrate surface; S02: Preparation and patterning of alternating metal-semiconductor thin film stacks: metal layers and semiconductor thin films are deposited sequentially on a cleaned substrate to form an alternating stack structure, and then the stack is patterned. S03: Fabrication of patterned metal capping layer. A patterned metal capping layer is fabricated on the patterned surface of alternating stacked layers to ensure good electrical connection with the edge of the semiconductor thin interlayer.

[0009] Preferably, the substrate is made of at least one of glass, silicon, resin, and ceramic, and the substrate surface undergoes a multi-step cleaning process to ensure the adhesion and growth quality of subsequent film deposition.

[0010] Preferably, the alternating metal-semiconductor thin layer stack comprises at least one metal layer and one semiconductor thin layer, and the metal and semiconductor thin layers are alternately stacked in the vertical direction to form a composite structure; The conductive structure pattern is a specific geometric structure with electrical signal transmission function.

[0011] Preferably, the metal layer is a titanium-copper bilayer metal layer, with the titanium layer having a thickness of 10-100 nm and the copper layer having a thickness of 10 nm-1 μm; Alternatively, a single copper metal layer with a thickness of 10nm-1μm.

[0012] Preferably, the semiconductor thin layer is a two-dimensional or quasi-two-dimensional semiconductor layer, preferably a metal oxide or metal nitride semiconductor, and more preferably a zinc oxide or indium gallium zinc oxide with a thickness of <10 nm.

[0013] Preferably, the patterned metal overlay is a copper metal layer with a thickness of 10 nm-1 μm; The edge of the semiconductor thin interlayer is a cross-section or line of the semiconductor thin interlayer.

[0014] Preferably, this structure can achieve a transmission line structure with a line width and line spacing of not less than 4μm.

[0015] Preferably, step S01 specifically includes: S011. Basic ultrasonic cleaning: The substrate is ultrasonically cleaned sequentially with acetone, isopropanol, deionized water and ethanol. Each cleaning step is completed at room temperature by an ultrasonic cleaner with an ultrasonic power of 50-300W, an ultrasonic frequency of 20-80kHz and a single cleaning time of 5-30min. After each cleaning step, rinse the substrate with the solvent of the next cleaning step to remove residual liquid. After all cleaning is completed, blow the substrate dry with a nitrogen gun. S012. Surface plasma cleaning: Place the dried substrate in an oxygen plasma cleaner for 2-10 minutes, with a power of 50-300W and an oxygen flow rate of 20-80 sccm.

[0016] Preferably, in step S02, the metal layer is deposited by magnetron sputtering under an argon atmosphere, and the two-dimensional semiconductor layer is deposited by atomic layer deposition and plasma-enhanced atomic layer deposition. In step S03, the metal coating is deposited in an argon atmosphere using magnetron sputtering, and the patterning process is the same as in step S02, preferably using the stripping and floating method.

[0017] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention introduces a two-dimensional / quasi-two-dimensional semiconductor material interlayer with low scattering and high mobility, and designs a metal-semiconductor edge contact with low contact resistance, enabling carriers to be efficiently injected into the interlayer and transported in a parallel direction with low impedance along the conductive structure. The two-dimensional / quasi-two-dimensional semiconductor material interlayer in this invention actually undertakes the responsibility of high-speed carrier transport, thus substantially changing the carrier transport mechanism, allowing the carrier transport process to break free from the physical limitations of traditional metal materials, especially the size effect limitations exhibited by metals when the size is extremely small, thereby making higher density redistribution layer wiring possible.

[0018] (2) Compared with the previously mentioned solutions such as coating the copper layer with graphene, this invention selects to sandwich an in-situ grown two-dimensional or quasi-two-dimensional semiconductor thin layer inside the copper layer. By selecting semiconductor materials with good adhesion (bonding ability) to copper, such as zinc oxide and indium gallium zinc oxide, good mechanical bonding between layers can be ensured while improving conductivity, thereby ensuring the overall long-term reliability and weather resistance of the redistribution layer structure, so as to meet the reliability requirements of advanced packaging substrates, interposers and other structures.

[0019] (3) Compared with traditional solutions, the present invention avoids the problems of large-area preparation or transfer of two-dimensional materials such as graphene and high cost. It is compatible with existing mature micro-nano processing technology and adopts plasma-enhanced atomic layer deposition and other methods that are easy to realize large-scale preparation, have highly controllable process parameters and easy-to-obtain raw materials to directly deposit two-dimensional / quasi-two-dimensional semiconductor thin layers on the substrate. While reducing the cost required for process implementation, it makes the process parameters simpler and more controllable, which is conducive to achieving batch manufacturing with good consistency and even large-scale production, and meets the needs of large-scale production. Attached Figure Description

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] Figure 1 The diagram shows the steps in this invention.

[0022] Figure 2 This is a photograph of the actual object in Embodiment 1 of the present invention.

[0023] Figure 3 The image shown is an optical microscope image of Example 1, illustrating a local transmission line structure. Detailed Implementation

[0024] The present invention provides a more detailed description of an improved conductivity structure and preparation method based on an intermetallic semiconductor thin sandwich layer, with reference to the accompanying drawings, but this is not intended to limit the scope of the invention.

[0025] A conductivity modification structure based on intermetallic semiconductor thin sandwich is disclosed. This structure uses a substrate as the base carrier and the core consists of alternating stacks of metal-semiconductor thin layers and a patterned metal capping layer. By optimizing the interlayer structure and contact method, the conductivity performance is significantly improved. The structure includes a substrate, alternating stacks of metal-semiconductor thin layers, and a patterned metal capping layer stacked sequentially from bottom to top.

[0026] The substrate serves as the supporting foundation for the entire structure. Its materials include, but are not limited to, glass, silicon, resin, and ceramics. Its surface undergoes multiple cleaning processes to ensure the adhesion and growth quality of subsequent film deposition.

[0027] The alternating stacked metal-semiconductor thin layers form the core conductive functional layer of the structure. It is disposed above the substrate and includes at least one metal layer and one semiconductor thin layer, which are stacked alternately in the vertical direction to form a composite structure. After patterning, it forms a preset conductive structure pattern and a specific geometric structure with electrical signal transmission function.

[0028] The metal layer is preferably a titanium-copper (Ti-Cu) bilayer metal layer or a copper (Cu) monolayer metal layer, with the titanium layer having a thickness of 10-100 nm and the copper layer having a thickness of 10 nm-1 μm; the semiconductor thin layer is a two-dimensional or quasi-two-dimensional semiconductor layer, preferably a metal oxide or metal nitride semiconductor, and more preferably one of zinc oxide (ZnO) or indium gallium zinc oxide (IGZO) with a thickness of <10 nm.

[0029] The patterned metal capping layer covers the surface of the alternating metal-semiconductor thin-layer stack, and forms a good electrical connection with the edge of the cross-section or line of the semiconductor thin interlayer, creating a stable carrier injection channel, thereby improving the conductivity of the entire structure. This metal capping layer is preferably a copper metal layer with a thickness of 10 nm-1 μm.

[0030] The core advantage of this structure lies in the edge contact design between the metal capping layer and the semiconductor thin interlayer, which enables efficient injection of charge carriers from the metal to the semiconductor thin layer. At the same time, by means of the alternating stacking of the metal and semiconductor thin layers, structural stability and conductivity are balanced, and a transmission line structure with a linewidth and line spacing of no less than 4μm can be achieved.

[0031] A method for fabricating a conductivity-improved structure based on an intermetallic semiconductor thin sandwich layer includes the following steps: S01: Substrate cleaning process First, the substrate material compatibility is checked. A multi-step cleaning process is then used to remove oil, impurities, and oxide layers from the substrate surface to ensure the quality of subsequent film deposition. The specific process is as follows: S011, Basic Ultrasonic Cleaning: The substrate was ultrasonically cleaned sequentially with acetone, isopropanol, deionized water and ethanol. Each cleaning step was completed at room temperature using an ultrasonic cleaner with an ultrasonic power of 50-300W and an ultrasonic frequency of 20-80kHz. The cleaning time for each step was 5-30 minutes. After each cleaning step, the substrate was rinsed with the solvent of the next cleaning step to remove residual liquid. After all ultrasonic cleaning was completed, the substrate was dried with a nitrogen gun.

[0032] S012, Surface plasma cleaning: After ultrasonic cleaning and drying, the substrate is placed in an oxygen plasma cleaner to further clean residual impurities on the surface. The cleaning time is 2-10 minutes, the power is 50-300W, and the oxygen flow rate is 20-80sccm.

[0033] S02: Fabrication and Patterning of Alternating Metal-Semiconductor Thin Films On the cleaned substrate, metal layers and semiconductor thin layers are deposited sequentially to form an alternating stacked structure. This stack is then patterned to form a predetermined conductive structure pattern. The specific process is as follows: S021, Film deposition: The titanium-copper metal layer is preferably deposited by magnetron sputtering in an argon atmosphere; the two-dimensional semiconductor layers such as ZnO and IGZO are preferably deposited by atomic layer deposition and plasma-enhanced atomic layer deposition to ensure uniform film thickness and tight interlayer bonding.

[0034] S022, Graphical processing: Using physical or chemical methods, one or more layers of alternating metal-semiconductor thin films are spatially distributed to form a specific geometric shape. Specific implementation methods include, but are not limited to, three types of processes: (1) Subtractive process: First, the whole film is formed, and then the excess part is selectively removed, such as reactive ion etching (RIE), inductively coupled plasma etching (ICP), chemical etching, ablation, etc. (2) Additive manufacturing process: selective deposition of materials in a region is achieved with the help of photomasks, photoresist patterns, etc., such as lift-off, screen printing, transfer printing, inkjet printing, etc. (3) Modification process: The local properties of the material are changed by means of ion implantation, local oxidation and other methods to achieve the definition of the pattern.

[0035] S03: Fabrication of Patterned Metal Overlay A patterned metal capping layer is fabricated on the patterned surface of the alternating metal-semiconductor thin film stack, ensuring that it completely covers the structure obtained in step 2 and forms a good electrical connection with the edge of the semiconductor thin film sandwich, thus constructing a stable carrier injection channel. The specific process is as follows: S031, Metal capping layer deposition: The preferred method is to deposit a copper metal layer in an argon atmosphere using magnetron sputtering, with the thickness controlled between 10 nm and 1 μm. During the deposition process, it is ensured that the film is uniform, defect-free, and tightly bonded to the underlying stacked structure.

[0036] S032, Graphical processing: Using the same patterning process as in step S02, the metal overlay is patterned using the preferred peeling and floating method to ensure accurate coverage of the target area. The edge contact effect is optimized to avoid problems such as poor contact and obstructed carrier injection.

[0037] The following embodiments are provided based on the above-described method for fabricating a conductive improved structure based on an intermetallic semiconductor thin sandwich layer: Example 1: A conductivity-improved transport structure comprising a metal-quasi-two-dimensional zinc oxide (ZnO)-metal stack is fabricated on the surface of a glass substrate, as follows: Figure 1 As shown, the actual object is as follows Figure 2 As shown.

[0038] S01: The fused silica glass substrate was ultrasonically cleaned sequentially using acetone, isopropanol, deionized water, and ethanol. The ultrasonic power was 100W, the ultrasonic frequency was 40kHz, and each ultrasonic cleaning step lasted 15 minutes. After each ultrasonic cleaning step, the substrate was rinsed with the solvent for the next ultrasonic cleaning step to remove residual liquid. After all ultrasonic cleaning steps were completed, the substrate was dried with a nitrogen gun and then placed in an oxygen plasma cleaner to clean the surface. The oxygen flow rate was 40sccm, the power was 100W, and the treatment time was 10 minutes.

[0039] S02: The following films are sequentially deposited on a clean substrate surface: S021 and titanium adhesion layer were deposited by radio frequency magnetron sputtering in an argon atmosphere at room temperature. The chamber was evacuated to a background vacuum of 1.2 × 10⁻⁶. -3 After Pa, argon gas is introduced, and ignition is performed at a pressure of 8 Pa. Pre-sputtering and formal sputtering are carried out at a pressure of 0.4 Pa, with a sputtering power of 300W, a pre-sputtering time of 300s, and a sputtering thickness of 5nm. The substrate is rotated at an angular velocity of 6rpm to ensure uniform sputtering.

[0040] S022 and copper layers were deposited by radio frequency magnetron sputtering in an argon atmosphere at room temperature. The chamber was evacuated to a background vacuum of 1.2 × 10⁻⁶. -3 After Pa, argon gas is introduced, and ignition is performed at a pressure of 8 Pa. Pre-sputtering and formal sputtering are carried out at a pressure of 0.4 Pa. The sputtering power is 200W, the pre-sputtering time is 300s, and the sputtering reaches a thickness of 50nm. The substrate is rotated at an angular velocity of 6rpm to ensure uniform sputtering.

[0041] SO23 and zinc oxide layers were deposited using ALD and PEALD methods. The substrate was heated to and maintained at 150°C. Five cycles of ALD deposition were performed as a seed / copper protective layer, each cycle comprising the following steps: 1. Introduce diethylzinc (DEZ) with a pulse duration of 0.02s and an argon purging duration of 10s; 2. Introduce water vapor, pulse duration 0.02s, argon purging duration 15s.

[0042] Subsequently, the gas was purged with argon for 120 seconds to completely remove any remaining gas.

[0043] Then, multiple cycles of PEALD deposition were performed until the zinc oxide layer thickness was made up to 2 nm. Each cycle included the following steps: 1. Introduce diethylzinc, pulse duration 0.02s, argon purging duration 10s; 2. Introduce oxygen plasma with a pulse duration of 2 seconds, RF power of 150W, oxygen flow rate of 40 sccm, and argon purging time of 15 seconds.

[0044] This method balances the quality of the zinc oxide thin layer and the aforementioned deposited metal layer. Before growing zinc oxide using the PEALD method, a layer of zinc oxide is first deposited on the copper layer surface using the conventional ALD method to provide interface protection, which can significantly reduce the degree of oxidation of the copper layer by oxygen plasma.

[0045] S024 and copper layers were deposited by radio frequency magnetron sputtering in an argon atmosphere at room temperature. The chamber was evacuated to a background vacuum of 1.2 × 10⁻⁶. -3 After Pa, argon gas is introduced, and ignition is performed at a pressure of 8 Pa. Pre-sputtering and formal sputtering are carried out at a pressure of 0.4 Pa. The sputtering power is 200W, the pre-sputtering time is 300s, and the sputtering reaches a thickness of 50nm. The substrate is rotated at an angular velocity of 6rpm to ensure uniform sputtering.

[0046] After all the aforementioned film layers were grown, the film layers were patterned using a combination of photolithography and ion beam etching (IBE). A photoresist pattern with a thickness of approximately 1 μm was fabricated on the surface of the film layer using photolithography. Subsequently, unprotected excess areas were etched away using ion beam etching. The working gas was argon, the beam current voltage was 400 V, the ion beam acceleration voltage was 100 V, and the chamber pressure was 1 × 10⁻⁶. -2 Pa, substrate rotation speed of 10 rpm to ensure uniform etching, substrate tilt angle of 45° to reduce secondary deposition of etched material on the structure sidewalls. The etching endpoint is when the aforementioned film layer is completely etched and the quartz substrate is exposed. After etching, the substrate is soaked in acetone to remove excess photoresist, then cleaned and dried.

[0047] S03: Fabricate a metal capping layer pattern on the surface of the metal-semiconductor thin-film-metal stack structure created in the previous step. First, a double-layer adhesive pattern for peeling and detachment is fabricated on the substrate surface using photolithography. The bottom layer is a non-photosensitive LOR-10A adhesive layer with a thickness of about 1 μm, and the top layer is a positive AR-P 5350 adhesive layer with a thickness of about 1 μm. After development, the adhesive layer as a whole exhibits an undercut structure, which can reduce the accumulation of subsequent deposited metal layers on the sidewalls of the adhesive layer, thereby optimizing the morphology of the metal capping layer and improving the peeling efficiency.

[0048] Subsequently, the following two metal layers were deposited on the substrate surface by radio frequency magnetron sputtering under a room temperature argon atmosphere as a metal capping layer: Copper layer: The chamber was evacuated to a background vacuum of 1.2 × 10⁻⁶. -3 After Pa, argon gas is introduced, and ignition is performed at 8 Pa pressure. Pre-sputtering and formal sputtering are carried out at 0.4 Pa pressure, with a sputtering power of 200W, a pre-sputtering time of 300s, and a sputtering thickness of 100nm. The substrate is rotated at an angular velocity of 6rpm to ensure uniform sputtering. Titanium adhesion layer: The chamber was evacuated to a base vacuum of 1.2 × 10⁻⁶. -3 After Pa, argon gas is introduced, and ignition is performed at a pressure of 8 Pa. Pre-sputtering and formal sputtering are carried out at a pressure of 0.4 Pa. The sputtering power is 300W, the pre-sputtering time is 300s, and the sputtering reaches a thickness of 5nm. The substrate is rotated at an angular velocity of 6rpm to ensure uniform sputtering.

[0049] The substrate was immersed in acetone until the excess metal layer and photoresist were completely removed. The substrate was then cleaned to obtain a conductivity-improved transport structure containing a metal-quasi-two-dimensional zinc oxide (ZnO)-metal stack.

[0050] It should be noted that the metal capping layer in step S03 should adequately cover the multilayer stacked structure described in step S02, especially the edges of the stacked structure, to create an edge contact structure at the edge of the semiconductor thin layer. This ensures that charge carriers can be injected from the metal to the edge of the semiconductor thin layer, thereby improving the overall conductivity of the conductive structure. Based on the aforementioned process, this embodiment can achieve a transmission line structure with a linewidth / spacing not inferior to 4μm / 4μm. The morphology of one such transmission line structure under an optical microscope is shown below. Figure 3 As shown.

[0051] Example 2: A conductivity-improved transport structure comprising a metal-quasi-two-dimensional indium gallium zinc oxide (IGZO) multilayer stack is fabricated on the surface of a glass substrate. By controlling the composition of IGZO, the characteristics of the semiconductor thin layer can be regulated, thereby further optimizing the conductivity performance of this improved transport structure.

[0052] S01: The same fused silica glass substrate as in Example 1 was used, and the ultrasonic cleaning and oxygen plasma cleaning processes were the same as in Example 1.

[0053] S02: Deposit the following film layer on a clean substrate surface.

[0054] S021 and titanium adhesion layer were deposited by radio frequency magnetron sputtering in an argon atmosphere at room temperature. The chamber was evacuated to a background vacuum of 1.2 × 10⁻⁶. -3 After Pa, argon gas is introduced, and ignition is performed at a pressure of 8 Pa. Pre-sputtering and formal sputtering are carried out at a pressure of 0.4 Pa, with a sputtering power of 300W, a pre-sputtering time of 300s, and a sputtering thickness of 5nm. The substrate is rotated at an angular velocity of 6rpm to ensure uniform sputtering.

[0055] S022 and copper layers were deposited by radio frequency magnetron sputtering in an argon atmosphere at room temperature. After the chamber was evacuated to a base vacuum of 1.2 × 10⁻³ Pa, argon gas was introduced and ignition was performed at a pressure of 8 Pa. Pre-sputtering and formal sputtering were carried out at a pressure of 0.4 Pa, with a sputtering power of 200 W, a pre-sputtering time of 300 s, and a sputtering thickness of 50 nm. The substrate was rotated at an angular velocity of 6 rpm to ensure uniform sputtering.

[0056] S023 and IGZO layers were deposited by radio frequency magnetron sputtering in a room temperature argon-oxygen mixed atmosphere. After the chamber was evacuated to a base vacuum of 1.2 × 10⁻³ Pa, argon gas was introduced, and ignition was performed at a pressure of 8 Pa. Pre-sputtering and formal sputtering were then carried out at a pressure of 0.4 Pa, with a sputtering power of 50 W and a pre-sputtering time of 300 s, sputtering to a thickness of 5 nm. The substrate was rotated at an angular velocity of 6 rpm to ensure uniform sputtering. By adjusting parameters such as the original composition of the IGZO target, the composition of the argon-oxygen mixed atmosphere, and the sputtering power, the composition and oxygen vacancy density of the sputtered IGZO thin layer can be controlled, thereby regulating its conductivity and its contact characteristics with the metal.

[0057] It should be noted that, in this embodiment, when growing this stacked structure, a titanium metal layer should first be grown as an adhesion layer between the substrate and the subsequent deposited layers. Then, copper and IGZO layers are grown alternately, with the copper layer as the topmost layer to protect the underlying IGZO layer. The above magnetron sputtering process can be completed sequentially and alternately at multiple sputtering targets in the same chamber, thereby avoiding frequent removal of the substrate from the chamber and preventing the external environment from affecting the deposited film.

[0058] After all the aforementioned film layers have been grown, the film layers are patterned using a combination of photolithography and ion beam etching (IBE), with the process and conditions described in step 2. When etching thicker stacked layers, the photoresist thickness or the post-baking time of the photoresist can be appropriately increased to improve the etching resistance of the resist layer.

[0059] S03: Create a metal overlay pattern on the surface of the multi-layered structure made in the previous step, with the same process and conditions as in Example 1.

[0060] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A conductivity-improved structure based on an intermetallic semiconductor thin sandwich layer, characterized in that: It includes a substrate stacked from bottom to top, alternating layers of metal-semiconductor thin films, and a patterned metal capping layer; The alternating stacking of metal-semiconductor thin layers forms the core conductive functional layer of the structure, which is then patterned to form a preset conductive structure pattern. The patterned metal overlay and the edge of the semiconductor thin interlayer form a good electrical connection, creating a carrier injection channel.

2. A method for fabricating a conductivity-improved structure based on an intermetallic semiconductor thin sandwich layer, characterized in that: Includes the following steps: S01: Substrate cleaning process, which uses a multi-step cleaning process to remove oil, impurities and oxide layer from the substrate surface; S02: Preparation and patterning of alternating metal-semiconductor thin film stacks: metal layers and semiconductor thin films are deposited sequentially on a cleaned substrate to form an alternating stack structure, and then the stack is patterned. S03: Fabrication of patterned metal capping layer. A patterned metal capping layer is fabricated on the patterned surface of alternating stacked layers to ensure good electrical connection with the edge of the semiconductor thin interlayer.

3. The improved conductivity structure according to claim 1, characterized in that: The substrate is made of at least one of glass, silicon, resin, and ceramic, and the substrate surface undergoes a multi-step cleaning process to ensure the adhesion and growth quality of subsequent film deposition.

4. The improved conductivity structure according to claim 1, characterized in that: The metal-semiconductor thin-layer alternating stack includes at least one metal layer and one semiconductor thin layer, and the metal and semiconductor thin layers are alternately stacked in the vertical direction to form a composite structure; The conductive structure pattern is a specific geometric structure with electrical signal transmission function.

5. The improved conductivity structure according to claim 4, characterized in that: The metal layer is a titanium-copper bilayer metal layer, with the titanium layer having a thickness of 10-100nm and the copper layer having a thickness of 10nm-1μm; Alternatively, a single copper metal layer with a thickness of 10nm-1μm.

6. The improved conductivity structure according to claim 4, characterized in that: The semiconductor thin layer is a two-dimensional or quasi-two-dimensional semiconductor layer, preferably a metal oxide or metal nitride semiconductor, and more preferably a zinc oxide or indium gallium zinc oxide with a thickness of <10 nm.

7. The improved conductivity structure according to claim 1, characterized in that: The patterned metal overlay is a copper metal layer with a thickness of 10nm-1μm; The edge of the semiconductor thin interlayer is a cross-section or line of the semiconductor thin interlayer.

8. The improved conductivity structure according to claim 1, characterized in that: This structure enables transmission line structures with linewidth and spacing no worse than 4μm.

9. The preparation method according to claim 2, characterized in that: Step S01 specifically includes: S011. Basic ultrasonic cleaning: The substrate is ultrasonically cleaned sequentially with acetone, isopropanol, deionized water and ethanol. Each cleaning step is completed at room temperature by an ultrasonic cleaner with an ultrasonic power of 50-300W, an ultrasonic frequency of 20-80kHz and a single cleaning time of 5-30min. After each cleaning step, rinse the substrate with the solvent of the next cleaning step to remove residual liquid. After all cleaning is completed, blow the substrate dry with a nitrogen gun. S012. Surface plasma cleaning: Place the dried substrate in an oxygen plasma cleaner for 2-10 minutes, with a power of 50-300W and an oxygen flow rate of 20-80 sccm.

10. The preparation method according to claim 2, characterized in that: In step S02, the metal layer is deposited by magnetron sputtering under an argon atmosphere, and the two-dimensional semiconductor layer is deposited by atomic layer deposition and plasma-enhanced atomic layer deposition. In step S03, the metal coating is deposited in an argon atmosphere using magnetron sputtering, and the patterning process is the same as in step S02, preferably using the stripping and floating method.

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