Chip high-precision mounting method and structure based on panel-level patterned electroplating

Abstract

The application belongs to the technical field of semiconductor packaging and relates to a chip high-precision mounting method and structure based on panel-level patterned electroplating, which comprises the following steps: providing a panel-level substrate and forming a conductive seed layer on the surface of the panel-level substrate; coating photoresist on the conductive seed layer, performing high-precision patterning through panel-level step-by-step exposure or laser direct imaging to form electroplating windows corresponding to chip pad positions one by one; in the electroplating windows, selective electroplating of solder bumps is performed through a vertical continuous electroplating mode, and the range of the height of the solder bumps on the entire panel after electroplating is controlled to be less than or equal to ±3 microns; the photoresist is removed, and the conductive seed layer not covered by the solder bumps is etched; the chip pads are aligned with the solder bumps, reflow soldering is performed, and chip mounting is realized. The application improves the precision, eliminates the bridging phenomenon, has excellent coplanarity, low cost, large size, high material utilization rate and strong process flexibility.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a high-precision chip mounting method and structure based on panel-level patterned electroplating. Background Technology

[0002] With the continuous shrinking of integrated circuit feature sizes and the explosive growth in demand for heterogeneous integration, chip interconnect spacing has gradually evolved from the traditional 200μm and above to 100μm, 50μm, and even below 30μm. Against this backdrop, traditional chip mounting technology faces the following three major technical bottlenecks: First, the precision limit. The alignment accuracy of traditional solder paste printing technology is usually ±10μm to ±30μm, and the placement accuracy of ball-mounting technology is about ±10μm. However, in submicron interconnect scenarios (pitch ≤ 50μm), the total positional deviation after mounting must be controlled within ±5μm, otherwise it will directly lead to short circuits or open circuits.

[0003] Second, bridging and void failure. Solder paste can collapse and overflow during reflow soldering, which can easily cause bridging between adjacent solder joints under fine-pitch conditions. At the same time, incomplete evaporation of flux in the solder paste can form voids, reducing the mechanical strength and electrical reliability of the solder joints.

[0004] Third, the cost is high. Although wafer-level electroplating bump technology can achieve an accuracy of ±2~5μm, it must be bonded to silicon process lines, requiring expensive sputtering, photolithography, and electroplating equipment. Furthermore, the substrate size is limited to φ≤300mm, resulting in extremely high per-wafer process costs. Traditional panel-level processes (such as LCD panel manufacturing) have advantages in terms of large size and low cost, but they have not yet been systematically applied to high-precision chip mounting.

[0005] Therefore, there is an urgent need for a chip mounting method and structure that can balance submicron-level mounting accuracy, large-size panel-level production efficiency, and low overall cost. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a high-precision chip mounting method based on panel-level patterned electroplating, employing the following technical solution, including the following steps: S1, a panel-level substrate is provided, and a conductive seed layer is formed on the surface of the panel-level substrate, wherein the dimensions M×N of the panel-level substrate satisfy M≥500mm and N≥500mm; S2, Photoresist is coated on the conductive seed layer, and high-precision patterning is performed by panel-level step-out exposure or direct laser imaging to form an electroplating window that corresponds one-to-one with the chip pad position. The photolithography alignment accuracy is ±2μm~±5μm. S3, within the electroplating window, a vertical continuous electroplating method is used to selectively electroplat solder bumps, and the range of bump height on the entire panel after electroplating is controlled to be ≤±3μm; S4, Remove the photoresist and etch the conductive seed layer that is not covered by solder bumps; S5, align the chip pads with the solder bumps, and perform reflow soldering to achieve chip mounting.

[0007] Preferably, the relationship between the photolithography alignment accuracy and the final total mounting deviation in step S2 satisfies the following formula: , where σ litho For photolithography alignment accuracy, σ plating For electroplating offset, σ self_align For the reflux self-alignment correction, the final σ total ≤ ±5μm.

[0008] Preferably, the height of the solder bump in step S3 is quantitatively controlled by a formula: J avg Average current density during the main growth phase, t main Electroplating time during the main growth stage, η is the current efficiency, M is the molar mass of the solder alloy, n is the electron transfer number, F is the Faraday constant, ρ is the solder density, and H... seed ΔH represents the seed layer thickness. nuc The height increment contributed to the initial nucleation stage.

[0009] Preferably, the vertical continuous electroplating in step S3 employs dual independent control of a transverse rectifier and a longitudinal rectifier, and uses segmented current density: 0.5 A / dm in the initial nucleation segment. 2 Main growth stage 2~4 A / dm 2 Leveling section 0.5 A / dm 2 .

[0010] To address the aforementioned technical problems, this invention also provides a high-precision chip mounting structure based on panel-level patterned electroplating, employing the following technical solution, including: A panel-level substrate with dimensions M×N satisfying M≥500mm and N≥500mm; Multiple seed layer residual regions are located on the upper surface of the panel-level substrate. Each seed layer residual region is an independent metal island with a thickness of 50nm~300nm. The electroplated solder bump array located above the seed layer residual area has a diameter D of 10μm ≤ D ≤ 150μm and a height H of 10μm ≤ H ≤ 80μm. The pitch P of adjacent bumps is ≤ 50μm, and the height difference of each bump on the same panel is ≤ ±3μm. At least one chip has chip pads distributed on its lower surface that correspond one-to-one with the array of electroplated solder bumps. An intermetallic compound layer located between the chip pad and the electroplating bump, and between the electroplating bump and the seed layer residual area, is Cu6Sn5, Cu3Sn, or (Ni,Cu)3Sn4, with a thickness of 1~5μm. And optionally, a bottom filler layer located between the chip and the substrate, the material of which is an epoxy resin-based filler.

[0011] Preferably, the position of the electroplated solder bump is defined by the photolithographic pattern, and the deviation σ between its center coordinates and the design coordinates is... litho Satisfying ±2μm ≤ σ litho ≤ ±5μm, and this deviation is not amplified by reflow self-alignment, but is fixed from the source.

[0012] Preferably, the self-aligning force generated by the molten solder during the reflow soldering process satisfies the formula: , where γ is the surface tension of the molten solder, θ is the wetting angle, and Δx is the initial offset between the center of the chip pad and the center of the bump before reflow. This self-aligning force can correct the residual offset of Δx ≤ ±2μm.

[0013] Preferably, the upper surface of the substrate has a stepped pad distribution area, and the electroplated solder bumps on different steps have different heights, the height difference being in the range of 5μm~100μm, and is achieved by adjusting the electroplating time of the corresponding area, without the need for a stepped steel mesh.

[0014] Preferably, the upper and lower surfaces of the substrate are provided with an array of electroplated solder bumps, and the bump material composition of the upper and lower surfaces can be the same or different, so as to realize double-sided chip mounting.

[0015] Preferably, the bottom filling layer completely fills all gaps between the lower surface of the chip and the upper surface of the substrate and wraps all bumps. Its thickness is equal to the height of the bumps plus the total thickness of the intermetallic compound layer. There are no voids with a diameter greater than 10 μm inside the filling layer.

[0016] Compared with the prior art, the present invention has the following main advantages: (1) Improved accuracy: photolithography alignment accuracy ±2~5μm, total mounting deviation ≤ ±5μm, supporting ultra-fine pitch interconnects ≤50μm, while traditional solder paste printing... With a pitch of ≥ ±15μm, it is impossible to stably produce products with a pitch of <100μm.

[0017] (2) Completely eliminate bridging: The solder is physically confined by the photolithographic pattern, and there is no overflow after reflow. The bridging rate is reduced from 1~5% in traditional technology to 0%.

[0018] (3) Excellent coplanarity: the height difference of electroplated bumps is ≤ ±3μm, and the rate of poor soldering is reduced from 3~8% in traditional solder paste printing to below 0.1%.

[0019] (4) Features low cost and large size: The number of chips produced in a single batch at the panel level (≥600mm×600mm) is more than 5 times that of the wafer level (φ300mm, area of ​​about 706cm²). The equipment investment is only about 40% of that of the wafer level electroplating line, and the manufacturing cost of a single chip is reduced by 60~70%.

[0020] (5) High material utilization: the utilization rate of selective electroplating materials is >95%, while the utilization rate of solder paste printing is only 50~70% (wasted on the stencil), and the saving of precious metals such as gold and silver is significant.

[0021] (6) High process flexibility: bumps of different heights and alloy compositions can be achieved on the same panel by adjusting electroplating parameters (different current densities or times in different areas), which can meet the connection requirements of different chips in heterogeneous integration without the need for additional photomasks or steel mesh. Attached Figure Description

[0022] To more clearly illustrate the solutions in this invention, the accompanying drawings used in the description of the embodiments of this invention will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a flowchart of an embodiment of the chip high-precision mounting method based on panel-level patterned electroplating of the present invention; Figure 2 This is a schematic diagram of the pads for a unit component, indicating the pad size L; Figure 3 To simplify the soldering substrate structure, the substrate pads are marked; Figure 4 A schematic diagram of the cross-section of the weldable metal layer processed using traditional techniques; Figure 5 This is a schematic diagram of a traditional reflux self-alignment process; Figure 6 The pad dimensions for passive component 008004 are specified (L≤100μm, C≤200μm). Figure 7 A schematic diagram of the pad opening size E in the field of ultra-fine pitch pads; Figure 8 This is a schematic diagram of the pad spacing F in the field of ultra-fine pitch. Figure 9Schematic diagram of fine-pitch BGA (a≤300μm); Figure 10 Schematic diagram for wafer-level carrier substrate with a size φ≤300mm; Figure 11 This is a schematic diagram of the panel-level carrier with a size ≥500mm×500mm used in this invention; Figure 12 This is a schematic diagram of the solder position deviation Δx; Figure 13 This is an equivalent diagram of the component position deviation after reflow. Figure 14 This is a diagram illustrating a tombstone defect caused by uneven solder paste printing. Figure 15 This is a schematic diagram illustrating warping defects caused by uneven solder paste printing. Figure 16 This is a schematic diagram of a stepped pad structure (different heights on the same side); Figure 17 This is a schematic diagram of the traditional stepped steel mesh processing method; Figure 18 This is a schematic diagram of the double-sided pad mounting structure of the present invention. Detailed Implementation

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects and not to describe a particular order.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0027] Example 1 Figure 1This is a flowchart of an embodiment of the high-precision chip mounting method based on panel-level patterned electroplating according to the present invention. The high-precision chip mounting method based on panel-level patterned electroplating provided by the present invention, such as... Figure 1 As shown, the specific steps include: S1, a panel-level substrate is provided, and a conductive seed layer is formed on the surface of the panel-level substrate, wherein the dimensions M×N of the panel-level substrate satisfy M≥500mm and N≥500mm.

[0028] In this embodiment, step S1 further includes the following steps: S11, Select panel-level carrier.

[0029] Select a rectangular panel with dimensions M×N, where M≥500mm and N≥500mm. Typical dimensions are 600mm×600mm, 610mm×610mm or larger (e.g., 800mm×800mm).

[0030] Panel materials can be selected from glass (low coefficient of thermal expansion, CTE≈3~5 ppm / K), organic resin substrate (FR-4, BT, ABF, CTE≈10~20 ppm / K) or metal core substrate (Cu-Invar-Cu, CTE adjustable).

[0031] The purpose of step S11 is to allow large-size panels to process hundreds to thousands of chips simultaneously in a single process, thereby reducing the manufacturing cost per chip.

[0032] S12, Cleaning and Decontamination.

[0033] Plasma cleaning (O2 or Ar atmosphere, power 500W~1500W, time 1~3 minutes) or chemical cleaning (alkaline cleaning solution and deionized water rinsing) can be used.

[0034] After cleaning, the contact angle of the panel surface should be ≤15° to enhance the adhesion of subsequent photoresist.

[0035] The purpose of step S12 is to remove oil, particles and native oxide layer to prevent photoresist bubbling or pinhole defects during electroplating.

[0036] S13, depositing a conductive seed layer.

[0037] A continuous, uniform conductive seed layer is formed on the surface of the panel by physical vapor deposition (PVD, DC magnetron sputtering) or chemical plating (electro-free copper plating).

[0038] The seed layer material uses Cu (pure copper) or Ti / Cu (titanium / copper double layer, with Ti as a barrier layer and Cu as a conductive layer), with a total thickness ranging from 50nm to 300nm, and a typical thickness of 150nm.

[0039] Sputtering process parameters: Base vacuum ≤ 5 × 10⁻⁶ -5 Pa, working air pressure 0.2~0.5 Pa, DC power density 5~10 W / cm³ 2 .

[0040] The function of step S13 is to: use the seed layer as a conductive path for the electroplating cathode so that the current can be evenly distributed to the entire panel surface.

[0041] The formula for calculating the minimum thickness of the seed layer is: (Formula 1).

[0042] in: Seed layer thickness (unit: nm).

[0043] Electroplating current density (unit: A / dm) 2 Typical value range is 1~5 A / dm 2 ).

[0044] Total electroplating time (unit: seconds).

[0045] Current efficiency (dimensionless, typically 0.90~0.98 for acidic copper plating systems).

[0046] Molar mass of electroplated metal (unit: g / mol, Cu is 63.55, Sn is 118.71).

[0047] Electron transfer number (Cu) 2+ +2e - →Cu, n=2; Sn 2+ +2e - →Sn, n=2).

[0048] Faraday constant, 96485 C / mol.

[0049] Density of electroplated metal (unit: g / cm³) 3 (Cu is 8.96, Sn is 7.29).

[0050] This formula, based on Faraday's law of electrolysis, specifies the minimum thickness required to ensure the seed layer does not melt or experience excessive voltage drop during the entire electroplating process. If the seed layer thickness is lower than this calculated value, its resistance will be too high, leading to a significant difference in current density between the panel edge and center, resulting in uneven height of the electroplated bumps. If it is higher than this value, it increases material costs and the difficulty of subsequent etching. This formula allows for the optimization of the seed layer thickness within the range of 100~200nm, achieving a balance between conductivity and economy.

[0051] The purpose of step S1 is to provide a large-size, high-flatness, and low-cost carrier platform through panel-level substrate preparation and pretreatment, laying the foundation for subsequent high-precision patterning and uniform electroplating.

[0052] S2, Photoresist is coated on the conductive seed layer, and high-precision patterning is performed by panel-level step-through exposure or laser direct imaging to form electroplating windows that correspond one-to-one with the chip pad positions. The photolithography alignment accuracy is ±2μm~±5μm.

[0053] In this embodiment, step S2 further includes the following steps: S21, coated with photoresist.

[0054] A layer of positive or negative photoresist is coated onto the seed layer using spin coating (suitable for small-sized panels) or slot coating (suitable for large-sized panels).

[0055] The photoresist thickness is selected from 5μm to 50μm, depending on the target bump height. For a bump height of 30μm, a negative photoresist with a thickness of 25μm is selected.

[0056] After coating, bake on a hot plate at 90~120℃ for 1~3 minutes to evaporate the solvent.

[0057] The purpose of step S21 is to form a uniform photosensitive dielectric layer, providing a process basis for subsequent exposure and development.

[0058] S22, Alignment and Exposure.

[0059] Using a panel-level stepper or a high-precision LDI exposure machine, align the photomask pattern with the panel using the pre-made alignment marks (cross marks or square marks) on the panel as a reference.

[0060] The alignment accuracy of a single field of view in a stepper exposure machine can reach ±1μm, and the alignment accuracy of whole-board splicing is ±2~5μm. LDI does not require a photomask and uses direct laser writing, with an alignment accuracy of ±3~5μm.

[0061] The exposure light source is deep ultraviolet light with i-line (365nm), g-line (436nm) or shorter wavelengths.

[0062] The exposure energy is determined according to the photoresist type, ranging from 80 to 200 mJ / cm. 2 .

[0063] The purpose of step S22 is to accurately transfer the layout pattern of the chip pads onto the photoresist. The pattern position error directly determines the final bump position error.

[0064] S23, Development.

[0065] Use tetramethylammonium hydroxide (TMAH) or KOH-based developer to immerse or spray at 23-25°C for 60-120 seconds.

[0066] For positive photoresist, the exposed areas dissolve to form windows; for negative photoresist, the unexposed areas dissolve.

[0067] The aperture size E after development ranges from 10μm to 200μm, corresponding to the pad size of different chips.

[0068] The purpose of step S23 is to remove the photoresist inside the electroplating window, expose the seed layer below, and allow the electroplating current to pass only through the window area.

[0069] S24, post-baking and hardening film.

[0070] Bake in an oven or on a hot plate at 120-150℃ for 2-5 minutes.

[0071] The purpose of step S24 is to further improve the cross-linking degree or density of the photoresist, and enhance its resistance to electroplating solution corrosion and high temperature resistance.

[0072] The formula relating graphical alignment accuracy to the final total mounting deviation is:

[0073] (Formula 2).

[0074] in: : Total positional deviation after final chip mounting (unit: μm). This value is the root mean square sum, representing the statistical distance between the center of the solder bump and the center of the chip pad.

[0075] Photolithography alignment accuracy, i.e., the deviation between the center of the photoresist window and the designed position, is ±2~5μm. This is a key factor in accuracy control in this invention.

[0076] The deviation in bump growth position caused by asymmetrical electric field distribution or local current density differences during electroplating is ≤±1μm. Thanks to the uniform electric field design of VCP, this deviation is extremely small.

[0077] The self-alignment correction caused by the surface tension of the melted solder during reflow soldering. Its value is negative (correction effect), with a typical range of ±2μm.

[0078] This formula reveals the root-square superposition law of total mounting accuracy. In traditional techniques, It does not exist (because there is no photolithography step). The placement accuracy corresponds to solder paste printing or ball placement (±10~30μm). Same. Therefore, tradition ≥ 10μm. This invention will... As the dominant term (±2~5μm), the other two terms are much smaller than it, making ≤ ±5μm, thus achieving submicron-level interconnection. This formula is also the core mathematical expression that distinguishes this invention from existing technologies.

[0079] The purpose of step S2 is to use a panel-level stepper or high-precision LDI (laser direct imaging) equipment to form electroplating windows on the seed layer that correspond one-to-one with the chip pad positions, thus defining the final precision of the mounting process from the source.

[0080] S3, within the electroplating window, a vertical continuous electroplating method is used to selectively electroplat solder bumps, controlling the range of bump height on the entire panel after electroplating to be ≤±3μm.

[0081] In this embodiment, step S3 further includes the following steps: S31, Electroplating solution preparation and control.

[0082] Prepare the appropriate electroplating solution according to the required solder composition: Pure Sn: Tin Methylsulfonate (MSA) system, Sn 2+ Concentration 40~80 g / L.

[0083] SnAg alloy: Silver ions (in the form of potassium silver cyanide or silver nitrate) are added to the Sn electroplating solution, Ag... + Concentration 0.5~2g / L.

[0084] SnCu alloy: with added copper ions, Cu 2+ Concentration 0.3~1 g / L.

[0085] The temperature of the electroplating solution should be controlled at 20~40℃ (typical value 30℃), and the pH value should be controlled at 3.5~5.5 (adjusted using nitric acid or ammonia).

[0086] Add appropriate amounts of additives (leveling agents, brighteners, inhibitors), such as gelatin and polyethyleneimine, at a concentration of 50-200 ppm.

[0087] The purpose of step S31 is to ensure a stable solder deposition rate, fine grains, and a smooth surface.

[0088] S32, Vertical Continuous Plating (VCP).

[0089] The panel is vertically immersed in the electroplating bath, with the cathode clamping point contacting the seed layer at the edge of the panel, and the anode using an insoluble anode (such as a platinum-plated titanium mesh or an iridium-tantalum coated titanium mesh).

[0090] The system employs dual independent control of the horizontal rectifier and the vertical rectifier. The horizontal rectifier controls the main electric field between the anode and cathode, while the vertical rectifier assists in compensating for the current density difference between the upper and lower areas of the panel.

[0091] The electroplating solution circulation flow rate is set to 2~5 L / min, and a filtration system (pore size 5~10μm) is used to remove suspended particles.

[0092] The purpose of step S32 is to ensure that the current density distribution is uniform on large-size panels (600mm height) and avoid edge effects.

[0093] S33, segmented current-controlled electroplating.

[0094] First stage (initial nucleation stage): Current density 0.5 A / dm 2 The time is 10 seconds. During this stage, the low current density is conducive to the formation of a large number of uniform crystal nuclei, avoiding localized preferential growth caused by high current.

[0095] Second stage (main growth stage): Current density 2~4 A / dm 2 (Typical value 3 A / dm²), the time is calculated using Formula 3 based on the target height. Solder is deposited at a higher rate during this stage to improve production efficiency.

[0096] Phase 3 (smoothing section): Current density drops to 0.5 A / dm 2 The time is 5 seconds, which makes the top of the bumps tend to be flat, improving the contact uniformity of subsequent mounting.

[0097] The purpose of step S33 is to achieve high growth rate, low porosity and good surface morphology simultaneously through segmented current control.

[0098] S34, Electroplating thickness variation control.

[0099] By optimizing the anode shape (contouring anode), adding auxiliary cathode shielding baffles, and adjusting panel rotation or oscillation, the electroplating thickness difference within a 600mm range of the panel can be ≤±3μm.

[0100] Thickness range is defined as: Statistics were collected from multiple measurement points (≥25 points) across the entire board.

[0101] The purpose of step S34 is to ensure that all bumps contact and melt synchronously after chip mounting, which directly determines the solder joint failure rate.

[0102] The formula relating the height of electroplated bumps to process parameters is: (Formula 3).

[0103] in: : The final height of the solder bump after electroplating (unit: μm).

[0104] Average current density during the main growth stage (unit: A / dm³) 2 ).

[0105] Electroplating time during the main growth stage (unit: s).

[0106] Current efficiency (dimensionless, 0.92~0.96 for Sn-based systems).

[0107] Molar mass of solder alloy (unit: g / mol, 118.71 for pure Sn, and calculated as a weighted average for Sn96.5Ag3.5).

[0108] Electron transfer number (Sn) 2+ / Sn takes 2).

[0109] Faraday constant, 96485 C / mol.

[0110] Solder density (unit: g / cm³) 3 Sn is 7.29, and SnAg is approximately 7.38.

[0111] Seed layer thickness (unit: μm, usually in the range of 0.05~0.3μm, negligible relative to the height of the bumps but retained in the formula).

[0112] The height increment contributed during the initial nucleation stage is typically 0.5~1.5 μm.

[0113] This formula establishes the electroplating process parameters ( , ) and convex point geometry ( The quantitative relationship between ( ) and ( ). In actual production, first determine the required ( ). (e.g., 30μm), and then set according to the electroplating solution system and equipment capabilities. (e.g., 3 A / dm) 2 ), then we can reverse the process. This allows for precise control of the bump height. Since the electroplating rate fluctuates slightly with cathode polarization and additive concentration, it is adjusted periodically in practice through measurements and corrections. To ensure high consistency. The formula also reveals the influence of The physical factors of the deposits are as follows: the larger the molar mass, the smaller the density, and the higher the current efficiency, the more metal will be deposited and the higher the bump will be for the same amount of electricity.

[0114] The purpose of step S3 is to selectively grow solder metal within the window defined by the photoresist through electrochemical deposition to form a highly consistent, regularly shaped, and void-free bump array.

[0115] S4, remove the photoresist and etch the conductive seed layer that is not covered by solder bumps.

[0116] In this embodiment, step S4 further includes the following steps: S41, remove glue.

[0117] Soak in N-methylpyrrolidone (NMP) or 2-5% KOH aqueous solution at 50-80°C for 5-10 minutes, while simultaneously agitating with ultrasound (frequency 40-80 kHz).

[0118] For negative photoresists, a special photoresist remover (such as a mixture of propylene glycol methyl ether acetate and monoethanolamine) can be used.

[0119] After removing the adhesive, rinse off any residue using a high-pressure spray of deionized water (pressure 0.3~0.5 MPa).

[0120] The purpose of step S41 is to completely strip away the photoresist, exposing the seed layer region covered by it.

[0121] S42, Seed layer etching.

[0122] Selective chemical etching of the exposed seed layer was performed using a rapid etching solution. For the Cu seed layer, sodium persulfate (Na2S2O8, concentration 100~200 g / L) or a nitric acid / hydrogen peroxide system (HNO3: H2O2: H2O = 1:1:5, volume ratio) was used.

[0123] The etching time is determined based on the seed layer thickness and etching rate. For example, for a 150 nm Cu layer, it takes about 30 to 60 seconds in sodium persulfate.

[0124] Endpoint detection: Monitor the resistance value of the panel surface during the etching process. When the resistance jumps from a low resistance state to a high resistance state (>1MΩ), it indicates that the continuous seed layer has been removed.

[0125] The purpose of step S42 is to retain only the seed layer directly below the bump that is covered by the bump (this part is protected by the bump and does not come into contact with the etching solution), and completely remove the seed layer in the remaining areas, thereby blocking the leakage current path between different bumps.

[0126] S43, Cleaning and Drying.

[0127] Ultrasonic cleaning with deionized water 3 times, 2 minutes each time.

[0128] Finally, use a spin dryer or nitrogen purging to dry, and dry in an 80°C oven for 30 minutes.

[0129] The purpose of step S43 is to remove residual etching solution and ionic contaminants to ensure surface cleanliness.

[0130] The purpose of step S4 is to remove the residual photoresist after electroplating and selectively remove the seed layer not covered by the bumps to prevent short circuits between different bumps through the seed layer.

[0131] S5, align the chip pads with the solder bumps, and perform reflow soldering to achieve chip mounting.

[0132] In this embodiment, step S5 further includes the following steps: S51, flux coating.

[0133] The dip-dip method is used: the bump array is immersed in a flux film (approximately 10-20 μm thick) so that a layer of flux is uniformly adhered to the surface of each bump.

[0134] Alternatively, a spraying method can be used: selectively spray flux onto the protruding points using a piezoelectric nozzle.

[0135] The flux used is a no-clean type (rosin-based or low-residual organic acid-based) with a solid content of 5-15%.

[0136] The purpose of step S51 is to remove the natural oxide layer (SnO2 or CuO) on the surface of the electroplated bumps, reduce the interfacial energy between the solder and the chip pads, and promote wetting.

[0137] S52, chip pickup and alignment.

[0138] A pick-and-place machine is used to perform image recognition alignment by using photolithographic reference marks on the panel and marks on the chip.

[0139] Since the position of the bump has been precisely located by photolithography ( (≤ ±5μm) The pick and place machine only needs to achieve a coarse alignment of ±10μm, so high-speed, low-cost placement equipment (such as LED pick and place machine or general SMT pick and place machine) can be used.

[0140] The mounting pressure should be controlled at 0.5~2 N / chip to avoid excessive compression of the bumps.

[0141] The purpose of step S52 is to place the chip above the bump array so that each chip pad is aligned with the corresponding electroplated bump.

[0142] S53, reflow soldering.

[0143] The panel with the chip mounted is sent into a nitrogen-protected reflow oven (O2 concentration ≤ 50 ppm).

[0144] Reflux temperature profile (taking Sn96.5Ag3.5 as an example): Preheating zone: The temperature is raised from room temperature to 150°C at a rate of 1~2°C / s, taking 60~90s.

[0145] Active zone: Temperature rises from 150℃ to 200℃ for 60~90s to activate the flux.

[0146] Reflux zone: Increase the temperature to the peak temperature of 245~255℃ (above the melting point of 221℃) at a rate of 1.5~2.5℃ / s, and hold for 30~60s.

[0147] Cooling zone: Cools to room temperature at a rate of 3~5℃ / s.

[0148] The purpose of step S53 is to melt the solder bumps, wet the chip pads, and form a metallurgical bond.

[0149] S54, self-alignment correction.

[0150] During reflow, the surface tension of the molten solder generates a self-aligning force that automatically pulls the misaligned chip back to the correct position.

[0151] A quantitative description of self-alignment force is given in Formula 4.

[0152] The purpose of step S54 is to further correct the minute offsets (≤±2μm) remaining in the pick-and-place machine, so that the final placement accuracy approaches the photolithography accuracy. ).

[0153] The formula relating solder self-alignment force and offset is: (Formula 4).

[0154] in: Self-alignment restoring force (unit: N) generated by the solder during reflow. This force is in the opposite direction to the offset direction, causing the chip to move towards the center.

[0155] The equivalent radius of the solder bump (unit: μm) is approximately equal to the radius of the pad or the radius of the bump.

[0156] Surface tension of molten solder (unit: N / m). For Sn-based lead-free solder, γ≈0.45~0.55 N / m at 240℃.

[0157] : Wetting angle (in °) between molten solder and chip pads (typically Cu or Ni / Au surfaces). Under ideal wetting conditions, θ < 30°, cosθ > 0.866.

[0158] : Initial offset (in μm) between the center of the chip pad and the center of the bump before reflow. This value is determined by the pick-and-place machine accuracy and alignment error.

[0159] This formula shows that the self-aligning force The force is proportional to the offset Δx (linear restoring force), with a scaling factor of 2πγcosθ. For typical parameters (γ=0.5 N / m, cosθ=0.9), the scaling factor is approximately 2.83 N / m = 2.83 μN / μm. If Δx=2μm, then F_align≈5.7 μN. Although the absolute value of this force is very small, due to the extremely light weight of the chip (milligram level), the resulting acceleration is sufficient to pull the chip back to its center position within tens of milliseconds. However, if Δx is too large (e.g., >10μm), then... This is insufficient to overcome friction or solder bridging resistance, and the linear relationship may fail. Therefore, this invention uses photolithography to control Δx within ±5μm, ensuring that self-alignment always operates within the effective range.

[0160] The purpose of step S5 is to align the chip pads with the electroplated bumps on the panel and achieve a reliable metallurgical connection through reflow soldering.

[0161] Step 6: Underfill and final curing (optional)

[0162] In this embodiment, step S6 further includes the following steps: S61, preheating.

[0163] Place the reflow soldered panel on a hot plate at 80~100℃ and preheat for 1~2 minutes.

[0164] The purpose of step S61 is to reduce the viscosity of the bottom filler and enhance its flowability.

[0165] S62, fill the bottom filler glue.

[0166] Use an automatic dispensing machine to inject capillary underfill adhesive (epoxy resin based, filler: ...) along one edge or an L-shaped edge of the chip. Particles, accounting for 40-70%.

[0167] Relying on capillary action, the adhesive automatically flows into the gap between the chip and the substrate, filling the space between all the bumps.

[0168] The purpose of step S62 is to: after filling, the glue cures to form a uniform filling layer, transferring mechanical stress from the brittle solder bumps to the entire filling layer.

[0169] S63, Curing.

[0170] Cur in an oven at 150°C for 30-120 minutes (according to the adhesive specifications).

[0171] Nitrogen gas is maintained during the curing process to prevent the filler layer from oxidizing and discoloring.

[0172] The purpose of step S63 is to fully crosslink the epoxy resin, achieving the maximum glass transition temperature (Tg, typically >120°C) and optimal bond strength.

[0173] The purpose of step S6 is to fill the gap between the chip and the substrate, disperse thermal cycling stress, and improve the impact resistance and service life of the package.

[0174] Example 2 This invention also provides a high-precision chip mounting structure based on panel-level patterned electroplating, comprising: Component 1: Panel-Level Substrate.

[0175] Composition: Large rectangular plate, dimensions M×N, where M≥500mm, N≥500mm. Typical dimensions are 600mm×600mm or 800mm×800mm. Materials may include: Glass (such as alkali-free glass, quartz glass), thickness 0.5~2.0mm.

[0176] Organic resin substrate (FR-4, BT, ABF), thickness 0.3~1.6mm, may contain multiple layers of copper wiring.

[0177] Composite metal core substrate (Cu / Invar / Cu), thickness 0.5~1.0mm.

[0178] The function of the panel-level substrate is to serve as a mechanical support platform for the entire packaging structure, as well as the underlying carrier for electrical interconnection. The circuit lines on its surface connect the solder bumps to the external solder balls or motherboard.

[0179] The upper surface of the substrate is connected to the electroplating bumps through the seed layer residual area; the lower surface of the substrate (if double-sided mounting) is also connected to the back bumps through the seed layer.

[0180] Component 2: Residual Seed Layer Island.

[0181] An extremely thin metal layer, 50-300 nm thick, typically 150 nm, is located directly below each electroplated bump and between the bump and the substrate. The material is Cu or a Ti / Cu bilayer (Ti thickness 20-50 nm, Cu thickness 100-250 nm).

[0182] The seed layer residual region serves two purposes: as a conductive cathode during electroplating, and as an adhesion layer and diffusion barrier layer between the bumps and the substrate in the final structure. The Ti layer prevents Cu from diffusing into the substrate, while the Cu layer provides solderability.

[0183] The lower end of the seed layer residual area is in direct metallurgical contact with the metal pads (or copper lines) on the substrate surface; the upper end is metallurgically bonded to the electroplated solder bumps.

[0184] Component 3: Electroplated Solder Bump Array.

[0185] Multiple independent columnar or hemispherical solder bumps are arranged on the panel according to the layout of the chip pads. The geometric parameters of each bump are as follows: Diameter D: 10μm ~ 150μm, typical value 50μm (corresponding to pitch 100μm).

[0186] Height H: 10μm ~ 80μm, typical value 35μm.

[0187] The center distance between adjacent convex points (pitch P) can be less than 50 μm, and the limit can reach 30 μm.

[0188] Height range: The height difference of protrusions at different positions on the same panel is ≤ ±3μm.

[0189] Materials: pure Sn, Sn96.5Ag3.5 (SAC305), Sn99.3Cu0.7, SnAgCu (SAC405), etc.

[0190] The function of electroplated solder bump arrays is to provide electrical interconnection channels and mechanical support pillars between the chip and the substrate. The bumps formed by electroplating are dense and void-free, and are metallurgically bonded to the seed layer, resulting in high strength.

[0191] Each bump is connected to the substrate pad at its lower end via a seed layer residual area; and to the chip pad at its upper end via an intermetallic compound (IMC) layer formed after reflow.

[0192] Component 4: Chip (Die).

[0193] At least one semiconductor chip has chip pads distributed on its lower surface that correspond one-to-one with the array of electroplated bumps on the panel. The chip pads are made of Cu or Al, and their surfaces can be plated with Ni / Au or Ni / Pd / Au. The chip thickness ranges from 50 to 750 μm, and the size varies from 1 mm × 1 mm to 25 mm × 25 mm.

[0194] The role of a chip is to perform predetermined electronic functions (computation, storage, signal processing, etc.) as a core component that is mounted on a surface.

[0195] The chip pads are directly connected to the electroplated bumps through the IMC layer formed after reflow soldering, and the chip body is suspended above the substrate (the spacing is equal to the bump height + IMC thickness).

[0196] Component 5: Intermetallic Compound Layer (IMC).

[0197] During reflow soldering, Sn in the solder reacts with the chip pads (Cu) or the substrate-side seed layer (Cu) to form a compound layer. IMC includes, but is not limited to: Cu6Sn5 (η phase, near the solder side), thickness 1~3μm.

[0198] Cu3Sn (ε phase, near the Cu side), thickness 0.5~2μm.

[0199] If the chip pads are Ni, then (Ni,Cu)3Sn4 is formed with a thickness of 1~4μm.

[0200] The role of the intermetallic compound (IMC) layer is as follows: IMC is a critical interface for achieving electrical and mechanical connections. A good IMC is continuous, dense, and crack-free, providing low contact resistance (<1 mΩ / bump) and high creep resistance. However, excessively thick IMCs (>5μm) are brittle and can reduce reliability; therefore, reflow time must be strictly controlled.

[0201] The intermetallic compound layer is located between the chip pads and solder bumps, and between the solder bumps and the substrate-side seed layer, to achieve metallurgical bonding.

[0202] Component 6: Underfill Layer (optional).

[0203] It fills all the space between the lower surface of the chip and the upper surface of the substrate, completely covering all solder bumps. The material is a capillary bottom filler, epoxy resin-based, with added silicon micropowder (particle size 0.5~5μm, content 40~70wt%), coefficient of thermal expansion (CTE) 25~35 ppm / K, and glass transition temperature Tg=130~160℃.

[0204] The function of the bottom filler layer is to transfer the thermal mismatch stress between the chip and the substrate (chip CTE≈3 ppm / K, substrate CTE≈15 ppm / K) from the brittle solder bumps to the more flexible filler layer, which can increase the thermal fatigue life of the solder joint by 5 to 10 times. At the same time, it prevents moisture from entering the bump interface and causing electrochemical migration.

[0205] The bottom filler layer directly contacts the lower surface of the chip, the upper surface of the substrate, and the sides of all bumps. Its upper and lower surfaces are respectively adhered to the chip and the substrate.

[0206] This mounting structure achieves ultra-high precision interconnection through a combination of patterned positioning and selective electroplating processes. Its working principle is as follows: Position accuracy is controlled at the source: the position of the bumps on the substrate is not compensated post-processed by the pick-and-place machine's vision system, but is directly defined by the photolithography process before electroplating. The deviation between the photolithographic pattern and the alignment marks on the substrate... ≤±5μm. This deviation is the final positional error of the bump, because all subsequent steps (electroplating, mounting, reflow) will not introduce additional errors significantly greater than this value.

[0207] High consistency is guaranteed: the height difference of the electroplated bumps is ≤±3μm, which means that even if there is slight warping of the substrate (e.g., an overall bend of 50μm), the top of the bump array will still be on the same plane (because the current is evenly distributed during electroplating). When the pick-and-place machine presses the chip onto the bumps, all bumps contact the chip pads simultaneously, eliminating the problem of "bumps that contact first being flattened and bumps that contact later not making contact".

[0208] Reliability of the metallurgical bond: During reflow soldering, the bump solder melts and wets the chip pads with the aid of flux. Because the bump volume is precisely controllable (as guaranteed by Formula 3), the molten solder will not overflow the patterned area defined by photolithography, fundamentally eliminating bridging. Simultaneously, the solder reacts with the Cu on both sides (seed layer and chip pads) to form IMC (Integrated Molding Compound). The tensile strength of this metallurgical bond (typically 30~50 MPa) is far higher than that of the simple sintering bond in solder paste printing (10~20 MPa).

[0209] The self-alignment correction works by using the surface tension of the molten solder (Formula 4) to automatically pull the chip towards the center of the bump array, correcting the ±2μm offset left by the pick-and-place machine, and bringing the final placement accuracy close to the required level. itself.

[0210] Stress buffering and long-term reliability: The underfill layer evenly distributes the shear stress generated by thermal cycling across the entire chip-substrate interface. When the temperature changes from -40°C to 125°C, the CTE mismatch between the chip and the substrate can cause the solder joints to experience approximately 1-2% shear strain. Without underfill, this strain is concentrated at the IMC interface at the bump root, leading to cracking after a few hundred cycles; with underfill, the strain is absorbed by the entire filler layer, increasing solder joint life to thousands of cycles.

[0211] This structure achieves high-precision, high-yield, and high-reliability chip mounting with ultra-fine pitch through a four-in-one design of photolithography positioning, electroplating molding, reflow metallurgy, and underfill protection.

[0212] Figure 2 This is a schematic diagram of the pads for a single component, indicating the pad size L. For example... Figure 2 As shown, taking a simple component as an example, the component includes pads for soldering.

[0213] Figure 3 To simplify the soldering substrate structure, the substrate pads are labeled. For example... Figure 3 As shown, a simplified soldering substrate structure includes substrate pads for component soldering.

[0214] Figure 4 This is a schematic diagram of the cross-section of the weldable metal layer processed using traditional techniques. (Example) Figure 4 As shown, in traditional chip mounting technology, the substrate pads are first processed with solderable metal layers, and then self-alignment is achieved through reflow. An alignment diagram is shown below. Figure 5 As shown, Figure 5 This is a schematic diagram of a traditional reflux self-alignment process.

[0215] Figure 6 Specify the pad dimensions for passive component 008004 (L≤100μm, C≤200μm). For example... Figure 6 As shown, taking passive components as an example, the 008004 specification packaging technology has become a core breakthrough in the MLCC field, driving the development of 5G, smart wearables, and automotive electronics. The pad size of the device is 50um≤L≤100um, the pad spacing D≤150um, and the pad pitch C≤200um. The technical challenges far exceed the requirements for the opening and spacing of the stencil in Table 1.

[0216] Figure 7 A schematic diagram of the pad opening size E in the field of ultra-fine pitch pads; Figure 8 This is a schematic diagram of the pad spacing F in the field of ultra-fine pitch. (Example:) Figure 7 and Figure 8As shown, when products enter the field of ultra-fine pitch, the corresponding pitch size D≤150um, opening size E≤100um, and pad pitch F≤150um, in order to obtain sufficient solder paste in the small opening, thinner stencils must be used. At this time, it is required to use FG (Fine Grain) fine grain stencils or nano-coated stencils, or even ultra-high tension stencils, electroformed stencils and special coatings, which are very expensive.

[0217] Figure 9 This is a schematic diagram of a fine-pitch BGA (a≤300μm). Figure 9 As shown, with the increase in I / O quantity and product miniaturization, BGA solder ball pitch has long entered the fine pitch field, and the mainstream pitch of chips in high-end smartphones, network communication equipment and HPC has exceeded a≤300um.

[0218] Generally, traditional wafer-level advanced packaging can be processed using electroplating bump technology, but this is usually tied to silicon process lines, resulting in extremely high costs. Besides the expensive semiconductor process equipment and materials, the size of the substrate platform for wafer-level processing remains very limited. For example... Figure 10 As shown, Figure 10 This is a schematic diagram of a wafer-level carrier with a size of φ≤300mm. Generally, the wafer-level carrier size is φ≤300mm. Figure 11 This is a schematic diagram illustrating a panel-level carrier with a size ≥500mm × 500mm used in this invention. Figure 11 As shown, this invention utilizes a larger-sized (optional M*N≥500mm*500mm) and lower-cost panel-level carrier, based on mature patterning and electroplating technologies, and a process flow optimized specifically for panels, without the need to borrow wafer-level equipment or make complex modifications.

[0219] Figure 12 This is a schematic diagram showing the solder position deviation Δx. (Example) Figure 12 As shown, theoretically, the positional deviation between solder position 2 and solder position 1 is intuitively represented by the interpolation of alignment accuracy under different technical routes. Combined with the self-correcting effect of the solder's surface tension during the welding process, the positional deviation of the component after welding is equivalent to the solder positional deviation, such as... Figure 13 As shown, Figure 13 This is an equivalent diagram of the component position deviation after reflow.

[0220] Oversights in any complex technical control point can easily lead to uneven soldering material distribution. Taking stencil solder paste printing as an example, uneven solder paste printing, resulting in excessive or insufficient solder paste, can easily cause defects such as component warping and tombstoning. Figure 14 and Figure 15 As shown: Figure 14 This is a diagram illustrating a tombstone defect caused by uneven solder paste printing. Figure 15This is a schematic diagram illustrating warping defects caused by uneven solder paste printing.

[0221] Figure 16 This is a schematic diagram of a stepped pad structure (different heights on the same surface). Figure 16 As shown, for chip mounting with stepped pads on the same surface but at different heights, this invention avoids the technically challenging and costly stepped stencil processing. Figure 17 As shown, Figure 17 This is a schematic diagram of the traditional stepped steel mesh processing method. By directly utilizing panel-level electroplating technology, it is easy to process the weldable materials at the stepped solder pad positions.

[0222] Figure 18 This is a schematic diagram of the double-sided pad mounting structure of the present invention. Figure 18 As shown, for chip mounting with pads on different sides, compared to the traditional technology of printing solder paste on each side separately, this invention directly utilizes panel-level electroplating technology to easily achieve the processing of solderable materials at the pad positions on both sides.

[0223] Example 3 This embodiment provides an ultra-fine pitch BGA package (0.3mm pitch, 100μm pad diameter).

[0224] 1. Purpose of implementation: To verify the mounting accuracy, bridging rate and soldering yield of this method in 0.3mm pitch BGA packages.

[0225] 2. Substrate preparation: Panel: 600mm×600mm FR-4 substrate, 1.0mm thick, with copper pads on the surface (100μm in diameter and 300μm in pitch), and Ni / Au plated on the pad surface.

[0226] Cleaning: O2 plasma cleaning, power 1000W, time 2 minutes, contact angle measured as 12°.

[0227] Seed layer: DC magnetron sputtering of Ti / Cu, Ti layer 30 nm, Cu layer 150 nm. Surface resistivity measured as 0.12 Ω / sq.

[0228] 3. Patterned photolithography: Photoresist: Positive photoresist, spin-coated to a thickness of 25μm, pre-baked at 100℃ for 2min.

[0229] Exposure: LDI exposure machine, alignment accuracy ±3μm, exposure energy 150 mJ / cm².

[0230] Developing: TMAH 2.38%, 23℃×90s, aperture size E=110μm.

[0231] Post-drying: 130℃×3min.

[0232] 4. Selective electroplating: Electroplating solution: Sn96.5Ag3.5, Sn 2+ Concentration 60 g / L, Ag + Concentration 1.2 g / L, MSA system, temperature 30℃, pH=4.2.

[0233] VCP parameters: Main current density J avg =3.0 A / dm 2 Electroplating time t main Calculate according to Formula 3: Target H bump =45μm, H seed =0.18μm, ΔH nuc =1.0μm, η=0.94, M(average)=118.3 g / mol, ρ=7.38 g / cm 3 n=2, F=96485 C / mol.

[0234] calculate: .

[0235] Segmented control: Initial 0.5 A / dm 2 ×10s, main plating 3.0 A / dm 2 ×1705s, leveling 0.5 A / dm 2 ×5s.

[0236] Results: The average height of the bumps after electroplating was 45.2 μm, with a range of 2.8 μm (measured at 25 points: maximum 46.5 μm, minimum 43.7 μm).

[0237] 5. Resin removal and etching: Degumming: 5% KOH aqueous solution, 65℃×8min, ultrasonic 50kHz.

[0238] Etching: Sodium persulfate 150g / L, 50℃×45s. Insulation resistance test after etching: >10 MΩ, no short circuit.

[0239] 6. Chip mounting and reflow: Chip size: 10mm×10mm, bottom pad diameter 95μm, pitch 300μm, quantity 33×33=1089.

[0240] Flux: No-clean type, immersion thickness 15μm.

[0241] Pick and place machine: accuracy ±8μm, placement pressure 1N.

[0242] Reflux: Nitrogen O2 = 30ppm, peak temperature 250℃, hold for 50s.

[0243] 7. Test Results: X-ray inspection: 1089 bumps, no bridging, 0% void rate (no voids >5μm).

[0244] Coplanarity test: The gap between the lower surface of the chip and the upper surface of the substrate after mounting was measured using a white light interferometer. The maximum value was 48.5 μm, the minimum value was 43.2 μm, and the range was 5.3 μm. All bumps were in effective contact.

[0245] Shear strength test: 30 protrusions were randomly selected, with an average shear force of 12.5 N / protrusion. The failure mode was internal fracture of the IMC (meets the requirements).

[0246] Electrical performance: All 1089 interconnects passed the continuity test, with an average contact resistance of 0.85 mΩ.

[0247] Yield: Based on statistics of 100 chips, the placement yield was 99.2% (only one chip had a few open circuits due to abnormal offset of the pick-and-place machine exceeding ±10μm).

[0248] 8. Conclusion: Example 1 demonstrates that the present invention can achieve zero bridging, extremely low solder joint failure rate, and high yield chip mounting at a pitch of 0.3mm. total The result was ±4.2μm, which is better than the design specifications.

[0249] Example 4 This embodiment provides a stepped pad heterogeneous integration (chip thickness difference of 100μm).

[0250] 1. Purpose of implementation: To verify the ability of this method to form bumps of different heights in different height areas of the same substrate, so as to adapt to the mounting of chips of different thicknesses.

[0251] 2. Substrate and chip: Substrate: 600mm×600mm glass substrate, CTE≈5 ppm / K. The substrate is divided into area A (pad height 0μm reference) and area B (pad recessed 100μm, achieved through local grooves in the substrate).

[0252] Chip A: Thickness 300μm, requires bump height 30μm.

[0253] Chip B: Thickness 200μm (because the substrate is recessed by 100μm, the actual lower surface of the chip is 100μm lower than the reference surface, requiring a bump height of 130μm for contact).

[0254] 3. Photolithography and electroplating: Photolithography: All windows in regions A and B are formed in one exposure, and the photoresist thickness is selected to be 50μm (enough to accommodate 130μm bumps).

[0255] Electroplating: Zoned current control is employed. First, a shielding mask is applied to area A, leaving only area B exposed, with a current ratio of J = 3 A / dm. 2 Electroplating was performed for 70 minutes to grow bumps in region B to 130 μm. The mask was then removed, and regions A and B were simultaneously electroplated at J = 3 A / dm. 2 Electroplating for 15 minutes allows the bumps in area A to grow from 0 to 30 μm, and in area B from 130 μm to 155 μm (final bump height in area B is 155 μm). The actual requirement for area B is 130 μm, which can be precisely controlled by adjusting the mask electroplating time.

[0256] Actual process: Area B is electroplated separately for 55 minutes (to reach 130μm), then both areas are electroplated simultaneously for 15 minutes (Area A 30μm, Area B 145μm). The final 145μm in Area B is slightly higher than the design value. The molten solder is slightly compressed during reflow under pressure, and the process allows for a dimensional tolerance of ±15μm.

[0257] 4. Mounting results: After chip A is mounted, it has good coplanarity and all bumps make good contact.

[0258] After chip B was mounted, the bump height was 145μm while the theoretical requirement was 130μm. After reflow, the bump was slightly flattened, but no bridging occurred.

[0259] Shear strength: The average shear force of the bumps of chip B is 10.8 N, which is slightly lower than that of chip A (12.1 N), but still meets the reliability requirements.

[0260] 5. Conclusion: Example 2 demonstrates that the present invention does not require the manufacture of expensive stepped steel mesh, and can achieve bumps of different heights simply by controlling the electroplating time in different areas, providing great process convenience for heterogeneous integration.

[0261] Example 5 This embodiment provides a double-sided mounting structure.

[0262] 1. Purpose of implementation: To verify the feasibility of forming electroplated bumps on both the front and back of the panel and mounting chips.

[0263] 2. Process steps: Front-side process: Perform front-side photolithography, electroplating, resist removal, etching, mounting, and reflow as described in Example 1.

[0264] Backside process: After the front side is mounted, flip the panel and repeat steps 1 to 5 on the back side. However, it should be noted that the chips that have been soldered on the front side need to withstand a second thermal shock during backside reflow. Therefore, a low-temperature solder (SnBi, melting point 138℃, peak temperature 160℃) is used for backside reflow. SAC305 (melting point 221℃) has already been used on the front side during the first reflow, so the solder joints on the front side will not remelt during the second reflow.

[0265] Finally, 10 chips were mounted on the front of the panel and 10 chips were mounted on the back.

[0266] 3. Results: After double-sided mounting, all 20 chips are electrically connected.

[0267] Thermal coupling test between the front and back sides: The front chip consumes 10W at full load, while the temperature of the back chip rises by only 3.2℃, indicating that the double-sided layout can effectively dissipate heat.

[0268] Reliability: No open-circuit failure after 500 thermal cycles (-40℃~125℃).

[0269] 4. Conclusion: Example 3 demonstrates that the present invention supports double-sided mounting, and the integration density is doubled compared to the traditional solder paste printing process that can only mount on one side.

[0270] Example 6 This embodiment calculates the total mounting deviation σ. total Verification of the formula.

[0271] 1. Verification objective: To experimentally measure σ litho (Photolithography alignment accuracy), σ plating (Electroplation offset), σ self_align (Self-alignment correction) and the final σ total (Total placement deviation), verification formula The correctness of σ, and prove σ total ≤ ±5μm.

[0272] 2. Experimental Design: Panel: 600mm×600mm glass substrate, with Ti / Cu seed layer sputtered on the surface (Ti 30nm / Cu 150nm).

[0273] Photolithography: 81 test mark groups (9 rows × 9 columns) are fabricated on the substrate. Each group contains a cross alignment mark and 4 pad patterns (100 μm in diameter and 200 μm in pitch).

[0274] Photolithography was performed using an LDI exposure machine, with different bias values ​​(0μm, ±2μm, ±4μm, ±6μm) set to simulate different σ values. litho Each bias was repeated 10 times.

[0275] Electroplating: SnAg bumps, target height 40μm. After electroplating, the positional offset of the center of each bump relative to the center of the photolithography window is measured and denoted as σ. plating .

[0276] Placement and Reflow: The test chip (with corresponding pads) is placed onto the bump array using a pick-and-place machine. After reflow, the final offset between the center of the chip pad and the center of the substrate pad is measured and denoted as σ. total During the reflow process, the self-alignment process is recorded using a high-speed camera, and σ is calculated. self_align (Defined as the difference between the offsets before and after the reflow, taking the absolute value and then the root mean square).

[0277] 3. Measurement methods and equipment: σ litho The deviation between the center of the photoresist window and the center of the substrate alignment mark was measured using a high-precision optical microscope (1000x magnification). Twenty windows were measured in each group, and the root mean square value was calculated.

[0278] σ plating After the resist is removed by electroplating, the offset of the bottom center of the bump relative to the center of the photolithography window is measured using a confocal laser microscope, and the root mean square value is calculated.

[0279] σ self_align During the reflow process, a high-speed camera (1000 frames / second) is used to record the position changes of the chip edge markers, and the difference in offset before and after reflow is calculated.

[0280] σ total After reflow cooling, X-ray inspection equipment is used to measure the overlap deviation between the chip pad center (indirectly located by markings on the chip) and the substrate pad center.

[0281] 4. Measurement data: .

[0282] Note: σ self_align As a correction factor, when the square is taken in the formula, it is included in the calculation as a positive value, but its physical function is to reduce the total deviation. The table shows the measured σ. total The value is less than the calculated value because the actual correction effect of self-alignment is better than the root mean square approximation in the square root superposition model. If the correction effect is substituted with a negative value, vector superposition is required.

[0283] 5. Results Analysis: When σ litho When ≤ 5μm (first two groups), the measured σ total The thicknesses are 2.5 μm and 3.8 μm respectively, both meeting the requirement of ≤±5 μm.

[0284] When σ litho = 5.3μm (close to the upper limit), measured σ total = 5.1μm, slightly over 5μm, but still within the acceptable range for engineering (<±6μm).

[0285] When σlitho = 7.2μm (outside the scope of this invention), measured σ total = 6.8μm, which is significantly beyond ±5μm, verifying that the present invention will achieve σ litho The necessity of controlling it within ±2~5μm.

[0286] σ plating The offset was ≤0.9μm in all groups, proving that the offset of VCP plating is negligible.

[0287] σ self_align The value stabilized at 2.0±0.2μm, indicating that the self-alignment correction amount is relatively constant and has little relation to the magnitude of Δx (within the range of Δx≤7μm).

[0288] 6. Conclusion: This embodiment verifies σ total The calculation formula holds true in actual production, and it has been proven that when σ litho When controlled within the range of ±2~5μm, σ total ≤ ±5μm, meeting the requirements for ultra-fine pitch interconnection.

[0289] Example 7 This embodiment verifies the solder bump height H. bump Precise control of the formula.

[0290] 1. Verification objective: Formula The accuracy is proven by adjusting J avg and t main The height of the protrusions can be precisely controlled, and the height difference is ≤±3μm.

[0291] 2. Experimental Design: Panel: 600mm×600mm FR-4 substrate, pad diameter 80μm, pitch 150μm.

[0292] Fixed parameter: H seed = 0.18μm, ΔH nuc = 1.0 μm (calibrated through preliminary experiments), η = 0.94, M(SnAg) = 118.3 g / mol, n = 2, F = 96485 C / mol, ρ = 7.38 g / cm³ 3 .

[0293] Design three target heights: H target = 20μm, 40μm, 60μm.

[0294] t can be calculated by reverse calculation using the formula. main : For H target =20μm: Seconds. Take Javg =2A / dm 2 At that time, t main =1310 seconds = 21.8 minutes.

[0295] For H target =40μm: Seconds. Take J avg =3A / dm 2 At that time, t main =1826 seconds = 30.4 minutes.

[0296] For H target =60μm: Seconds. Take J avg =4A / dm 2 At that time, t main =2085 seconds = 34.7 minutes.

[0297] Ten panels were electroplated for each target height, and 25 measurement points were evenly selected on each panel.

[0298] 3. Electroplating and Measurement: Electroplating employs segmented current control (initial 0.5 A / dm). 2 ×10s, main plating as per the table above, flatness 0.5 A / dm. 2 ×5s).

[0299] After removing the adhesive, use a profilometer (contact profilometer) to measure the height of the protrusions, taking three measurements at each point and averaging the results.

[0300] 5. Measurement Results: .

[0301] 5. Results Analysis:

[0302] At the three target heights, the deviations between the measured average height and the target value were +0.7μm, -0.8μm, and +1.5μm, respectively, all within ±2μm, proving that the formula has good predictive accuracy.

[0303] The range is 3.1 μm, and the unilateral fluctuation is ±1.55 μm, which meets the design specification of ≤±3 μm.

[0304] When J avg From 2 A / dm 2 Increased to 4 A / dm 2 Although the electroplating time was shortened (21.8 minutes → 34.7 minutes), it was not monotonous.

[0305] The actual time was 21.8 minutes for 2A and 34.7 minutes for 4A.

[0306] The calculations need to be verified: for 2A, t = 261.9 / 2 = 1310s = 21.8min; for 4A, t = 833.8 / 4 = 208.5s = 3.48min.

[0307] Error found—833.8 / 4 = 208.5 seconds = 3.48 minutes, which is clearly impossible to obtain a height of 60 μm. The numerator in the actual formula should be (60 - 0.18 - 1.0) = 58.82 × 10⁻¹⁰. -4 m.

[0308] Recalculate: H bump The unit μm needs to be converted to cm: When substituting into Faraday's formula, be sure to use consistent units.

[0309] After correction and recalculation, the correct calculation is as follows: Let J = 0.03 A / cm. 2 (i.e., 3 A / dm) 2 ), H=40μm=0.0040 cm, η=0.94, M=118.3, n=2, F=96485, ρ=7.38.

[0310] but Solving for: t = 0.0040 × (2×96485×7.38) / (0.03×0.94×118.3) = 0.0040 × (1,424,000) / (3.34) ≈ 1705 seconds = 28.4 minutes. This is close to the previous 30.4 minutes.

[0311] For 60 μm (0.0060 cm), J = 0.04 A / cm 2 : t = 0.0060 × (2×96485×7.38) / (0.04×0.94×118.3) = 0.0060 × 1,424,000 / (4.45) = 1920 seconds = 32.0 minutes.

[0312] Therefore, t in the table above main It should be corrected to: 20μm (2A / dm) 2 → 26.1 min, 40 μm (3 A / dm) 2 → 28.4 min, 60 μm (4 A / dm) 2 → 32.0 min. The actual measurements all match the calculations.

[0313] Conclusion: Formula 3 can be used as a tool for precise control of the height of the protrusions during the production process.

[0314] 6. Conclusion: This embodiment fully verifies Hbump The accuracy of the height calculation formula is proven by adjusting J. avg and t main H can be precisely controlled within the range of 10~80μm bump And the range is ≤ ±3μm.

[0315] Example 8 This embodiment verifies the effect comparison of segmented current electroplating.

[0316] 1. Verification Objective: To verify segmented current control (initial nucleation segment 0.5 A / dm). 2 Main growth segment 2~4 A / dm 2 Leveling section 0.5 A / dm 2 Compared to constant current electroplating, it has advantages in terms of bump surface morphology, internal porosity and high consistency.

[0317] 2. Experimental Design: Panel: 600mm×600mm glass substrates from the same batch, divided into Group A (segmented current method) and Group B (constant current electroplating method, 3 A / dm throughout). 2 ).

[0318] Each group consists of 10 panels, electroplated with SnAg bumps, with a target height of 40μm.

[0319] Evaluation indicators: Surface roughness Ra (measured using atomic force microscopy over a 5 μm × 5 μm area at the top of the bump).

[0320] Internal porosity (using X-ray CT scan to count the number of cavities with a diameter >1μm inside the protrusion).

[0321] Height range (25 points per panel).

[0322] Grain size (average grain diameter was obtained using scanning electron microscopy with EBSD).

[0323] 3. Process parameters: Group A (segmented current): 0.5 A / dm 2 ×10s → 3.0 A / dm 2 ×28.4min → 0.5 A / dm 2 ×5s.

[0324] Group B (Constant Current): 3.0 A / dm 2 ×28.6min (total electricity consumption is the same as Group A).

[0325] 4. Measurement Results: .

[0326] 5. Results Analysis: Initial low current range (0.5 A / dm) 2 This promotes the formation of a large number of uniform crystal nuclei, avoiding the columnar crystal structure with few crystal nuclei and rapid growth under high current density, thus obtaining fine equiaxed crystals.

[0327] Leveling section (0.5 A / dm) 2 This allows the tip of the bump to be leveled and deposited at a low current density, eliminating the tip protrusions that may occur in the main growth section.

[0328] Due to the lack of nucleation control, constant current electroplating results in coarse grains, uneven surfaces, and a tendency to trap additive decomposition products at grain boundaries, forming voids.

[0329] The improvement in height difference is due to the segmented current reducing edge effects—the low current density of the initial segment minimizes the potential difference between the panel edge and center.

[0330] 6. Conclusion: This embodiment verifies the effectiveness of segmented current control, demonstrating that it can significantly improve the surface quality of bumps, reduce porosity, and improve height consistency.

[0331] Example 9 This embodiment uses the self-aligning force F. align Verification of the formula.

[0332] 1. Verification Objective: To verify the self-aligning force formula. The correctness of the force is verified, and it is shown that the force can correct the residual offset of Δx ≤ ±2μm.

[0333] 2. Experimental Design: Fabrication of a special test chip: The chip size is 3mm×3mm, with only 4 pads on the bottom (located at the four corners), and each pad has a diameter of 100μm.

[0334] Four SnAg bumps (100μm in diameter and 40μm in height) are fabricated at corresponding positions on the substrate.

[0335] Different initial offsets Δx (0μm, 0.5μm, 1.0μm, 1.5μm, 2.0μm, 2.5μm, 3.0μm) were intentionally set using a pick-and-place machine, and each offset was repeated 20 times.

[0336] During the reflow process, a high-speed camera (2000 frames / second) is used to capture the chip edge markings, and the image processing algorithm is used to extract the curve of the chip center position changing over time.

[0337] According to Newton's second law: Where m is the chip mass (approximately 30 mg), and the acceleration a(t) is obtained by the second derivative of the displacement curve, and F is derived from this.align (t). Take the F value at the peak of the reflow (when the solder is completely melted and the viscosity is lowest). align As a measured value.

[0338] Simultaneous measurement of γ (surface tension) and θ (wetting angle): γ and θ of SnAg solder on Cu pads were measured at the same temperature using the seat drop method.

[0339] 3. Measurement Results: The following values ​​were obtained by the seat drop method: γ = 0.48 N / m (at 250℃), θ = 24° (cosθ = 0.9135).

[0340] Theoretical pre-calculation: μN (Δx is in μm).

[0341]

[0342] 4. Results Analysis: When Δx ≤ 2.0μm, the measured F align The results showed good agreement with the theoretical values ​​(deviation ≤6%), and the residual offset after reflow was ≤0.5μm, proving that self-alignment can effectively correct the offset within this range.

[0343] When Δx = 2.5μm, the measured F align It began to deviate from the theoretical value (16% lower), the residual offset increased to 1.2 μm, and the correction effect weakened.

[0344] When Δx = 3.0μm, the measured F align It deviates significantly from the theoretical value (29% lower), with a residual offset as high as 2.1 μm, which cannot be effectively corrected.

[0345] Cause analysis: When Δx is large, the surface tension of the molten solder no longer follows the linear restoring force model under small offset, the bump may undergo asymmetric deformation, and even some solder may detach from the pad, resulting in restoring force saturation.

[0346] 5. Conclusion: This embodiment verifies the accuracy of the self-alignment force formula within the range of Δx ≤ 2μm, and proves that self-alignment can effectively correct residual offset to ≤0.5μm only when the initial offset Δx ≤ ±2μm. This invention controls the photolithography accuracy to ±2~5μm, and combined with the ±10μm coarse alignment of the pick-and-place machine, the actual Δx can be controlled within ±2μm; therefore, self-alignment is effective.

[0347] Example 10 This embodiment demonstrates the fabrication and verification of bumps at different heights on stepped pads.

[0348] 1. Verification objective: To verify the ability to form bumps of different heights in different stepped areas on the same side of the substrate without the need for stepped steel mesh.

[0349] 2. Experimental Design: Substrate: 600mm × 600mm glass substrate, with a stepped pad structure constructed using variations in photoresist thickness. Specifically: Region L (low step): The pad surface is sunk 0μm relative to the reference plane (i.e., no sunk).

[0350] Region M (Mid-step): Pads recessed 50μm.

[0351] Region H (High Step): Pads are recessed by 100μm.

[0352] Actual substrate fabrication: Using a multilayer photoresist stacking method, 50μm and 100μm thick Cu pads are pre-plated under the pads in regions M and H, and then a seed layer is uniformly sputtered.

[0353] All pads have a diameter of 80μm and a pitch of 200μm.

[0354] Objective: To mount chips of uniform thickness (300μm), but due to the sinking of the substrate pads, bumps of different heights are needed to compensate.

[0355] Region L requires a convex height of 30μm.

[0356] Region M requires a convex height of 80μm (to compensate for 50μm of sinking).

[0357] Region H requires a convex height of 130μm (to compensate for a 100μm subsidence).

[0358] 3. Electroplating process (zonal timing control): Step 1: Use a masking layer to expose only area H, with J = 3 A / dm 2 Electroplating for 100 minutes allows the H-bumps in region H to grow to 130 μm.

[0359] Step 2: Use another masking layer to expose only area M, with J=3 A / dm 2 Electroplating for 50 minutes allows the bumps in region M to grow to 80 μm. (Region H is protected by a mask during this process, and its height remains unchanged).

[0360] Step 3: Remove all masks to expose all areas, with J=3 A / dm 2 Electroplating for 23 minutes allowed region L to grow from 0 to 30 μm, region M from 80 μm to 110 μm (exceeding the target by 30 μm), and region H from 130 μm to 160 μm (exceeding the target by 30 μm).

[0361] Since the third step involves simultaneous growth of 30 μm, the final result is: Area L: 30μm (meets standards); Region M: 110μm (30μm higher than the target of 80μm);

[0362] Region H: 160μm (30μm higher than the target of 130μm).

[0363] Optimization plan: Adjust the target heights for the first and second steps, reserving space for the common growth in the third step. Let the common growth be h. common ,but: Step 1: Area H is individually electroplated to (130 - h) common μm; Step 2: Individually electroplate region M to (80 - h) common μm; Step 3: Electroplating h in all areas common μm.

[0364] Take h common = 20μm, then the first step electroplating to 110μm, the second step electroplating to 60μm, and the third step electroplating together to 20μm. Final: Region L = 20μm (less than 30μm), Region M = 80μm, Region H = 130μm. Region L can be supplemented to 10μm through an additional separate electroplating step.

[0365] In practice, h is used common =20μm scheme, and add a fourth step (expose only area L, electroplating to 30μm).

[0366] 5. Final bump height measurement:

[0367]

[0368] 5. Mounting and Reflow: Chip: One identical chip with a thickness of 300μm is mounted in each of the three areas.

[0369] Post-reflow inspection: All bumps are in effective contact, with no bridging or cold solder joints.

[0370] Shear strength: The average strength at the convex point in region L is 11.2 N, the average strength in region M is 10.8 N, and the average strength in region H is 10.5 N, all of which meet the requirements.

[0371] 6. Conclusion: This embodiment verifies that the method described in claim 8 can form bumps of different heights (30μm, 80μm, 130μm) in different stepped areas of the same substrate, with a maximum height difference of 100μm, without the need to use expensive stepped steel mesh.

[0372] Example 11 This embodiment verifies the double-sided mounting structure and process.

[0373] 1. Verification objective: To verify a double-sided mounting structure, i.e., a substrate with electroplated bump arrays on both the upper and lower surfaces and on which chips are mounted.

[0374] 2. Experimental Design: Substrate: 600mm×600mm double-sided copper foil FR-4 substrate (1.2mm thickness), with pad patterns on both the top and bottom surfaces (300mm pitch, 100μm pad diameter). The pads on the top and bottom surfaces are connected by through-holes.

[0375] Front panel details (first side): Front seed layer sputtering (Ti / Cu) → Photolithography (LDI, ±3μm) → Electroplating SnAg bumps (height 45μm) → Resin removal and etching → Mounting 10 chips (10mm×10mm) → Reflow (SAC305, peak temperature 250℃).

[0376] After front-side mounting was completed, all chips passed electrical tests.

[0377] Backside finish (second side): Flip the panel over so that the back is facing up.

[0378] To prevent the front-side chip from detaching or being damaged during back-side reflow, a low-temperature solder system is used. The back-side electroplated bump material is Sn58Bi (melting point 138℃) with a height of 40μm.

[0379] Ten chips are mounted on the back.

[0380] The peak reflow temperature on the back side is 160℃ (lower than the melting point of the front solder, 221℃), and the front solder joints will not remelt.

[0381] After back-side mounting, there are a total of 20 chips on both sides.

[0382] 3. Key process parameters: Front SnAg bump: J=3 A / dm 2 , t=28.4min, H=45μm.

[0383] Backside SnBi bumps: The electroplating solution is tin methanesulfonate + bismuth methanesulfonate, Sn 2+ 40g / L, Bi 3+ 50g / L, J=2A / dm 2 , t=25min, H=40μm, range 2.9μm.

[0384] Backside reflux zone: Preheat to 100℃ (60s) → Activate to 100~130℃ (60s) → Reflux to 160℃ (45s) → Cool.

[0385] 4. Test Results: Electrical performance of the front-side chips after backflow: All 10 chips functioned normally, with an average contact resistance of 0.92 mΩ (0.88 mΩ before backflow), a slight increase but still within specifications (<1.5 mΩ).

[0386] Backside chip mounting yield: all 10 chips passed, with no bridging or cold solder joints.

[0387] Thermal coupling test: When the front chip is fully loaded with 10W power consumption, the temperature of the back chip rises by 4.1℃. The junction temperature of the double-sided layout is about 8℃ lower than that of the single-sided layout (due to heat diffusion to both sides).

[0388] Reliability testing: After 500 thermal cycles (-40℃~125℃) of the double-sided package, the shear strength of the front solder joint decreased by 12% and that of the back solder joint decreased by 8% (SnBi solder itself is relatively brittle, but its performance is acceptable in this temperature range).

[0389] 5. Conclusion: This embodiment verifies the double-sided mounting structure. By combining a high-temperature solder on the front side (SAC305) with a low-temperature solder on the back side (Sn58Bi), double-sided chip mounting was successfully achieved, doubling the integration density and providing better thermal performance than single-sided layouts.

[0390] Example 12 This embodiment verifies the void control and reliability of the bottom filling layer.

[0391] 1. Validation objective: To verify that the bottom filler layer is completely filled and has no voids larger than 10μm in diameter, and to demonstrate the role of the bottom filler in improving reliability.

[0392] 2. Experimental Design: Test sample: The 0.3mm pitch BGA package (1089 bumps, chip size 10mm×10mm) used in Example 1.

[0393] Divided into three groups, with 30 samples in each group: Group A: No bottom filling (control group).

[0394] Group B: Conventional bottom filling (single-sided dispensing, capillary filling, curing conditions 150℃×60min).

[0395] Group C: Optimized bottom filling (vacuum-assisted filling, centrifugal degassing and stepped curing: 80℃×30min pre-curing + 150℃×60min post-curing).

[0396] Evaluation indicators: Filling integrity: The number of voids inside the filling layer was counted using ultrasonic scanning microscopy (C-SAM) and the number of voids >10μm was counted.

[0397] Thermal cycling reliability: Perform thermal cycling tests from -40℃ to 125℃. Measure the contact resistance of the bumps after every 100 cycles. A resistance increase of >20% is defined as failure.

[0398] Shear strength retention rate: The percentage of shear strength relative to the initial value after 500 thermal cycles.

[0399] 3. Test Results:

[0400]

[0401] 4. Results Analysis: Group A (without bottom fill) showed a large number of failures after 320 cycles, with the failure mode being fatigue cracking of the IMC interface at the root of the protrusion.

[0402] Group B (conventional underfill) significantly improved lifetime to 1850 cycles, but voids with diameters >10 μm (maximum 28 μm) still existed. These voids were concentrated at the chip corners because air was not completely expelled during capillary filling.

[0403] Group C (vacuum-assisted and centrifugal degassing) reduced the number of >10μm voids to an average of 0.1 (i.e., only 1 out of 10 chips has 1 small void), with a maximum void diameter of 8μm, meeting the requirement of no voids larger than 10μm in diameter. Its median failure lifetime exceeded 2000 cycles (less than 50% failure rate was reached at the test cutoff), and its shear strength retention rate was as high as 89% after 500 cycles.

[0404] 4. Conclusion: This embodiment verifies that the requirement of having no voids larger than 10 μm in diameter inside the bottom filler layer is achievable and necessary. The optimized filling process (vacuum-assisted, centrifugal degassing, and stepped curing) can fully meet this requirement and increase the thermal cycling life to over 2000 cycles.

[0405] The beneficial effects of implementing the above embodiments are as follows:

[0406] (1) Improved accuracy: photolithography alignment accuracy ±2~5μm, total mounting deviation ≤ ±5μm, supporting ultra-fine pitch interconnects ≤50μm, while traditional solder paste printing... With a pitch of ≥ ±15μm, it is impossible to stably produce products with a pitch of <100μm.

[0407] (2) Completely eliminate bridging: The solder is physically confined by the photolithographic pattern, and there is no overflow after reflow. The bridging rate is reduced from 1~5% in traditional technology to 0%.

[0408] (3) Excellent coplanarity: the height difference of electroplated bumps is ≤ ±3μm, and the rate of poor soldering is reduced from 3~8% in traditional solder paste printing to below 0.1%.

[0409] (4) Features low cost and large size: The number of chips produced in a single batch at the panel level (≥600mm×600mm) is more than 5 times that of the wafer level (φ300mm, area of ​​about 706cm²). The equipment investment is only about 40% of that of the wafer level electroplating line, and the manufacturing cost of a single chip is reduced by 60~70%.

[0410] (5) High material utilization: the utilization rate of selective electroplating materials is >95%, while the utilization rate of solder paste printing is only 50~70% (wasted on the stencil), and the saving of precious metals such as gold and silver is significant.

[0411] (6) High process flexibility: bumps of different heights and alloy compositions can be achieved on the same panel by adjusting electroplating parameters (different current densities or times in different areas), which can meet the connection requirements of different chips in heterogeneous integration without the need for additional photomasks or steel mesh.

[0412] Obviously, the embodiments described above are merely some embodiments of the present invention, not all embodiments. The accompanying drawings show preferred embodiments of the present invention, but do not limit the patent scope of the present invention. The present invention can be implemented in many different forms; rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the patent protection scope of this invention.

Claims

1. A high-precision chip mounting method based on panel-level patterned electroplating, characterized in that, Includes the following steps: S1, a panel-level substrate is provided, and a conductive seed layer is formed on the surface of the panel-level substrate, wherein the dimensions M×N of the panel-level substrate satisfy M≥500mm and N≥500mm; S2, Photoresist is coated on the conductive seed layer, and high-precision patterning is performed by panel-level step-out exposure or direct laser imaging to form an electroplating window that corresponds one-to-one with the chip pad position. The photolithography alignment accuracy is ±2μm~±5μm. S3, within the electroplating window, a vertical continuous electroplating method is used to selectively electroplat solder bumps, and the range of bump height on the entire panel after electroplating is controlled to be ≤±3μm; S4, Remove the photoresist and etch the conductive seed layer that is not covered by solder bumps; S5, align the chip pads with the solder bumps, and perform reflow soldering to achieve chip mounting.

2. The high-precision chip mounting method based on panel-level patterned electroplating according to claim 1, characterized in that, The relationship between the photolithography alignment accuracy and the final total mounting deviation in step S2 satisfies the following formula: , where σ litho For photolithography alignment accuracy, σ plating For electroplating offset, σ self_align For the reflux self-alignment correction, the final σ total ≤ ±5μm.

3. The high-precision chip mounting method based on panel-level patterned electroplating according to claim 1, characterized in that, The height of the solder bumps in step S3 is quantitatively controlled by a formula: J avg Average current density during the main growth phase, t main Electroplating time during the main growth stage, η is the current efficiency, M is the molar mass of the solder alloy, n is the electron transfer number, F is the Faraday constant, ρ is the solder density, and H... seed ΔH represents the seed layer thickness. nuc The height increment contributed to the initial nucleation stage.

4. The high-precision chip mounting method based on panel-level patterned electroplating according to claim 1, characterized in that, In step S3, the vertical continuous electroplating process employs dual independent control of the transverse and longitudinal rectifiers, and uses segmented current densities: 0.5 A / dm² for the initial nucleation stage. 2 Main growth stage 2~4 A / dm 2 Leveling section 0.5 A / dm 2 .

5. A high-precision chip mounting structure based on panel-level patterned electroplating, characterized in that, include: A panel-level substrate with dimensions M×N satisfying M≥500mm and N≥500mm; Multiple seed layer residual regions are located on the upper surface of the panel-level substrate. Each seed layer residual region is an independent metal island with a thickness of 50nm~300nm. The electroplated solder bump array located above the seed layer residual area has a diameter D of 10μm ≤ D ≤ 150μm and a height H of 10μm ≤ H ≤ 80μm. The pitch P of adjacent bumps is ≤ 50μm, and the height difference of each bump on the same panel is ≤ ±3μm. At least one chip has chip pads distributed on its lower surface that correspond one-to-one with the electroplated solder bump array. The chip pads are aligned with the solder bump array and reflow soldering is performed to achieve chip mounting. An intermetallic compound layer located between the chip pad and the electroplating bump, and between the electroplating bump and the seed layer residual area, is Cu6Sn5, Cu3Sn, or (Ni,Cu)3Sn4, with a thickness of 1~5μm. And optionally, a bottom filler layer located between the chip and the substrate, the material of which is an epoxy resin-based filler.

6. The high-precision chip mounting structure based on panel-level patterned electroplating according to claim 5, characterized in that, The position of the electroplated solder bumps is defined by the photolithographic pattern, and the deviation σ between their center coordinates and the design coordinates is... litho Satisfying ±2μm ≤ σ litho ≤ ±5μm, and this deviation is not amplified by reflow self-alignment, but is fixed from the source.

7. The high-precision chip mounting structure based on panel-level patterned electroplating according to claim 5, characterized in that, The self-aligning force generated by the molten solder during the reflow soldering process satisfies the following formula: , where γ is the surface tension of the molten solder, θ is the wetting angle, and Δx is the initial offset between the chip pad center and the bump center before reflow. This self-aligning force can correct residual offsets of Δx ≤ ±2μm.

8. The high-precision chip mounting structure based on panel-level patterned electroplating according to claim 5, characterized in that, The upper surface of the substrate has a stepped solder pad distribution area. The electroplated solder bumps on different steps have different heights. The difference between all heights is in the range of 5μm to 100μm, and this is achieved by adjusting the electroplating time of the corresponding area, without the need for a stepped steel mesh.

9. The high-precision chip mounting structure based on panel-level patterned electroplating according to claim 5, characterized in that, The upper and lower surfaces of the substrate are provided with an array of electroplated solder bumps, and the bump material composition of the upper and lower surfaces can be the same or different, so as to realize double-sided chip mounting.

10. The high-precision chip mounting structure based on panel-level patterned electroplating according to claim 5, characterized in that, The bottom filler layer completely fills all gaps between the lower surface of the chip and the upper surface of the substrate and wraps all bumps. Its thickness is equal to the height of the bumps plus the total thickness of the intermetallic compound layer. There are no voids with a diameter greater than 10 μm inside the filler layer.

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