A non-cavity bottom filling process for wafer level SMT patch assembly

Abstract

The application discloses a kind of bottom filling processes of wafer level surface mount technology patch assembly.It includes: the substrate with bare chip is placed in microwave energy excitation plasma environment and is treated on surface;According to linear or right angle broken line type path, bottom filling glue is coated along the boundary of bare chip;After coating glue solution, the substrate is placed in the first pressure environment with air pressure value lower than standard atmospheric pressure to carry out preliminary defoaming;The substrate is executed heating procedure including first, second, third constant temperature stage of step type, and second pressure environment with air pressure lower than standard atmospheric pressure and third pressure environment with air pressure higher than standard atmospheric pressure are alternately applied during temperature rising period.By surface activation, one-way fluid coating and step type heat pressure cooperative treatment, the wettability and flowability of glue solution in micro gap are improved, gas in solidification process is excluded and residual micropore is compressed, bottom filling glue void ratio is reduced, and structural reliability in secondary reflow soldering and other high temperature processes is improved.

Description

Technical Field

[0001] This invention relates to the field of wafer-level SMT processing technology, and more particularly to a void-free bottom filling process for wafer-level SMT chip assembly. Background Technology

[0002] With the continuous development of advanced semiconductor packaging technologies, the reliability of the interface between the chip and the substrate is crucial in hybrid mounting processes that combine surface mount technology (SMT) with flip-chip technology (such as EIC electrical chips and PIC optical chips). To protect the fragile microbumps and alleviate thermal stress, underfill is usually required after chip mounting.

[0003] However, existing technologies have the following significant technical drawbacks in the underfill and curing baking process: Firstly, due to the extremely small micro-gap size, conventional adhesives are easily hindered by substrate trenches, flux residues, or surface tension during capillary flow, leading to air entrapment. Secondly, existing baking and curing processes often use conventional air or nitrogen ovens for single-dimensional heating, preventing the effective removal of tiny air bubbles trapped inside the adhesive during thermal cross-linking. Once these voids form, the internal gas can expand rapidly during subsequent high-temperature processes such as reflow soldering, causing serious defects such as adhesive bursting, overflow, or even micro-bump breakage in the underfill adhesive. This poses a significant threat to the yield and long-term reliability of high-precision components such as optical communication modules.

[0004] Therefore, it is necessary to improve the existing underfill technology for wafer-level SMT assembly to overcome the shortcomings of the existing technology. Summary of the Invention

[0005] To overcome the problems existing in related technologies, the purpose of this invention is to provide a void-free underfill process for wafer-level SMT assembly. This void-free underfill process for wafer-level SMT assembly involves surface activation treatment of a substrate with bare chips, application of underfill adhesive along a straight path or a right-angled zigzag path, degassing in a first pressure environment, and alternating between a second and third pressure environment during a heating process that sequentially includes a first isothermal stage, a second isothermal stage, and a third isothermal stage. This overcomes the problems in the prior art, such as poor wettability of the underfill adhesive in micro-gaps, ineffective air bubble removal during curing leading to the risk of adhesive explosion and low reliability during secondary reflow soldering.

[0006] A void-free underfill process for wafer-level SMT assembly includes: The substrate with the bare chip mounted is placed in a microwave-energized plasma environment for surface activation treatment. The underfill adhesive is applied along one outer boundary of the bare chip in a straight line, or along two adjacent outer boundaries of the bare chip in a right-angled zigzag line. The substrate, after being coated with the bottom filler adhesive, is placed in a first pressure environment with an air pressure value lower than standard atmospheric pressure; A heating process is performed on the substrate; the heating process includes a first constant temperature stage, a second constant temperature stage, and a third constant temperature stage in sequence; during the heating process, the environment of the substrate is alternately switched between a second pressure environment and a third pressure environment; the pressure value of the second pressure environment is lower than the standard atmospheric pressure, and the pressure value of the third pressure environment is higher than the standard atmospheric pressure.

[0007] Furthermore, in the step of placing the substrate with the bare chip mounted on it in a microwave-energized plasma environment for surface activation treatment, the microwave frequency for energizing the plasma environment is 2.45 GHz, and the ambient temperature of the plasma environment is below 70°C.

[0008] Conventional plasma pretreatment typically employs radio frequency plasma (e.g., 13.56 MHz) and does not impose strict low-temperature constraints on the operating environment. This invention specifies a microwave frequency of 2.45 GHz for exciting the plasma environment, with an ambient temperature below 70°C. 2.45 GHz microwave plasma exhibits extremely high plasma density (10⁻⁶ / 10⁻⁶) compared to traditional radio frequency plasma. 12 Up to 10 13 cm -3 Furthermore, the discharge is more uniform, and more importantly, microwave excitation does not require physical electrode contact, thus physically avoiding the damage caused by the powerful bombardment of heavy ions and the risks of metal sputtering and electrostatic discharge (ESD). Simultaneously, by forcibly limiting the operating temperature to a low-temperature plasma state below 70°C, thermal stress transfer is effectively avoided. While achieving sufficient hydrophilic activation of the chip's underlying gaps, this design maximizes the protection of the mounted bare chip, sensitive microbump structures, and organic substrate from thermal damage, ensuring the structural integrity of the component.

[0009] Furthermore, the underfill adhesive comprises a base resin and a curing agent; The base resin is selected from at least one of bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenolic type epoxy resin and alicyclic epoxy resin; The curing agent is selected from at least one of aliphatic amine curing agents, aromatic amine curing agents, acid anhydride curing agents, and phenolic resin curing agents.

[0010] Existing underfill adhesives mostly use conventional or broad epoxy resin formulations, without specific material selection for the stringent alternating vacuum pressure curing process. This invention limits the specific types of base resins (bisphenol A / F, phenolic resins, alicyclic resins) and curing agents (aliphatic amines / aromatic amines / acid anhydrides / phenolic resins). The carefully selected combination of these base resins and curing agents maintains extremely low initial viscosity at room temperature and during the initial heating phase, and possesses excellent crosslinking latency characteristics. This prevents the underfill adhesive from undergoing premature and violent network crosslinking reactions when placed in the vacuum environment of the first and second stages, thus maintaining high rheological properties and unobstructed venting channels. Furthermore, it endows the adhesive with the ability to fully respond to external pressure and undergo microscopic deformation when encountering positive pressure in the later stages, perfectly coordinating thermodynamics and pressure changes, thoroughly crushing any remaining extremely fine pores and completing the final curing process.

[0011] Furthermore, the bottom filler also includes silica filler, the silica filler having an average particle size of 5 μm and a maximum particle size of less than 20 μm; The dynamic viscosity of the bottom filler is in the range of 10 Pa·s.

[0012] Traditional filling processes offer limited control over the rheological parameters of the adhesive, resulting in significant inhomogeneity in filler size and a high risk of physical blockage during penetration into micro-particle-sized areas (flip-chips). This invention limits the average particle size of the silica filler to 5 μm, with a maximum particle size less than 20 μm, and precisely anchors the dynamic viscosity to within 10 Pa·s. By controlling the average silica particle size to the nanometer to micrometer level (5 μm) and implementing large particle truncation (<20 μm), the physical size of the filler eliminates the risk of bridging, jamming, and agglomeration in the narrow gaps of chip microbumps, preventing localized dead zones and voids caused by particle accumulation. Simultaneously, quantifying the dynamic viscosity to 10 Pa·s achieves an excellent balance between microscopic capillary surface tension and fluid resistance. When combined with a plasma-activated surface, this viscosity allows the adhesive to fill any dead corners extremely smoothly and uniformly, ensuring efficient, bubble-free, unidirectional penetration from a hydrodynamic perspective.

[0013] Furthermore, the underfill adhesive has an inherent glass transition temperature; The coefficient of thermal expansion of the underfill adhesive is 28 ppm / °C in the range below the glass transition temperature and 104 ppm / °C in the range above the glass transition temperature.

[0014] Existing underfill processes often focus only on shrinkage rate at room temperature when selecting materials, lacking high-precision dual-temperature zone control to address thermal expansion mismatch between the bare die and the packaging substrate when crossing different temperature thresholds. This invention limits the coefficient of thermal expansion (CTE) of the underfill adhesive to 28 ppm / °C below the glass transition temperature (Tg) and 104 ppm / °C above the Tg. The thermal expansion properties between silicon-based bare dies and PCB / ceramic substrates differ by orders of magnitude, resulting in significant shear stress at the interface. By precisely anchoring the Tg CTE to an extremely low 28 ppm / °C through a specific filler ratio, the interfacial stress of the product during room and low-temperature use is greatly reduced; simultaneously, setting the Tg CTE to 104 ppm / °C provides excellent buffering flexibility at extremely high temperatures. This precise matching of dual temperature zones endows the adhesive layer with extremely strong stress absorption capacity from the thermodynamics of the material, enabling the product to have sufficient deformation matching margin when facing sudden changes in ultra-high temperature such as subsequent 260°C secondary reflow soldering, completely eliminating the phenomenon of interface peeling or micro-bump tearing and breakage caused by uneven thermal expansion.

[0015] Furthermore, in the step of applying the underfill adhesive along a straight path along one outer boundary of the bare chip, or along two adjacent outer boundaries of the bare chip along a right-angled zigzag path, the overflow width of the underfill adhesive at the edge of the bare chip on the adhesive inlet side is less than 1 mm; the overflow width of the underfill adhesive at the edge of the bare chip on the adhesive outlet side is less than 0.35 mm.

[0016] Conventional dispensing processes lack precise numerical limits on the width of adhesive overflow at the edges for macroscopic molding control, making them susceptible to subjective process parameters that can lead to severe adhesive buildup or insufficient supply. This invention limits the overflow width of the bottom filler adhesive to less than 1mm on the injection side and less than 0.35mm on the exit side. By strictly constraining the overflow width on both sides within these small and specific numerical ranges, on the one hand, the volume shrinkage rate of the adhesive at the chip edges during subsequent curing is precisely controlled, avoiding the large, uneven tensile stress generated by excess adhesive at the periphery under alternating vacuum and positive pressure (this stress can easily induce hidden voids at the chip edges); on the other hand, strictly controlling the exit side to less than 0.35mm effectively prevents adhesive creep and contamination of adjacent SMT precision sensitive devices. This not only ensures the defect-free and dense micro-filling but also significantly improves the electrical safety distance and appearance quality of wafer-level high-density mixed-assembly boards.

[0017] Furthermore, in the step of performing the heating process on the substrate, the temperature setting range of the first constant temperature stage is 70°C to 80°C; the temperature setting range of the second constant temperature stage is 85°C to 95°C; and the temperature setting range of the third constant temperature stage is 155°C to 165°C.

[0018] Traditional heat curing equipment typically employs simple single-stage or two-stage wide-range temperatures for baking, without establishing a precise rheological temperature gradient deeply matched to the alternating vacuum and positive pressure environments. This invention defines three extremely specific temperature ranges: a first isothermal stage of 70°C to 80°C, a second isothermal stage of 85°C to 95°C, and a third isothermal stage of 155°C to 165°C. The division of these three specific temperature ranges represents a precise application of the activation energy of the bottom filler reaction: the first isothermal stage (70-80°C) provides the optimal environment for low-temperature flexible penetration and initial solvent evaporation. Applying negative pressure during this stage allows bubbles at extremely low viscosity to be rapidly extracted without the adhesive hardening; the second isothermal stage (85-95°C) coincides with the cross-linking latency period, where vacuum and positive pressure are gradually and alternately introduced. The slow establishment of the polymer pre-network, combined with external pressure, effectively squeezes out tiny residual bubbles; the third isothermal stage (155-165°C) serves as a high-temperature densification molding zone. Combined with positive pressure, this completely locks in the compressed micro-voids and completes rapid cross-linking and curing. This thermodynamic gradient and physical pressure change work seamlessly together, reducing the possibility of bubble retention.

[0019] Furthermore, the duration of the first isothermal stage is 25 minutes; The duration of the second isothermal stage is 40 minutes; The duration of the third isothermal stage is 30 minutes; The total duration of the heating process performed on the substrate is less than 2 hours.

[0020] Existing heating processes often rely on experience for time allocation. Too short a time results in incomplete degassing or insufficient cross-linking, while too long a time can easily lead to thermal aging and brittleness, severely slowing down production. This invention quantitatively limits the first stage to 25 minutes, the second stage to 40 minutes, and the third stage to 30 minutes, strictly controlling the total duration of the heating process to less than 2 hours. The 25-minute timeframe ensures sufficient but not excessive loss of initial low-temperature degassing and capillary filling; the 40-minute timeframe provides the optimal reaction time for the adhesive to undergo extreme microbubble extrusion and breathing at the critical cross-linking point under alternating pressure; and the 30-minute high temperature ensures complete release of internal stress within the polymer and dense formation of the physical structure. Through a scientifically sound formulation and synergistic hot-pressing, the total curing time is reduced to less than 2 hours. While achieving the quality standard of zero voids, this reduces the risk of overheating, yellowing, and embrittlement, and improves the production line efficiency for wafer-level mass production.

[0021] Furthermore, the substrate has a solder resist layer disposed toward the bare chip, and the surface flatness difference of the solder resist layer is in the range of 5μm to 15μm.

[0022] In traditional SMT (Surface Mount Technology) hybrid mounting, including both surface mount and flip chip mounting, the flatness control of the solder mask on the packaging substrate is relatively rough, often resulting in groove-like structures of varying depths on the microscopic surface. This invention limits the surface flatness variation of the solder mask layer to within the range of 5μm to 15μm. Excessive surface flatness variation leads to micrometer-level trenches on the substrate surface. These deep trenches easily trap flux residue and a large amount of air during unidirectional fluid propagation, forming stubborn voids that are difficult to remove. By requiring the solder mask flatness variation to be controlled within 5μm to 15μm, the trenches are eliminated from the underlying physical morphology of the substrate, ensuring that the microscopic contact lines of the capillary fluid surface remain absolutely uniform and smooth during propagation. The smooth physical characteristics of the substrate, combined with the microwave-activated highly hydrophilic surface above, form an ideal fluid channel, providing a fundamental guarantee for achieving zero void defects in the final product.

[0023] A wafer-level SMT assembly is manufactured using the void-free underfill process described above for wafer-level SMT assemblies.

[0024] In surface mount components manufactured using conventional underfill processes, there is a high probability that microscopic air bubbles, invisible to the naked eye, are randomly hidden within the adhesive layer at the bottom of the chip and substrate. The final component product manufactured using the process described in this invention exhibits extremely dense microstructure and a perfectly void-free adhesive layer at the bottom of the bare chip (the void ratio is far below the industry-standard defect threshold). This fundamentally eliminates the risk of adhesive failure due to the instantaneous expansion of internal air bubbles, or micro-bump breakage, when the component faces harsh end-user environments, especially during the extremely severe high-temperature thermal expansion tests of secondary reflow oven reflow.

[0025] The beneficial effects of this invention are as follows: This invention provides a void-free underfill process for wafer-level SMT assembly. This process utilizes a microwave-excited plasma environment for surface activation, chemically breaking the chemical bonds at the micro-gap interface and introducing polar groups, significantly reducing the interface contact angle and eliminating microscopic resistance to subsequent adhesive penetration. By applying the underfill adhesive along a straight or right-angled zigzag path, macroscopic fluid dynamics ensure unidirectional wavefront propagation of the adhesive, completely eliminating the physical defects caused by air trapping due to complex closed-loop paths. The substrate is placed in an environment with a pressure lower than standard atmospheric pressure. In the first pressure environment, during the physical time window when the adhesive has not yet been heated and cross-linked and its viscosity is at its lowest, the initial large air bubbles are forcibly removed by initial negative pressure. Through a series of heating processes including a first, second, and third isothermal stage, a gradual, stepwise evaporation of the solvent is achieved, avoiding localized boiling and sealing of the adhesive caused by sudden temperature increases. During the heating process, the second pressure environment (lower than standard atmospheric pressure) and the third pressure environment (higher than standard atmospheric pressure) are alternately switched. While the negative pressure further draws out gas, the strong physical pressure of the positive pressure compresses the deep, unexpellable micro-voids to their limits. From surface energy modification, fluid path guidance, initial degassing to thermodynamic synergistic pressurization, the possibility of void formation is systematically reduced, contributing to truly void-free bottom filling and ensuring the reliability of wafer-level surface mount components during secondary reflow soldering. Attached Figure Description

[0026] Figure 1 A flowchart of the void-free bottom filling process for wafer-level SMT assembly provided by the present invention; Figure 2 This is a top view of the arrangement of the bottom filler adhesive applied using a straight path in an embodiment of the present invention; Figure 3 This is a top view schematic diagram of the bottom filler adhesive being applied using a right-angled zigzag path in an embodiment of the present invention; Figure 4Comparison of C-SAM (scanning ultrasonic microscope) inspection results for patch assemblies fabricated using existing processes and processes according to embodiments of the present invention; Figure 5 This is a cross-sectional microscopic image of the micro-gap and micro-bump regions inside the patch assembly obtained in an embodiment of the present invention. Detailed Implementation

[0027] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0028] Example 1

[0029] like Figures 1 to 5 As shown, this embodiment provides a void-free underfill process for wafer-level SMT assembly, which includes: The substrate with the bare chip mounted is placed in a microwave-energized plasma environment for surface activation treatment. The underfill adhesive is applied along one outer boundary of the bare chip in a straight line, or along two adjacent outer boundaries of the bare chip in a right-angled zigzag line. The substrate, after being coated with the bottom filler adhesive, is placed in a first pressure environment with an air pressure value lower than standard atmospheric pressure; A heating process is performed on the substrate; the heating process includes a first constant temperature stage, a second constant temperature stage, and a third constant temperature stage in sequence; during the heating process, the environment of the substrate is alternately switched between a second pressure environment and a third pressure environment; the pressure value of the second pressure environment is lower than the standard atmospheric pressure, and the pressure value of the third pressure environment is higher than the standard atmospheric pressure.

[0030] In the field of advanced semiconductor packaging, with the development of surface mount technology (SMT), it is often necessary to mount bare chips (such as electrical chips, optical chips, etc.) and SMT devices together on the same substrate. In order to alleviate the stress caused by the mismatch of thermal expansion coefficients between silicon-based chips and organic or ceramic substrates, and to protect the fragile bottom microbump structure, the industry's original common practice was to inject underfill adhesive into the bottom of the chip after mounting, and then send it into a conventional air oven or nitrogen oven for unidirectional heat curing.

[0031] However, existing underfill structures and curing methods face significant challenges. Due to the extremely small gaps between micro-pitch particles, coupled with solder resist trenches or flux residue on the substrate surface, air is easily trapped in the adhesive during capillary flow. During subsequent conventional atmospheric pressure heating, solvent evaporation readily generates new microbubbles, which are trapped by the viscous adhesive and cannot escape, eventually curing into voids. When such components undergo ultra-high temperature processes such as reflow soldering, the gas within the sealed voids expands rapidly, leading to fatal reliability failures such as adhesive bursting, overflow, and even micro-bump breakage.

[0032] To address the aforementioned pain points, this embodiment provides a void-free bottom filling process for wafer-level surface mount technology (SMT) chip assemblies. More specifically, the process includes the following steps: Step 1: Microwave-excited plasma activation treatment The substrate with the bare chips already mounted is placed in a plasma environment excited by microwave energy to activate the gap at the bottom of the chips and the surface of the substrate.

[0033] Traditional radio frequency plasma generates strong physical bombardment, which can easily cause minor damage to existing micro-bumps or surface passivation layers, and poses a risk of electrostatic discharge. In contrast, microwave-excited plasma produces more uniform and higher-density discharge, and is usually an electrodeless remote plasma mode. It mainly relies on chemical reactions (such as oxygen free radical reactions) to break the chemical bonds at the interface and introduce polar groups, thereby safely and significantly improving the hydrophilicity of the material surface and significantly reducing the contact angle of the adhesive.

[0034] The bare chip of the surface mount assembly can be a DSP chip, TIA chip, driver chip, PD chip, or PIC optical chip, etc.; the substrate can be a ceramic substrate, organic PCB substrate, or glass substrate, etc. The excitation microwave frequency can be 2.45 GHz, 915 MHz, or 5.8 GHz, etc.; the working gas of the plasma can be pure gas or a mixture of oxygen, argon, nitrogen, or hydrogen.

[0035] Step 2: Apply bottom filler adhesive to the specific path The underfill adhesive is applied along one outer boundary of the bare chip in a straight line (i.e., an I-shaped path), or along two adjacent outer boundaries of the bare chip in a right-angled zigzag path (i.e., an L-shaped path). Figure 2 and Figure 3 As shown, Figure 2 This demonstrates the layout of a straight (I-shaped) dispensing path. Figure 3The diagram shows the arrangement of a right-angled zigzag (L-shaped) dispensing path. In these two diagrams, the middle rectangle represents the bare chip (the diagram uses a PIC optical chip as an example), the thick black solid line immediately outside the rectangle represents the coating path of the bottom filler adhesive, and the arrows represent the initial coating of the adhesive and its propagation direction through capillary action within the micro-gap.

[0036] If a U-shaped or dot-matrix closed-loop dispensing path is used, the multiple adhesive streams can easily trap the air in the middle when they converge at the bottom of the chip, forming a huge central void. Using an open, straight or right-angled zigzag path can force the adhesive to advance forward in a single wavefront under the action of microscopic surface tension, thus driving away the air from a physical fluid dynamics perspective.

[0037] The coating tool can be a pneumatic dispensing valve, a piezoelectric jet valve, or a screw valve. The underfill adhesive used can be any commercially available epoxy resin adhesive, polyurethane adhesive, or acrylic underfill adhesive with rheological properties.

[0038] Step 3: Initial negative pressure degassing (first pressure environment) After the substrate is coated with the bottom filler, it is placed in a first pressure environment with an air pressure value lower than the standard atmospheric pressure for processing.

[0039] Immediately after dispensing, before the adhesive undergoes a cross-linking reaction due to heat, the viscosity of the adhesive is at its lowest. Applying negative pressure immediately allows for the forced extraction of macroscopic air bubbles trapped within the adhesive and initial air trapped in the dead corners of the micro-bumps with minimal resistance.

[0040] The equipment used to create this initial pressure environment can be a stand-alone vacuum degassing chamber or a curing oven cavity with a pre-vacuum function. The set negative pressure value can be any value lower than the standard atmospheric pressure, such as 10Pa, 100Pa, 1000Pa, or a semi-vacuum state.

[0041] Step 4: Synergistic curing of stepped heating and alternating pressure The substrate is subjected to a heating process, which is forcibly divided into a first isothermal stage, a second isothermal stage, and a third isothermal stage, performed sequentially. At the same time, during the entire heating process, the environment in which the substrate is located is alternately switched between a second pressure environment (negative pressure) below standard atmospheric pressure and a third pressure environment (positive pressure) above standard atmospheric pressure.

[0042] Direct high-temperature baking can cause the edges of the colloid to solidify and seal instantly, or even cause the solvent to boil over (colloid explosion). Using a stepped heating process with first, second, and third isothermal stages allows the solvent to evaporate slowly, and the adhesive to sequentially pass through the lowest viscosity period, the gelation period, and the final curing period. Even more ingeniously, alternating negative and positive pressures are applied during the heating and gelation process. The negative pressure continues to remove free gas, while the positive pressure (introducing gas and pressurizing) acts like an invisible hand, in the high-temperature later stage when the colloid is about to solidify, directly compressing and even crushing the very few deep, impenetrable micro-voids to their ultimate limit, thus completely locking in a perfect, void-free state.

[0043] The temperature gradient can be different combinations such as "60℃→100℃→150℃" or "80℃→120℃→165℃"; the positive pressure environment can be achieved by filling with nitrogen, pure compressed air or inert argon, and the positive pressure value can be 0.2MPa, 0.5MPa or 0.8MPa; the alternation frequency can be once every 10 minutes, or it can be dynamically switched in an irregular cycle according to the settings of each isothermal stage.

[0044] In this embodiment, surface treatment is performed using a plasma environment excited by microwave energy. This alters the surface energy of the gap between the substrate and the bottom layer of the chip without direct electrode contact, reducing the contact angle and improving the interfacial wettability during subsequent adhesive penetration. A linear or right-angled unidirectional dispensing path is used, allowing the bottom filler adhesive to advance unidirectionally under capillary action, reducing the probability of air entrapment when multiple adhesive streams converge in complex closed-loop paths. After adhesive filling is complete, a first pressure environment (negative pressure) is introduced. Utilizing the low viscosity of the adhesive before thermal cross-linking, macroscopic air bubbles trapped during dispensing are extracted. The heating process employs three-stage isothermal control, allowing the solvent to evaporate gradually along the temperature gradient, avoiding sudden high temperatures that could cause solvent boiling and pore formation. Simultaneously, negative and positive pressures are alternately applied during heating. Negative pressure helps the expanding gas escape, while positive pressure physically compresses residual micro-voids that are difficult to expel during the gradual solidification and shaping of the adhesive, effectively reducing the void ratio of the finished product.

[0045] Example 2

[0046] like Figures 1 to 5 As shown, this embodiment provides a void-free bottom filling process for wafer-level SMT assembly. This embodiment is a further elaboration based on the above embodiments.

[0047] Furthermore, in the process summarized in this embodiment, in the step of placing the substrate with the bare chip mounted in a microwave-energized plasma environment for surface activation treatment, the microwave frequency for energizing the plasma environment is 2.45 GHz, and the ambient temperature of the plasma environment is below 70°C.

[0048] The underfill adhesive comprises a base resin and a curing agent; The base resin is selected from at least one of bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenolic type epoxy resin and alicyclic epoxy resin; The curing agent is selected from at least one of aliphatic amine curing agents, aromatic amine curing agents, acid anhydride curing agents, and phenolic resin curing agents.

[0049] The bottom filler contains silica filler, the average particle size of the silica filler is 5 μm, and the maximum particle size of the silica filler is less than 20 μm; The dynamic viscosity of the bottom filler is in the range of 10 Pa·s.

[0050] The underfill adhesive has an inherent glass transition temperature; The coefficient of thermal expansion of the underfill adhesive is 28 ppm / °C in the range below the glass transition temperature and 104 ppm / °C in the range above the glass transition temperature.

[0051] In the step of applying the underfill adhesive along a straight path along one outer boundary of the bare chip, or along two adjacent outer boundaries of the bare chip along a right-angled zigzag path, the overflow width of the underfill adhesive at the edge of the bare chip on the adhesive inlet side is less than 1 mm; the overflow width of the underfill adhesive at the edge of the bare chip on the adhesive outlet side is less than 0.35 mm.

[0052] The substrate has a solder resist layer disposed facing the bare chip, and the surface flatness difference of the solder resist layer is in the range of 5 μm to 15 μm.

[0053] When faced with the hybrid mounting of high-density, ultra-fine pitch (flip-chip) high-end optical communication modules, conventional materials still exhibit significant rheological resistance at the microscale. Ordinary epoxy resin fillers are prone to agglomeration and jamming, and thermal stress mismatch under extremely high and low temperature alternating environments can still lead to implicit delamination at the interface. To push the void-free process to its limit and enable the product to have automotive-grade environmental resistance, Example 2, based on Example 1, further precisely defined the plasma energy parameters, material chemical formulation, physical rheological properties, and substrate bottom layer structure.

[0054] More specifically, the process in this embodiment includes the following steps: Pre-process preparation: Customization of substrate and adhesive This invention provides a PCB substrate for wafer-level surface mount technology (SMT) and enables mixed surface mount assembly of bare chips (such as optical communication PIC chips) and conventional SMT devices. To eliminate microscopic traps, the solder mask layer facing the bare chip is manufactured using a dry film process, strictly controlling the surface flatness difference within the range of 5μm to 15μm, thereby avoiding the formation of trench-like dead corners that easily trap air.

[0055] A specialized low-viscosity underfill adhesive was formulated. The base resin was a mixture of bisphenol A and bisphenol F epoxy resins, combined with an anhydride curing agent to achieve excellent latent crosslinking properties. Nanoscale silica filler was incorporated into the adhesive, rigorously sieved to control the average particle size to 5 μm and ensure the maximum particle size was absolutely less than 20 μm to prevent physical jamming between micro-pitch bumps. The dynamic viscosity of the formulated underfill adhesive was adjusted to approximately 10 Pa·s. Thermomechanical analysis (TMA) determined that the adhesive's coefficient of thermal expansion was 28 ppm / °C below its glass transition temperature (Tg) and 104 ppm / °C above Tg, achieving optimal thermal stress matching with the silicon-based chip and substrate.

[0056] Step 1: Ultra-low damage microwave plasma activation The substrate with the bare chip mounted on it is placed into the sealed cavity of the microwave plasma cleaning system. The microwave generator is activated, and the microwave frequency for exciting the plasma environment is set to a specific 2.45 GHz, generating a high density of oxygen free radicals in a remote electrodeless mode. Throughout the activation process, the ambient temperature of the plasma environment is strictly controlled below 70°C using a cooling system.

[0057] This step utilizes the characteristics of 2.45GHz microwaves to reduce the contact angle of the underfill gap interface from the conventional 45° or more to about 21° without causing any physical ion bombardment damage, electrostatic risks, or chip thermal aging, thus giving the microgap extreme hydrophilic wettability.

[0058] Step 2: One-way coating with precise overflow control Use high-precision piezoelectric injection valves or screw valves, such as Figure 2 As shown, along a linear path along one of the outer boundaries of the bare chip, or as... Figure 3 As shown, the prepared bottom filler with a viscosity of 10 Pa·s is evenly applied along the two adjacent outer boundaries in a right-angled zigzag path.

[0059] During the coating process, visual recognition and a precision fluid volume control system are used to strictly limit the rise and overflow of the adhesive under capillary action, so that the overflow width of the bottom filler adhesive at the edge of the bare chip on the adhesive inlet side is strictly less than 1 mm, and the overflow width at the edge of the bare chip on the adhesive outlet side is strictly less than 0.35 mm.

[0060] Step 3: Initial negative pressure defoaming during the gold rheological window Before the bottom filler has fully penetrated the micro-gap and before the curing agent has undergone a cross-linking reaction due to heat (i.e., the adhesive is in its optimal flow window), the substrate is immediately moved into a vacuum chamber. The air is then evacuated to place the substrate in a first pressure environment with a pressure value lower than the standard atmospheric pressure (e.g., a vacuum of tens of Pascals). The substrate is kept still to degas, and the macroscopic air bubbles remaining during the filling process are forcibly extracted.

[0061] Step 4: Curing with alternating pressure based on conventional stepped temperature increases The pre-degassed substrate is transferred into a variable pressure thermosetting device, and the heating process is started. The substrate sequentially goes through the first isothermal stage, the second isothermal stage, and the third isothermal stage (the specific temperature and time parameters for this stage can adopt the industry-standard three-stage setting, such as preheating, gelling, and main curing).

[0062] During the entire heating process, the PLC control system dynamically adjusts the chamber pressure, alternating between a second pressure environment (vacuum, absolute pressure below standard atmospheric pressure) and a third pressure environment (e.g., filled with high-purity nitrogen, absolute pressure above standard atmospheric pressure). This process utilizes negative pressure for continued venting and positive pressure to completely crush invisible micro-voids during the later stages of polymer cross-linking, ultimately producing a void-free, highly reliable wafer-level surface mount assembly.

[0063] In this embodiment, the microwave frequency is limited to 2.45 GHz and the operating temperature is below 70°C. This achieves surface activation while reducing physical ion bombardment and thermal stress damage to the sensitive bare chip microbumps. The average particle size of the silica filler is controlled to 5 μm, with a maximum of no more than 20 μm. Combined with a dynamic viscosity of 10 Pa·s, this improves the physical permeability of the adhesive in the gaps between the microbumps and reduces the risk of local blockage caused by particle agglomeration. The coefficients of thermal expansion of the adhesive before and after Tg are controlled to 28 ppm / °C and 104 ppm / °C, respectively, so that it can better match the deformation difference between the silicon-based chip and the packaging substrate in different temperature zones and reduce the interfacial shear stress in temperature cycling tests. The surface difference of the solder mask is controlled to 5-15 μm, and the adhesive overflow width at both ends of the bare chip is precisely limited to the millimeter and sub-millimeter level (<1 mm and <0.35 mm). This not only reduces the possibility of air trapped in the substrate trenches, but also prevents uneven shrinkage stress and contamination of adjacent components caused by excessive adhesive overflow.

[0064] Example 3

[0065] like Figures 1 to 5 As shown, this embodiment provides a void-free bottom filling process for wafer-level SMT assembly. This embodiment is a further elaboration based on the above embodiments.

[0066] Furthermore, in the process of this embodiment, in the step of performing the heating process on the substrate, the temperature setting range of the first constant temperature stage is 70°C to 80°C; the temperature setting range of the second constant temperature stage is 85°C to 95°C; and the temperature setting range of the third constant temperature stage is 155°C to 165°C.

[0067] The duration of the first isothermal stage is 25 minutes; The duration of the second isothermal stage is 40 minutes; The duration of the third isothermal stage is 30 minutes; The total duration of the heating process performed on the substrate is less than 2 hours.

[0068] More specifically, this embodiment, through stringent time constraints on heating time, stepped temperature, and alternating pressure, completely eliminates deep micro-voids, ultimately producing a highly reliable physical product that can perfectly withstand the test of secondary reflow soldering. The specific operation steps are as follows: A wafer-level surface mount technology substrate with pre-assembled bare dies and conventional devices is provided. The substrate is placed in a microwave-excited plasma environment for surface activation to reduce the contact angle of the micro-gap. Subsequently, an underfill adhesive is applied along one peripheral boundary of the bare die in a straight line, or along two adjacent peripheral boundaries of the bare die in a right-angled zigzag line, relying on physical capillary action to allow the adhesive to penetrate unidirectionally into the micro-gap at the bottom of the bare die.

[0069] Before the underfill adhesive has physically penetrated but before it has chemically crosslinked due to heat, immediately transfer the substrate coated with the underfill adhesive to a sealed vacuum chamber. Start the vacuum equipment and place the substrate in a first pressure environment with a pressure value lower than standard atmospheric pressure (e.g., evacuate to an absolute pressure of about 100 Pa).

[0070] During the golden physical time window when the adhesive viscosity is lowest and the fluidity is strongest, the initial negative pressure is used to forcibly remove macroscopic air bubbles entrained during the dispensing process and air trapped in dead corners.

[0071] The pre-degassed substrate is transferred into a constant-temperature heating furnace equipped with alternating pressure, and a heating process is performed on the substrate. To avoid solvent boiling and splattering caused by direct high temperature, the thermodynamic curve is specially designed in this embodiment: First isothermal stage (low-temperature penetration and slow volatilization zone): The oven temperature should be set between 70°C and 80°C, and the duration of this stage should be strictly controlled to 25 minutes. At this point, the adhesive is at its lowest viscosity, and the solvent begins to evaporate slowly.

[0072] Second isothermal stage (gel critical point and microbubble extrusion zone): The temperature was gradually increased, with the temperature set between 85°C and 95°C, and the duration strictly controlled to 40 minutes. At this point, the colloid officially entered the cross-linking latency period, and the polymer network began to slowly build up, exhibiting a gel state.

[0073] Third isothermal stage (high-temperature densification forming zone): The temperature is then gradually increased in stages, with the temperature set between 155°C and 165°C, and the duration strictly controlled for 30 minutes. This stage promotes complete cross-linking of the epoxy resin macromolecules and releases internal stress.

[0074] During the entire heating process described above, the control system forces the environment of the substrate to switch frequently between a second pressure environment (a negative pressure for pumping air with an absolute pressure lower than the standard atmospheric pressure) and a third pressure environment (a positive pressure for filling gas with an absolute pressure higher than the standard atmospheric pressure, such as filling with high-purity nitrogen at 0.5 MPa).

[0075] In the first and second isothermal stages, the alternating negative pressure is responsible for removing the deep free gas that expands due to heat. At the end of the second stage and in the third isothermal stage, when the cross-linked network is about to harden and solidify, the alternating positive pressure will subject the very few micron-sized residual pores that cannot escape to extreme physical compression, or even crush them to collapse.

[0076] The total duration of the entire heating process is forcibly limited to less than 2 hours. This achieves the minimum requirement of zero voids while avoiding the risk of thermal aging, such as yellowing or embrittlement of the substrate due to prolonged high-temperature baking, thus significantly increasing production line capacity.

[0077] To verify the actual effectiveness of the process in this embodiment, the processed product underwent internal non-destructive testing and physical cross-section analysis. For example... Figure 4 As shown, Figure 4 These are comparison images of C-SAM (Cellular-Scanning Acoustic Microscopy) detection. From... Figure 4 As can be seen on the left, in the defective product prepared using the existing conventional process without alternating pressure and plasma intervention, a large number of ultrasonic reflection anomalies are randomly distributed on the bottom of the bare chip (circled in the image), indicating that there are obvious residual air bubbles inside; while observing Figure 4 On the right, a normal product prepared using the above-described process of the present invention has a uniform grayscale across the entire chip substrate area, with no voids or defects observed.

[0078] Furthermore, combined Figure 5 The microscopic morphology of the bottom section shows that after physical cross-sectioning, the bottom filler has densely and uniformly wrapped and filled all the microbumps and tiny gaps on the bottom of the bare chip; the micron-level filler is evenly distributed, and no particles are stuck, bridged or residual air gaps are observed in the extremely narrow structural gaps. Figure 4 and Figure 5 The microscopic verification results objectively confirm that this process completely eliminates internal encapsulated bubbles. When the component is put into end-use application or undergoes a secondary reflow soldering process, it can fundamentally avoid the hidden dangers of bottom explosion and micro-bump breakage caused by the rapid expansion of bubbles due to heat, and achieves high electrical stability and long mechanical life.

[0079] In this embodiment, three clearly defined temperature ranges (70-80°C, 85-95°C, 155-165°C) and their corresponding holding times (25 min, 40 min, 30 min) precisely correspond to the low-viscosity flow period, gelation period, and final cross-linking and molding period of the underfill adhesive. This temperature gradient and alternating positive and negative pressure changes maintain a synchronous response on the time axis, ensuring that venting and micro-gap compression occur at the most suitable material rheological nodes. The total heating time is constrained to within 2 hours, reducing the risk of substrate yellowing and thermal aging embrittlement caused by prolonged heating of the substrate and chip, while also considering production efficiency, while meeting the cross-linking and curing depth requirements. Wafer-level surface mount technology (SMT) components manufactured using this process exhibit high density of the underfill adhesive and low measured void ratio. During subsequent secondary reflow soldering processes such as 260°C, the probability of failure due to underfill adhesive cracking, overflow, or micro-bump breakage induced by the thermal expansion of internal encapsulated gas is reduced, improving the reliability and yield of the final component.

[0080] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this application. Any specific values ​​in all examples shown and discussed herein should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0081] Furthermore, it should be noted that the use of terms such as "first" and "second" is merely for ease of distinction, and unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application.

[0082] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A void-free bottom filling process for wafer-level SMT assembly, characterized in that, include: The substrate with the bare chip mounted is placed in a microwave-energized plasma environment for surface activation treatment. The underfill adhesive is applied along one outer boundary of the bare chip in a straight line, or along two adjacent outer boundaries of the bare chip in a right-angled zigzag line. The substrate, after being coated with the bottom filler adhesive, is placed in a first pressure environment with an air pressure value lower than standard atmospheric pressure; A heating process is performed on the substrate; the heating process includes a first constant temperature stage, a second constant temperature stage, and a third constant temperature stage in sequence; during the heating process, the environment of the substrate is alternately switched between a second pressure environment and a third pressure environment; the pressure value of the second pressure environment is lower than the standard atmospheric pressure, and the pressure value of the third pressure environment is higher than the standard atmospheric pressure.

2. The void-free bottom filling process for wafer-level SMT assembly according to claim 1, characterized in that: In the step of placing the substrate with the bare chip mounted in a microwave-excited plasma environment for surface activation treatment, the microwave frequency for exciting the plasma environment is 2.45 GHz, and the ambient temperature of the plasma environment is below 70°C.

3. The void-free bottom filling process for wafer-level SMT assembly according to claim 1, characterized in that: The underfill adhesive comprises a base resin and a curing agent; The base resin is selected from at least one of bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenolic type epoxy resin and alicyclic epoxy resin; The curing agent is selected from at least one of aliphatic amine curing agents, aromatic amine curing agents, acid anhydride curing agents, and phenolic resin curing agents.

4. The void-free bottom filling process for wafer-level SMT assembly according to claim 3, characterized in that: The bottom filler also includes silica filler, the silica filler having an average particle size of 5 μm and a maximum particle size of less than 20 μm; The dynamic viscosity of the bottom filler is in the range of 10 Pa·s.

5. The void-free bottom filling process for wafer-level SMT assembly according to claim 1, characterized in that: The underfill adhesive has an inherent glass transition temperature; The coefficient of thermal expansion of the underfill adhesive is 28 ppm / °C in the range below the glass transition temperature and 104 ppm / °C in the range above the glass transition temperature.

6. The void-free bottom filling process for wafer-level SMT assembly according to claim 1, characterized in that: In the step of applying the underfill adhesive along a straight path along one outer boundary of the bare chip, or along two adjacent outer boundaries of the bare chip along a right-angled zigzag path, the overflow width of the underfill adhesive at the edge of the bare chip on the adhesive inlet side is less than 1 mm; the overflow width of the underfill adhesive at the edge of the bare chip on the adhesive outlet side is less than 0.35 mm.

7. The void-free bottom filling process for wafer-level SMT assembly according to claim 1, characterized in that: In the step of performing the heating process on the substrate, the temperature setting range of the first constant temperature stage is 70°C to 80°C; the temperature setting range of the second constant temperature stage is 85°C to 95°C; and the temperature setting range of the third constant temperature stage is 155°C to 165°C.

8. The void-free bottom filling process for wafer-level SMT assembly according to claim 7, characterized in that: The duration of the first isothermal stage is 25 minutes; The duration of the second isothermal stage is 40 minutes; The duration of the third isothermal stage is 30 minutes; The total duration of the heating process performed on the substrate is less than 2 hours.

9. The void-free bottom filling process for wafer-level SMT assembly according to claim 1, characterized in that: The substrate has a solder resist layer disposed facing the bare chip, and the surface flatness difference of the solder resist layer is in the range of 5 μm to 15 μm.

10. A wafer-level SMT assembly, characterized in that, It is manufactured by a void-free underfill process for wafer-level SMT assembly as described in any one of claims 1 to 9.

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