Chip stacking structure and manufacturing method thereof, chip packaging structure, and electronic device

Abstract

The application provides a chip stacking structure and a manufacturing method thereof, a chip packaging structure and an electronic device, and relates to the technical field of packaging. The application provides a chip stacking structure, which comprises a first chip, a plurality of second chips, at least one carrier plate and a molding layer. The plurality of second chips are arranged on the first chip. The carrier plate is arranged on the side of the plurality of second chips away from the first chip. The molding layer is filled into the gap between the adjacent second chips and wraps the side of the plurality of second chips and the carrier plate. The chip stacking structure can be bonded to the carrier plate on the back of the stacking structure in a C2C (chip to chip) mode, and the gap between the chips can be filled by a molding process, so that the manufacturing cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a chip stacking structure and its fabrication method, a chip packaging structure, and an electronic device. Background Technology

[0002] As chip manufacturing processes gradually approach the limits of physical dimensions, 3D (three-dimensional) packaging technology has become an important technical route to improve chip integration and performance. However, as the spacing between chip interconnect pins in 3D packaging continues to shrink, conventional microbump (μbump) processes can no longer meet the requirements, and hybrid bonding processes are gradually becoming one of the key technologies for 3D stacked packaging and architecture design.

[0003] refer to Figure 1 As shown, some existing 3D packaging methods first use a C2W (chip to wafer) HB (hybrid bonding) approach to stack the chips. After C2W, a costly CVD (chemical vapor deposition) process is used to fill the gaps between the chips and provide protection. Furthermore, chips packaged using this C2W HB method are relatively thin and prone to localized hot spots during operation. Therefore, a W2W (wafer to wafer) approach is needed to bond a carrier wafer on top of the stacked structure to reduce the chip temperature. Finally, the chips are diced to form individual 3D stacked packages.

[0004] The above-mentioned manufacturing process requires the use of costly CVD technology and W2W bonding of the substrate, which increases the cost of the packaging structure. Summary of the Invention

[0005] This application provides a chip stacking structure and its fabrication method, a chip packaging structure, and an electronic device. The carrier board is bonded to the back of the stacking structure using a C2C (chip to chip) method, and the gaps between the chips are filled using a molding process, which can reduce the manufacturing cost.

[0006] This application provides a chip stacking structure, which includes a first chip, a plurality of second chips, at least one carrier board, and a molding layer. The plurality of second chips are disposed on the first chip. The carrier board is disposed on the side of the plurality of second chips away from the first chip. The molding layer fills the gaps between adjacent second chips and covers the sides of the plurality of second chips and the carrier board.

[0007] In this chip stacked packaging structure, a molding layer fills the gaps between adjacent second chips and wraps the sides of multiple second chips and the carrier board. In other words, the molding layer encapsulates the entire stacked structure after the carrier wafer is bonded to the second chips. Since the thickness of the entire stacked structure is relatively large after the carrier wafer is bonded to the second chips, it meets the requirements of the molding process. Compared to the existing technology that requires a costly CVD process to fill the gaps between chips, this application uses a molding layer to fill the gaps between multiple second chips and wrap the sides of the second chips and the carrier board, which not only improves the stability of the stacked structure but also reduces manufacturing costs. Furthermore, this application uses a C2C method instead of the existing W2W (wafer to wafer) method for bonding the carrier board, which further reduces manufacturing costs.

[0008] In some possible implementations, the chip stack structure includes a carrier board that covers all the second chips. In this case, the carrier board can dissipate the heat generated by the multiple second chips during operation, thus preventing localized hot spots from forming during chip operation.

[0009] In some possible implementations, the chip stacking structure includes multiple carrier boards, with each carrier board covering one or more second chips. The heat generated by the multiple second chips during operation is dissipated through the multiple carrier boards, thus preventing localized hot spots from forming during chip operation.

[0010] In some possible implementations, the chip stack structure also includes a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are disposed between the second chip and the carrier board, and the second metal layer is located on the side of the first metal layer closer to the carrier board. Since metals have higher thermal conductivity, the heat dissipation capacity of the stack structure can be improved through the metal layers.

[0011] In some possible implementations, the molding layer includes a resin, and the resin contains at least one of a high thermal conductivity material such as diamond, boron nitride, alumina (Al₂O₃), aluminum nitride (AlN), or silicon micropowder. Adding a high thermal conductivity material to the resin can improve the structure's heat dissipation capacity.

[0012] In some possible implementations, the first chip and the second chip are connected using hybrid bonding. This bonding method can accommodate interconnect pin pitches below 10μm, thereby increasing interconnect density.

[0013] In some possible implementations, the material forming at least one carrier plate includes at least one of silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), silicon nitride (SiN), and diamond.

[0014] This application also provides a method for fabricating a chip stack structure, which may include: providing a first wafer; a plurality of first chips are disposed on the first wafer; bonding a plurality of second chips onto the first chips using a chip-to-wafer (C2W) method; bonding one or more carrier boards onto the plurality of second chips using a chip-to-chip (C2C) method; forming a molding compound layer using a molding process to encapsulate the plurality of second chips and the carrier boards, and filling the gaps between adjacent second chips; cutting along the side region of the first chips to form a single-chip stack structure; wherein, on the side of the chip stack structure, the molding compound layer encapsulates the plurality of second chips and the carrier boards.

[0015] The manufacturing method of this application uses a C2C approach to bond a carrier board to the second chip, and uses a molding process to fill the gaps between the second chips, so that the sides of the second chip and the carrier board are molded and encapsulated, which can improve the stability of the product and reduce the manufacturing cost.

[0016] In some possible implementations, the aforementioned bonding of multiple second chips onto the first chip can include: employing a hybrid bonding process to bond multiple second chips onto the first chip. This bonding method can achieve interconnect pin pitches below 10 μm, thereby increasing interconnect density.

[0017] In some possible implementations, before bonding one or more carrier boards onto the multiple second chips, the fabrication method may further include forming a metal layer on the surface of the second chips. Since metals have higher thermal conductivity, the metal layer can improve the heat dissipation capacity of the stacked structure.

[0018] This application also provides a chip packaging structure, which includes a substrate and a chip stack structure as provided in any of the aforementioned possible implementations, wherein the substrate and the chip stack structure are electrically connected. Since metals have higher thermal conductivity, the heat dissipation capacity of the stack structure can be improved through the metal layer.

[0019] This application also provides an electronic device, which includes a circuit board and a chip package structure as described above, wherein the circuit board and the chip package structure are electrically connected. Attached Figure Description

[0020] Figure 1 This provides a method for fabricating a 3D packaging structure in the prior art;

[0021] Figure 2 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0022] Figure 3This is a schematic diagram of a chip stacking structure provided in an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of a chip stacking structure provided in an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of a chip stacking structure provided in an embodiment of this application;

[0025] Figure 6 This is a schematic diagram showing the distribution of the second chip and the carrier board in a chip stacking structure provided in an embodiment of this application;

[0026] Figure 7 A flowchart illustrating a method for fabricating a chip stacking structure provided in this application embodiment;

[0027] Figure 8 A schematic diagram illustrating the fabrication process of a chip stacking structure provided in an embodiment of this application;

[0028] Figure 9 A schematic diagram illustrating the fabrication process of a chip stacking structure provided in this application embodiment;

[0029] Figure 10 A schematic diagram illustrating the fabrication process of a chip stacking structure provided in this application embodiment;

[0030] Figure 11 A schematic diagram illustrating the fabrication process of a chip stacking structure provided in an embodiment of this application;

[0031] Figure 12 This is a schematic diagram illustrating the fabrication process of a chip stacking structure provided in an embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. "At least one" means one or more, and "more" means two or more. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, they can refer to electrical connections or mechanical connections; fixed connections or detachable connections or integral connections; direct connections or indirect connections through an intermediate medium; or internal communication between two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Terms such as “up,” “down,” “left,” and “right” are used only in relation to the orientation of the components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and they can change accordingly depending on the orientation of the components in the accompanying drawings.

[0034] This application provides an electronic device with a chip packaging structure. The chip packaging structure adopts a novel chip stacking structure (also known as a 3D chip). During the manufacturing process, a carrier board is bonded to the top of the stacking structure using a C2C (chip to chip) method, and the chip and carrier board are encapsulated as a whole using a molding process. The gaps between the chips are filled, which not only improves the stability of the stacking structure, but also reduces the manufacturing cost.

[0035] This application does not limit the form of the above-mentioned electronic device. The electronic device can be any electronic product with a 3D chip, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronics, etc.

[0036] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can include servers, storage devices, radar, base stations, and other communication equipment.

[0037] Depending on the actual needs, the above-mentioned electronic device may also be equipped with other devices that are electrically connected to the 3D chip, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0038] For illustrative purposes only, please refer to the following: Figure 2 As shown, this application embodiment provides an electronic device 01, which includes a PCB and a chip packaging structure 1 disposed on the PCB. The chip packaging structure 1 includes a substrate Sub and a chip stack structure 10 (3D chip) disposed on the substrate Sub, as well as other chips, such as HMB (high bandwidth memory). The chip stack structure 10 adopts the novel structure provided by this application embodiment, which can not only improve the stability of the stack structure, but also reduce the manufacturing cost.

[0039] Furthermore, this application does not impose any restrictions on the configuration or application field of the chip stacking structure 10; in practice, it can be configured as needed.

[0040] As illustrated, in some possible implementations, the chip stack structure 10 described above can be a system on chip (SOC), a central processing unit (CPU), a graphics processing unit (GPU), etc.

[0041] The novel chip stacking structure 10 provided in the embodiments of this application will be further described below.

[0042] For illustrative purposes only, please refer to the following: Figure 3 As shown, this application embodiment provides a chip stacking structure 10, which includes a first chip D1 (also referred to as a first die), a plurality of second chips D2 (also referred to as second dies), and a carrier 100. The plurality of second chips D2 are stacked on the first chip D1, and the carrier 100 is stacked on the plurality of second chips D2.

[0043] As illustrated, the second chip D2 is bonded to the first chip D1, and the carrier 100 is bonded to the second chip D2. The bonding type can be set as needed, and this application does not limit it.

[0044] It should be understood that the carrier 100 is mainly designed to improve the heat dissipation efficiency of the stacked structure.

[0045] As illustrated, in some possible implementations, the second chip D2 is connected to the first chip D1 using a hybrid bonding (HB) method. Because the stacked structure is relatively thin, hot spots are prone to occur during operation. By using a carrier 100, heat dissipation efficiency is improved, thereby reducing the chip temperature.

[0046] As illustrated, in some possible implementations, the carrier 100 and the second chip D2 can be bonded together using methods such as fusion bonding (FB), thermal interface material (TIM), paste, or solder.

[0047] This application does not impose any restrictions on the material of the carrier 100; in practice, it can be set as needed.

[0048] As illustrated, the carrier 100 can be made of at least one of the following materials: silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), silicon nitride (SiN), and diamond. For example, in some possible implementations, the carrier 100 can be made of silicon.

[0049] Based on this, continue to refer to Figure 3 As shown, the chip stack structure 10 also includes a molding layer 200, which wraps around the sides of the second chip D2 and the carrier 100 and fills the gaps between the multiple second chips D2. In other words, the molding layer 200 encapsulates the entire stack structure after the carrier 100 is bonded to the second chips D2. Since the thickness of the entire stack structure is relatively large after the carrier 100 is bonded to the second chips D2, it meets the requirements of the molding process.

[0050] Furthermore, compared to existing technologies that require costly CVD processes to fill the areas between chips, this application uses a molding layer 200 to fill the gaps between multiple second chips D2 and to wrap the sides of the second chips D2 and the carrier board 100. This improves the stability of the stacked structure and significantly reduces manufacturing costs.

[0051] Since this application requires the use of molding processes to fill the gaps between multiple second chips D2, a C2C method can be used instead of the W2W method used in the prior art to bond the substrate, thereby further reducing manufacturing costs.

[0052] This application does not impose any restrictions on the specific material of the molding layer 200; in practice, it can be set as needed.

[0053] Indicatively, in some possible implementations, the aforementioned molding layer 200 may be made of resin-based materials, such as epoxy molding compound (EMC), but is not limited to this.

[0054] Of course, in order to enhance the thermal conductivity of the molding layer 200, one or more of the following high thermal conductivity materials may be added to the molding layer 200 in some possible ways: diamond, boron nitride, aluminum oxide Al2O3, aluminum nitride AlN, and silicon micro powder.

[0055] In addition, this application does not limit the number of carrier wafers 100 in the chip stacking structure 10, which can be set as needed in practice.

[0056] For example, in some possible implementations, such as Figure 3 As shown, the chip stack structure 10 may include a carrier board 100, which covers multiple second chips D2 and is integrally bonded to the multiple second chips D2. In this case, the carrier board 100 can dissipate the heat generated by the multiple second chips D2 during operation, thereby avoiding local hot spots in the chips during operation.

[0057] For example, in some possible implementation methods, such as Figure 4 As shown, the chip stack structure 10 may include multiple carrier boards 100, each carrier board 100 being bonded to a second chip D2. In this case, the heat generated by the multiple second chips D2 during operation is dissipated through the multiple carrier boards 100, thereby preventing localized hot spots from appearing during chip operation.

[0058] Of course, in some other possible implementations, the chip stack structure 10 includes multiple carrier boards 100. Depending on the actual needs, some carrier boards 100 can be bonded to a single second chip D2, and some carrier boards 100 can be bonded to multiple second chips D2.

[0059] When the chip stacking structure 10 includes multiple carrier boards 100, the materials, specifications, and dimensions of the multiple carrier boards 100 can be set according to actual needs. The materials, specifications, and dimensions of the multiple carrier boards 100 do not have to be exactly the same. This application does not impose any restrictions on this, and the settings can be made as needed in practice.

[0060] Building upon this, to further improve the heat dissipation capability of the stacked structure, a metal layer can be used for bonding between the carrier board 100 and the second chip D2. Since the metal layer is very thin (<100nm) and has higher thermal conductivity, the heat dissipation capability of the stacked structure can be improved.

[0061] For illustrative purposes only, please refer to the following: Figure 5 As shown, in some possible implementations, the chip stack structure 10 may further include a first metal layer 300 and a second metal layer 400, located between the second chip D2 and the carrier 200. The first metal layer 300 is located on the side closer to the second chip D2, and the second metal layer 400 is located on the side closer to the carrier 200. During fabrication, the first metal layer 300 can be fabricated on the upper surface of the second chip D2 (i.e., the side facing the carrier 200), and the second metal layer 400 can be fabricated on the lower surface of the carrier 100 (i.e., the side facing the second chip D2). The first metal layer 300 and the second metal layer 400 are bonded together. The first metal layer 300 and the second metal layer 400 can improve the heat dissipation capability of the stack structure.

[0062] The first metal layer 300 and the second metal layer 400 can be made of the same material and have the same structure, or they can be made of different materials and have different structures. This application does not impose any restrictions on this, and in practice, they can be set as needed.

[0063] In addition, the application-based setup method does not restrict the arrangement, quantity, type, size, or specifications of the chips and carrier boards. In practice, it can be set according to the needs.

[0064] For illustrative purposes only, please refer to the following: Figure 6 As shown in (a), (b), (c), and (d), a chip stack structure 10 can include one carrier board 200, or two or more carrier boards 200. Similarly, a carrier board can cover one second chip D2, or two or more second chips D2. The arrangement of the second chip D2 and the carrier board 200 can be configured as needed.

[0065] The following section provides a further explanation of the chip stacking structure 10, in conjunction with the manufacturing method.

[0066] As illustrated, this application embodiment also provides a method for fabricating the chip stacking structure 10 as described above, referring to... Figure 7 As shown, the manufacturing method may include:

[0067] Step 11, Reference Figure 8 As shown, a first wafer W1 is provided; wherein, a plurality of first chips D1 are disposed on the first wafer W1.

[0068] Figure 8 (a) is a planar schematic diagram of the first wafer W1, and (b) is a cross-sectional schematic diagram.

[0069] For illustrative purposes only, please refer to the following: Figure 8 As shown, in some possible implementations, step 11 may include: providing a silicon wafer (W1) on which a plurality of first chips D1 are disposed. One of the first chips D1 serves as the bottom chip in a 3D chip (chip stacking structure). Subsequently, bonding pads (such as copper pads) can be fabricated on the bottom of the silicon wafer (W1) using techniques such as photolithography, electroplating, and chemical mechanical polishing. The bonding pads are then polished using chemical mechanical polishing equipment to reduce roughness and clean the surface. The bonding pads can be made of conductive materials such as copper (Cu) or aluminum (Al), and the dielectric material around the bonding pads can be materials such as polyimide (PI) or silicon dioxide (SiO2).

[0070] Step 12, Reference Figure 9 As shown, a C2W (chip-to-wafer) method is used to bond multiple second chips D2 onto the first chip D1.

[0071] For illustrative purposes only, please refer to the following: Figure 9 As shown, in some possible implementations, step 12 may include: using a C2W (Chip-to-Whip) method, multiple second chips D2 are flip-chip bonded to the bottom first chip D1 via a hybrid bonding process (HB). In this case, the bonding pads (e.g., copper pads) on the surface of the second chips D2 are connected to the bonding pads (e.g., copper pads) on the surface of the first chip D1, forming a data interconnect channel. Then, the backside of the second chips D2 is subjected to backside grinding (BG) and chemical vapor deposition (CMP) to reduce the thickness and surface roughness of the second chips.

[0072] Step 13, Reference Figure 10As shown, one or more carrier boards 100 are bonded onto multiple second chips D2 using a C2C (chip-to-chip) method.

[0073] For illustrative purposes only, please refer to the following: Figure 10 As shown, in some possible implementations, step 13 may include bonding the carrier 100 to the second chip D2 one-to-one using a C2C method. The carrier 100 and the second chip D2 can be bonded using methods such as fused bonding (FB), thermal interface material (TIM), paste, or solder. The carrier 100 can be made of at least one of the following materials: silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), silicon nitride (SiN), or diamond.

[0074] Among other possible implementation methods, see [reference]. Figure 5 As shown, before bonding the carrier plate 100 onto the second chip D2, a physical vapor deposition (PVD) process can be used to form a first metal layer 300 on the upper surface of the second chip D2 and a second metal layer 400 on the lower surface of the carrier plate 100. This allows the first metal layer 300 and the second metal layer 400 to further improve the heat dissipation capability of the stacked structure. For specific details regarding the configuration of the first metal layer 300 and the second metal layer 400, please refer to the relevant explanations above.

[0075] Step 14, Reference Figure 11 As shown, a molding process is used to form a molding layer 200, which encapsulates multiple second chips D2 and a carrier board 100, and fills the gaps between adjacent second chips D2.

[0076] Illustratively, in some possible implementations, step 14 above may include: referencing Figure 11 As shown in Figure (a), epoxy resin is used to form a molding layer 200, which encapsulates multiple second chips D2 and a carrier board 100, and fills the gaps between the multiple second chips D2. The epoxy resin may contain one or more of the following high thermal conductivity materials: diamond, boron nitride, alumina (Al2O3), aluminum nitride (AlN), and silicon micropowder. (The text then continues with a reference to...) Figure 11 As shown in (b), back-side grinding (BG) and chemical mechanical polishing (CMP) can be used to remove excess molding compound from the top of the carrier board 100, exposing the carrier board 100 and reducing its surface roughness. Finally, the back side of the first chip D1 can also be thinned.

[0077] Step 15, Reference Figure 12As shown, the area along the side of the first chip D1 is cut to form a single chip stack structure 10; wherein, on the side of the chip stack structure 10, a molding compound 200 encapsulates multiple second chips D2 and a carrier board 100.

[0078] Illustratively, in some possible implementations, step 14 above may include: referencing Figure 11 As shown in (a) to (b), the wafer is cut into multiple independent chip stack structures 10 along the molding compound 200 on the side of the first chip D1 using methods such as laser cutting, blade cutting, and etching. In this case, the molding compound 200 will wrap around the side of the chip stack structure 10 (i.e., the cutting position) and the side of the carrier board 100.

[0079] Compared to existing technologies that use a costly CVD process to fill the gaps between chips and a W2W bonding method to bond the substrate, the fabrication method of this application uses a C2C method to bond the substrate 100 to the second chip D2 and uses a molding process to fill the gaps between the second chips D2, so that the sides of the second chip D2 and the substrate 100 are wrapped by the molding seal 200, which can improve the stability of the product and reduce the manufacturing cost.

[0080] It should be understood that, in the embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0081] For other related content in the above manufacturing method, please refer to the corresponding description in the aforementioned structural section, which will not be repeated here; for other settings in the aforementioned structural embodiments, please refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.

[0082] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip stacking structure, characterized in that, include: First chip; Multiple second chips are disposed on the first chip; At least one carrier board is disposed on the side of the plurality of second chips away from the first chip; A molding layer is applied to fill the gaps between adjacent second chips and to wrap the sides of the plurality of second chips and the carrier board.

2. The chip stacking structure according to claim 1, characterized in that, The chip stacking structure includes a carrier board, and the carrier board covers all the second chips.

3. The chip stacking structure according to claim 1, characterized in that, The chip stacking structure includes multiple carrier boards, with each carrier board covering one or more of the second chips.

4. The chip stacking structure according to any one of claims 1-3, characterized in that, The chip stacking structure also includes a first metal layer and a second metal layer; The first metal layer and the second metal layer are disposed between the second chip and the carrier board, and the second metal layer is located on the side of the first metal layer closer to the carrier board.

5. The chip stacking structure according to any one of claims 1-4, characterized in that, The molding layer includes resin, and the resin contains at least one of diamond, boron nitride, aluminum oxide (Al2O3), aluminum nitride (AlN), and silicon micropowder.

6. The chip stacking structure according to any one of claims 1-5, characterized in that, The first chip and the second chip are connected by a hybrid bonding method.

7. The chip stacking structure according to any one of claims 1-6, characterized in that, The material forming the at least one carrier plate includes at least one of silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), silicon nitride (SiN), and diamond.

8. A method for fabricating a chip stacking structure, characterized in that, include: A first wafer is provided; a plurality of first chips are disposed on the first wafer; Using a chip-to-wafer (C2W) approach, multiple second chips are bonded onto the first chip; One or more carrier boards are bonded onto the plurality of second chips using a chip-to-chip (C2C) approach. A molding process is used to form a molding layer, which encapsulates the plurality of second chips and the carrier board, and fills the gaps between adjacent second chips. The first chip is cut along the side of the chip to form a single chip stack structure; wherein, on the side of the chip stack structure, the molding compound encapsulates the plurality of second chips and the carrier board.

9. The method for fabricating a chip stacking structure according to claim 8, characterized in that, The step of bonding multiple second chips onto the first chip includes: A hybrid bonding process is used to bond multiple second chips onto the first chip.

10. The method for fabricating a chip stacking structure according to claim 8 or 9, characterized in that, Before bonding one or more carrier boards onto the plurality of second chips, the fabrication method further includes: A metal layer is formed on the surface of the second chip.

11. A chip packaging structure, characterized in that, It includes a substrate and a chip stacking structure as described in any one of claims 1-7, wherein the substrate is electrically connected to the chip stacking structure.

12. An electronic device, characterized in that, It includes a circuit board and a chip packaging structure as described in claim 9, wherein the circuit board is electrically connected to the chip packaging structure.

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