Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises an electric chip, a second bonding layer, a first bonding layer and an optical chip stacked from bottom to top, the optical chip is bonded on the electric chip through the first bonding layer and the second bonding layer, a pad is formed on the optical chip, and / or a tin ball is arranged below the electric chip, and the tin ball is electrically connected with the electric chip. The technical scheme of the application can realize high-density stacking interconnection of the optical chip and the electric chip, and reduce the loss.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Currently, when integrating optical and electrical chips using 3D packaging technology, the electrical chip is bonded to the optical chip. After light enters from the side of the electrical chip away from the optical chip, it needs to pass through the electrical chip before reaching the grating coupler inside the optical chip, resulting in significant losses. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which reduces losses while achieving high-density stacking and interconnection of optical and electrical chips.

[0004] To achieve the above objectives, the present invention provides a semiconductor device comprising an electrical chip, a second bonding layer, a first bonding layer, and an optical chip stacked from bottom to top. The optical chip is bonded to the electrical chip via the first bonding layer and the second bonding layer. Pads are formed on the optical chip, and / or solder balls are disposed below the electrical chip, and the solder balls are electrically connected to the electrical chip.

[0005] Optionally, the optical chip includes a first substrate and a first interlayer dielectric layer. The first substrate is located between the first bonding layer and the first interlayer dielectric layer. A first metal interconnect structure is formed in the first interlayer dielectric layer. The first bonding layer includes a first insulating layer and a first bonding pad. The first bonding pad is formed in the first insulating layer and is electrically connected to the first metal interconnect structure through a via conductive structure. The pad is electrically connected to the first metal interconnect structure.

[0006] Optionally, an edge coupler is formed in the first interlayer dielectric layer, and the edge coupler is exposed on the sidewall of the first interlayer dielectric layer.

[0007] Optionally, the side of the first interlayer dielectric layer where the edge coupler is formed is recessed relative to the first substrate.

[0008] Optionally, the electrical chip includes a second substrate and a second interlayer dielectric layer, the second interlayer dielectric layer being located between the second substrate and the second bonding layer, a second metal interconnect structure being formed in the second interlayer dielectric layer, the second bonding layer including a second insulating layer and a second bonding pad formed in the second insulating layer, the second bonding pad being electrically connected to the second metal interconnect structure, and the second bonding pad being electrically connected to the first bonding pad.

[0009] Optionally, the sidewall of the optical chip is recessed inward relative to the sidewall of the electrical chip.

[0010] Optionally, the semiconductor device further includes:

[0011] The substrate on which the electrical chip is fixed away from the optical chip is a substrate.

[0012] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0013] A first wafer is provided, the first wafer having a first surface and a second surface opposite to each other, a first bonding layer is formed on the second surface of the first wafer, and the first wafer includes an array of optical chips; a second wafer is provided, the second wafer having a first surface and a second surface opposite to each other, a second bonding layer is formed on the first surface of the second wafer, and the second wafer includes an array of electrical chips.

[0014] The first wafer is bonded to the second wafer through the first bonding layer and the second bonding layer;

[0015] A pad is formed on the first surface of the first wafer, and the pad is electrically connected to the optical chip; and / or, solder balls are disposed on the second surface of the second wafer, and the solder balls are electrically connected to the electrical chip.

[0016] The first wafer, the first bonding layer, the second bonding layer, and the second wafer are cut to obtain a plurality of bonding structures containing the optical chip and the electrical chip.

[0017] Optionally, before forming the first bonding layer on the second surface of the first wafer, the method of manufacturing the semiconductor device further includes:

[0018] The first surface of the first wafer is bonded to a carrier sheet;

[0019] Thinning the first wafer from the second surface of the first wafer;

[0020] After bonding the first wafer to the second wafer via the first bonding layer and the second bonding layer, the method of manufacturing the semiconductor device further includes:

[0021] The first surface of the first wafer is debonded to the carrier sheet.

[0022] Optionally, the first wafer includes a first substrate and a first interlayer dielectric layer formed on the first substrate, the side of the first substrate away from the first interlayer dielectric layer is the second surface of the first wafer; a first metal interconnect structure is formed in the first interlayer dielectric layer, the first bonding layer includes a first insulating layer and a first bonding pad, the first bonding pad is formed in the first insulating layer, and the first bonding pad is electrically connected to the first metal interconnect structure through a through-hole conductive structure.

[0023] Optionally, an edge coupler is formed in the first interlayer dielectric layer, and the edge coupler is exposed on the sidewall of the first interlayer dielectric layer after the first wafer, the first bonding layer, the second bonding layer and the second wafer are cut.

[0024] Optionally, before dicing the first wafer, the first bonding layer, the second bonding layer, and the second wafer, the method of manufacturing the semiconductor device further includes:

[0025] The first interlayer dielectric layer is etched so that the sidewalls of the etched first interlayer dielectric layer expose the edge coupler.

[0026] Optionally, the second wafer includes a second substrate and a second interlayer dielectric layer formed on the second substrate, the side of the second interlayer dielectric layer away from the second substrate being the first surface of the second wafer; a second metal interconnect structure is formed in the second interlayer dielectric layer, the second bonding layer includes a second insulating layer and a second bonding pad formed in the second insulating layer, the second bonding pad is electrically connected to the second metal interconnect structure, and the second bonding pad is electrically connected to the first bonding pad.

[0027] Optionally, after dicing the first wafer, the first bonding layer, the second bonding layer, and the second wafer, the sidewalls of the optical chip are recessed inward relative to the sidewalls of the electrical chip.

[0028] Optionally, the method for manufacturing the semiconductor device further includes:

[0029] The side of the electrical chip away from the optical chip is fixed to a substrate. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0031] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0032] Figures 3a-3hyes Figure 2 A schematic diagram of the device structure in the manufacturing method of the semiconductor device shown.

[0033] Among them, the appendix Figures 1-3h The annotations in the attached figures are explained as follows:

[0034] 111-First substrate; 112-First interlayer dielectric layer; 113-First metal interconnect structure; 114-Groove; 121-First insulating layer; 122-First bonding pad; 123-Through-hole conductive structure; 13-Edge coupler; 14-Pad; 15-Passivation layer; 16-Carrier sheet; 211-Second substrate; 212-Second interlayer dielectric layer; 213-Second metal interconnect structure; 221-Second insulating layer; 222-Second bonding pad. Detailed Implementation

[0035] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device and its manufacturing method proposed in this invention will be further described in detail below. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0036] An embodiment of the present invention provides a semiconductor device including an electrical chip, a second bonding layer, a first bonding layer, and an optical chip stacked from bottom to top. The optical chip is bonded to the electrical chip through the first bonding layer and the second bonding layer. The optical chip has pads formed on it, and / or solder balls are disposed below the electrical chip and are electrically connected to the electrical chip.

[0037] See below. Figure 1 The semiconductor device provided in this embodiment is described in detail below. Figure 1 This is a schematic diagram of a longitudinal cross-section.

[0038] The semiconductor device includes an electrical chip, a second bonding layer, a first bonding layer, and an optical chip stacked from bottom to top. The optical chip is bonded to the electrical chip via the first bonding layer and the second bonding layer. A pad 14 is formed on the optical chip, and the pad 14 is electrically connected to the optical chip. And / or, a solder ball (not shown) is disposed below the electrical chip, and the solder ball is electrically connected to the electrical chip. The side of the first bonding layer away from the optical chip is bonded to the side of the second bonding layer away from the electrical chip.

[0039] The pad 14 can be used for testing, wire bonding, or as an input / output interface.

[0040] In one embodiment, the optical chip includes a first substrate 111 and a first interlayer dielectric layer 112. The first substrate 111 is located between the first bonding layer and the first interlayer dielectric layer 112. A first metal interconnect structure 113 is formed in the first interlayer dielectric layer 112. The first bonding layer includes a first insulating layer 121 and a first bonding pad 122. The first bonding pad 122 is formed in the first insulating layer 121. The first bonding pad 122 is electrically connected to the first metal interconnect structure 113 through a through-hole conductive structure 123. The pad 14 is electrically connected to the first metal interconnect structure 113.

[0041] The first bonding pad 122 is exposed on the side of the first insulating layer 121 away from the first substrate 111.

[0042] In one embodiment, the via conductive structure 123 extends upward from the first bonding pad 122 through the first insulating layer 121 and the first substrate 111 and into the first interlayer dielectric layer 112, so as to realize that the first bonding pad 122 is electrically connected to the first metal interconnect structure 113 through the via conductive structure 123.

[0043] An insulating medium is also sandwiched between the through-hole conductive structure 123 and the first substrate 111, so that the through-hole conductive structure 123 is insulated from the first substrate 111.

[0044] In one embodiment, the first substrate 111 may be an SOI (Semiconductor-On-Insulator) substrate, and the optical chip may have device structures such as photodetectors, modulators and waveguides formed therein. The photodetectors and modulators may be electrically connected to the corresponding first metal interconnect structure 113 as needed.

[0045] In one embodiment, an edge coupler 13 is formed in the first interlayer dielectric layer 112, and the sidewall of the first interlayer dielectric layer 112 exposes the edge coupler 13, so that the subsequent optical fiber can be aligned with the edge coupler 13 to realize the optical signal incident from the side of the optical chip.

[0046] In one embodiment, the side of the first interlayer dielectric layer 112 where the edge coupler 13 is formed is recessed inward relative to the first substrate 111 to form a groove 114. The groove 114 can serve as an optical inlet, making it easier to align the optical fiber with the edge coupler 13. The bottom surface of the groove 114 can expose the first substrate 111.

[0047] In one embodiment, the edge coupler 13 is made of silicon nitride.

[0048] In one embodiment, the semiconductor device further includes a passivation layer 15 formed on the side of the optical chip away from the electrical chip and extending to a portion of the surface of the pad 14. The passivation layer 15 can extend from the side of the first interlayer dielectric layer 112 away from the first substrate 111 to a portion of the surface of the pad 14 to prevent moisture and contaminants from entering the interior of the optical chip from the interface between the pad 14 and the first interlayer dielectric layer 112.

[0049] In one embodiment, the electrical chip includes a second substrate 211 and a second interlayer dielectric layer 212, the second interlayer dielectric layer 212 being located between the second substrate 211 and the second bonding layer. A second metal interconnect structure 213 is formed in the second interlayer dielectric layer 212. The second bonding layer includes a second insulating layer 221 and a second bonding pad 222 formed in the second insulating layer 221. The second bonding pad 222 is electrically connected to the second metal interconnect structure 213 and electrically connected to the first bonding pad 122. The first bonding layer and the second bonding layer are coupled using a hybrid bonding method.

[0050] The side of the second insulating layer 221 away from the second substrate 211 exposes the second bonding pad 222.

[0051] In one embodiment, the second bonding pad 222 may extend from the second insulating layer 221 into the second interlayer dielectric layer 212 to achieve electrical connection between the second bonding pad 222 and the second metal interconnect structure 213.

[0052] In one embodiment, the electrical chip may have device structures such as transistors, resistors, and capacitors, which can be electrically connected to the corresponding second metal interconnect structure 213 as needed.

[0053] In one embodiment, the solder ball is electrically connected to the second substrate 211; or, in another embodiment, the solder ball is electrically connected to the second metal interconnect structure 213 through a conductive structure, the sidewalls of which are wrapped with insulating material.

[0054] It should be noted that, in one embodiment, there are multiple first bonding pads 122, some of which are electrically connected to the first metal interconnect structure 113 through the through-hole conductive structure 123, while other first bonding pads 122 are not electrically connected to the first metal interconnect structure 113. The other part of the first bonding pads 122 is only used for bonding with the second bonding pads 222. In another embodiment, there are multiple second bonding pads 222, some of which are electrically connected to the second metal interconnect structure 213, while other part of the second bonding pads 222 are not electrically connected to the second metal interconnect structure 213. The other part of the second bonding pads 222 is only used for bonding with the first bonding pads 122.

[0055] In one embodiment, the sidewall of the optical chip is recessed relative to the sidewall of the electrical chip.

[0056] The semiconductor device further includes a substrate (not shown), wherein the side of the electrical chip away from the optical chip is fixed on the substrate.

[0057] In one embodiment, the electrical chip is electrically connected to the substrate via the solder ball.

[0058] In one embodiment, the substrate is a PCB (printed circuit board), and the side of the electrical chip away from the optical chip can be fixed to the substrate by processes such as soldering.

[0059] As can be seen from the above, the semiconductor device provided by the present invention, in which the optical chip is bonded to the electrical chip through the first bonding layer and the second bonding layer, and the optical chip has a pad 14 formed on the optical chip, and / or a solder ball is disposed below the electrical chip, the solder ball being electrically connected to the electrical chip, that is, the optical chip is disposed above the electrical chip, and the optical signal is incident from one side of the optical chip, so that the optical signal does not need to pass through the electrical chip but is directly incident into the optical chip, thereby reducing loss. Therefore, while achieving high-density stacked interconnection between the optical chip and the electrical chip, the problem of optical loss caused by high-density stacked interconnection is also solved.

[0060] In one embodiment, an edge coupler 13 is formed in the first interlayer dielectric layer 112, and the sidewall of the first interlayer dielectric layer 112 exposes the edge coupler 13. Compared to a scheme where the optical signal is incident from the side of the electrical chip away from the optical chip, passes through the interlayer dielectric layer in the electrical chip and the optical chip, and then enters the grating coupler, this embodiment allows the optical signal to be directly incident on the edge coupler 13 from the side of the optical chip, thereby further reducing the loss. For example, the scheme using the grating coupler has a 10 times larger optical bandwidth and a 0.5 dB greater coupling loss than the scheme using the edge coupler 13.

[0061] In addition, the present invention places the optical chip above the electrical chip, and the optical chip is provided with the edge coupler 13, so that the semiconductor device can share the equipment and materials of the existing packaging process, thereby reducing the packaging risk and reducing the problems of increased cost and increased packaging risk caused by the investment of new packaging equipment or materials.

[0062] An embodiment of the present invention provides a method for manufacturing a semiconductor device, see below. Figure 2 , Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method comprising:

[0063] Step S1: Provide a first wafer, the first wafer having a first surface and a second surface opposite to each other, forming a first bonding layer on the second surface of the first wafer, the first wafer containing an array of optical chips; provide a second wafer, the second wafer having a first surface and a second surface opposite to each other, forming a second bonding layer on the first surface of the second wafer, the second wafer containing an array of electrical chips;

[0064] Step S2: Bond the first wafer to the second wafer through the first bonding layer and the second bonding layer;

[0065] Step S3: Forming a pad on the first surface of the first wafer, the pad being electrically connected to the optical chip; and / or, setting solder balls on the second surface of the second wafer, the solder balls being electrically connected to the electrical chip;

[0066] Step S4: Cut the first wafer, the first bonding layer, the second bonding layer, and the second wafer to obtain a plurality of bonding structures containing the optical chip and the electrical chip.

[0067] See below. Figures 3a-3h The manufacturing method of the semiconductor device provided in this embodiment will be described in more detail. It should be noted that... Figures 3a-3gThe diagram only illustrates the structure of one optical chip in the first wafer and one electrical chip in the second wafer. The actual first and second wafers contain multiple optical chips arranged in an array. Figures 3a-3g The structure shown has cutting channels between adjacent optical chips and between adjacent electrical chips. Figure 3h The image shows the structure after cutting.

[0068] Following step S1, as follows Figure 3c As shown, a first wafer is provided, the first wafer having a first surface and a second surface opposite to each other, a first bonding layer being formed on the second surface of the first wafer, and the first wafer comprising an array of optical chips; as shown Figure 3d As shown, a second wafer is provided, the second wafer having a first surface and a second surface opposite to each other, a second bonding layer being formed on the first surface of the second wafer, the second wafer containing an array of electrical chips.

[0069] In one embodiment, the first surface is the front side and the second surface is the back side.

[0070] In one embodiment, the first wafer includes a first substrate 111 and a first interlayer dielectric layer 112 formed on the first substrate 111. The side of the first substrate 111 away from the first interlayer dielectric layer 112 is the second surface of the first wafer. A first metal interconnect structure 113 is formed in the first interlayer dielectric layer 112. The first bonding layer includes a first insulating layer 121 and a first bonding pad 122. The first bonding pad 122 is formed in the first insulating layer 121 and is electrically connected to the first metal interconnect structure 113 through a through-hole conductive structure 123.

[0071] The first bonding pad 122 is exposed on the side of the first insulating layer 121 away from the first substrate 111.

[0072] In one embodiment, the via conductive structure 123 extends from the side of the first bonding pad 122 near the first substrate 111 through the first insulating layer 121 and the first substrate 111 and into the first interlayer dielectric layer 112, so as to realize that the first bonding pad 122 is electrically connected to the first metal interconnect structure 113 through the via conductive structure 123.

[0073] An insulating medium is also sandwiched between the through-hole conductive structure 123 and the first substrate 111, so that the through-hole conductive structure 123 is insulated from the first substrate 111.

[0074] In one embodiment, the first substrate 111 may be an SOI (Semiconductor-On-Insulator) substrate, and the optical chip may have device structures such as photodetectors, modulators and waveguides formed therein. The photodetectors and modulators may be electrically connected to the corresponding first metal interconnect structure 113 as needed.

[0075] In one embodiment, an edge coupler 13 is formed in the first interlayer dielectric layer 112.

[0076] In one embodiment, the edge coupler 13 is made of silicon nitride.

[0077] The second wafer includes a second substrate 211 and a second interlayer dielectric layer 212 formed on the second substrate 211. The side of the second interlayer dielectric layer 212 away from the second substrate 211 is the first surface of the second wafer. A second metal interconnect structure 213 is formed in the second interlayer dielectric layer 212. The second bonding layer includes a second insulating layer 221 and a second bonding pad 222 formed in the second insulating layer 221. The second bonding pad 222 is electrically connected to the second metal interconnect structure 213 and is electrically connected to the first bonding pad 122.

[0078] The side of the second insulating layer 221 away from the second substrate 211 exposes the second bonding pad 222.

[0079] In one embodiment, the second bonding pad 222 may extend from the second insulating layer 221 into the second interlayer dielectric layer 212 to achieve electrical connection between the second bonding pad 222 and the second metal interconnect structure 213.

[0080] In one embodiment, the electrical chip may have device structures such as transistors, resistors, and capacitors, which can be electrically connected to the corresponding second metal interconnect structure 213 as needed.

[0081] Following step S2, as Figure 3e As shown, the first wafer is bonded to the second wafer through the first bonding layer and the second bonding layer.

[0082] The first bonding layer and the second bonding layer are bonded together in a hybrid manner.

[0083] It should be noted that, in one embodiment, there are multiple first bonding pads 122, some of which are electrically connected to the first metal interconnect structure 113 through the through-hole conductive structure 123, while other first bonding pads 122 are not electrically connected to the first metal interconnect structure 113. The other part of the first bonding pads 122 is only used for bonding with the second bonding pads 222. In another embodiment, there are multiple second bonding pads 222, some of which are electrically connected to the second metal interconnect structure 213, while other part of the second bonding pads 222 are not electrically connected to the second metal interconnect structure 213. The other part of the second bonding pads 222 is only used for bonding with the first bonding pads 122.

[0084] In one embodiment, before forming the first bonding layer on the second surface of the first wafer, the method of manufacturing the semiconductor device further includes: Figure 3a As shown, the first surface of the first wafer is bonded to a carrier sheet 16; as Figure 3b As shown, the first wafer is thinned from the second surface of the first wafer; wherein, the first substrate 111 is thinned.

[0085] In one embodiment, the carrier sheet 16 may be a wafer or glass, etc.

[0086] In one embodiment, the first surface of the first wafer and the carrier sheet 16 may be temporarily bonded together by bonding adhesive.

[0087] In one embodiment, the first substrate 111 may be thinned using etching and / or chemical mechanical polishing processes.

[0088] In one embodiment, such as Figure 3f As shown, after bonding the first wafer to the second wafer via the first bonding layer and the second bonding layer, the method of manufacturing the semiconductor device further includes: debonding the first surface of the first wafer to the carrier sheet 16.

[0089] Following step S3, as follows Figure 3g As shown, a pad 14 is formed on the first surface of the first wafer, and the pad 14 is electrically connected to the optical chip; and / or, solder balls (not shown) are disposed on the second surface of the second wafer, and the solder balls are electrically connected to the electrical chip.

[0090] In one embodiment, the pad 14 is electrically connected to the first metal interconnect structure 113.

[0091] The pad 14 can be used for testing, wire bonding, or as an input / output interface.

[0092] In one embodiment, the solder ball is electrically connected to the second substrate 211; or, in another embodiment, the solder ball is electrically connected to the second metal interconnect structure 213 through a conductive structure (not shown), the sidewalls of which are wrapped with insulating material.

[0093] In one embodiment, after forming the pad 14, a passivation layer 15 is formed on the side of the optical chip away from the electrical chip and extends to a portion of the surface of the pad 14. The passivation layer 15 can extend from the side of the first interlayer dielectric layer 112 away from the first substrate 111 to a portion of the surface of the pad 14 to prevent moisture and contaminants from entering the interior of the optical chip from the interface between the pad 14 and the first interlayer dielectric layer 112.

[0094] According to step S4, the first wafer, the first bonding layer, the second bonding layer, and the second wafer are cut to obtain a plurality of bonding structures containing the optical chip and the electrical chip.

[0095] The first wafer, the first bonding layer, the second bonding layer, and the second wafer are cut along the dicing channels between adjacent optical chips and between adjacent electrical chips.

[0096] In one embodiment, after dicing the first wafer, the first bonding layer, the second bonding layer, and the second wafer, the sidewall of the first interlayer dielectric layer 112 exposes the edge coupler 13, allowing subsequent optical fibers to be aligned with the edge coupler 13 to achieve optical signal incident from the side of the optical chip.

[0097] In one embodiment, such as Figure 3h As shown, before dicing the first wafer, the first bonding layer, the second bonding layer, and the second wafer, the method for manufacturing the semiconductor device further includes: etching the first interlayer dielectric layer 112 to form a groove 114, such that the sidewalls of the etched first interlayer dielectric layer 112 expose the edge coupler 13, and the groove 114 still exists after dicing the first wafer, the first bonding layer, the second bonding layer, and the second wafer. The groove 114 can serve as an optical inlet, making it easier to align the optical fiber with the edge coupler 13. The bottom surface of the groove 114 can expose the first substrate 111.

[0098] In one embodiment, after dicing the first wafer, the first bonding layer, the second bonding layer, and the second wafer, the sidewalls of the optical chip are recessed inward relative to the sidewalls of the electrical chip.

[0099] In one embodiment, the method of manufacturing the semiconductor device further includes fixing the side of the electrical chip away from the optical chip onto a substrate (not shown).

[0100] In one embodiment, the electrical chip is electrically connected to the substrate via the solder ball.

[0101] In one embodiment, the substrate is a PCB (printed circuit board), and the side of the electrical chip away from the optical chip can be fixed to the substrate by processes such as soldering.

[0102] As can be seen from the above, compared to bonding multiple electrical chips onto a wafer containing optical chips, the semiconductor device manufacturing method provided by the present invention bonds the first wafer containing an array of optical chips onto a second wafer containing an array of electrical chips via the first bonding layer and the second bonding layer, thereby reducing costs and improving manufacturing efficiency. Furthermore, in the bonded structure containing the optical chips and electrical chips obtained after dicing, the optical chips are positioned above the electrical chips, and the optical signal is incident from one side of the optical chip, allowing the optical signal to directly enter the optical chip without passing through the electrical chip, thus reducing losses. Therefore, while achieving high-density stacked interconnection between the optical chips and the electrical chips, the problem of optical loss caused by high-density stacked interconnection is also solved.

[0103] In one embodiment, an edge coupler 13 is formed in the first interlayer dielectric layer 112, and the sidewall of the first interlayer dielectric layer 112 exposes the edge coupler 13. Compared to a scheme where the optical signal is incident from the side of the electrical chip away from the optical chip, passes through the interlayer dielectric layer in the electrical chip and the optical chip, and then enters the grating coupler, this embodiment allows the optical signal to be directly incident on the edge coupler 13 from the side of the optical chip, thereby further reducing the loss. For example, the scheme using the grating coupler has a 10 times larger optical bandwidth and a 0.5 dB greater coupling loss than the scheme using the edge coupler 13.

[0104] In addition, the present invention places the optical chip above the electrical chip, and the optical chip is provided with the edge coupler 13, so that the semiconductor device can share the equipment and materials of the existing packaging process, thereby reducing the packaging risk and reducing the problems of increased cost and increased packaging risk caused by the investment of new packaging equipment or materials.

[0105] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, The device includes an electrical chip, a second bonding layer, a first bonding layer, and an optical chip stacked from bottom to top. The optical chip is bonded to the electrical chip through the first bonding layer and the second bonding layer. The optical chip has pads formed on it, and / or solder balls are disposed below the electrical chip and are electrically connected to the electrical chip.

2. The semiconductor device as claimed in claim 1, characterized in that, The optical chip includes a first substrate and a first interlayer dielectric layer. The first substrate is located between the first bonding layer and the first interlayer dielectric layer. A first metal interconnect structure is formed in the first interlayer dielectric layer. The first bonding layer includes a first insulating layer and a first bonding pad. The first bonding pad is formed in the first insulating layer and is electrically connected to the first metal interconnect structure through a through-hole conductive structure. The pad is electrically connected to the first metal interconnect structure.

3. The semiconductor device as claimed in claim 2, characterized in that, An edge coupler is formed in the first interlayer dielectric layer, and the edge coupler is exposed on the sidewall of the first interlayer dielectric layer.

4. The semiconductor device as claimed in claim 3, characterized in that, The side of the first interlayer dielectric layer where the edge coupler is formed is recessed inward relative to the first substrate.

5. The semiconductor device as claimed in claim 2, characterized in that, The electrical chip includes a second substrate and a second interlayer dielectric layer. The second interlayer dielectric layer is located between the second substrate and the second bonding layer. A second metal interconnect structure is formed in the second interlayer dielectric layer. The second bonding layer includes a second insulating layer and a second bonding pad formed in the second insulating layer. The second bonding pad is electrically connected to the second metal interconnect structure and is electrically connected to the first bonding pad.

6. The semiconductor device as claimed in claim 1, characterized in that, The sidewall of the optical chip is recessed inward relative to the sidewall of the electrical chip.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The semiconductor device further includes: The substrate on which the electrical chip is fixed away from the optical chip is a substrate.

8. A method for manufacturing a semiconductor device, characterized in that, include: A first wafer is provided, the first wafer having a first surface and a second surface opposite to each other, a first bonding layer is formed on the second surface of the first wafer, and the first wafer includes an array of optical chips; A second wafer is provided, the second wafer having a first surface and a second surface opposite to each other, a second bonding layer is formed on the first surface of the second wafer, and the second wafer contains an array of electrical chips; The first wafer is bonded to the second wafer through the first bonding layer and the second bonding layer; A pad is formed on the first surface of the first wafer, and the pad is electrically connected to the optical chip; and / or, solder balls are disposed on the second surface of the second wafer, and the solder balls are electrically connected to the electrical chip. The first wafer, the first bonding layer, the second bonding layer, and the second wafer are cut to obtain a plurality of bonding structures containing the optical chip and the electrical chip.

9. The method for manufacturing a semiconductor device as claimed in claim 8, characterized in that, Before forming the first bonding layer on the second surface of the first wafer, the method of manufacturing the semiconductor device further includes: The first surface of the first wafer is bonded to a carrier sheet; Thinning the first wafer from the second surface of the first wafer; After bonding the first wafer to the second wafer via the first bonding layer and the second bonding layer, the method of manufacturing the semiconductor device further includes: The first surface of the first wafer is debonded to the carrier sheet.

10. The method of manufacturing a semiconductor device as claimed in claim 8, characterized in that, The first wafer includes a first substrate and a first interlayer dielectric layer formed on the first substrate. The side of the first substrate away from the first interlayer dielectric layer is the second surface of the first wafer. A first metal interconnect structure is formed in the first interlayer dielectric layer. The first bonding layer includes a first insulating layer and a first bonding pad. The first bonding pad is formed in the first insulating layer and is electrically connected to the first metal interconnect structure through a via conductive structure.

11. The method of manufacturing a semiconductor device as claimed in claim 10, characterized in that, An edge coupler is formed in the first interlayer dielectric layer, and the edge coupler is exposed on the sidewall of the first interlayer dielectric layer after the first wafer, the first bonding layer, the second bonding layer and the second wafer are cut.

12. The method of manufacturing a semiconductor device as claimed in claim 11, characterized in that, The method of manufacturing the semiconductor device, prior to dicing the first wafer, the first bonding layer, the second bonding layer, and the second wafer, further includes: The first interlayer dielectric layer is etched so that the sidewalls of the etched first interlayer dielectric layer expose the edge coupler.

13. The method of manufacturing a semiconductor device as claimed in claim 10, characterized in that, The second wafer includes a second substrate and a second interlayer dielectric layer formed on the second substrate. The side of the second interlayer dielectric layer away from the second substrate is the first surface of the second wafer. A second metal interconnect structure is formed in the second interlayer dielectric layer. The second bonding layer includes a second insulating layer and a second bonding pad formed in the second insulating layer. The second bonding pad is electrically connected to the second metal interconnect structure and is electrically connected to the first bonding pad.

14. The method for manufacturing a semiconductor device as claimed in claim 8, characterized in that, After dicing the first wafer, the first bonding layer, the second bonding layer, and the second wafer, the sidewalls of the optical chip are recessed inward relative to the sidewalls of the electrical chip.

15. The semiconductor device according to any one of claims 8 to 14, characterized in that, The method for manufacturing the semiconductor device further includes: The side of the electrical chip away from the optical chip is fixed to a substrate.

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