Test method for insulated gate type sic semiconductor element, Insulated gate type sic semiconductor element

Abstract

The present application provides a kind of test method of insulated gate type SiC semiconductor element, which can accurately screen non-standard product difficult to determine by existing test method.A kind of test method of insulated gate type SiC semiconductor element, characterized in that, with (a) the step of being tested element is loaded into the H bridge type circuit with inductive load;And (b) according to the gate voltage signal of the H bridge type circuit, the step of repeatedly conducting on / off switch, makes the current of two-way flow to the tested element.The tested element is set as Vav [kV] when the rated breaking voltage is set, the gate insulating film thickness is set as t [nm], the voltage variation speed when on / off switch is set as dv / dt [kV / us], satisfies the relationship formula dv / dt>0.06×t×Vav.

Description

Technical Field

[0001] This invention relates to a test method for semiconductor devices and semiconductor devices thereof, and particularly to an effective technique for screening tests of insulated-gate SiC semiconductor devices. Background Technology

[0002] Silicon carbide (SiC) has attracted attention as a semiconductor material capable of manufacturing power semiconductor devices with excellent low resistance, high voltage withstand capability, heat resistance, and high-speed characteristics. Power semiconductor devices using SiC include SBD (Schottky Barrier Diode), PND (PN Diode), MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and IGBT (Insulated Gate Bipolar Transistor).

[0003] The dielectric breaking electric field strength of SiC is about 10 times higher than that of Si (silicon). Therefore, it is possible to fabricate high-voltage power semiconductor devices with hundreds of V to thousands of V using drift layers with higher impurity concentration and thinner film thickness compared to Si semiconductor devices, and to achieve high-voltage devices with very low on-resistance per unit area.

[0004] Furthermore, in Si, to mitigate the increased on-resistance associated with higher breakdown voltage, minority carrier devices such as IGBTs are primarily used. However, this results in significant switching losses, and the resulting heat generation limits high-frequency drive. On the other hand, in SiC, high breakdown voltage can be achieved using majority carrier devices such as SBDs and MOSFETs, which are high-speed device structures. Therefore, it is possible to simultaneously achieve high breakdown voltage, low on-resistance, and high speed.

[0005] Furthermore, since the band gap is about three times wider than that of Si, it is also characterized by the ability to realize power semiconductor devices that can operate at high temperatures.

[0006] As background technology in this field, there is, for example, technology like Patent Document 1. Patent Document 1 discloses "a method for screening silicon carbide semiconductor devices, which can screen out silicon carbide semiconductor devices whose reliability will not decrease even when used at high temperatures for a long time in an inverter circuit in which diodes and silicon carbide semiconductor devices are connected in reverse parallel".

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent Document 1: Japanese Patent Application Publication No. 2018-205251 Summary of the Invention

[0010] The problem that the invention aims to solve

[0011] However, in power semiconductor devices (such as power MOSFETs), a voltage is repeatedly and intermittently applied between the drain and source during switching. When the MOSFET switches from a conducting state (on) to a de-conducting state (off), the voltage applied to the drain electrode of the MOSFET increases sharply. Due to this change in drain voltage, a displacement current is generated through the depletion layer capacitance between the source and drain. This displacement current flows within the P-well and into the source electrode, but at this time, a voltage proportional to the magnitude of the current is generated within the P-well. (See below) Figure 1 。

[0012] In the portion of the gate oxide film sandwiched between the P-well and the gate electrode, a high electric field is applied to the gate oxide film due to the high voltage, which can sometimes damage the gate oxide film. Especially in the case of high-voltage components with large power supply voltages, the displacement current generated during switching is also large, and the electric field applied to the gate oxide film is also large. Therefore, there is a concern that long-term use may lead to the accumulation of damage and cause component failure.

[0013] Although we try to prevent damage caused by internal electric fields through component structure design, due to deviations in manufacturing process and foreign objects that cannot be completely removed, it is inevitable that there will be easily damaged components. Therefore, such fragile components need to be screened out through stress testing.

[0014] In addition, the destructive resistance of high-voltage components is closely related to the rated breaking voltage of the component being tested and the thickness of the gate insulating film. It is also affected by the switching speed during stress testing. Therefore, stress tests that take these factors into account are necessary.

[0015] In the aforementioned patent document 1, these parameters were not considered, leaving room for improvement in high-precision screening.

[0016] Therefore, the purpose of this invention is to provide a test method for an insulated gate type SiC semiconductor device and an insulated gate type SiC semiconductor device using the same, which can accurately screen out non-standard products that are difficult to identify in existing test methods.

[0017] Methods for solving problems

[0018] To address the aforementioned issues, the present invention provides a testing method for an insulated-gate SiC semiconductor device, characterized by comprising: (a) a step of assembling the device under test into an H-bridge circuit with an inductive load; and (b) a step of repeatedly switching the device on and off according to the gate voltage signal of the H-bridge circuit to allow bidirectional current to flow to the device under test, wherein the device under test satisfies the relationship dv / dt > 0.06 × t × Vav when the rated open-circuit withstand voltage is set to Vav [kV], the gate insulating film thickness is set to t [nm], and the voltage change rate during switching on and off is set to dv / dt [kV / µs].

[0019] Furthermore, the present invention is an insulated-gate SiC semiconductor device having a gate terminal, a source terminal, and a drain terminal. The current flowing between the source terminal and the drain terminal is controlled by applying a voltage to the gate terminal. The insulated-gate SiC semiconductor device is characterized by having the following characteristics: it is installed in an H-bridge circuit with an inductive load; and bidirectional current flows to the device under test by repeatedly switching the gate voltage signal of the H-bridge circuit on and off. When the rated open-circuit withstand voltage is set to Vav [kV], the gate insulating film thickness is set to t [nm], and the voltage change rate during switching on and off is set to dv / dt [kV / us], the relationship dv / dt > 0.06 × t × Vav is satisfied.

[0020] Invention Effects

[0021] According to the present invention, a test method for an insulated-gate SiC semiconductor device and an insulated-gate SiC semiconductor device using the same method are available, which can screen out non-standard products that are difficult to identify in existing test methods with high precision.

[0022] This can help improve the reliability and extend the lifespan of insulated-gate SiC semiconductor devices.

[0023] Other issues, structures, and effects not mentioned above will be clarified through the following description of the implementation methods. Attached Figure Description

[0024] Figure 1 This is a schematic diagram showing the cross-sectional structure of the SiC-MOSFET of Embodiment 1 of the present invention.

[0025] Figure 2A This is a graph showing the relationship between the rated withstand voltage of a component and the rate of change of voltage dv / dt required for defect screening.

[0026] Figure 2B This is a graph showing the relationship between the gate insulating film thickness and the voltage change rate dv / dt required for defect screening.

[0027] Figure 3 This is a diagram illustrating the H-bridge test circuit of Embodiment 1 of the present invention.

[0028] Figure 4 It means Figure 3 The diagram shows an example of the test waveforms for the H-bridge test circuit.

[0029] Figure 5 It means to utilize Figure 3 The graph shows the temperature of the components during the test of the H-bridge test circuit.

[0030] Figure 6 This is a flowchart illustrating the test method for the SiC semiconductor device according to Embodiment 1 of the present invention. Detailed Implementation

[0031] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. Furthermore, the same reference numerals are used to denote the same structures in the drawings, and detailed descriptions of repeated parts are omitted.

[0032] Example 1

[0033] Reference Figures 1 to 6 The test method for the SiC semiconductor device of Embodiment 1 of the present invention and the SiC semiconductor device thereunder will be described.

[0034] Figure 1 This is a schematic diagram showing the cross-sectional structure of the SiC-MOSFET of this embodiment, using a planar MOSFET as an example.

[0035] like Figure 1 As shown, in this embodiment, the SiC-MOSFET1 has an n-type drift layer 3, also made of SiC, disposed on the main surface of the n+ type SiC substrate 2.

[0036] Near the surface of the drift layer 3, there are a p-type main region 4, an n+ type source region 5 containing n-type dopants at a higher concentration than the n-type drift layer 3, and a p+ type contact region 6 containing p-type dopants at a higher concentration than the p-type main region 4.

[0037] An active electrode 7 is formed by grounding at least a portion of the n+ type source region 5 and the p+ type contact region 6 near the surface of the drift layer 3.

[0038] In addition, a gate insulating film 8 and a gate electrode 9 are formed in the p-type main region 4 near the surface of the drift layer 3 and grounded.

[0039] A drain electrode 10 is disposed on the back side of the SiC substrate 2.

[0040] If the gate electrode 9 is biased at a voltage higher than a certain threshold voltage (VGSth) relative to the source electrode 7, the portion of the p-type main region 4 that is in contact with the gate insulating film 8 is reversed to n-type, forming a conductive channel. In this state, if the drain electrode 10 is positively biased relative to the source electrode 7, electrons flow from the n+ type source region 5 to the drain electrode 10 through the conductive channel.

[0041] When the gate voltage is below the threshold voltage VGSth, no conductive channel is formed. When a high drain voltage is applied, a depletion region is formed in the drift layer 3, so that only a very small leakage current flows to the drain electrode 10.

[0042] In this way, by controlling the voltage applied to the gate electrode 9, the current can be turned on / off (switching action).

[0043] use Figure 6 The flowchart illustrates the test method for the SiC semiconductor device in this embodiment.

[0044] First, in step S1, the SiC semiconductor device to be tested is loaded into an H-bridge circuit with an inductive load. (See below) Figure 3 。

[0045] Next, in step S2, the gate voltage signal input is used to repeatedly turn the switch on and off, so that bidirectional current flows to the SiC semiconductor device, thereby applying stress to the SiC semiconductor device.

[0046] When the switch is activated, the action conditions are set in a manner that satisfies the relationship in equation (1).

[0047] dv / dt>0.06×t×Vav···(1)

[0048] Here, Vav [kV] is the rated open-circuit withstand voltage of the SiC semiconductor device, t [nm] is the thickness of the gate insulating film, and dv / dt [kV / us] is the voltage change rate during switching.

[0049] Next, in step S3, the SiC semiconductor element is removed from the H-bridge circuit.

[0050] Next, in step S4, the gate leakage current of the SiC semiconductor element taken from the H-bridge circuit is measured.

[0051] Next, in step S5, it is determined whether the gate leakage current value is within a specified range. If the gate leakage current value is within the specified range (Yes), the process proceeds to step S6, where the product is selected as a qualified product. On the other hand, if the gate leakage current value deviates from the specified range (No), the process proceeds to step S7, where the product is selected as a non-qualified product.

[0052] According to the test method of this embodiment, by setting the operating conditions in the H-bridge circuit in a manner that satisfies the above relation (1), the fragile components will cause malfunction or damage and will be excluded as defective products.

[0053] In addition, since components with high rated breaking voltage exert greater stress on the gate oxide film, efficient screening is possible if the rated voltage is above 2kV.

[0054] In addition, although using Figure 5 As will be described later, since the internal temperature of the component can be increased by the self-heating caused by the energization, higher stress can be applied. Therefore, the maximum current flowing during the test is more than 1 / 5 (preferably more than 1 / 2) of the rated current of the component, and it is desirable that the junction temperature of the component be heated to more than 100°C.

[0055] use Figure 2A as well as Figure 2B The voltage change rate dv / dt required for screening non-conforming products is explained.

[0056] Figure 2A This is a graph showing the relationship between the rated withstand voltage of a component and the rate of voltage change (voltage change rate) dv / dt required for defect screening. Figure 2B This is a graph showing the relationship between the gate insulating film thickness and the voltage change rate (voltage change rate) dv / dt required for defect screening.

[0057] The result of calculating the voltage change rate dv / dt that allows for the selection of fragile components as defective products is as follows: Figure 2A and Figure 2B The relationship shown.

[0058] like Figure 2A As shown, the required rate of voltage change dv / dt for screening increases proportionally with the component's rated withstand voltage (disconnected from the rated voltage). This is because the higher the rated voltage, the smaller the capacitance of the depletion layer, and the smaller the displacement current accompanying the capacitance change.

[0059] In addition, such as Figure 2B As shown, the thinner the gate insulating film, the lower the withstand voltage, and therefore the smaller the voltage change rate dv / dt required for screening.

[0060] Based on the voltage change rate dv / dt shown in these two figures, the relationship shown in equation (1) above is obtained.

[0061] The case of the test element (SiC semiconductor element) being installed in the H-bridge test circuit is shown below. Figure 3 .

[0062] The H-bridge circuit consists of four switching elements (SW2, SW3, and SW4) in addition to SW1, which serves as the Device Under Test (DUT), a DC power supply 11, and an inductive load 12. Gate drivers (GD) for inputting gate signals to each switching element are connected to the switching elements SW1 to SW4.

[0063] With a rated breaking voltage of 3.3kV and a rated current capacity of 1000A for the switching element, for example, the voltage of DC power supply 11 is 1.8kV and the inductive load 12 is 2mH.

[0064] In this embodiment, switching element SW1 is used as the device under test (DUT), and switching elements SW2 to SW4 are used as auxiliary elements to form an H-bridge circuit. However, in order to apply sufficient stress to switching element SW1 as the device under test (DUT), it is preferable that the rated breaking voltage and rated current capacity of switching elements SW2 to SW4 are greater than those of switching element SW1. Alternatively, switching elements SW2 to SW4 can be fitted with the same components as switching element SW1, and all four can be used as devices under test (DUT) for testing.

[0065] Additionally, if the product that becomes the device under test (DUT) is a type that integrates two switching elements in a single package (two-in-one type), it is also possible to... Figure 3 The switching elements SW1 and SW2 in the circuit were tested by incorporating them into a single package.

[0066] To control the switching speed (voltage change rate) dv / dt, the gate voltage during turn-on / turn-off and the resistance value connected between the gate drive output and the gate terminal of the device under test are adjusted. To apply high stress more efficiently, a high gate turn-on voltage, a low gate turn-off voltage, and a low gate resistance are required.

[0067] The signals input to the gates of each switching element in an H-bridge circuit can be controlled by pulse width modulation (PWM) by comparing the magnitude of a sinusoidal modulated wave with that of a sawtooth carrier wave.

[0068] Figure 4 express Figure 3 Example of test waveforms for the H-bridge test circuit.

[0069] Figure 4This represents the waveform of the gate voltage signal input to the device under test (DUT), the drain voltage of the DUT, and the current flowing to the DUT when PWM control is performed based on a 50Hz modulation wave and a 1kHz carrier wave.

[0070] The drain voltage applied to the device under test changes repeatedly depending on the on / off signal input to the gate. If the switching speed (voltage change rate) dv / dt at this time falls within the range shown in equation (1) above, stress can be effectively applied to the device under test. Figure 3 In the H-bridge test circuit shown, the current reverses direction within one cycle, indicating bidirectional current flow. This H-bridge circuit allows for testing of all operating modes of the switching elements, including both forward and reverse recovery.

[0071] Figure 5 Indicates the use of Figure 3 The temperature of the components during testing of the H-bridge test circuit.

[0072] Figure 5 This indicates the change in the contact temperature of the tested element during the test. Due to Joule heating caused by the current flowing during the test, the temperature of the switching element gradually rises. This temperature rise also depends on the thermal characteristics determined by the construction of the switching element and the cooling method of the switching element, but it reaches a roughly constant stable temperature in approximately a few seconds to tens of seconds.

[0073] The test preferably involves repeated energizing for a sufficient period of time to achieve such a stable state, with the temperature reaching 100°C or higher. Furthermore, to achieve this temperature, the current applied to the tested element needs to be at least 1 / 5 (preferably at least 1 / 2) of its maximum rated current. If the current is low and the maximum temperature reached is low, the stress may become insufficient.

[0074] As explained above, the test method for the SiC semiconductor device in this embodiment includes: (a) the step of loading the device under test into an H-bridge circuit with an inductive load; and (b) the step of repeatedly switching on and off according to the gate voltage signal of the H-bridge circuit to allow bidirectional current to flow to the device under test, wherein the device under test satisfies the relationship dv / dt > 0.06 × t × Vav when the rated open circuit withstand voltage is set to Vav [kV], the gate insulating film thickness is set to t [nm], and the voltage change rate during switching on and off is set to dv / dt [kV / us].

[0075] Furthermore, the SiC semiconductor device in this embodiment is an insulated-gate SiC semiconductor device that includes a gate terminal, a source terminal, and a drain terminal. The current flowing between the source terminal and the drain terminal is controlled by applying a voltage to the gate terminal. It has a history of being installed in an H-bridge circuit with an inductive load, and having bidirectional current flowing to the insulated-gate SiC semiconductor device by repeatedly switching the gate voltage signal of the H-bridge circuit on and off. When the rated circuit breaking withstand voltage is set to Vav [kV], the gate insulating film thickness is set to t [nm], and the voltage change rate during switching on and off is set to dv / dt [kV / us], the relationship dv / dt > 0.06 × t × Vav is satisfied.

[0076] Therefore, it is possible to perform high-precision screening of out-of-specification products that are difficult to identify using existing testing methods, which can help improve the reliability and extend the lifespan of insulated-gate SiC semiconductor devices.

[0077] Furthermore, the present invention is not limited to the embodiments described above, but includes various modifications. For example, the embodiments described above are examples that have been explained in detail for the purpose of easily understanding the present invention, and are not necessarily limited to having all the structures described. In addition, a part of the structure of one embodiment can be replaced with the structure of another embodiment, and it is also possible to add the structure of another embodiment to the structure of one embodiment. Furthermore, with respect to a part of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0078] Symbol Explanation

[0079] 1: SiC-MOSFET, 2: SiC substrate (n+ type), 3: Drift layer (n type), 4: Body region (p type), 5: Source region (n+ type), 6: Contact region (p+ type), 7: Source electrode, 8: Gate insulating film, 9: Gate electrode, 10: Drain electrode, 11: DC power supply, 12: Inductive load, GD: Gate driver, SW1~SW4: Switching elements.

Claims

1. A test method for an insulated-gate SiC semiconductor device, characterized in that, have: (a) The procedure of assembling the component under test into an H-bridge circuit with an inductive load; as well as (b) The step of repeatedly turning the switch on and off according to the gate voltage signal of the H-bridge circuit to allow bidirectional current to flow to the device under test. When the rated breaking withstand voltage of the tested component is set to Vav [kV], the gate insulating film thickness is set to t [nm], and the voltage change rate during switching on / off is set to dv / dt [kV / µs], The condition dv / dt > 0.06 × t × Vav is satisfied. The relational expression.

2. The test method for the insulated-gate SiC semiconductor device according to claim 1, characterized in that, The rated breaking withstand voltage of the tested element is above 2kV.

3. The test method for the insulated-gate SiC semiconductor device according to claim 1, characterized in that, In step (b), the bonding temperature of the tested element is heated to above 100°C by self-heating through an energized circuit.

4. The test method for the insulated-gate SiC semiconductor device according to claim 1, characterized in that, In step (b), the maximum value of the bidirectional current flowing to the element under test is more than 1 / 5 of the maximum rated current of the element under test.

5. The test method for the insulated-gate SiC semiconductor device according to claim 1, characterized in that, In step (b), the maximum value of the bidirectional current flowing to the element under test is more than 1 / 2 of the maximum rated current of the element under test.

6. An insulated-gate SiC semiconductor device comprising a gate terminal, a source terminal, and a drain terminal, wherein the current flowing between the source terminal and the drain terminal is controlled by applying a voltage to the gate terminal, characterized in that... Has the following resume: Install an H-bridge circuit with an inductive load; and The H-bridge circuit repeatedly switches on and off based on the gate voltage signal, allowing bidirectional current to flow to the insulated-gate SiC semiconductor element. When the rated breaking voltage is set to Vav [kV], the gate insulating film thickness is set to t [nm], and the voltage change rate during switching on / off is set to dv / dt [kV / µs], The condition dv / dt > 0.06 × t × Vav is satisfied. The relational expression.

7. The insulated-gate SiC semiconductor device according to claim 6, characterized in that, The rated breaking voltage is above 2kV.

8. The insulated-gate SiC semiconductor device according to claim 6, characterized in that, During the repeated switching on and off, the junction temperature is heated to over 100°C by the self-heating of the energized circuit.

9. The insulated-gate SiC semiconductor device according to claim 6, characterized in that, During the repeated switching on and off, the maximum bidirectional current flowing to the insulated gate SiC semiconductor element is more than 1 / 5 of the maximum rated current of the insulated gate SiC semiconductor element.

10. The insulated-gate SiC semiconductor device according to claim 6, characterized in that, During the repeated switching on and off, the maximum bidirectional current flowing to the insulated gate SiC semiconductor element is more than 1 / 2 of the maximum rated current of the insulated gate SiC semiconductor element.

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