Array substrate, display panel, near-eye display device and manufacturing method

Abstract

An array substrate, a display panel, a near-eye display device and a manufacturing method. The array substrate comprises: a substrate (1); a first active layer (2) located on one side of the substrate (1) and comprising a plurality of first active patterns (20); a first insulating layer (31) located on a side of the first active layer (2) away from the substrate (1) and having a plurality of first through holes (K1); and a first metal layer (M1) located on a side of the first insulating layer (31) away from the first active layer (2) and comprising a plurality of first metal lines (M11), wherein the first metal lines (M11) are electrically connected to the first active patterns (20) through the first through holes (K1), and a maximum dimension of the first through holes (K1) in a first direction (X) in an orthographic projection of the substrate (1) is not equal to a maximum dimension in a second direction (Y), and the first direction (X) and the second direction (Y) intersect.

Description

Array substrate, display panel, near-eye display device and manufacturing method Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, a display panel, a near-eye display device, and a manufacturing method. Background Technology

[0002] As consumer demands for display technology continue to evolve, thinner, smaller, and higher resolution have become the mainstream trends in current display technology products. Fast-response liquid crystal displays (Fast-LCDs) occupy an important position in the field of high-resolution near-eye displays due to their low cost, fast response speed, and high pixel density. Low-temperature polycrystalline oxide (LTPO) technology, as a low-power display technology, effectively reduces panel driving frequency through its oxide semiconductor layer, thereby reducing screen display power consumption. With the support of LTPO technology, Fast-LCDs combine the high mobility of Low-Temperature Poly-Silicon (LTPS) with the low leakage current and low refresh rate characteristics of oxide semiconductor transistors. Summary of the Invention

[0003] This disclosure provides an array substrate, a display panel, a near-eye display device, and a method for manufacturing it. The array substrate includes:

[0004] Substrate;

[0005] The first active layer, located on one side of the substrate, includes: a plurality of first active patterns;

[0006] A first insulating layer, located on the side of the first active layer opposite to the substrate, has a plurality of first vias;

[0007] A first metal layer, located on the side of the first insulating layer opposite to the first active layer, includes: a plurality of first metal lines; the first metal lines are electrically connected to the first active pattern through the first via;

[0008] Wherein, the maximum size of the first via projected onto the substrate along the first direction is not equal to the maximum size along the second direction, and the first direction intersects the second direction.

[0009] In one possible implementation, the maximum size of the first via projected onto the substrate along the first direction is greater than the maximum size along the second direction.

[0010] In one possible implementation, the plurality of first metal wires are arranged sequentially along the first direction;

[0011] The array substrate includes: a plurality of first active pattern groups extending along the first direction and arranged along the second direction; the first active pattern group includes: a plurality of first active patterns arranged sequentially along the first direction.

[0012] Multiple first active patterns in the same first active pattern group are electrically connected to multiple first metal lines through the same first via.

[0013] In one possible implementation, the length of the first via in the first direction is greater than or equal to the length of the first active pattern group in the first direction.

[0014] In one possible implementation, the maximum dimension of the first via in the second direction is greater than the maximum dimension of the first metal wire in the first direction.

[0015] In one possible implementation, the array substrate further includes: a second insulating layer located on the side of the first metal layer facing away from the substrate, and a third insulating layer located between the first active layer and the substrate; the first metal line includes: a first surface facing away from the substrate, and two side surfaces connected to the first surface; the first active pattern has a second surface facing away from the substrate; the third insulating layer has a third surface facing away from the substrate.

[0016] In the region where the first via is located and along the first direction, the first via exposes a portion of the second surface and the third surface between adjacent first active patterns. The first metal wire covers a portion of the second surface through the first via. The second insulating layer covers the first surface and the side of the first metal wire, and covers the second surfaces on both sides of the first metal wire through the first via, as well as the third surface between adjacent first active patterns.

[0017] In one possible implementation, the first metal wire extends along a second direction at the outer boundary of the first via.

[0018] In one possible implementation, the first insulating layer includes a plurality of first vias arranged along the first direction; in the first direction, the spacing between two adjacent first vias is smaller than the spacing between two adjacent first metal lines.

[0019] In one possible implementation, the first via has a rectangular shape when projected onto the substrate.

[0020] In one possible implementation, the first via includes: a via main portion and a via protrusion; the via main portion extends along the first direction, and the via protrusion is connected at the position where the via main portion intersects with the first metal wire, and extends along the second direction.

[0021] In one possible implementation, the first via includes two via protrusions, which are located on different sides of the main via along the second direction.

[0022] In one possible implementation, the via main portion has a rectangular orthographic projection on the substrate, and the via protrusion has an arc-shaped orthographic projection on the substrate.

[0023] In one possible implementation, the maximum size of the first via projected onto the substrate along the first direction is smaller than the maximum size along the second direction.

[0024] In one possible implementation, the outer boundary of the first via is at least partially curved when projected onto the substrate.

[0025] In one possible implementation, the first via includes: two first ends and two second ends; the distance between the two first ends is the maximum distance of the first via along the second direction, and the distance between the two second ends is the maximum distance of the first via along the first direction;

[0026] Along the outer boundary of the first via from the first end to the second end, the curvature of the outer boundary of the first via gradually decreases.

[0027] In one possible implementation, the ratio of the maximum size of the first via projected onto the substrate along the first direction to the maximum size along the second direction ranges from 0.5 to 0.9.

[0028] In one possible implementation, the orthographic projection shape of the first via on the substrate is elliptical.

[0029] Based on the same inventive concept, embodiments of this disclosure also provide an array substrate, comprising:

[0030] Substrate;

[0031] The first active layer, located on one side of the substrate, includes: a plurality of first active patterns;

[0032] A first insulating layer, located on the side of the first active layer opposite to the substrate, has a plurality of first vias;

[0033] A first metal layer, located on the side of the first insulating layer opposite to the first active layer, includes: a plurality of first metal lines; the first metal lines are electrically connected to the first active pattern through the first via;

[0034] Wherein, the maximum size of the first via projected onto the substrate along the first direction is equal to the maximum size along the second direction, the first direction intersects the second direction, and at least a portion of the outer boundary of the first via projected onto the substrate is straight.

[0035] In one possible implementation, the first via has a square shape when projected onto the substrate.

[0036] In one possible implementation, the longest dimension of the first via in the first direction is greater than the maximum dimension of the first metal wire in the first direction.

[0037] In one possible implementation, the first via includes: a first sub-via portion; the orthographic projection of the first sub-via portion onto the substrate overlaps with the orthographic projection of the first metal line onto the substrate;

[0038] The array substrate further includes: a plurality of first shielding portions, wherein the orthographic projection of the first shielding portions on the substrate at least covers the orthographic projection of the first sub-via portion on the substrate.

[0039] In one possible implementation, the width of the first blocking portion in the first direction is greater than the width of the first metal line in the first direction; and the width of the first blocking portion in the second direction is greater than the maximum width of the first via in the second direction.

[0040] In one possible implementation, the array substrate includes: a second metal layer located on the side of the first metal layer facing the substrate, and a third metal layer located on the side of the second metal layer facing the substrate;

[0041] The second metal layer includes a plurality of second metal lines extending along a first direction; the third metal layer includes a plurality of third metal lines extending along the first direction;

[0042] The first shielding portion is located in at least one of the second metal layer and the third metal layer.

[0043] In one possible implementation, the array substrate further includes: a second insulating layer located on the side of the first metal layer opposite to the substrate, a first conductive layer located on the side of the second insulating layer opposite to the first metal layer, and a second via penetrating the second insulating layer and the first insulating layer.

[0044] The first conductive layer includes: a plurality of transition electrodes; the transition electrodes are electrically connected to the first active pattern through the second via;

[0045] The array substrate further includes: a plurality of second shielding portions; the orthographic projection of the second shielding portions on the substrate covers the orthographic projection of the second via on the substrate.

[0046] In one possible implementation, the second shielding portion and the first shielding portion are made of the same layer and material.

[0047] In one possible implementation, the array substrate further includes: a fourth insulating layer located on the side of the first conductive layer opposite to the first metal layer, a second conductive layer located on the side of the fourth insulating layer opposite to the first conductive layer, and a third via.

[0048] The second conductive layer includes: a plurality of sub-pixel electrodes; the third via penetrates the fourth insulating layer and a portion of the second insulating layer, and exposes a portion of the transition electrode; the sub-pixel electrodes are electrically connected to the transition electrode through the third via.

[0049] In one possible implementation, the first conductive layer further includes: a plurality of first blocking portions; the first blocking portions are spaced apart from the transition electrode;

[0050] The orthographic projection of the first blocking portion on the substrate at least covers the orthographic projection of the first sub-via portion on the substrate.

[0051] In one possible implementation, the first active pattern includes: a first active portion, a second active portion, and a third active portion;

[0052] The first active portion extends along the second direction, and its orthographic projection on the substrate overlaps with the orthographic projection of the first metal line on the substrate, and is electrically connected through the first via at the overlapping position.

[0053] The second active portion extends along the second direction, and in the orthographic projection of the substrate, it is located between the orthographic projections of the two adjacent first metal lines on the substrate, and overlaps with the orthographic projection of the transfer electrode on the substrate, and is electrically connected through the second via at the overlapping position.

[0054] The third active part extends along a third direction and connects the first active part and the second active part. The third direction intersects the first direction and the second direction.

[0055] In one possible implementation, the array substrate further includes: a second active layer located on the side of the first active layer facing the substrate, and a driving source, a driving drain, and a driving gate;

[0056] The material of the first active layer includes: metal oxide; the material of the second active layer includes: low-temperature polycrystalline silicon.

[0057] Based on the same inventive concept, this disclosure also provides a display panel, which includes the array substrate as provided in the embodiments of this disclosure, and further includes a counter substrate disposed opposite to the array substrate.

[0058] Based on the same inventive concept, embodiments of this disclosure also provide a near-eye display device, which includes the display panel as described in embodiments of this disclosure.

[0059] Based on the same inventive concept, this disclosure also provides a method for fabricating an array substrate as described in the embodiments of this disclosure, wherein the fabrication method includes:

[0060] A first active layer having multiple first active patterns is formed on one side of the substrate;

[0061] A first insulating layer having a plurality of first vias is formed on the side of the first active layer away from the substrate, wherein the maximum size of the first vias projected onto the substrate along a first direction is not equal to the maximum size along a second direction, and the first direction intersects the second direction;

[0062] A first metal layer having multiple first metal lines is formed on the side of the first insulating layer opposite to the first active layer, wherein the first metal lines are electrically connected to the first active pattern through the first via.

[0063] In one possible implementation, forming a first insulating layer having a plurality of first vias on the side of the first active layer opposite to the substrate includes:

[0064] A first insulating film is formed on the side of the first active layer opposite to the substrate;

[0065] A first photoresist layer is formed on the side of the first insulating film opposite to the first active layer, wherein the first photoresist layer is a positive photoresist.

[0066] The first photoresist layer is exposed through a first mask, wherein the first mask has a first cutout extending along a first direction and arranged sequentially along a second direction, and the orthographic projection of the first cutout on the substrate overlaps with the orthographic projection of the first via on the substrate.

[0067] A developing and etching process is performed to remove the first photoresist layer in the first hollow area and form a first insulating layer having a plurality of first vias, wherein the plurality of first vias extend along the first direction and are arranged along the second direction.

[0068] In one possible implementation, forming a first insulating layer having a plurality of first vias on the side of the first active layer opposite to the substrate includes:

[0069] A first insulating film is formed on the side of the first active layer opposite to the substrate;

[0070] A second photoresist layer is formed on the side of the first insulating film opposite to the first active layer, wherein the second photoresist layer is a negative photoresist;

[0071] The second photoresist layer is exposed by a second mask, wherein the second mask has second light-shielding portions extending along a first direction and arranged sequentially along a second direction;

[0072] The second photoresist layer is exposed by a third mask, wherein the third mask has a third light-shielding portion extending along the second direction and arranged sequentially along the first direction;

[0073] In the development process, the second photoresist layer at the overlapping area of ​​the second and third masking portions is removed, while the second photoresist layer in the remaining areas is retained, forming a photoresist masking pattern with multiple photoresist cutouts. The orthographic projection of the photoresist cutouts on the substrate coincides with the orthographic projection of the overlapping area of ​​the second and third masking portions on the substrate.

[0074] Under the cover of the photoresist masking pattern, the first insulating film is etched to form the first insulating layer having a plurality of first vias. Attached Figure Description

[0075] Figure 1A is a schematic diagram showing that the data line is elliptical at the via location;

[0076] Figure 1B is a schematic diagram of polarization state decomposition when light passes through the lower polarizer and reaches the elliptical boundary of the data line.

[0077] Figure 1C is a schematic diagram of polarization state decomposition after light passes through the elliptical boundary of the data line;

[0078] Figure 2A is one of the top views of the array substrate provided in the embodiments of this disclosure;

[0079] Figure 2B is a schematic diagram of the cross section along the dashed line f1 in Figure 2A;

[0080] Figure 2C is a schematic diagram of the cross section along the dashed line f2 in Figure 2A;

[0081] Figure 2D is a second top view of the array substrate provided in the embodiment of this disclosure;

[0082] Figure 2E is a schematic diagram of the cross section along the dashed line f3 in Figure 2D;

[0083] Figure 2F is a schematic diagram of the single film layer of the third metal layer in Figure 2D;

[0084] Figure 2G is a schematic diagram of the single film layer of the first active layer in Figure 2D;

[0085] Figure 2H is a schematic diagram of a single film layer of the second metal layer in Figure 2D;

[0086] Figure 2I is a schematic diagram of the single film layer of the first metal layer in Figure 2D;

[0087] Figure 2J is a schematic diagram of a single film layer of the first conductive layer in Figure 2D;

[0088] Figure 2K is a schematic diagram of a single film layer of the sub-pixel electrode layer in Figure 2D;

[0089] Figure 2L is a schematic diagram showing that Figure 2D also includes a fourth metal layer and a third conductive layer.

[0090] Figure 2M is a schematic diagram of the fourth metal layer in Figure 2L;

[0091] Figure 2N is a schematic diagram of a single film layer of the third conductive layer in Figure 2L;

[0092] Figure 20 is a schematic diagram of three first active patterns corresponding to one first via provided in an embodiment of this disclosure;

[0093] Figure 3A is a third top view of the array substrate provided in the embodiment of this disclosure;

[0094] Figure 3B is one of the schematic diagrams of the first metal wire and the first via provided in the embodiments of this disclosure;

[0095] Figure 4 is a top view of the array substrate provided in the embodiment of this disclosure;

[0096] Figure 5 is a top view of the array substrate provided in the embodiment of this disclosure;

[0097] Figure 6 is a top view of the array substrate provided in the embodiment of this disclosure;

[0098] Figure 7 is a top view of the array substrate provided in the embodiment of this disclosure;

[0099] Figure 8 is a schematic diagram of the angle between light rays at a circular via and an elliptical via;

[0100] Figure 9 is a top view of the array substrate provided in the embodiment of this disclosure (eighth one);

[0101] Figure 10 is a top view of the array substrate provided in the embodiment of this disclosure;

[0102] Figure 11 is a top view of the array substrate provided in the embodiment of this disclosure;

[0103] Figure 12A is a schematic diagram of the mask used to fabricate the square first via in an embodiment of this disclosure;

[0104] Figure 12B is a schematic diagram of one of the mask plates in Figure 12A;

[0105] Figure 12C is a schematic diagram of another mask plate in Figure 12A;

[0106] Figure 13A is an eleventh top view schematic diagram of the array substrate provided in the embodiment of this disclosure;

[0107] Figure 13B is a schematic diagram of the single film layer of the third metal layer in Figure 13A;

[0108] Figure 14A is a top view of the array substrate provided in an embodiment of this disclosure, number 12.

[0109] Figure 14B is a schematic diagram of a single film layer of the second metal layer in Figure 14A;

[0110] Figure 15 is one of the cross-sectional schematic diagrams of the array substrate corresponding to the dashed line f3 in Figure 2D provided in the embodiments of this disclosure;

[0111] Figure 16A is one of the cross-sectional schematic diagrams of the display panel corresponding to the dashed line f1 in Figure 2A provided in an embodiment of this disclosure;

[0112] Figure 16B is one of the cross-sectional schematic diagrams of the display panel corresponding to the dashed line f2 in Figure 2A provided in an embodiment of this disclosure;

[0113] Figure 17 is a schematic diagram of the fabrication process of the array substrate provided in the embodiments of this disclosure. Detailed Implementation

[0114] Different forms may be used to implement this disclosure. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited solely to the content described in the following embodiments. Without conflict, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0115] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0116] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure can include two or more quantities.

[0117] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0118] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0119] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0120] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0121] Furthermore, the gate of a transistor can be referred to as the control electrode. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0122] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.

[0123] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0124] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0125] In this specification, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this specification, "roughly the same" can mean that the values ​​differ by no more than 10%.

[0126] Light leakage in LCD technology has always been a bottleneck limiting static contrast. Unlike factors affecting contrast in conventional products, virtual reality (VR) displays have small pixel sizes. Besides the scattering of linearly polarized light by materials such as liquid crystal and color resist, the flatness of the array substrate film and the depolarization problem caused by metal along holes in the panel structure are also major factors causing light leakage in high-PPI LCDs, thus limiting the static contrast. Research on the light leakage status of 1200ppi and 1400ppi products revealed that the main light leakage points occur at vias connecting data lines and active patterns, vias connecting pixel electrodes and transition electrodes, and vias connecting transition electrodes and active patterns. The degree of light leakage is ranked as follows: vias connecting data lines and active patterns > vias connecting pixel electrodes and transition electrodes > vias connecting transition electrodes and active patterns. In other words, the light leakage is most severe at the vias connecting data lines and active patterns. The light leakage images and locations are shown in Figure 1A.

[0127] By observing the image at grayscale 0 under a microscope, it can be found that there is light leakage at the location of the via K (i.e., the interlayer dielectric (ILD) hole) where the data line is connected to the active pattern. As shown in Figures 1A-1C, this is because the data line 01 overlaps on the hole wall of via K. During the etching process, the morphology of the data line will be distributed along the elliptical hole wall of via K, resulting in the data line 01 at the location of via K appearing as an ellipse.

[0128] Referring to Figures 1B and 1C, Figure 1B is a schematic diagram of the polarization state decomposition when light passes through the lower polarizer and reaches the elliptical boundary of data line 01, and Figure 1C is a schematic diagram of the polarization state decomposition after light passes through the elliptical boundary of data line 01. O1 represents the transmission axis direction of the front polarizer (i.e., the lower polarizer), and O2 represents the transmission axis direction of the rear polarizer (i.e., the upper polarizer). When light passes through the lower polarizer of the LCD, it becomes linearly polarized light with a magnitude of Ex. When the linearly polarized light passes through the elliptical data line 01, its propagation direction is deflected by an angle of β due to diffraction. During the deflection process, the S-component remains unchanged, but the P-component undergoes an angle deflection (becoming P'). Therefore, after passing through data line 01, the resultant polarization direction of the light is deflected, allowing some light components to pass through the upper polarizer with a magnitude of E. y =E x *cosα*sinα*(1-cosβ), meaning there will be light leakage at the L0 gray level, resulting in low contrast. In other words, the display product will leak light in the dark, which will seriously affect the user experience.

[0129] In view of the above, this disclosure provides an array substrate, as shown in Figures 2A-2C, wherein Figure 2B is a cross-sectional view along the dashed line f1 in Figure 2A, and Figure 2C is a cross-sectional view along the dashed line f2 in Figure 2A. The array substrate includes:

[0130] Substrate 1;

[0131] The first active layer 2 is located on one side of the substrate 1 and includes: a plurality of first active patterns 20;

[0132] The first insulating layer 31 is located on the side of the first active layer 2 away from the substrate 1 and has a plurality of first vias K1;

[0133] The first metal layer M1 is located on the side of the first insulating layer 31 opposite to the first active layer 2, and includes: multiple first metal lines M11; the first metal lines M11 are electrically connected to the first active pattern 20 through the first via K1; optionally, the first metal lines M11 can be data lines.

[0134] Wherein, the maximum size a1 of the first via K1 projected onto the substrate 1 along the first direction X is not equal to the maximum size a2 along the second direction Y. The first direction X intersects the second direction Y. Optionally, the first direction X is perpendicular to the second direction Y.

[0135] In this embodiment, the maximum size a1 of the first via K1 projected onto the substrate 1 along the first direction X is not equal to the maximum size a2 along the second direction Y. That is, the first via K1, which connects the first metal line M11 to the first active pattern 20, is set as a strip shape. This effectively avoids the problem that if the first via K1 is a circular hole, the first metal line M11 (data line) overlapping the circular hole will affect the refraction direction of the deflected light at the four corner arcs of the circular hole, thus causing light leakage.

[0136] In related technologies, the common approach to improve light leakage at the first via is to add a metal block to block the light, reduce the aperture of the first via, increase the line width of the first metal line M11 (data line), or increase the overall width of the black matrix. However, adding a metal block requires an additional masking process, which increases the manufacturing cost. Reducing the aperture of the first via or increasing the line width of the first metal line M11 (data line) can lead to insufficient margin and the limiting of equipment capacity in actual production due to the high pixel density and small wiring line width of high PPI display products. Increasing the overall width of the black matrix can significantly reduce the overall pixel opening, and there is also the problem of insufficient exposure of the black matrix opening. In this embodiment, by making the first via K1 with a maximum size a1 along the first direction X that is not equal to the maximum size a2 along the second direction Y, compared with conventional solutions, this embodiment can not only break through the limit of the aperture of the exposure equipment of 1.9μm-2.0μm, but also avoid light leakage caused by light deflection after the first metal line M11 (data line) overlaps with the circular hole. At the same time, it saves a mask process, thereby increasing production and reducing costs.

[0137] In one possible implementation, referring to FIG2A, the maximum dimension a1 of the first via K1 projected onto the substrate 1 along the first direction X is greater than the maximum dimension a2 along the second direction Y. That is, the first via K1 is a long strip in the first direction X.

[0138] In one possible implementation, referring to FIG2A, multiple first metal lines M11 are arranged sequentially along a first direction X; the array substrate includes: multiple first active pattern groups 200 extending along the first direction X and arranged along a second direction Y; the first active pattern group 200 includes: multiple first active patterns 20 arranged sequentially along the first direction X; the multiple first active patterns 20 of the same first active pattern group 200 are electrically connected to the multiple first metal lines M11 respectively through the same first via K1. In this embodiment of the present disclosure, the first via K1 corresponding to the same first active pattern group 200 can be set as a through hole, that is, the first via K1 of a sub-pixel row is a through hole, which can improve the light leakage problem at the first via K1 with a small modification to the existing process and at a lower process cost.

[0139] In practice, the mask corresponding to the first via K1 can be set as a strip-shaped first cutout at the first via (the orthographic projection of the first cutout on the substrate can coincide with the orthographic projection of the first via K1 on the substrate), and positive photoresist can be used. The strip-shaped first cutout of the mask is the unmasked area, and the rest are the masked areas. The strip-shaped first via can be made in one mask process, which is simple and low cost.

[0140] Optionally, the first active pattern group 200 may correspond to a sub-pixel row, that is, the first active pattern group 200 may include a first active pattern 20 with a sub-pixel row.

[0141] In one possible implementation, referring to FIG2A, the length a1 of the first via K1 in the first direction X is greater than or equal to the length a3 of the first active pattern group 200 in the first direction X.

[0142] Optionally, the length a3 of the first active pattern group 200 in the first direction X can be the maximum distance between the two outermost first active patterns 20 in the first active pattern group 200 in the first direction X. For example, it can be the distance between the leftmost edge of the leftmost first active pattern 20 in Figure 2A and the rightmost edge of the rightmost first active pattern 20.

[0143] It should be noted that, due to the limited area shown in the attached figures, Figure 2A is only used to illustrate the first active pattern group 200 containing 7 first active patterns 20. In actual implementation, it is not limited to this.

[0144] In one possible implementation, a portion of the first active patterns 20 in a first active pattern group 200 may correspond to a first via K1. For example, two first active patterns 20 may be electrically connected to the corresponding first metal line M11 through the same first via K1. As shown in FIG20, three first active patterns 20 may be electrically connected to the corresponding first metal line M11 through the same first via K1, that is, a first via K1 may be made for every three sub-pixels (one pixel). For example, four first active patterns 20 may be electrically connected to the corresponding first metal line M11 through the same first via K1. For example, five first active patterns 20 may be electrically connected to the corresponding first metal line M11 through the same first via K1.

[0145] In one possible implementation, referring to FIG2A, the maximum dimension a2 of the first via K1 in the second direction Y is smaller than the maximum dimension a4 of the first metal wire M11 in the first direction X.

[0146] In one possible implementation, as shown in Figure 2C, the slope angle α of the first through hole K1 can be in the range of 60° to 70°.

[0147] In another possible implementation, as shown in FIG3A, the maximum dimension a2 of the first via K1 in the second direction Y is greater than the maximum dimension a4 of the first metal wire M11 in the first direction X.

[0148] In one possible implementation, referring to FIG3B, the outer boundary of the first metal line M11 at the first via K1 extends along the second direction Y. That is, in this embodiment of the present disclosure, for the actually formed first metal line M11 at the first via K1, its boundary can be a straight line extending along the second direction Y, which can avoid forming a circular shape as shown in FIG1A, and thus avoid the problem of light leakage caused by the first metal line M11 affecting the polarization direction at the circular first via.

[0149] Optionally, referring to Figure 3A, the maximum dimension a2 of the first via K1 in the second direction Y ranges from 1.2μm to 2.5μm; this is to achieve a smaller dimension of the first via K1 in the second direction Y within the limits of process capability, so as to avoid the maximum dimension a2 of the first via K1 in the second direction Y being too large, which would cause the exposed area of ​​the first active pattern 20 below to be too large, affecting the characteristics; optionally, the maximum dimension a2 of the first via K1 in the second direction Y ranges from 1.9μm to 2.0μm; optionally, the first The maximum dimension a2 of the via K1 in the second direction Y is 1.8μm, 1.9μm, 2.0μm, and 2.1μm. Currently, since the lower limit of the exposure machine is 1.9μm to 2.0μm, the maximum dimension a2 of the first via K1 in the second direction Y can be set according to the lower limit of the exposure machine. That is, the maximum dimension a2 of the first via K1 in the second direction Y can be 2.0μm. This is to avoid the maximum dimension a2 of the first via K1 in the second direction Y being too large, which would cause the exposed area of ​​the first active pattern 20 below to be too large and affect the characteristics.

[0150] In one possible implementation, referring to Figures 2A-2C, the array substrate further includes: a second insulating layer 32 located on the side of the first metal layer M1 facing away from the substrate 1, and a third insulating layer 33 located between the first active layer 2 and the substrate 1; the first metal line M11 includes: a first surface f1a on the side facing away from the substrate 1, and two side surfaces f1b connected to the first surface f1a; the first active pattern 20 has a second surface f2 on the side facing away from the substrate 1; the third insulating layer 33 has a third surface f3 on the side facing away from the substrate 1.

[0151] In the region where the first via K1 is located and along the first direction X, the first via K1 exposes a portion of the second surface f1 (optionally, it can expose the entire second surface f2 along the first direction X) and exposes the third surface f3 between adjacent first active patterns 20. The first metal line M11 covers a portion of the second surface f2 through the first via K1. The second insulating layer 32 covers the first surface f1a and side surface f1b of the first metal line M11, and covers the second surfaces f2 on both sides of the first metal line M11 through the first via K1, as well as the third surface f3 between adjacent first active patterns 20. That is, as shown in Figure 2A, when the first insulating layer 31 is laterally removed to form the first via K1, the depth of the removal in the direction perpendicular to the substrate 1 can reach the second surface f2 of the first active pattern 20 on the side facing away from the substrate 1. Since a through hole is to be formed in the first direction X, the third surface f3 of the third insulating layer 33 below the first active pattern 20 on both sides of the first active pattern 20 will also be exposed (as shown in Figure 2B). When the first metal line M11 extending along the second direction Y is formed, as shown in Figure 2A, along the second direction Y, the first metal line M11 overlaps the upper surface of the first insulating layer 31 in the area above and below the first via K1, and is recessed at the position of the first via K1, with the exposed first active pattern 20. The second surface f2 of the source pattern 20 contacts and overlaps; when the second insulating layer 32 is covered above the first metal line M11, the second insulating layer 32 covers the first metal line M11 along the second direction Y, the upper surface of the second insulating layer 31 covering the area outside the first via K1 and the first metal line M11, and at the first via K1 extending laterally, as shown in FIG2B, the second insulating layer 32 covers the second surface f2 of the first active pattern 20 exposed by the first via K1, covered by the first metal line M11 and located on the left and right sides of the first metal line M11 (as shown in the dashed box S1 in FIG2B), and covers the third surface f3 of the lower third insulating layer 33 between the two first active patterns 20 (that is, as shown in the dashed box S2 in FIG2B).

[0152] In one possible implementation, referring to Figure 4, the first insulating layer 31 includes a plurality of first vias K1 arranged along the first direction X. That is, each of the first vias K1 in the first direction X can also be a non-connected structure. However, the first vias K1 are also elongated structures, which can also avoid the problem of light leakage caused by the first metal line M11 affecting the polarization direction at the circular first via. Moreover, compared with a first active pattern group 200 for the same first via K1, the plurality of first vias K1 are mutually spaced and independent structures, which can be beneficial to the uniformity of the thickness of the upper film layer. For example, it can be beneficial to the uniformity of the color resist film layer formed subsequently. As shown in Figure 4, in the first direction X, the spacing a5 between two adjacent first vias K1 can be smaller than the spacing a6 between two adjacent first metal lines M11.

[0153] Due to limitations of the exposure equipment, the spacing a5 between two adjacent first vias K1 in Figure 4 is ≥ 1.4 μm; similarly, due to limitations of the exposure equipment, the minimum size a2 of the first via K1 in the second direction Y is ≥ 1.4 μm; the minimum size a2 of the first via K1 in the second direction Y is ≤ 2.0 μm, to avoid the first via K1 being too large in the second direction Y, exposing too much area of ​​the first active pattern 20, which would affect the transistor characteristics; in the first direction X, the minimum size a1 of the first via K1 in the first direction X is ≥ 2.0 μm, to satisfy the requirement that the first via K1 needs to be larger than the linewidth of the first metal line M11, and the process margin on both sides of the first metal line M11, that is, the minimum size a1 of the first via K1 in the first direction X needs to satisfy ≥ the linewidth of the first metal line M11 + 2 * single-sided wrapping margin.

[0154] In one possible implementation, as shown in FIG2A or FIG4, the orthogonal projection shape of the first via K1 onto the substrate 1 is rectangular.

[0155] In one possible implementation, referring to Figure 5, the maximum dimension a1 of the first via K1 projected onto the substrate 1 along the first direction X is smaller than the maximum dimension a2 along the second direction Y. That is, the first via K1 is a long strip in the second direction Y. In this embodiment of the present disclosure, the maximum dimension a1 of the first via K1 projected onto the substrate 1 along the first direction X is smaller than the maximum dimension a2 along the second direction Y. This also avoids the problem of light leakage caused by the first metal line M11 (data line) at the four arc-shaped corners of the circular via K1 affecting the refraction direction of the deflected light when the first via K1 is a perfectly circular via.

[0156] In one possible implementation, as shown in FIG5, at least a portion of the outer boundary of the first via K1 projected onto the substrate 1 is curved.

[0157] In one possible implementation, referring to FIG5, the first via K1 includes: two first ends K1A and two second ends K1B; the distance between the two first ends K1A is the maximum distance of the first via K1 along the second direction Y, and the distance between the two second ends K1B is the maximum distance of the first via K1 along the first direction X.

[0158] Along the outer boundary of the first via K1 from the first end K1A to the second end K1B, the curvature of the outer boundary of the first via K1 gradually decreases.

[0159] In one possible implementation, referring to Figure 5, the ratio of the maximum dimension a1 of the first via K1 projected onto the substrate 1 along the first direction X to the maximum dimension a2 along the second direction Y ranges from 0.5 to 0.9. In another possible implementation, the ratio of the maximum dimension a1 of the first via K1 projected onto the substrate 1 along the first direction X to the maximum dimension a2 along the second direction Y can be 0.5, 0.6, 0.7, 0.8, or 0.9.

[0160] In one possible implementation, due to actual process limitations, when the first via K1 is designed as a rectangle with a longer second direction Y before actual fabrication, the shape of the actually fabricated first via K1 may deviate from the design. For example, it may be arc-shaped at the corner, or as shown in FIG6, the orthographic projection shape of the first via K1 on the substrate 1 is elliptical, or as shown in FIG7, the orthographic projection shape of the first via K1 on the substrate 1 is a rectangle with an arc at the corner.

[0161] In actual manufacturing processes, a hole designed as a square may actually be produced as a perfect circle using conventional processes; a hole designed as a rectangle may actually be produced as an elliptical hole using conventional processes. The actual shape of the first metal line M11 at the first via K1 is determined by the actual exposure shape of the first via K1. The angle between the outline of the first metal line M11 within the first via K1 and the linear polarizer determines the light leakage intensity; the gentler the angle, the lower the light leakage intensity. See Figure 8 for details; the left-hand attached figure shows a perfect circle first via K1 and an elliptical via K1. At the circular first via K1, a schematic diagram of the angle α between the chamfer of the first metal line M11's shape profile within the first via K1 and the direction of light polarization is shown. The attached diagram on the right shows a schematic diagram of the angle α between the chamfer of the first metal line M11's shape profile within the first via K1 and the direction of light polarization. As can be seen from Figure 8, at the elliptical first via K1, the angle α between the chamfer of the first metal line M11's shape profile within the first via K1 and the direction of light polarization is smaller and gentler, resulting in less light leakage.

[0162] Compared to an ellipse that is longer in the first direction X, the angle α between the chamfer of the first metal line M11 and the light polarization direction in the first via K1 will be larger, resulting in greater light leakage. However, in the embodiments of this disclosure, for the first via K1 shown in Figure 6 or Figure 7, which is an ellipse that is longer in the second direction Y, the angle α between the chamfer of the first metal line M11 and the light polarization direction in the first via K1 can be smaller, the angle is gentler, and the light leakage will be less.

[0163] In one possible implementation, the first via K1 can also be a via that is longer in the first direction X and a via that is longer in the second direction Y, which are superimposed to form a hole. Specifically, as shown in FIG9, the first via K1 includes: a via main part K1A and a via protrusion K1B; the via main part K1A extends along the first direction X, and the via protrusion K1B is connected at the position where the via main part K1A intersects with the first metal line M11, and extends along the second direction Y.

[0164] In one possible implementation, as shown in FIG9, the first via K1 includes two via protrusions K1B, which are located on different sides of the main via K1A along the second direction X.

[0165] In one possible implementation, referring to FIG9, the orthographic projection shape of the via main portion K1A on the substrate 1 is rectangular, and the orthographic projection shape of the via external protrusion K1B on the substrate 1 is arc-shaped. For example, the orthographic projection shape of the via external protrusion K1B on the substrate 1 is semi-circular or semi-elliptical.

[0166] Based on the same inventive concept, this disclosure also provides an array substrate, as shown in FIG10, wherein the array substrate includes:

[0167] Substrate 1;

[0168] The first active layer 2 is located on one side of the substrate 1 and includes: a plurality of first active patterns 20;

[0169] The first insulating layer 31 is located on the side of the first active layer 2 away from the substrate 1 and has a plurality of first vias K1;

[0170] The first metal layer M1 is located on the side of the first insulating layer 31 opposite to the first active layer 2, and includes: multiple first metal lines M11; the first metal lines M11 are electrically connected to the first active pattern 20 through the first via K1.

[0171] Wherein, the maximum dimension a1 of the first via K1 projected onto the substrate 1 along the first direction X is equal to the maximum dimension a2 along the second direction Y. The first direction X intersects the second direction Y, and at least part of the outer boundary of the first via K1 projected onto the substrate 1 is straight.

[0172] Unlike the array substrates shown in Figures 2A, 3A-7, and 9, in this embodiment, the maximum size a1 of the first via K1 projected onto the substrate 1 along the first direction X is equal to the maximum size a2 along the second direction Y, and at least a portion of the outer boundary of the first via K1 projected onto the substrate 1 is straight.

[0173] In this embodiment, by improving the process of the first via K1, the first via K1, which is designed to be square, can be fabricated to be approximately square in actual form through the improved process. Specifically, referring to Figures 12A-12C, when forming the square first via K1, it can be formed through two photomasks and negative photoresist PR, using a two-stage masking process. Figure 12A is a schematic diagram of the photoresist layer being masked by one of the second photomasks MK1, which has second light-shielding portions B1 extending along the first direction X and arranged sequentially along the second direction Y. Figure 12B is a schematic diagram of the photoresist layer being masked by one of the third photomasks MK2, which has second light-shielding portions B1 extending along the first direction X and arranged sequentially along the second direction Y. The third light-shielding part B2 extends in the Y direction and is arranged sequentially along the first direction X. Since the area blocked by the negative photoresist PR disappears after development during exposure, the unblocked area will remain. That is, the area that is exposed will remain after development. Therefore, after two exposures by the mask shown in Figures 12A and 12B, except for the photoresist PR corresponding to the overlapping area B3 which is not exposed and will be removed, the photoresist PR in the other areas will be exposed to light and will remain. Then, in the development stage, except for the overlapping area B3, the other positions are protected by photoresist PR. In the etching stage, the overlapping area B3 is etched. The other areas are protected by photoresist PR and will not be etched. A square first via K1 can be formed in the B3 area.

[0174] When forming a square first via in a conventional process, a mask with multiple cutouts (the cutout areas correspond to the first via K1) is used, and positive photoresist is used for patterning. The designed square first via, through this conventional process, will usually actually produce a perfectly circular first via.

[0175] In one possible implementation, as shown in FIG10, the orthographic projection shape of the first via K1 onto the substrate 1 is a square.

[0176] In one possible implementation, referring to Figure 11, the orthographic projection shape of the first via K1 onto the substrate 1 can be a square with an arc shape at the corner. That is, for the first via K1 fabricated using the improved process, the actual fabricated first via K1 may also have a part with an arc shape at the corner, but through the process improvement, the probability of forming a completely circular hole is already low.

[0177] In one possible implementation, as shown in Figure 10 or Figure 11, the longest dimension a1 of the first via K1 in the first direction X is greater than the maximum dimension a4 of the first metal wire M11 in the first direction X.

[0178] In one possible implementation, referring to Figures 2D-2N, where Figure 2E is a cross-sectional view of Figure 2D along the dashed line f3, Figure 2F is a single-film diagram of the third metal layer in Figure 2D, Figure 2G is a single-film diagram of the first active layer in Figure 2D, Figure 2H is a single-film diagram of the second metal layer in Figure 2D, Figure 2I is a single-film diagram of the first metal layer in Figure 2D, Figure 2J is a single-film diagram of the first conductive layer in Figure 2D, Figure 2K is a single-film diagram of the sub-pixel electrode layer in Figure 2D, Figure 2L is a schematic diagram of Figure 2D further comprising a fourth metal layer and a third conductive layer, and Figure 2M is a schematic diagram of the fourth metal layer in Figure 2L. Figure 2N is a schematic diagram of a single film layer of the third conductive layer in Figure 2L. The array substrate includes: a second metal layer M2 located on the side of the first metal layer M1 facing the substrate 1, and a third metal layer M3 located on the side of the second metal layer M2 facing the substrate 1; the second metal layer M2 includes multiple second metal lines M20 extending along the first direction X; the third metal layer M3 includes multiple third metal lines M30 extending along the first direction X; optionally, the second metal lines M20 can be gate lines; the third metal lines M30 can be used to shield the channel region of the first active pattern 20 to avoid the influence of external ambient light on the channel region.

[0179] In one possible implementation, referring to Figures 2D-2N, the array substrate further includes: a second insulating layer 32 located on the side of the first metal layer M1 facing away from the substrate 1, a first conductive layer D1 located on the side of the second insulating layer 32 facing away from the first metal layer M1, and a second via K2 penetrating the second insulating layer 32 and the first insulating layer 31; the first conductive layer D1 includes: a plurality of transition electrodes D10; the transition electrodes D10 are electrically connected to the first active pattern 20 through the second via K2.

[0180] In one possible implementation, referring to Figures 2D-2N, the array substrate further includes: a fourth insulating layer 34 located on the side of the first conductive layer D1 opposite to the first metal layer M1, a second conductive layer D2 located on the side of the fourth insulating layer 34 opposite to the first conductive layer D1, and a third via K3; the second conductive layer D2 includes: a plurality of sub-pixel electrodes D21; the third via K3 penetrates the fourth insulating layer 34 and a portion of the second insulating layer 32, and exposes a portion of the transition electrode D10; the sub-pixel electrodes D21 are electrically connected to the transition electrode D10 through the third via K3.

[0181] In one possible implementation, referring to Figures 2L-2N, the array substrate further includes: a fourth metal layer M4 located on the side of the second conductive layer D2 facing away from the substrate 1, and a third conductive layer D3 located on the side of the fourth metal layer M4 facing away from the substrate 1; wherein, the fourth metal layer M4 may include: multiple fourth metal lines M40 extending along the second direction Y, the orthographic projection of the fourth metal lines M40 on the substrate 1 may overlap with the orthographic projection of the first metal line M11 on the substrate 11; the third conductive layer M3 may include multiple cutouts D30; the cutouts D30 expose at least part of the sub-pixel electrode D21; the material of the third conductive layer D3 may be the same as the material of the second conductive layer D2 and the first conductive layer D1, for example, both may be indium tin oxide; the third conductive layer D3 and the fourth metal layer M4 may be in direct contact, so as to reduce the overall resistance of the third conductive layer D3 through the fourth metal lines M40.

[0182] In one possible implementation, referring to Figures 13A, 13B, 14A, and 14B, where Figure 13B is a schematic diagram of a single film layer of the third metal layer in Figure 13A and Figure 14B is a schematic diagram of a single film layer of the second metal layer in Figure 14A, the first via K1 includes: a first sub-via portion K11; the orthographic projection of the first sub-via portion K11 on the substrate 1 overlaps with the orthographic projection of the first metal line M11 on the substrate 1; that is, the portion of the first via K1 that overlaps with the first metal line M11 can be used as the first sub-via portion K11; the array substrate further includes: a plurality of first shielding portions Z1, the orthographic projection of the first shielding portions Z1 on the substrate 1 at least covers the orthographic projection of the first sub-via portion K11 on the substrate.

[0183] In this embodiment of the present disclosure, the first shielding part Z1 can shield the first sub-via part K11, thereby further preventing light leakage at the first sub-via part K11.

[0184] In one possible implementation, referring to Figures 13A and 14A, the width b1 of the first blocking portion Z1 in the first direction X is greater than the width a4 of the first metal line M11 in the first direction X; the width b2 of the first blocking portion Z1 in the second direction Y is greater than the maximum width a2 of the first via K1 in the second direction Y. Thus, the first metal line M11 and the first sub-via portion K11 are completely covered around the first via K1, achieving light shielding at the first sub-via portion K11.

[0185] In one possible implementation, referring to Figures 13A, 13B, 14A, and 14B, the first shielding portion Z1 is located in at least one of the second metal layer M2 and the third metal layer M3. For example, in Figure 13B, the first shielding portion Z1 is located in the third metal layer M3; and as another example, in Figure 14B, the first shielding portion Z1 is located in the second metal layer M2.

[0186] Besides the light leakage at the first via K1, the light leakage at the second via K2 also significantly affects the contrast. The mechanism of light leakage at the second via K2 is mainly due to the mismatch in the refractive index of the film layers in the array substrate. The tightness of the contact between the transition electrode D10 (usually made of indium tin oxide) at the second via K2 and the lower film layer (such as the second insulating layer 32) will aggravate the light leakage at this location, even to the extent that it is comparable to the light leakage at the first via K1. Therefore, to avoid light leakage at the second via K2, in one possible implementation, as shown in Figures 13A, 13B, 14A, and 14B, the array substrate further includes: a plurality of second shielding portions Z2; the orthographic projection of the second shielding portions Z2 onto the substrate 1 covers the orthographic projection of the second via K2 onto the substrate 1. In this embodiment, a second shielding portion Z2 is also provided at the second via K2 to prevent light leakage at the second via K2.

[0187] In one possible implementation, as shown in Figures 13A, 13B, 14A, and 14B, the second shielding part Z2 is made of the same layer and material as the first shielding part Z1.

[0188] In one possible implementation, referring to FIG13B, when the second shielding part Z2 is located in the third metal layer M3, the second shielding part Z2 can be integrally formed with the third metal line M30; in another possible implementation, referring to FIG14B, when the second shielding part Z2 is located in the second metal layer M2, the second shielding part Z2 can be integrally formed with the second metal line M20.

[0189] In addition to light leakage at the first via K1 and the second via K2, light leakage also exists at the third via K3. The degree of light leakage at the third via K3 is second only to that at the first via K1. Through mechanism analysis, the light leakage at the third via K3 is mainly due to the etching residue of the fourth metal line M4 of the fourth metal layer M4 on the inclined wall of the third via K3. In specific implementation, as shown in Figure 2E, the light leakage of the third via K3 can be reduced by widening the line width of the third metal line M30, or by reducing the bottom size of the third via K3, or by thinning the thickness of the fourth insulating layer 34. In this way, the third metal line M30 can block the top of the third via K3.

[0190] Optionally, the bottom dimension of the third via K3 in the first direction X and / or the second direction Y can be designed to be 2.0μm to 3.0μm, for example, 2.0μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, 2.8μm, 2.9μm, 3.0μm;

[0191] Optionally, the top dimension of the third via K3 in the first direction X and / or the second direction Y can be designed to be 4.5μm to 5.5μm, for example, 4.5μm, 4.6μm, 4.7μm, 4.8μm, 4.9μm, 5.0μm, 5.1μm, 50μm, 5.23μm, 5.3μm, 5.4μm, 5.5μm;

[0192] Optionally, the width of the third metal line K3 in the second direction Y can be designed to be in the range of 6.5μm to 8.5μm, for example, 6.5μm, 7μm, 7.5μm, 8μm, or 8.5μm.

[0193] Furthermore, due to the smaller linewidth and aperture of high PPI display panels, as shown in Figure 2E, the insulating layer (such as the second insulating layer 32) above the first via K1 may have poor coverage of the first via K1. For example, gaps may exist around the first via K1. When etching to form the transition electrode D11, the etching liquid may enter the gaps, corroding the first metal line M11 inside the first via K1, and even corroding the oxide active pattern connected to the first metal line M11, resulting in bright spots, dark lines, and other related display defects on the display panel. In view of this, in one possible embodiment, referring to Figures 2D, 2E, and 2J, the first conductive layer D1 further includes: a plurality of first blocking portions D11; the first blocking portions D11 are spaced apart from the transition electrode D10; the orthographic projection of the first blocking portions D11 onto the substrate 1 at least covers the orthographic projection of the first sub-via portion K11 onto the substrate 1.

[0194] In this embodiment, by adding the first blocking part D11 to block the position of the first via K1, the etching solution of the etching transition electrode D10 is effectively prevented from entering the first via K1 through the gap at the edge of the hole and corroding the first metal line M11 and the first active pattern 20, thereby causing defects such as bright spots and bright and dark lines. Moreover, since the first blocking part D11 is on the same layer as the transition electrode D10, and the transition electrode D10 is usually made of transparent material, which is transparent in the visible light wavelength range, the use of the first blocking part D11 does not affect the transmittance of the entire display panel.

[0195] In related technologies, on high-resolution LTPO structure display panels, the first metal line M11 needs to be extremely fine. The film layer above the first via K1 has poor coverage of the first via K1, resulting in broken pores. The transition electrode D10 above the second insulating layer 32 is made of a transparent material (e.g., indium tin oxide). Wet etching is generally used during etching. Since the etching solution is an acidic solution, when gaps appear at the location of the first via K1 due to the poor coverage of the second insulating layer 32, the etching solution can enter the first via K1 through the gaps, thereby corroding the first metal line M11 and the first active pattern 20 below the first metal line M11. This will lead to high resistance of the first metal line M11 and even breakage. In addition, due to the chemical reaction between the acidic etching solution and the oxide first active pattern 20 (e.g., indium gallium zinc oxide), for example, Zn is deposited, which causes the electrical characteristics of the oxide transistor to become negatively biased, resulting in bright spots and other related electrical defects. In this embodiment of the present disclosure, referring to FIG2D, by covering the location of the first via K1 with a first blocking part D11, the first blocking part D11 blocks the location of the first via K1, effectively preventing the etching solution from entering the hole of the first via K1 through the gap at the hole edge, thereby preventing the etching solution from corroding the first metal line M11 and / or the first active pattern 20, and thus improving the defects such as bright spots and bright and dark lines caused by the corrosion of the first metal line M11 and / or the first active pattern 20.

[0196] In one possible implementation, as shown in FIG2D, there may be a plurality of first blocking portions D11 in the first direction X, and the plurality of first blocking portions D11 are spaced apart from each other independently; in another possible implementation, when the first through hole K1 is a through hole along the first direction X, the first blocking portion D11 may also be a through strip extending along the first direction X, that is, the first blocking portion D11 in the first direction X is an integrally connected structure.

[0197] In one possible implementation, as shown in FIG2G, the first active pattern 20 includes: a first active portion 21, a second active portion 22, and a third active portion 23.

[0198] The first active part 21 extends along the second direction Y, and its orthographic projection on the substrate 1 overlaps with the orthographic projection of the first metal line M11 on the substrate 1, and is electrically connected through the first via K1 at the overlapping position.

[0199] The second active part 22 extends along the second direction Y. In the orthographic projection of the substrate 1, it is located between the orthographic projections of the two adjacent first metal lines M11 in the substrate 1, and overlaps with the orthographic projection of the transfer electrode D10 in the substrate 1. It is electrically connected through the second via K2 at the overlapping position.

[0200] The third active part 23 extends along the third direction Z, connecting the first active part 21 and the second active part 22. The third direction Z intersects the first direction X and the second direction Y. Optionally, the angle formed by the third direction Z and the second direction Y is in the range of 30° to 60°, for example, the angle formed by the third direction Z and the second direction Y is 45°.

[0201] In one possible implementation, referring to Figure 15, the array substrate may have a display area AA and a peripheral area BB located around the display area AA, wherein the first active layer 2 may be located in the display area AA; the array substrate further includes: a second active layer C2 located on the side of the first active layer 2 facing the substrate 1, and driving source MQ2, driving drain MQ3, and driving gate MQ1; the second active layer C2 may be the peripheral area BB; the material of the first active layer 2 includes: metal oxide; the material of the second active layer C2 includes: low temperature polycrystalline silicon. In this embodiment of the present disclosure, the array substrate uses LTPO (Low Temperature Polycrystalline Oxide) technology to integrate two types of TFTs (Thin Film Transistors): LTPS (Low Temperature Poly-Silicon) and Oxide, which can enable AR and VR products to have high resolution (e.g., above 1000 PPI), high aperture ratio, and high transmittance.

[0202] In one possible implementation, the material of the first active layer 2 includes a metal oxide semiconductor material. The metal oxide semiconductor material may include any one or more of the following: amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), or indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxides (RE-OS), wherein the rare earth element-doped metal oxide may include lanthanide-doped metal oxides (Ln-OS). The crystallization state of the active layer material can be amorphous, partially crystalline, or polycrystalline. In this embodiment, the material of the first active layer 2 is a rare earth element-doped metal oxide. Even when exposed to light, the first active layer 2 can maintain stable performance, thus eliminating the need for a light-shielding layer in the pixel light-transmitting area and further improving the aperture ratio of the display panel. In this embodiment, the first active layer 2 of the display area transistor can be an oxide active layer; that is, thin-film transistors with oxide active layers have advantages such as low leakage current.

[0203] In one possible implementation, the peripheral region BB may include a plurality of driving transistors, which may include a second active pattern C21, a driving source MQ2, a driving drain MQ3, and a driving gate MQ1.

[0204] In one possible implementation, referring to FIG15, the array substrate further includes the following in the peripheral region BB: a first driving electrode MD3, a second driving electrode MQ2, a third driving electrode MD2, and a fourth driving electrode MD1, wherein the first driving electrode MD3 is electrically connected to the second driving electrode MQ2, and the third driving electrode MD2 and the fourth driving electrode MD1 are electrically connected. Specifically, the first driving electrode MD3 can serve as a first signal line, and the third driving electrode MD2 can serve as a second signal line. The first signal line may include a signal line electrically connected to the gate driving circuit, and / or a signal line electrically connected to a multiplexer; the second signal line may include a signal line electrically connected to the gate driving circuit, and / or a signal line electrically connected to a multiplexer. The first signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light emission control line. The second signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light emission control line.

[0205] In one possible implementation, referring to FIG15, the driving gate MQ1 and the second driving electrode MQ2 may be located in the third metal layer M3; the first driving electrode MD3, the third driving electrode MD2, the driving source MQ2, and the driving drain MQ3 may be located in the first metal layer M1; the fourth driving electrode MD1 may be located in the second metal layer M2.

[0206] In one possible implementation, the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 can be made of the same material. For example, the materials of the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 can include metal oxides. For example, one or a combination of indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), and indium-doped cadmium oxide.

[0207] In one possible implementation, referring to FIG2A, the first metal line M11 may extend along the second direction Y. That is, the first metal line M10 is a straight line extending along the second direction Y. In another possible implementation, the first metal line M11 may also be a broken line.

[0208] In one possible implementation, as shown in FIG2E, the array substrate further includes: a buffer layer 11 located on one side of the substrate 1, a first gate insulating layer 12 located on the side of the buffer layer 11 away from the substrate 1, a first interlayer dielectric layer 13 located on the side of the first gate insulating layer 12 away from the buffer layer 11, a second gate insulating layer 311 located on the side of the first interlayer dielectric layer 13 away from the first gate insulating layer 12, a second interlayer dielectric layer 312 located on the side of the second gate insulating layer 311 away from the first interlayer dielectric layer 13, a third interlayer dielectric layer (i.e., the second insulating layer 32) located on the side of the second interlayer dielectric layer 32 away from the second gate insulating layer 31, a planarization layer 34 located on the side of the third interlayer dielectric layer away from the second interlayer dielectric layer 312, and a passivation layer 16 located on the side of the planarization layer 34 away from the third interlayer dielectric layer.

[0209] The first insulating layer 31 may include a second gate insulating layer 311 and a second interlayer dielectric layer 312; the third insulating layer 33 may include a buffer layer 11, a first gate insulating layer 12, and a first interlayer dielectric layer 13.

[0210] Based on the same inventive concept, this disclosure also provides a display panel, which includes an array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate.

[0211] In one possible implementation, referring to Figures 16A and 16B, the opposing substrate may include an opposing substrate 21 and a black matrix layer located on the side of the opposing substrate 21 facing the array substrate. The black matrix layer may include a first black matrix portion 22. The orthogonal projection of the first black matrix portion 22 onto the substrate 1 may overlap with the portion where the first via K1 intersects with the first metal line M11 (i.e., the first sub-via K11) to achieve light leakage at the portion where the first via K1 intersects with the first data line M11.

[0212] In one possible implementation, as shown in Figures 16A and 16B, the array substrate may further include a plurality of color resists 35, which may be red, blue, or green. In this embodiment of the present disclosure, the array substrate is further provided with a color resist layer, which can prevent color mixing between different sub-pixels and is applicable to display products with a PPI of 1500 or higher.

[0213] In one possible implementation, the array substrate may not have a color filter layer. Instead, a fourth metal layer M4 can be used to improve cross-color between different sub-pixels, thereby reducing the level of cross-color without increasing the black matrix.

[0214] Based on the same inventive concept, this disclosure also provides a display device, which includes the display panel provided in this disclosure. The display device provided in this disclosure can be applied to any product or component with display functionality, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, smartwatches, fitness wristbands, and personal digital assistants.

[0215] Based on the same inventive concept, embodiments of this disclosure also provide a near-eye display device, which includes a display panel as provided in embodiments of this disclosure. For example, the near-eye display device can be applied to virtual reality (VR) glasses. Optionally, the virtual reality glasses include two displays L and R, which provide different images to the left and right eyes to achieve virtual reality display; the two displays L and R respectively include the display substrates provided in embodiments of this disclosure. The virtual reality glasses may also include a display screen, including the display panel provided in embodiments of this disclosure, wherein the effective pixel area of ​​the display screen may include a left-eye pixel area PL and a right-eye pixel area PR, and the left-eye pixel area PL and the right-eye pixel area PR respectively display different images to achieve virtual reality display.

[0216] In some embodiments, the near-eye display device provided in this disclosure can be a liquid crystal display (LCD). The LCD may include a backlight module and a display panel located on the light-emitting side of the backlight module. The display panel includes a display substrate and a counter substrate placed opposite each other, a liquid crystal layer located between the display substrate and the counter substrate, a sealant surrounding the liquid crystal layer between the display substrate and the counter substrate, a first alignment layer on the display substrate near the liquid crystal layer, a second alignment layer on the counter substrate near the liquid crystal layer, a first polarizer on the display substrate away from the liquid crystal layer, and a second polarizer on the counter substrate away from the liquid crystal layer. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. The backlight module may include a light source, a stacked reflector, a light guide plate, a diffuser, a prism assembly, etc. The light source can be a light-emitting diode (LED), such as a miniature LED (Mini LED, Micro LED, etc.).

[0217] In some embodiments, the display device provided in this disclosure may include, but is not limited to, components such as: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip may be a central processing unit, a digital signal processor, a system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and implement power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code, etc. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0218] Based on the same inventive concept, this disclosure also provides a method for fabricating an array substrate as described in this disclosure, as shown in FIG17, wherein the fabrication method includes:

[0219] Step S100: Form a first active layer having a plurality of first active patterns on one side of the substrate;

[0220] Step S200: A first insulating layer with a plurality of first vias is formed on the side of the first active layer away from the substrate, wherein the maximum size of the first vias projected onto the substrate along the first direction is not equal to the maximum size along the second direction, and the first direction and the second direction intersect.

[0221] Step S300: A first metal layer with multiple first metal lines is formed on the side of the first insulating layer away from the first active layer, wherein the first metal lines are electrically connected to the first active pattern through a first via.

[0222] In one possible implementation, regarding step S200, forming a first insulating layer having a plurality of first vias on the side of the first active layer facing away from the substrate includes:

[0223] A first insulating film is formed on the side of the first active layer away from the substrate;

[0224] A first photoresist layer is formed on the side of the first insulating film opposite to the first active layer, wherein the first photoresist layer is a positive photoresist;

[0225] The first photoresist layer is exposed by the first mask, wherein the first mask has a first cutout extending along a first direction and arranged sequentially along a second direction, and the orthographic projection of the first cutout on the substrate overlaps with the orthographic projection of the first via on the substrate.

[0226] A developing and etching process is performed to remove the second photoresist layer in the first hollow area and form a first insulating layer with multiple first vias, wherein the multiple first vias extend along a first direction and are arranged along a second direction; specifically, a developing process is performed to remove the first photoresist layer in the first hollow area, and the first insulating film is etched under the cover of the first photoresist layer to form multiple first vias in the first insulating film.

[0227] In this embodiment of the disclosure, the above steps can be used to form a first through hole K1 with a relatively long length in the first direction X, as shown in FIG2A.

[0228] In one possible implementation, regarding step S200, forming a first insulating layer having a plurality of first vias on the side of the first active layer facing away from the substrate includes:

[0229] A first insulating film is formed on the side of the first active layer away from the substrate;

[0230] A second photoresist layer is formed on the side of the first insulating film opposite to the first active layer, wherein the second photoresist layer is a negative photoresist;

[0231] The second photoresist layer is exposed by the second mask, wherein the second mask has a second light-shielding portion extending along the first direction and arranged sequentially along the second direction; as shown in FIG12A, the second mask has a second light-shielding portion B1 extending along the first direction X and arranged sequentially along the second direction Y.

[0232] The second photoresist layer is exposed by a third mask, wherein the third mask has a third light-shielding portion extending along the second direction and arranged sequentially along the first direction; as shown in FIG12B, the third mask has a third light-shielding portion B2 extending along the second direction Y and arranged sequentially along the first direction X.

[0233] In the development process, the second photoresist layer at the overlapping area of ​​the second and third masking parts is removed, while the second photoresist layer in the remaining areas is retained, forming a photoresist masking pattern with multiple photoresist cutouts. The orthogonal projection of the photoresist cutouts (i.e., the area shown in B3 in Figure 12A) onto the substrate coincides with the orthogonal projection of the area overlapping the second and third light-shielding parts onto the substrate.

[0234] Under the cover of the photoresist masking pattern, the first insulating film is etched to form a first insulating layer with multiple first vias.

[0235] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0236] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; The first active layer, located on one side of the substrate, includes: a plurality of first active patterns; A first insulating layer, located on the side of the first active layer opposite to the substrate, has a plurality of first vias; A first metal layer, located on the side of the first insulating layer opposite to the first active layer, includes: a plurality of first metal lines; the first metal lines are electrically connected to the first active pattern through the first via; Wherein, the maximum size of the first via projected onto the substrate along the first direction is not equal to the maximum size along the second direction, and the first direction intersects the second direction.

2. The array substrate as claimed in claim 1, wherein, The maximum dimension of the first via projected onto the substrate along the first direction is greater than the maximum dimension along the second direction.

3. The array substrate as described in claim 2, wherein, The plurality of first metal wires are arranged sequentially along the first direction; The array substrate includes: a plurality of first active pattern groups extending along the first direction and arranged along the second direction; the first active pattern group includes: a plurality of first active patterns arranged sequentially along the first direction. Multiple first active patterns in the same first active pattern group are electrically connected to multiple first metal lines through the same first via.

4. The array substrate as claimed in claim 3, wherein, The length of the first via in the first direction is greater than or equal to the length of the first active pattern group in the first direction.

5. The array substrate as described in claim 3 or 4, wherein, The maximum dimension of the first via in the second direction is greater than the maximum dimension of the first metal wire in the first direction.

6. The array substrate according to any one of claims 3-5, wherein, The array substrate further includes: a second insulating layer located on the side of the first metal layer facing away from the substrate, and a third insulating layer located between the first active layer and the substrate; the first metal line includes: a first surface facing away from the substrate, and two side surfaces connected to the first surface; the first active pattern has a second surface facing away from the substrate; the third insulating layer has a third surface facing away from the substrate. In the region where the first via is located and along the first direction, the first via exposes a portion of the second surface and the third surface between adjacent first active patterns. The first metal wire covers a portion of the second surface through the first via. The second insulating layer covers the first surface and the side of the first metal wire, and covers the second surfaces on both sides of the first metal wire through the first via, as well as the third surface between adjacent first active patterns.

7. The array substrate according to any one of claims 3-6, wherein, The first metal line extends along the second direction at the outer boundary of the first via.

8. The array substrate as claimed in claim 2, wherein, The first insulating layer includes a plurality of first vias arranged along the first direction; in the first direction, the spacing between two adjacent first vias is less than the spacing between two adjacent first metal lines.

9. The array substrate according to any one of claims 2-8, wherein, The first via has a rectangular shape when projected onto the substrate.

10. The array substrate according to any one of claims 2-8, wherein, The first via includes: a main via portion and a protruding via portion; the main via portion extends along the first direction, and the protruding via portion is connected at the position where the main via portion intersects with the first metal wire, and extends along the second direction.

11. The array substrate as claimed in claim 10, wherein, The first via includes two via protrusions, which are located on different sides of the main via along the second direction.

12. The array substrate as claimed in claim 10 or 11, wherein, The via's main portion has a rectangular orthographic projection onto the substrate, while the via's protruding portion has an arc-shaped orthographic projection onto the substrate.

13. The array substrate as claimed in claim 1, wherein, The maximum dimension of the first via projected onto the substrate along the first direction is smaller than the maximum dimension along the second direction.

14. The array substrate as claimed in claim 13, wherein, The outer boundary of the first via is at least partially curved when projected onto the substrate.

15. The array substrate as claimed in claim 14, wherein, The first via includes: two first ends and two second ends; the distance between the two first ends is the maximum distance of the first via along the second direction, and the distance between the two second ends is the maximum distance of the first via along the first direction; Along the outer boundary of the first via from the first end to the second end, the curvature of the outer boundary of the first via gradually decreases.

16. The array substrate according to any one of claims 13-15, wherein, The ratio of the maximum size of the first via projected onto the substrate along the first direction to the maximum size along the second direction is in the range of 0.5 to 0.

9.

17. The array substrate according to any one of claims 13-16, wherein, The first via has an elliptical shape when projected onto the substrate.

18. An array substrate, wherein, include: Substrate; The first active layer, located on one side of the substrate, includes: a plurality of first active patterns; A first insulating layer, located on the side of the first active layer opposite to the substrate, has a plurality of first vias; A first metal layer, located on the side of the first insulating layer opposite to the first active layer, includes: a plurality of first metal lines; the first metal lines are electrically connected to the first active pattern through the first via; Wherein, the maximum size of the first via projected onto the substrate along the first direction is equal to the maximum size along the second direction, the first direction intersects the second direction, and at least a portion of the outer boundary of the first via projected onto the substrate is straight.

19. The array substrate as claimed in claim 18, wherein, The first via has a square shape when projected onto the substrate.

20. The array substrate according to any one of claims 13-19, wherein, The longest dimension of the first via in the first direction is greater than the maximum dimension of the first metal wire in the first direction.

21. The array substrate according to any one of claims 1-20, wherein, The first via includes: a first sub-via portion; the orthographic projection of the first sub-via portion on the substrate overlaps with the orthographic projection of the first metal line on the substrate; The array substrate further includes: a plurality of first shielding portions, wherein the orthographic projection of the first shielding portions on the substrate at least covers the orthographic projection of the first sub-via portion on the substrate.

22. The array substrate as claimed in claim 21, wherein, The width of the first shielding portion in the first direction is greater than the width of the first metal line in the first direction; the width of the first shielding portion in the second direction is greater than the maximum width of the first via in the second direction.

23. The array substrate as claimed in claim 21 or 22, wherein, The array substrate includes: a second metal layer located on the side of the first metal layer facing the substrate, and a third metal layer located on the side of the second metal layer facing the substrate; The second metal layer includes a plurality of second metal lines extending along a first direction; the third metal layer includes a plurality of third metal lines extending along the first direction; The first shielding portion is located in at least one of the second metal layer and the third metal layer.

24. The array substrate as claimed in claim 23, wherein, The array substrate further includes: a second insulating layer located on the side of the first metal layer opposite to the substrate, a first conductive layer located on the side of the second insulating layer opposite to the first metal layer, and a second via penetrating the second insulating layer and the first insulating layer; The first conductive layer includes: a plurality of transition electrodes; the transition electrodes are electrically connected to the first active pattern through the second via; The array substrate further includes: a plurality of second shielding portions; the orthographic projection of the second shielding portions on the substrate covers the orthographic projection of the second via on the substrate.

25. The array substrate as claimed in claim 24, wherein, The second shielding part and the first shielding part are made of the same layer and material.

26. The array substrate as claimed in claim 24 or 25, wherein, The array substrate further includes: a fourth insulating layer located on the side of the first conductive layer opposite to the first metal layer, a second conductive layer located on the side of the fourth insulating layer opposite to the first conductive layer, and a third via. The second conductive layer includes: a plurality of sub-pixel electrodes; the third via penetrates the fourth insulating layer and a portion of the second insulating layer, and exposes a portion of the transition electrode; the sub-pixel electrodes are electrically connected to the transition electrode through the third via.

27. The array substrate according to any one of claims 24-26, wherein, The first conductive layer further includes: a plurality of first blocking portions; the first blocking portions are spaced apart from the transition electrode; The orthographic projection of the first blocking portion on the substrate at least covers the orthographic projection of the first sub-via portion on the substrate.

28. The array substrate according to any one of claims 25-27, wherein, The first active pattern includes: a first active portion, a second active portion, and a third active portion; The first active portion extends along the second direction, and its orthographic projection on the substrate overlaps with the orthographic projection of the first metal line on the substrate, and is electrically connected through the first via at the overlapping position. The second active portion extends along the second direction, and in the orthographic projection of the substrate, it is located between the orthographic projections of the two adjacent first metal lines on the substrate, and overlaps with the orthographic projection of the transfer electrode on the substrate, and is electrically connected through the second via at the overlapping position. The third active part extends along a third direction and connects the first active part and the second active part. The third direction intersects the first direction and the second direction.

29. The array substrate as claimed in claim 28, wherein, The array substrate further includes: a second active layer located on the side of the first active layer facing the substrate, and a driving source, a driving drain, and a driving gate; The material of the first active layer includes: metal oxide; the material of the second active layer includes: low-temperature polycrystalline silicon.

30. A display panel, wherein, The array substrate includes the array substrate as described in any one of claims 1-29, and further includes a counter substrate disposed opposite to the array substrate.

31. A near-eye display device, wherein, Includes the display panel as described in claim 30.

32. A method for manufacturing an array substrate as described in any one of claims 1-29, wherein, The manufacturing method includes: A first active layer having multiple first active patterns is formed on one side of the substrate; A first insulating layer having a plurality of first vias is formed on the side of the first active layer away from the substrate, wherein the maximum size of the first vias projected onto the substrate along a first direction is not equal to the maximum size along a second direction, and the first direction intersects the second direction; A first metal layer having multiple first metal lines is formed on the side of the first insulating layer opposite to the first active layer, wherein the first metal lines are electrically connected to the first active pattern through the first via.

33. The manufacturing method as described in claim 32, wherein, The step of forming a first insulating layer having a plurality of first vias on the side of the first active layer opposite to the substrate includes: A first insulating film is formed on the side of the first active layer opposite to the substrate; A first photoresist layer is formed on the side of the first insulating film opposite to the first active layer, wherein the first photoresist layer is a positive photoresist. The first photoresist layer is exposed through a first mask, wherein the first mask has a first cutout extending along a first direction and arranged sequentially along a second direction, and the orthographic projection of the first cutout on the substrate overlaps with the orthographic projection of the first via on the substrate. A developing and etching process is performed to remove the first photoresist layer in the first hollow area and form a first insulating layer having a plurality of first vias, wherein the plurality of first vias extend along the first direction and are arranged along the second direction.

34. The manufacturing method as described in claim 32 or 33, wherein, The step of forming a first insulating layer having a plurality of first vias on the side of the first active layer opposite to the substrate includes: A first insulating film is formed on the side of the first active layer opposite to the substrate; A second photoresist layer is formed on the side of the first insulating film opposite to the first active layer, wherein the second photoresist layer is a negative photoresist; The second photoresist layer is exposed by a second mask, wherein the second mask has second light-shielding portions extending along a first direction and arranged sequentially along a second direction; The second photoresist layer is exposed by a third mask, wherein the third mask has a third light-shielding portion extending along the second direction and arranged sequentially along the first direction; In the development process, the second photoresist layer at the overlapping area of ​​the second and third masking portions is removed, while the second photoresist layer in the remaining areas is retained, forming a photoresist masking pattern with multiple photoresist cutouts. The orthographic projection of the photoresist cutouts on the substrate coincides with the orthographic projection of the overlapping area of ​​the second and third masking portions on the substrate. Under the cover of the photoresist masking pattern, the first insulating film is etched to form the first insulating layer having a plurality of first vias.

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