Computing storage system and method of operation thereof, electronic system

Abstract

The embodiments of the present disclosure provide a computing storage system and an operating method thereof and an electronic system, the computing storage system comprising a controller, a first memory coupled with the controller, and a computing processing component for executing a program; the controller is configured to: receive a command sent by a host coupled with the computing storage system, the command being used to instruct the computing processing component to execute a program, and the command being configured to define association information of input data and / or output data in a corresponding address in the first memory during the program execution process; and obtain, according to the association information, the input data and / or the output data in the corresponding address in the first memory during the program execution process from the host.

Description

Computing storage systems and their operating methods, electronic systems Technical Field

[0001] This disclosure relates to, but is not limited to, a computing storage system and its operating method, and an electronic system. Background Technology

[0002] Semiconductor memories can be roughly divided into two categories, depending on whether they retain stored data when power is off: volatile memory and non-volatile memory. Volatile memory loses stored data when power is off, while non-volatile memory retains stored data when power is off. Summary of the Invention

[0003] According to a first aspect of the present disclosure, an electronic system is provided, the electronic system including a host and a computing storage system coupled to the host; the computing storage system including a controller, a first memory coupled to the controller, and a computing processing component for executing a program; the host is configured to: send a command, the command being used to instruct the computing processing component to execute the program, and the command being configured to define association information of corresponding addresses of input data and / or output data in the first memory during the execution of the program; the controller is configured to: receive the command, and obtain from the host the corresponding addresses of input data and / or output data in the first memory during the execution of the program according to the association information.

[0004] In some implementations, the command carries first pointer information, as well as a first parameter and / or a second parameter; the first parameter contains the number of input data during the program execution process, and the second parameter contains the number of output data during the program execution process; the first pointer information points to a first region in the cache of the host, the first region storing the corresponding address of each input data in the first memory and the corresponding address of each output data in the first memory.

[0005] In some implementations, the controller is configured to: obtain from the host's cache the corresponding address of each input data in the first memory and / or the corresponding address of each output data in the first memory during the program execution process, based on the first pointer information and the first parameter and / or the second parameter.

[0006] In some embodiments, the host is configured to: sequentially store the corresponding addresses of each input data and each output data in the first memory in the first memory in the first area according to a first preset order; the controller is configured to: obtain from the host the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory during program execution, based on the capacity of the buffer occupied by each corresponding address of each input data and each output data in the first memory, the information of the first preset order, the number of input data, and the number of output data.

[0007] In some embodiments, the host is configured to: store each input data and each output data in the first memory in a first area of ​​the host's buffer in the order that the corresponding addresses of the input data in the first memory are stored first, and the corresponding addresses of the output data in the first memory are stored later; or, store each input data and each output data in the first memory in a first area of ​​the host's buffer in the order that the corresponding addresses of the output data in the first memory are stored first, and the corresponding addresses of the input data in the first memory are stored later.

[0008] In some implementations, the command carries second pointer information; the second pointer information points to a second region in the cache of the host; the second region stores the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory.

[0009] In some embodiments, the host is configured to: sequentially store the number of input data during program execution, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory in the second area according to a second preset order; the controller is configured to: obtain from the host the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory during program execution.

[0010] In some implementations, the host is configured to: determine the number of input data and / or the number of output data during the execution of the program, based on the functional characteristics of the program.

[0011] In some implementations, the command carries third pointer information and / or fourth pointer information; the third pointer information points to a third region in a buffer in the host, the third region storing the corresponding address of each input data during program execution in the first memory; the fourth pointer information points to a fourth region in the buffer, the fourth region storing the corresponding address of each output data during program execution in the first memory; the controller is configured to: obtain the corresponding address of the input data during program execution in the first memory from the host based on the address stored in the third region; and / or, obtain the corresponding address of the output data during program execution in the first memory from the host based on the address stored in the fourth region.

[0012] In some implementations, the corresponding address of each input data in the first memory occupies the same size of the buffer and is a first value, and the corresponding address of each output data in the first memory occupies the same size of the buffer and is a second value, wherein the first value and the second value are equal.

[0013] In some implementations, the corresponding address of each input data / output data in the first memory includes information about the first memory to which the region storing the corresponding input data / output data belongs, the size of the input data / output data, and the starting address of the input data / output data in the first memory.

[0014] In some embodiments, the computing processing component is configured to: read input data from a corresponding area of ​​the first memory according to the corresponding address of the input data in the first memory during program execution, and execute the program; and store the output data obtained after the program processes the input data into a corresponding area of ​​the first memory according to the corresponding address of the output data in the first memory during program execution.

[0015] In some implementations, the command further carries a first identifier: the controller is configured to: based on the value of the first identifier as a third value, and according to the association information of the corresponding addresses of the input data and output data in the first memory during the program execution process as defined by the program unique identifier carried by the command, obtain the corresponding addresses of the input data and output data in the first memory during the program execution process from the host; or, based on the value of the first identifier as a fourth value, and according to the association information of the corresponding addresses of the input data and output data in the first memory during the program execution process as defined by the command, obtain the corresponding addresses of the input data and output data in the first memory during the program execution process from the host.

[0016] In some embodiments, the computing storage system further includes a second memory coupled to the controller, the controller being configured to: write input data during program execution stored in the second memory into the first memory; and write output data during program execution stored in the first memory into the second memory.

[0017] In some embodiments, the computing storage system includes a non-volatile namespace, a computing namespace, and a subsystem local storage namespace; the non-volatile namespace includes the second memory, the computing namespace includes the computing processing component, and the subsystem local storage namespace includes the first memory.

[0018] According to a second aspect of the present disclosure, a computing storage system is provided, the computing storage system including a controller, a first memory coupled to the controller, and a computing processing component for executing a program; the controller is configured to: receive a command sent by a host coupled to the computing storage system, the command being used to instruct the computing processing component to execute the program, and the command being configured to define association information of corresponding addresses of input data and / or output data in the first memory during the execution of the program; and obtain, from the host, the corresponding addresses of input data and / or output data in the first memory during the execution of the program based on the association information.

[0019] In some implementations, the command carries first pointer information, as well as a first parameter and / or a second parameter; the first parameter contains the number of input data during program execution, and the second parameter contains the number of output data during program execution; the first pointer information points to a first region in the cache of the host, the first region storing the corresponding address of each input data in the first memory and the corresponding address of each output data in the first memory, and the corresponding addresses of each input data in the first memory and the corresponding addresses of each output data in the first memory during program execution are stored sequentially in the first region according to a first preset order.

[0020] In some implementations, the controller is configured to: obtain from the host's cache the corresponding address of each input data in the first memory and / or the corresponding address of each output data in the first memory during the program execution process, based on the first pointer information and the first parameter and / or the second parameter.

[0021] In some implementations, the controller is configured to: obtain from the host the corresponding addresses of input data and / or output data in the first memory during program execution, based on the capacity of the buffer occupied by each input data and each output data at its respective address in the first memory, information about the first preset order, the number of input data, and the number of output data.

[0022] In some implementations, the first preset order includes: the corresponding address of the input data in the first memory is stored first, and the corresponding address of the output data in the first memory is stored later; or, the corresponding address of the output data in the first memory is stored first, and the corresponding address of the input data in the first memory is stored later.

[0023] In some implementations, the command carries second pointer information; the second pointer information points to a second region in the cache of the host; the second region stores the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory, and the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory during the program execution process are stored in the second region in a second preset order.

[0024] In some implementations, the controller is configured to: obtain from the host the corresponding addresses of input data and / or output data in the first memory during program execution, based on the number of input data, the corresponding address of each input data in the first memory, the number of output data, the capacity of the buffer occupied by the corresponding address of each output data in the first memory, information of the second preset order, the number of input data, and the number of output data.

[0025] In some implementations, the host is configured to: determine the number of input data and / or the number of output data during the execution of the program, based on the functional characteristics of the program.

[0026] In some implementations, the command carries third pointer information and / or fourth pointer information; the third pointer information points to a third region in a buffer in the host, the third region storing the corresponding address of each input data during program execution in the first memory; the fourth pointer information points to a fourth region in the buffer, the fourth region storing the corresponding address of each output data during program execution in the first memory; the controller is configured to: obtain the corresponding address of the input data during program execution in the first memory from the host based on the address stored in the third region; and / or, obtain the corresponding address of the output data during program execution in the first memory from the host based on the address stored in the fourth region.

[0027] In some implementations, the corresponding address of each input data in the first memory occupies the same size of the buffer and is a first value, and the corresponding address of each output data in the first memory occupies the same size of the buffer and is a second value, wherein the first value and the second value are equal.

[0028] In some implementations, the corresponding address of each input data / output data in the first memory includes information about the first memory to which the region storing the corresponding input data / output data belongs, the size of the input data / output data, and the starting address of the input data / output data in the first memory.

[0029] According to a third aspect of the present disclosure, a method for operating a computing storage system is provided, the method comprising: receiving a command sent by a host coupled to the computing storage system, the command being used to instruct a computing processing component to execute a program, and the command being configured to define association information of corresponding addresses of input data and / or output data during the execution of the program in a first memory coupled to a controller of the computing storage system; and obtaining, based on the association information, the corresponding addresses of the input data and / or output data during the execution of the program in the first memory from the host.

[0030] In some implementations, the command carries first pointer information, as well as a first parameter and / or a second parameter; the first parameter contains the number of input data during program execution, and the second parameter contains the number of output data during program execution; the first pointer information points to a first region in the cache of the host, the first region storing the corresponding address of each input data in the first memory and the corresponding address of each output data in the first memory, and the corresponding addresses of each input data in the first memory and the corresponding addresses of each output data in the first memory during program execution are stored sequentially in the first region according to a first preset order.

[0031] In some implementations, obtaining the corresponding addresses of input data and / or output data in the first memory during program execution from the host based on the associated information includes: obtaining the corresponding address of each input data and / or each output data in the first memory during program execution from the host's buffer based on the first pointer information, and the first parameter and / or the second parameter.

[0032] In some implementations, obtaining the corresponding addresses of input data and / or output data in the first memory during program execution from the host based on the associated information includes: obtaining the corresponding addresses of input data and / or output data in the first memory from the host based on the capacity of the buffer occupied by each input data and each output data in the first memory, the information of the first preset order, the number of input data and the number of output data.

[0033] In some implementations, the first preset order includes: the corresponding address of the input data in the first memory is stored first, and the corresponding address of the output data in the first memory is stored later; or, the corresponding address of the output data in the first memory is stored first, and the corresponding address of the input data in the first memory is stored later.

[0034] In some implementations, the command carries second pointer information; the second pointer information points to a second region in the cache of the host; the second region stores the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory, and the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory during the program execution process are stored in the second region in a second preset order.

[0035] In some implementations, obtaining the corresponding addresses of input data and / or output data in the first memory during program execution from the host based on the associated information includes: obtaining the corresponding addresses of input data and / or output data in the first memory during program execution from the host based on the number of input data, the corresponding address of each input data in the first memory, the number of output data, the capacity of the buffer occupied by the corresponding address of each output data in the first memory, the information of the second preset order, the number of input data, and the number of output data.

[0036] In some embodiments, the operation method further includes: determining the number of input data and / or the number of output data during the execution of the program based on the functional characteristics of the program.

[0037] In some implementations, the command carries third pointer information and / or fourth pointer information; the third pointer information points to a third region in a buffer in the host, the third region storing the corresponding address of each input data during program execution in the first memory; the fourth pointer information points to a fourth region in the buffer, the fourth region storing the corresponding address of each output data during program execution in the first memory; obtaining the corresponding address of the input data and / or output data during program execution in the first memory from the host based on the associated information includes: obtaining the corresponding address of the input data during program execution in the first memory from the host based on the address stored in the third region; and / or, obtaining the corresponding address of the output data during program execution in the first memory from the host based on the address stored in the fourth region.

[0038] In some implementations, the corresponding address of each input data in the first memory occupies the same size of the buffer and is a first value, and the corresponding address of each output data in the first memory occupies the same size of the buffer and is a second value, wherein the first value and the second value are equal.

[0039] In some implementations, the corresponding address of each input data / output data in the first memory includes information about the first memory to which the region storing the corresponding input data / output data belongs, the size of the input data / output data, and the starting address of the input data / output data in the first memory. Attached Figure Description

[0040] Figure 1 is a schematic diagram of the structure of an electronic system provided in an embodiment of this disclosure;

[0041] Figure 2 is a schematic diagram of the structure of a computing storage system provided in an embodiment of this disclosure;

[0042] Figure 3 is a schematic diagram of an example of loading a program in an electronic system according to an embodiment of the present disclosure;

[0043] Figure 4 is a schematic diagram illustrating an example of program execution in an electronic system according to an embodiment of this disclosure;

[0044] Figure 5 is a schematic diagram of a memory range and a set of memory ranges provided in an embodiment of this disclosure;

[0045] Figure 6 is a schematic diagram of the structure of a computing storage system provided in an embodiment of this disclosure;

[0046] Figure 7 is a flowchart illustrating a program execution process provided in an embodiment of this disclosure;

[0047] Figure 8 is a schematic diagram of the structure of a computing storage system provided in an embodiment of this disclosure;

[0048] Figure 9 is a schematic diagram of the structure of an electronic system provided in an embodiment of this disclosure;

[0049] Figure 10 is a flowchart illustrating an operation method of a computing storage system provided in an embodiment of this disclosure. Detailed Implementation

[0050] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0052] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0053] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0055] Figure 1 is a schematic diagram of an electronic system provided in an embodiment of this disclosure. Figure 2 is a schematic diagram of a computing and storage system provided in an embodiment of this disclosure.

[0056] Referring to FIG1, the electronic system 100 may include a host 110 and at least one computing storage system 120. The host 110 may include a host processor 111 and a host memory 112. The host processor 111 controls the overall operation of the host 110. The host processor 111 may be implemented as at least one of various processing units, including, for example, a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a neural processing unit (NPU), a field-programmable gate array (FPGA), and / or a microprocessor. In some embodiments, the host processor 111 may be implemented as a system-on-chip (SoC). The host memory 112 may store data, instructions, and programs required for the operation of the host processor 111. The host memory 112 may be volatile memory. Volatile memory includes, but is not limited to, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and double data rate synchronous dynamic random access memory (DDR SDRAM).

[0057] The computing storage system 120 may be a semiconductor device that provides computing services and data storage services. The computing storage system 120 may be used as both a data storage device and a computing device for executing programs in the electronic system 100. In some embodiments, for example, the computing storage system 120 may be implemented as part of a data center or an artificial intelligence training data device.

[0058] In some embodiments, host 110 and compute storage system 120 are physically connected via an interface and communicate in accordance with the corresponding PCIe / NVMe protocol. Exemplarily, host 110 and compute storage system 120 can be connected via a network link, such as based on the NVMe-OF protocol. Exemplarily, host 110 and compute storage system 120 can also be connected via a Compute Express Link (CXL) interface, through which host 110 can control the operation of compute storage system 120. Compute storage system 120 is configured to conform to the NVMe compute storage protocol. The CXL interface may include CXL.io, CXL.cache, and CXL.mem as sub-protocols. Host 110 can load predetermined programs into compute storage system 120 for processing. Host 110 can load various types of programs (such as applications, kernels, and / or compute) into compute storage system 120. Programs may include, for example, encryption programs, compression programs, image recognition programs, filtering programs, and / or artificial intelligence programs.

[0059] Referring to FIG2, in some embodiments, the compute storage system 200 may include a controller 210, one or more sub-system local memory namespaces (SLM NS) 230, one or more non-volatile memory namespaces (NVM NS) 240, and one or more compute namespaces (CNS) 220. The compute storage system 200 may correspond to one of the plurality of compute storage systems 120 shown in FIG1. ​​The sub-system local memory namespace 230 may be a namespace implemented in volatile memory, which is closer to the compute processing components of the compute namespace 220 than the namespace implemented in non-volatile memory. The non-volatile namespace 240 may be a namespace implemented in non-volatile memory.

[0060] In some embodiments, the computing storage system 200 may use Non-Volatile Memory Fast Protocol (NVMe Protocol) as the storage protocol, and the controller 210 may be an NVMe controller. The controller 210 may, in response to input / output (I / O) requests from the host, store input / output data during program execution in the subsystem local storage namespace 230, and / or read input / output data stored in the subsystem local storage namespace 230.

[0061] In some embodiments, the controller 210 may perform various operations for controlling the non-volatile namespace 240 or other non-volatile storage devices. For example, these operations may include address mapping operations, wear leveling operations, and / or garbage collection operations. Address mapping operations may be translation operations between logical addresses managed by the host or controller and physical addresses of the non-volatile namespace 240. Wear leveling may be an operation that evens out the frequency or number of uses of multiple storage blocks included in the non-volatile namespace 240. Garbage collection operations may be an operation that copies valid data from a source block in the non-volatile namespace 240 to a target block and then erases the source block to ensure available or free blocks in the non-volatile namespace 240.

[0062] In some embodiments, compute namespace 220 can serve as an abstraction representing one or more compute engines for executing programs. Compute engine resources can consist of one or more CPUs, FPGAs, GPUs, ASICs, etc. For example, a compute namespace can include CPU cores and FPGAs. Compute engine resources can be part of controller 210 or separate from controller 210. The compute engine can execute programs pre-loaded from the host. In some embodiments, programs can be stored in program slots. Program slots can be formed within the compute engine or allocated in separate memory. In some embodiments, program slots storing programs can be within compute namespace 220, or compute namespace 220 can be formed as an entity capable of executing programs. Compute namespace 220 can be, for example, an entity in an NVMe subsystem. Compute namespace 220 can access subsystem local storage namespace 230. In some embodiments, compute storage system 200 can include one or more compute namespaces 220. If the computing storage system 200 includes multiple computing namespaces 220, the host can load multiple programs into the multiple computing namespaces 220 respectively (e.g., in a one-to-one relationship). Therefore, each loaded program can be managed in its respective computing namespace 220, and this disclosure is not limited thereto.

[0063] In some embodiments, the controller 210 may copy data stored in the non-volatile namespace 240 to the subsystem local storage namespace 230, and / or copy data stored in the subsystem local storage namespace 230 to the non-volatile namespace 240. That is, the controller 210 may control the data migration between the non-volatile namespace 240 and the local storage namespace 230 as needed for the program processing of the computation namespace 220.

[0064] The subsystem local storage namespace 230 may store input data used by the program to be executed, or it may store the results (output data) obtained by executing the program. In some embodiments, the subsystem local storage namespace 230 may also be accessed by the controller 210. The subsystem local storage namespace 230 may be implemented as, for example, DRAM.

[0065] In some embodiments, controller 210 may further include a first control portion (not shown) of the control subsystem local storage namespace 230, such as a cache controller. In some embodiments, the first control portion may be configured as a separate chip from controller 210. In some other embodiments, the first control portion may be configured as an internal component of controller 210.

[0066] The non-volatile namespace 240 may store input / output data during program execution. The non-volatile namespace 240 may include, for example, flash memory (such as NAND flash memory). In another example, the non-volatile namespace 240 may include, for example, phase-change memory, resistive memory, magnetoresistive memory, ferroelectric memory, or polymer memory. In some embodiments, the computing storage system 200 may also include a second control portion, such as a flash memory controller, that controls or is configured to control the non-volatile namespace 240, and this second control portion may be included in controller 210.

[0067] In this embodiment of the disclosure, the computing processing components in the computing storage system, including computing engine resources, are abstracted into one or more computing namespaces for user use. The RAM within the computing processing components of the computing storage system, as well as the common RAM within the computing storage system and the RAM within the controller, can all be abstracted into subsystem local namespaces for user use. For the user, these computing namespaces and subsystem local storage namespaces are parallel entities. In some implementations, the user can be informed, based on the specific internal physical implementation, that a particular subsystem local storage namespace is used by a particular computing namespace (due to physical dependencies).

[0068] Figure 3 is a schematic diagram of an example of loading a program in an electronic system according to an embodiment of the present disclosure.

[0069] Referring to Figure 3, host 310 can load programs into compute storage system 320. In Figure 3, compute storage system 320 is shown as including compute namespace 322 and compute namespace 323 (e.g., compute namespaces 0 and 1), but the number of compute namespaces is not limited to this.

[0070] In some embodiments, compute namespaces 322 and 323 may support device-defined programs and / or downloadable programs. Device-defined programs may be, for example, fixed programs provided by a manufacturer, while downloadable programs may be programs loaded into compute namespaces 322 and 323 by the host 310. For example, device-defined program 323a may be set in compute namespace 323.

[0071] In some embodiments, the controller 321 of the computing storage system 320 may receive programs 322a and 323b transmitted from the host 310 and store them in the computing storage system 320. The computing engine of the computing namespace may, in response to a program execution command from the host 310, use input data stored in the subsystem local storage namespace 324 to execute programs 322a, 323a, and / or 323b in computing namespaces 322 and 323. The input data may include corresponding input parameters required for program execution.

[0072] Figure 4 is a schematic diagram of an example of program execution in an electronic system according to an embodiment of the present disclosure. In Figure 4, it is assumed that program 422a is loaded into the computing namespace 422 of computing storage system 420.

[0073] Referring to Figure 4, in operation S431, the host 410 may send a data copy command to the controller 421 of the computing storage system 420. In operation S432, in response to the data copy command, input data stored in the non-volatile namespace 424 (e.g., a non-volatile memory device) may be copied to the subsystem local storage namespace 423. In some embodiments, the controller 421 may control the non-volatile namespace 424 and the subsystem local storage namespace 423 in response to the data copy command to transfer input data from the non-volatile namespace 424 to the subsystem local storage namespace 423.

[0074] It should be noted that Figure 4 is only an example and is not intended to limit the transmission path of input and output data in the embodiments of this disclosure. In some embodiments, the host 410 can directly write input data into the subsystem local storage namespace 423, and the output data obtained after the program processes the input data is stored in the subsystem local storage namespace 423. The host 410 can directly obtain the output data from the subsystem local storage namespace 423. That is, the non-volatile namespace 424 may not participate in the storage of input data and output data. In other embodiments, the non-volatile namespace 424 can also participate in the storage of input data and output data. The host 410 can write input data into the non-volatile namespace 424, the non-volatile namespace 424 copies the input data to the subsystem local storage namespace 423, the output data obtained after the program processes the input data is stored in the subsystem local storage namespace 423, the output data in the subsystem local storage namespace 423 is copied to the non-volatile namespace 424, and the host can obtain the output data from the non-volatile namespace 424. In some other embodiments, the non-volatile namespace 424 may only be used for either storing input data or storing output data. For example, the host 410 may directly write input data into the subsystem local storage namespace 423, and the output data obtained after the program processes the input data is stored in the subsystem local storage namespace 423. The output data in the subsystem local storage namespace 423 is copied to the non-volatile namespace 424, and the host 410 can obtain the output data from the non-volatile namespace 424. Alternatively, the host 410 may write input data into the non-volatile namespace 424, and the input data in the non-volatile namespace 424 is copied to the subsystem local storage namespace 423. The output data obtained after the program processes the input data is stored in the subsystem local storage namespace 423, and the host 410 can directly obtain the output data from the subsystem local storage namespace 423.

[0075] After the data has been copied from the NVM namespace 424 to the subsystem local storage namespace 423, in operation S433, the controller 421 may send a read success message to the host 410.

[0076] In order to execute the program, in operation S441, host 410 may send a program execution command to computing storage system 420 to execute program 422a in computing namespace 422. In some embodiments, controller 421 may receive the program execution command from host 410. In operation S442, in response to the program execution command, the computing engine in computing namespace 422 may use input data stored in subsystem local storage namespace 423 to execute program 422a in computing namespace 422. In operation S443, computing namespace may store the execution result (output data) of program 422a in subsystem local storage namespace 423. After the execution of program 422a in computing namespace 422 is completed, in operation S444, controller 421 may send a message indicating successful program execution to host 410.

[0077] In some embodiments, during operation S451, host 410 may send a read command instructing the computing storage system 420 to read output data from subsystem local storage namespace 423. During operation S452, controller 421 may read output data (e.g., the execution result of program 422a) from subsystem local storage namespace 423 and transmit the data to host 410.

[0078] In some embodiments, after the program 422a has finished executing, the output data can be flushed from the subsystem local storage namespace 423 to the non-volatile namespace 424.

[0079] The electronic system can execute programs on the computing storage system 420 by performing the above operations. Furthermore, if requested by the host 410, the electronic system can provide the execution results of the program from the computing storage system 420 to the host 410.

[0080] In some embodiments, the controller 421, in response to a host command, configures a corresponding storage region in the memory of the sub-system local memory namespace 423 to store input / output data during program execution. In some embodiments, the controller can configure the corresponding storage region by creating memory ranges. A memory range (MR) defines a corresponding storage region. A memory range can be represented by the sub-system local memory namespace identity (SLM NS ID), the starting address (Starting Byte) of the storage region within that local memory namespace, and the data length. Each memory range specifies the accessible range within the sub-system local memory namespace. The collection of memory ranges constitutes a memory range set (MRS). The memory range set can be stored in the compute namespace, and each execution of the program is limited to accessing ranges other than those specified in the memory range set in the program name. As shown in Figure 5, memory range 1 and memory range 2 in computing namespace 501 form memory range set 1, and memory range 1, memory range 2, and memory range 3 in computing namespace 502 form memory range set 2. Each memory range includes the Sub-system Local Memory Namespaces Identity (SLM NS ID), the starting address (Starting Byte) of the storage region in the local storage namespace, and information related to the data length. The information included in the memory range allows us to determine a region within the corresponding sub-system local storage namespace. It should be noted that Figure 5 illustrates an example of storing a storage range set within a computing namespace, but this embodiment is not limited to this; the storage range set can also be stored in other storage-functional memories within the computing storage system.

[0081] The complexity of executing program commands lies in the diversity of computational program functions. Each function of a computational program has a different number of input / output data points, and the command format for executing the program will inevitably differ. Therefore, the NVMe Association currently needs to define a Program Unique Identifier Registry. Different functions of programs correspond to different Program Unique Identifiers (PUIDs). The Program Unique Identifier is configured to define the association information of the corresponding addresses of input data and output data in the local storage namespace during program execution. Obtaining the corresponding addresses of input and output data in the local storage namespace through PUIDs allows the host and the compute storage system to reach a consensus on program execution, but it lacks flexibility. The corresponding addresses of input and output data in the local storage namespace during program execution must be determined according to the PUID definition. This process requires prior discussion and application for a PUID by the NVMe Association or vendors, and its addition to the PUID registry. For a newly developed program, the cycle for it to be executed by the compute storage system is relatively long.

[0082] This disclosure provides a computing storage system, as shown in FIG6. The computing storage system 600 includes a controller 601, a first memory 602 coupled to the controller 601, and a computing processing component 603 for executing a program. The controller 601 is configured to: receive a command sent by a host coupled to the computing storage system 600, the command being used to instruct the computing processing component 603 to execute a program, and the command being configured to define association information of the corresponding addresses of input data and / or output data in the first memory 602 during the program execution process; and obtain the corresponding addresses of the input data and / or output data in the first memory 602 during the program execution process from the host according to the association information.

[0083] In some specific examples, as shown in FIG6, the first memory 602 includes a first storage area 606 configured for input data during the execution of a program by the computing processing component 603, and a second storage area 607 configured for output data during the execution of a program by the computing processing component 603.

[0084] In this embodiment, the addresses of input data in the first storage area 606 and the addresses of output data in the second storage area 607 during program execution are stored in the host. The commands sent by the host directly define the association information of the corresponding addresses of the input data and / or output data in the first memory 602. This association information can be understood as follows: the corresponding address of the input data and / or output data in the first memory 602 corresponds to an address stored in the host's cache. Using the information stored in the cache corresponding to that address, the corresponding address of the input data and / or output data in the first memory 602 can be obtained.

[0085] In some specific examples, the command sent by the host may be a command instructing the computing processing component 603 to execute a program.

[0086] In some specific examples, the first memory 602 is volatile memory, including but not limited to random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and double data rate synchronous dynamic random access memory (DDR SDRAM). The computing processing component 603 has computing functions, including but not limited to a computing engine, whose resources may consist of one or more of a CPU, FPGA, GPU, etc. The computing processing component 603 may be part of the controller 601 or a component independent of the controller 601.

[0087] In this embodiment, the controller 601 receives a command sent by the host to instruct the computing processing component 603 to execute a program. This command is configured to define the association information of the corresponding addresses of the input data and / or output data in the first memory 602 during program execution. The controller 601 parses the association information to obtain the corresponding addresses of the input data and / or output data in the first memory 602 during program execution, and obtains the corresponding addresses of the input data and / or output data in the first memory 602 during program execution from the host, thereby enabling the program to execute normally. In other words, in this embodiment, it is not necessary to rely on a program unique identifier. The association information of the corresponding addresses of the input data and / or output data in the first memory 602 during program execution can be directly defined by the command sent by the host, and then the corresponding addresses of the input data and / or output data in the first memory 602 during program execution can be obtained from the host. Even if the program has not applied for or has applied for but has not yet passed the corresponding program unique identifier, it can still execute normally, making the way the controller 601 obtains the corresponding addresses of the input data and / or output data in the first memory 602 during program execution more flexible.

[0088] In this embodiment of the disclosure, multiple methods are provided for how to specifically implement the command to define the association information of the corresponding addresses of input data and / or output data in the first memory 602 during the execution of the program.

[0089] In some embodiments, the command carries first pointer information, as well as a first parameter and / or a second parameter; the first parameter contains the number of input data during program execution, and the second parameter contains the number of output data during program execution; the first pointer information points to a first region in the cache of the host, the first region storing the corresponding address of each input data in the first memory 602 and the corresponding address of each output data in the first memory 602, and the corresponding addresses of each input data in the first memory 602 and the corresponding addresses of each output data in the first memory 602 during program execution are stored sequentially in the first region according to a first preset order.

[0090] In some specific examples, the cache in the host is volatile memory, including but not limited to random access memory, dynamic random access memory, static random access memory, synchronous dynamic random access memory, and double data rate synchronous dynamic random access memory.

[0091] In the above embodiments, the command carries first pointer information, which points to a first region in the buffer of the host. The corresponding addresses of each input data and each output data in the first memory 602 during program execution are stored in the first region, and these addresses are sequentially stored in the first region according to a first preset order. Furthermore, the first parameter carried in the command sent by the host includes the number of input data during program execution, and the second parameter carried in the command includes the number of output data during program execution.

[0092] As shown in Table 1, the number of input data items during program execution contained in the first parameter can be recorded using a fixed number of p bytes. The first p bytes of the first parameter are used to store the number of input data items during program execution. As shown in Table 2, the number of output data items during program execution contained in the second parameter can be recorded using a fixed number of q bytes. The first q bytes of the second parameter are used to store the number of output data items during program execution. The specific values ​​of p and q can be determined based on the size of the information regarding the number of input data items and the number of output data items, respectively. In some specific examples, p and q are equal, and the total number of bytes configured for the first and second parameters is m bytes. The remaining bytes configured for the first and second parameters can be reserved for subsequent optimization.

[0093] Table 1

[0094] Table 2

[0095] In some embodiments, the controller 601 is configured to: obtain from the host's cache the corresponding address of each input data in the first memory 602 and / or the corresponding address of each output data in the first memory 602 during the program execution process, based on the first pointer information and the first parameter and / or the second parameter.

[0096] In this embodiment of the disclosure, when the corresponding addresses of each input data in the first memory 602 and the corresponding addresses of each output data in the first memory 602 are stored in the first area in a first preset order during program execution, the controller 601 can determine which addresses stored in the first area of ​​the host are the corresponding addresses of the input data in the first storage area and which are the corresponding addresses of the output data in the second storage area based on the first pointer information carried by the command, as well as the first parameter and / or the second parameter.

[0097] In some embodiments, the controller 601 is configured to: obtain from the host the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory 602 during the program execution process, based on the capacity of the buffer occupied by each corresponding address of each input data and each output data in the first memory 602, the information of the first preset order, the number of input data, and the number of output data.

[0098] In some embodiments, the corresponding address of each input data in the first memory 602 occupies the same capacity of the cache and is a first value, and the corresponding address of each output data in the first memory 602 occupies the same capacity of the cache and is a second value, wherein the first value and the second value are equal.

[0099] It is understood that in the solution provided by the embodiments of this disclosure, the capacity of the buffer occupied by each corresponding address of each input data in the first memory 602 is equal, and the capacity of the buffer occupied by each corresponding address of each output data in the first memory 602 is the same, and the first value and the second value are equal. This allows the controller 601 to reduce the parsing difficulty based on the capacity of the buffer occupied by each corresponding address of each input data and each output data in the first memory 602, the information of the first preset order, the number of input data, and the number of output data. This enables the controller 601 to more quickly parse and obtain the corresponding addresses of the input data and / or the output data in the first memory 602 during program execution.

[0100] In some embodiments, the first preset order may be that the corresponding addresses of input data and output data in the first memory 602 are stored alternately in a first region. In the alternating storage method, the first region may begin with the corresponding address of the input data in the first memory 602, or the first region may begin with the corresponding address of the output data in the first memory 602.

[0101] In some embodiments, the first preset order includes: the corresponding address of the input data in the first memory 602 is stored first, and the corresponding address of the output data in the first memory 602 is stored later; or, the corresponding address of the output data in the first memory 602 is stored first, and the corresponding address of the input data in the first memory 602 is stored later.

[0102] It is understood that the first preset order is that, as mentioned in the above embodiment, the corresponding address of the input data in the first memory 602 is stored first, and the corresponding address of the output data in the first memory 602 is stored later; or, the corresponding address of the output data in the first memory 602 is stored first, and the corresponding address of the input data in the first memory 602 is stored later. This can further reduce the parsing difficulty of the controller 601, so that the controller 601 can more quickly parse and obtain the corresponding address of the input data in the first memory 602 and / or the corresponding address of the output data in the first memory 602 during the program execution process.

[0103] In some embodiments, the command may carry only one of the first parameter and the second parameter. When only one of the first parameter and the second parameter is carried in the command, a reasonable first preset order can also obtain the corresponding addresses of the input data and the output data in the first memory. For example, the first preset order may be that the corresponding addresses of the input data in the first memory are stored first, followed by the corresponding addresses of the output data; or, the corresponding addresses of the input data in the first memory are stored later, followed by the corresponding addresses of the output data in the first memory.

[0104] In some embodiments, the corresponding address of each input data / output data in the first memory 602 includes information about the first memory 602 to which the region storing the corresponding input data / output data belongs, the size of the input data / output data, and the starting address of the input data / output data in the first memory 602.

[0105] It is understandable that by storing information about the first memory 602 to which the corresponding input / output data belongs, the size of the input / output data, and the starting address of the input / output data in the first memory 602, the specific location of the input / output data in the first memory 602 can be determined.

[0106] The following example, using the first preset order of storing the corresponding addresses of input data in the first memory 602 first and the corresponding addresses of output data in the first memory 602 last, illustrates how the controller 601 obtains the corresponding addresses of input data and output data in the first memory 602 during program execution.

[0107] As shown in Table 3, each input data is recorded in the first memory 602 using a fixed number of n bytes. These n bytes sequentially record the identifier of the first memory 602 to which the corresponding input data area belongs, the size of the input data, and the starting address of the input data in the first memory 602. Similarly, each output data is recorded in the first memory 602 using a fixed number of n bytes. These n bytes sequentially record the identifier of the first memory 602 to which the corresponding output data area belongs, the size of the output data, and the starting address of the output data in the first memory 602. Taking a program involving two input data points and two output data points as an example, (n-1):00 stores the address of the first input data in the first memory 602. Specifically, a:00 records the identifier of the first memory 602 to which the area storing the first input data belongs, b:(a+1) records the size of the first input data, and (n-1):(b+1) records the starting address of the first input data in the first memory 602. (2n-1): n stores the corresponding address of the second input data in the first memory 602. Specifically, c: n records the identifier of the first memory 602 to which the area storing the second input data belongs, d: (c+1) records the size of the second input data, and (2n-1): (d+1) records the starting address of the second input data in the first memory 602. (3n-1): (2n) stores the corresponding address of the first output data in the first memory 602. Specifically, e: 2n records the identifier of the first memory 602 to which the area storing the first output data belongs, f: (e+1) records the size of the first output data, and (3n-1): (f+1) records the starting address of the first output data in the first memory 602. (4n-1): (3n) stores the corresponding address of the second output data in the first memory 602. Specifically, g: 3n records the identifier of the first memory 602 to which the area storing the second output data belongs, h: (g+1) records the size of the second output data, and (4n-1): (h+1) records the starting address of the second output data in the first memory 602. The input data and the corresponding addresses of the output data in the first memory 602 during the execution of this program are stored in the first area of ​​the host's buffer. The capacity of the first area is (4n) bytes. Here, n can be set according to the capacity required to record the corresponding address. Here, b is greater than (a+1), (n-1) is greater than (b+1), c is greater than n, d is greater than (c+1), (2n-1) is greater than (d+1), e is greater than (2n), f is greater than (e+1), (3n-1) is greater than (f+1), g is greater than (3n), h is greater than (g+1), and (4n-1) is greater than (h+1).

[0108] Table 3

[0109] In some examples, the information in Table 3 above can be directly included in the sent command. In other examples, the information in Table 3 above can also be stored in a cache on the host, and the sent command carries pointer information pointing to a region in the host cache where Table 3 is stored.

[0110] In the above example, the first preset order is that the corresponding addresses of input data in the first memory 602 are stored first, and the corresponding addresses of output data in the first memory 602 are stored later. The capacity of the buffer occupied by the corresponding address of each input data and each output data in the first memory 602 is n bytes. The number of input data is 2, and the number of output data is 2. Based on this information, the controller 601 can parse the 4n bytes of information stored in the first area of ​​the host's buffer, where the 0th byte to the (n-1)th byte stores the corresponding address of the first input data in the first memory 602, and the nth byte... The (2n-1)th byte stores the corresponding address of the second input data in the first memory 602, the (2n)th byte to the (3n-1)th byte stores the corresponding address of the first output data in the first memory 602, and the (3n)th byte to the (4n-1)th byte stores the corresponding address of the second output data in the first memory 602. This enables the controller 601 to obtain the corresponding address of each input data in the first memory 602 and / or the corresponding address of each output data in the first memory 602 from the first area of ​​the host's buffer based on the parsed information.

[0111] In the above embodiments, the number of input data and the number of output data are carried in the command of the execution program. The corresponding addresses of the input data and output data stored in the first memory are transmitted in the host's buffer. The length of the corresponding address of each input data / output data in the first memory is fixed. In this way, when the controller parses the command of the execution program, it does not need to know the program's unique identifier, but can still find the corresponding input data and the corresponding output data, so that the program can execute normally.

[0112] In some embodiments, the command carries second pointer information; the second pointer information points to a second region in the cache of the host; the second region stores the number of input data, the corresponding address of each input data in the first memory 602, the number of output data, and the corresponding address of each output data in the first memory 602, and the number of input data, the corresponding address of each input data in the first memory 602, the number of output data, and the corresponding address of each output data in the first memory 602 during the program execution process are stored in the second region in a second preset order.

[0113] It is understood that in the above embodiments, the commands sent by the host may not carry the first parameter and the second parameter. The number of input data, the number of output data, the corresponding address of each input data in the first memory 602, and the corresponding address of each output data in the first memory 602 may be stored together in the second area of ​​the host's cache in a second preset order.

[0114] The second preset order here includes several cases: 1. The number of input data is placed first, followed by the corresponding address of each input data in the first memory 602, then the number of output data, and finally the corresponding address of each output data in the first memory 602; 2. The number of output data is placed first, followed by the corresponding address of each output data in the first memory 602, then the number of input data, and finally the corresponding address of each input data in the first memory 602; 3. The number of input data and the number of output data are placed first, and the order can be either input data first and output data second, or output data first and input data second, followed by the corresponding addresses of each input data and each output data in the first memory 602, and the order can also be either input data first and output data second, or output data first and input data second.

[0115] It should be noted that the second preset order listed above is only an example and is not intended to limit the specific setting of the second preset order in the embodiments of this disclosure. In addition to the three methods listed above, the second preset order can also be other feasible setting methods.

[0116] In some embodiments, the controller 601 is configured to: obtain from the host the corresponding addresses of the input data in the first memory 602 and / or the corresponding addresses of the output data in the first memory 602 during the program execution process, based on the number of input data, the corresponding address of each input data in the first memory 602, the number of output data, the capacity of the buffer occupied by the corresponding address of each output data in the first memory 602, information of the second preset order, the number of input data, and the number of output data.

[0117] In some specific examples, the size of the buffer occupied by the corresponding address of each input data in the first memory 602 is a first value, the size of the buffer occupied by the corresponding address of each output data in the first memory 602 is a second value, the size of the buffer occupied by the number of input data is a fifth value, and the size of the buffer occupied by the number of output data is a sixth value.

[0118] In some specific examples, the first, second, fifth, and sixth values ​​may all be unequal; or, the first and second values ​​may be equal, the fifth and sixth values ​​may be unequal, and the first, fifth, and sixth values ​​may all be unequal; or, the first, second, fifth, and sixth values ​​may all be equal.

[0119] It is understood that, in the above embodiment, the controller 601 can obtain the corresponding addresses of the input data in the first memory 602 and the corresponding addresses of the output data in the first memory 602 from the host according to the number of input data, the corresponding address of each input data in the first memory 602, the number of output data, the capacity of the buffer occupied by the corresponding address of each output data in the first memory 602, the information of the second preset order, the number of input data, and the number of output data, thereby enabling the program to execute normally.

[0120] In some embodiments, the host is configured to: determine the number of input data and / or the number of output data during the execution of the program, based on the functional characteristics of the program.

[0121] It is understandable that the number of input data and the number of output data during program execution can be determined based on the program's functional characteristics. Programs with different functional characteristics may have different numbers of input data and output data.

[0122] In some embodiments, the command carries third pointer information and / or fourth pointer information; the third pointer information points to a third region in a buffer in the host, the third region storing the corresponding address of each input data during program execution in the first memory 602; the fourth pointer information points to a fourth region in the buffer, the fourth region storing the corresponding address of each output data during program execution in the first memory 602; the controller 601 is configured to: obtain the corresponding address of the input data during program execution in the first memory 602 from the host based on the address stored in the third region; and / or, obtain the corresponding address of the output data during program execution in the first memory 602 from the host based on the address stored in the fourth region.

[0123] The controller 601 parses and obtains the corresponding addresses of the output data and input data in the first memory 602 during program execution. This can be independent of the number of input and output data. In the above embodiment, the number of input and output data is not involved. The command carries third and / or fourth pointer information. The third pointer information points to a third region in the buffer of the host, where the corresponding address of each input data in the first memory 602 is stored. The fourth pointer information points to a fourth region in the buffer, where the corresponding address of each output data in the first memory 602 is stored. Thus, the controller 601 can obtain the corresponding address of the input data in the first memory 602 from the buffer based on the third pointer information, and obtain the corresponding address of the output data in the first memory 602 from the fourth region based on the fourth pointer information.

[0124] In some embodiments, the computing processing component 603 is configured to: read input data from a corresponding area of ​​the first memory 602 according to the corresponding address of the input data in the first memory 602 during program execution, and execute the program; and store the output data obtained after the program processes the input data into a corresponding area of ​​the first memory 602 according to the corresponding address of the output data in the first memory 602 during program execution.

[0125] In this embodiment of the present disclosure, after the controller 601 obtains the corresponding address of the input data in the first memory 602 during program execution, the controller 601 can inform the computing processing component 603 of the corresponding address of the input data in the first memory 602 during program execution. This enables the computing processing component 603 to obtain the input data from the area corresponding to the corresponding address in the first memory 602 and process the input data. The program in the computing processing component 603 then refreshes the output data obtained after processing the input data to the area corresponding to the corresponding address in the first memory 602, so that the program can execute normally.

[0126] In some embodiments, the command further carries a first identifier: the controller 601 is configured to: based on the value of the first identifier as a third value, and according to the association information of the corresponding addresses of the input data and output data in the first memory 602 during the program execution process as defined by the program unique identifier carried by the command, obtain the corresponding addresses of the input data and output data in the first memory 602 during the program execution process from the host; or, based on the value of the first identifier as a fourth value, and according to the association information of the corresponding addresses of the input data and output data in the first memory 602 during the program execution process as defined by the command, obtain the corresponding addresses of the input data and output data in the first memory 602 during the program execution process from the host.

[0127] Understandably, when an electronic system possesses the ability to obtain the corresponding addresses of input data and output data in the first memory 602 based on the association information of the corresponding addresses of input data and output data in the first memory 602 during program execution, as defined by the program's unique identifier carried in the command, and also possesses the ability to obtain the corresponding addresses of input data and output data in the first memory 602 from the host based on the association information of the corresponding addresses of input data and output data in the first memory 602 during program execution, as defined in the command, the host can carry a first identifier in the sent command to instruct the controller 601 to specifically use which of the above two methods to obtain the corresponding addresses of input data and output data in the first memory 602 during program execution. For example, the third value is either "0" or "1", and the fourth value is either "0" or "1".

[0128] In some specific examples, when the value of the first identifier is the third value, the command also carries a program-unique identifier; when the value of the first identifier is the fourth value, the command does not carry a program-unique identifier.

[0129] In some embodiments, the computing processing component 603 is configured to load the program to be executed.

[0130] In some specific examples, the program to be executed may not be loaded through the computation processing component 603, for example, for a fixed program provided by the manufacturer.

[0131] In some embodiments, as shown in FIG6, the computing storage system 600 further includes a second memory 604 coupled to the controller 601.

[0132] In some specific examples, the second memory 604 is a non-volatile memory, including but not limited to flash memory (such as NAND flash memory), phase-change memory, resistive memory, magnetoresistive memory, ferroelectric memory, or polymer memory. The second memory can be used to store input / output data during program execution.

[0133] In some embodiments, the controller 601 is configured to: write input data during program execution stored in the second memory 604 into the first memory 602; and write output data during program execution stored in the first memory 602 into the second memory 604.

[0134] In some embodiments, the output data during program execution may not be written to the second memory 604, but the host may directly read the output data during program execution stored in the first memory 602.

[0135] Figure 7 is a flowchart illustrating a program execution process according to an embodiment of this disclosure. As shown in Figure 7, the process includes the following steps: Step S100, the host writes the input data required for program execution into the first memory in advance; Step S101, the host creates a command to execute the program, and according to the program's functional characteristics, places the corresponding number of input data and output data into the first parameter and the second parameter respectively, and transmits the corresponding address of each input / output data in the first memory to the host's buffer; finally, the command to execute the program is sent; Step S102, after receiving the command to execute the program, the computing storage system parses the number of input data and the number of output data in the first parameter and the second parameter, and parses the corresponding address of the input data in the first memory and the corresponding address of the output data in the first memory in the buffer according to the number of input data and the number of output data; finds the specific input parameter data required by the program and executes the program; after the program processes the input data, the output data obtained is placed in the buffer in the area specified by the corresponding address of the output data in the first memory, thus completing the program execution.

[0136] In some embodiments, as shown in FIG8, the computing storage system 600 includes a non-volatile namespace 610, a computing namespace 608, and a subsystem local storage namespace 609; the non-volatile namespace 610 includes the second memory 604, the computing namespace 608 includes the computing processing component 603, and the subsystem local storage namespace 609 includes the first memory 602.

[0137] The solution provided in this disclosure does not require the application of a program unique identifier. Through a universal command format, the host can communicate with the controller and execute the program. The universal approach is more in line with the idea of ​​standardization, which can reduce the complexity of the host and computing storage system implementation and improve the efficiency of the program from development to running in the computing processing component.

[0138] Based on the above-described computing and storage system, this disclosure also provides an electronic system, as shown in FIG9. The electronic system includes a host 605 and a computing and storage system 600 coupled to the host 605. The computing and storage system 600 includes a controller 601, a first memory 602 coupled to the controller 601, and a computing processing component 603 for executing a program. The host 605 is configured to send a command to instruct the computing processing component 603 to execute a program, and the command is configured to define association information of the corresponding addresses of input data and / or output data in the first memory 602 during the program execution process. The controller 601 is configured to receive the command and, based on the association information, obtain from the host 605 the corresponding addresses of the input data and / or output data in the first memory 602 during the program execution process.

[0139] As shown in FIG9, the first memory 602 includes a first storage area 606 configured for input data during the execution of a program by the computing processing component 603, and a second storage area 607 configured for output data during the execution of a program by the computing processing component 603.

[0140] As shown in Figure 9, the host 605 includes a cache 611, which is a volatile memory. The volatile memory includes, but is not limited to, random access memory, dynamic random access memory, static random access memory, synchronous dynamic random access memory, and double data rate synchronous dynamic random access memory.

[0141] In some embodiments, the command carries first pointer information, as well as a first parameter and / or a second parameter; the first parameter contains the number of input data during the program execution process, and the second parameter contains the number of output data during the program execution process; the first pointer information points to a first region in the buffer of the host 605, and the first region stores the corresponding address of each input data in the first memory 602 and the corresponding address of each output data in the first memory 602.

[0142] In some embodiments, the controller 601 is configured to: obtain from the register of the host 605 the corresponding address of each input data in the first memory 602 and / or the corresponding address of each output data in the first memory 602 during the program execution process, based on the first pointer information and the first parameter and / or the second parameter.

[0143] In some embodiments, the host 605 is configured to: sequentially store the corresponding addresses of each input data and each output data in the first memory 602 in the first area according to a first preset order; the controller 601 is configured to: obtain the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory 602 from the host 605 based on the capacity of the buffer occupied by each corresponding address of each input data and each output data in the first memory 602, the information of the first preset order, the number of input data and the number of output data.

[0144] In some embodiments, the host 605 is configured to: store the corresponding addresses of each input data and each output data in the first memory 602 in the first memory 602 in a first area of ​​the host 605's buffer, in the order that the corresponding addresses of the input data in the first memory 602 are stored first, and the corresponding addresses of the output data in the first memory 602 are stored later; or, store the corresponding addresses of each input data and each output data in the first memory 602 in the first area of ​​the host 605's buffer, in the order that the corresponding addresses of the output data in the first memory 602 are stored first, and the corresponding addresses of the input data in the first memory 602 are stored later.

[0145] In some embodiments, the command carries second pointer information; the second pointer information points to a second region in the cache of the host 605; the second region stores the number of input data, the corresponding address of each input data in the first memory 602, the number of output data, and the corresponding address of each output data in the first memory 602.

[0146] In some embodiments, the host 605 is configured to: sequentially store the number of input data during program execution, the corresponding address of each input data in the first memory 602, the number of output data, and the corresponding address of each output data in the first memory 602 in the second area according to a second preset order; the controller 601 is configured to: obtain the corresponding addresses of the input data in the first memory 602 and / or the corresponding addresses of the output data in the first memory 602 from the host 605 according to the number of input data, the corresponding address of each input data in the first memory 602, the number of output data, the capacity of the buffer occupied by each corresponding address of each output data in the first memory 602, the information of the second preset order, the number of input data, and the number of output data.

[0147] In some embodiments, the host 605 is configured to: determine the number of input data and / or the number of output data during the execution of the program based on the functional characteristics of the program.

[0148] In some embodiments, the command carries third pointer information and / or fourth pointer information; the third pointer information points to a third region in a buffer in the host 605, the third region storing the corresponding address of each input data during program execution in the first memory 602; the fourth pointer information points to a fourth region in the buffer, the fourth region storing the corresponding address of each output data during program execution in the first memory 602; the controller 601 is configured to: obtain the corresponding address of the input data during program execution in the first memory 602 from the host 605 based on the address stored in the third region; and / or, obtain the corresponding address of the output data during program execution in the first memory 602 from the host 605 based on the address stored in the fourth region.

[0149] In some embodiments, the corresponding address of each input data in the first memory 602 occupies the same capacity of the cache and is a first value, and the corresponding address of each output data in the first memory 602 occupies the same capacity of the cache and is a second value, wherein the first value and the second value are equal.

[0150] In some embodiments, the corresponding address of each input data / output data in the first memory 602 includes information about the first memory 602 to which the region storing the corresponding input data / output data belongs, the size of the input data / output data, and the starting address of the input data / output data in the first memory 602.

[0151] In some embodiments, the computing processing component 603 is configured to: read input data from a corresponding area of ​​the first memory 602 according to the corresponding address of the input data in the first memory 602 during program execution, and execute the program; and store the output data obtained after the program processes the input data into a corresponding area of ​​the first memory 602 according to the corresponding address of the output data in the first memory 602 during program execution.

[0152] In some embodiments, the command further carries a first identifier: the controller 601 is configured to: based on the value of the first identifier as a third value, and according to the association information of the corresponding addresses of the input data and output data in the first memory 602 during the program execution process as defined by the program unique identifier carried by the command, obtain the corresponding addresses of the input data and output data in the first memory 602 during the program execution process; or, based on the value of the first identifier as a fourth value, and according to the association information of the corresponding addresses of the input data and output data in the first memory 602 during the program execution process as defined by the command, obtain the corresponding addresses of the input data and output data in the first memory 602 during the program execution process from the host 605.

[0153] In some embodiments, the computing storage system 600 further includes a second memory coupled to the controller 601, the controller 601 being configured to: write input data during program execution stored in the second memory into the first memory 602; and write output data during program execution stored in the first memory 602 into the second memory.

[0154] In some embodiments, the computing storage system 600 includes a non-volatile namespace, a computing namespace, and a subsystem local storage namespace; the non-volatile namespace includes the second memory, the computing namespace includes the computing processing component 603, and the subsystem local storage namespace includes the first memory 602.

[0155] Other details regarding the aforementioned electronic system have been described in detail in the foregoing embodiments concerning the computing and storage system, and will not be repeated here for the sake of brevity.

[0156] Based on the above-described computing storage system, this disclosure also provides an operation method for the computing storage system, as shown in FIG10. The operation method includes the following steps: Step S200, receiving a command sent by a host coupled to the computing storage system, the command being used to instruct a computing processing component to execute a program, and the command being configured to define association information of the corresponding addresses of input data and / or output data during the program execution process in a first memory coupled to the controller of the computing storage system; Step S201, obtaining the corresponding addresses of input data and / or output data during the program execution process in the first memory from the host according to the association information.

[0157] In some embodiments, the command carries first pointer information, as well as a first parameter and / or a second parameter; the first parameter contains the number of input data during the program execution process, and the second parameter contains the number of output data during the program execution process; the first pointer information points to a first area in the cache of the host, the first area stores the corresponding address of each input data in the first memory and the corresponding address of each output data in the first memory, and the corresponding addresses of each input data in the first memory and the corresponding addresses of each output data in the first memory during the program execution process are stored sequentially in the first area according to a first preset order.

[0158] In some embodiments, obtaining the corresponding addresses of input data and / or output data in the first memory during program execution from the host according to the association information includes: obtaining the corresponding address of each input data and / or each output data in the first memory during program execution from the host's buffer according to the first pointer information, and the first parameter and / or the second parameter.

[0159] In some embodiments, obtaining the corresponding addresses of input data and / or output data in the first memory during program execution from the host according to the associated information includes: obtaining the corresponding addresses of input data and / or output data in the first memory from the host according to the capacity of the buffer occupied by each input data and each output data in the first memory, the information of the first preset order, the number of input data and the number of output data.

[0160] In some embodiments, the first preset order includes: the corresponding address of the input data in the first memory is stored first, and the corresponding address of the output data in the first memory is stored later; or, the corresponding address of the output data in the first memory is stored first, and the corresponding address of the input data in the first memory is stored later.

[0161] In some embodiments, the command carries second pointer information; the second pointer information points to a second region in the cache of the host; the second region stores the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory, and the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory during the program execution process are stored in the second region in a second preset order.

[0162] In some embodiments, obtaining the corresponding addresses of input data and / or output data in the first memory during program execution from the host according to the associated information includes: obtaining the corresponding addresses of input data and / or output data in the first memory during program execution from the host according to the number of input data, the corresponding address of each input data in the first memory, the number of output data, the capacity of the buffer occupied by the corresponding address of each output data in the first memory, the information of the second preset order, the number of input data, and the number of output data.

[0163] In some embodiments, the operation method further includes: determining the number of input data and / or the number of output data during the execution of the program based on the functional characteristics of the program.

[0164] In some embodiments, the command carries third pointer information and / or fourth pointer information; the third pointer information points to a third region in a buffer in the host, the third region storing the corresponding address of each input data during program execution in the first memory; the fourth pointer information points to a fourth region in the buffer, the fourth region storing the corresponding address of each output data during program execution in the first memory; obtaining the corresponding address of the input data and / or output data during program execution in the first memory from the host according to the association information includes: obtaining the corresponding address of the input data during program execution in the first memory from the host according to the address stored in the third region; and / or, obtaining the corresponding address of the output data during program execution in the first memory from the host according to the address stored in the fourth region.

[0165] In some embodiments, the corresponding address of each input data in the first memory occupies the same capacity of the buffer and is a first value, and the corresponding address of each output data in the first memory occupies the same capacity of the buffer and is a second value, wherein the first value and the second value are equal.

[0166] In some embodiments, the corresponding address of each input data / output data in the first memory includes information about the first memory to which the region storing the corresponding input data / output data belongs, the size of the input data / output data, and the starting address of the input data / output data in the first memory.

[0167] The operation method of the computing storage system mentioned in the above embodiments has been described in detail in the foregoing embodiments concerning the computing storage system, and will not be repeated here for the sake of brevity.

[0168] Based on the above-described operation method of the computing storage system, this disclosure also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the operation method of the computing storage system described in any of the above embodiments.

[0169] Here, implementing all or part of the operational methods of the computing storage system in the above embodiments can be accomplished by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc or a compact disc read-only memory (CD-ROM), etc.; the storage medium can also include combinations of the above types of memory.

[0170] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0171] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0172] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An electronic system comprising a host computer and a computing storage system coupled to the host computer; the computing storage system comprising a controller, a first memory coupled to the controller, and a computing processing component for executing a program; The host is configured to send a command to instruct the computing processing component to execute a program, and the command is configured to define the association information of the corresponding addresses of input data and / or output data in the first memory during the execution of the program. The controller is configured to: receive the command and, based on the association information, obtain from the host the corresponding addresses of the input data and / or output data during the program execution process in the first memory.

2. The electronic system according to claim 1, wherein, The command carries first pointer information, as well as a first parameter and / or a second parameter; the first parameter contains the number of input data during the program execution process, and the second parameter contains the number of output data during the program execution process; the first pointer information points to a first area in the cache of the host, and the first area stores the corresponding address of each input data in the first memory and the corresponding address of each output data in the first memory.

3. The electronic system according to claim 2, wherein, The controller is configured to: obtain from the host's cache the corresponding address of each input data in the first memory and / or the corresponding address of each output data in the first memory during the program execution process, based on the first pointer information and the first parameter and / or the second parameter.

4. The electronic system according to claim 2, wherein, The host is configured to: sequentially store the corresponding addresses of each input data in the first memory and the corresponding addresses of each output data in the first memory in the first area according to a first preset order; The controller is configured to: obtain from the host the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory during the program execution process, based on the capacity of the buffer occupied by each input data and each output data in the first memory, the information of the first preset order, the number of input data, and the number of output data.

5. The electronic system according to claim 4, wherein, The host is configured to: store each input data and each output data in the first memory in the first memory in a first area of ​​the host's buffer, in the order that the input data is stored first and the output data is stored last; or, store each input data and each output data in the first memory in the first memory in the first area of ​​the host's buffer, in the order that the output data is stored first and the input data is stored last.

6. The electronic system according to claim 1, wherein, The command carries second pointer information; the second pointer information points to a second region in the cache of the host; the second region stores the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory.

7. The electronic system according to claim 6, wherein, The host is configured to: store the number of input data during the program execution process, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory in the second area in a second preset order; The controller is configured to: Based on the number of input data, the corresponding address of each input data in the first memory, the number of output data, the capacity of the buffer occupied by each corresponding address of each output data in the first memory, the information of the second preset order, the number of input data, and the number of output data, the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory during the program execution process are obtained from the host.

8. The electronic system according to any one of claims 2 to 7, wherein, The host is configured as follows: Based on the functional characteristics of the program, determine the number of input data and / or the number of output data during the program execution process.

9. The electronic system according to claim 1, wherein, The command carries third pointer information and / or fourth pointer information; the third pointer information points to a third region in the buffer of the host, the third region storing the corresponding address of each input data during program execution in the first memory; the fourth pointer information points to a fourth region in the buffer, the fourth region storing the corresponding address of each output data during program execution in the first memory; the controller is configured to: Based on the address stored in the third region, the corresponding address of the input data during program execution in the first memory is obtained from the host; and / or, based on the address stored in the fourth region, the corresponding address of the output data during program execution in the first memory is obtained from the host.

10. The electronic system according to claim 2, 6, or 9, wherein, Each input data occupies the same size of the buffer at its corresponding address in the first memory, and both are of the first value. Each output data occupies the same size of the buffer at its corresponding address in the first memory, and both are of the second value. The first value and the second value are equal.

11. The electronic system according to claim 2, 6, or 9, wherein, The corresponding address of each input / output data in the first memory includes information about the first memory to which the region storing the corresponding input / output data belongs, the size of the input / output data, and the starting address of the input / output data in the first memory.

12. The electronic system according to claim 1, wherein, The computational processing component is configured as follows: Based on the corresponding address of the input data in the first memory during program execution, the input data in the corresponding area of ​​the first memory is read, and the program is executed. Based on the corresponding address of the output data during the program execution process in the first memory, the output data obtained after the program processes the input data is stored in the corresponding area of ​​the first memory.

13. The electronic system according to claim 1, wherein, The command also carries a first identifier: The controller is configured to: Based on the value of the first identifier being a third value, and according to the association information of the corresponding addresses of the input data and output data in the first memory during the program execution process as defined by the program unique identifier carried by the command, the corresponding addresses of the input data and output data in the first memory during the program execution process are obtained; or, Based on the value of the first identifier as the fourth value, and according to the association information of the corresponding addresses of the input data and output data in the first memory during the program execution process as defined by the command, the corresponding addresses of the input data and output data in the first memory during the program execution process are obtained from the host.

14. The electronic system according to claim 1, wherein, The computing storage system also includes a second memory coupled to the controller, the controller being configured to: Write the input data during the program execution process stored in the second memory into the first memory; Write the output data of the program execution process stored in the first memory into the second memory.

15. The electronic system according to claim 14, wherein, The computing storage system includes a non-volatile namespace, a computing namespace, and a subsystem local storage namespace; the non-volatile namespace includes the second memory, the computing namespace includes the computing processing component, and the subsystem local storage namespace includes the first memory.

16. A computing storage system, the computing storage system comprising a controller, a first memory coupled to the controller, and a computing processing component for executing a program; the controller being configured to: The system receives a command sent by a host coupled to the computing storage system, the command being used to instruct the computing processing component to execute a program, and the command being configured to define the association information of the corresponding addresses of input data and / or output data in the first memory during the execution of the program; Based on the associated information, the corresponding addresses of the input data and / or output data during the program execution process in the first memory are obtained from the host.

17. The computing storage system according to claim 16, wherein, The command carries first pointer information, as well as a first parameter and / or a second parameter; the first parameter contains the number of input data during the program execution process, and the second parameter contains the number of output data during the program execution process; the first pointer information points to a first area in the cache of the host, the first area stores the corresponding address of each input data in the first memory and the corresponding address of each output data in the first memory, and the corresponding addresses of each input data in the first memory and the corresponding addresses of each output data in the first memory during the program execution process are stored in the first area in a first preset order.

18. The computing storage system according to claim 17, wherein, The controller is configured to: obtain from the host's cache the corresponding address of each input data in the first memory and / or the corresponding address of each output data in the first memory during the program execution process, based on the first pointer information and the first parameter and / or the second parameter.

19. The computing storage system according to claim 17, wherein, The controller is configured to: obtain from the host the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory during the program execution process, based on the capacity of the buffer occupied by each input data and each output data in the first memory, the information of the first preset order, the number of input data, and the number of output data.

20. The computing storage system according to claim 17, wherein, The first preset order includes: the corresponding address of the input data in the first memory is stored first, and the corresponding address of the output data in the first memory is stored later; or, the corresponding address of the output data in the first memory is stored first, and the corresponding address of the input data in the first memory is stored later.

21. The computing storage system according to claim 16, wherein, The command carries second pointer information; the second pointer information points to a second area in the cache of the host; the second area stores the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory. The number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory during the program execution process are stored in the second area in a second preset order.

22. The computing storage system according to claim 21, wherein, The controller is configured to: Based on the number of input data, the corresponding address of each input data in the first memory, the number of output data, the capacity of the buffer occupied by each corresponding address of each output data in the first memory, the information of the second preset order, the number of input data, and the number of output data, the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory during the program execution process are obtained from the host.

23. The computing storage system according to any one of claims 17 to 22, wherein, The host is configured as follows: Based on the functional characteristics of the program, determine the number of input data and / or the number of output data during the program execution process.

24. The computing storage system according to claim 16, wherein, The command carries third pointer information and / or fourth pointer information; the third pointer information points to a third region in the buffer of the host, the third region storing the corresponding address of each input data during program execution in the first memory; the fourth pointer information points to a fourth region in the buffer, the fourth region storing the corresponding address of each output data during program execution in the first memory; the controller is configured to: Based on the address stored in the third region, the corresponding address of the input data during program execution in the first memory is obtained from the host; and / or, based on the address stored in the fourth region, the corresponding address of the output data during program execution in the first memory is obtained from the host.

25. The computing storage system according to claim 17, 21, or 24, wherein, Each input data occupies the same size of the buffer at its corresponding address in the first memory, and both are of the first value. Each output data occupies the same size of the buffer at its corresponding address in the first memory, and both are of the second value. The first value and the second value are equal.

26. The computing storage system according to claim 17, 21, or 24, wherein, The corresponding address of each input / output data in the first memory includes information about the first memory to which the region storing the corresponding input / output data belongs, the size of the input / output data, and the starting address of the input / output data in the first memory.

27. A method of operating a computing storage system, the method comprising: Receive a command sent by a host coupled to the computing storage system, the command being used to instruct a computing processing component to execute a program, and the command being configured to define the association information of the corresponding addresses of input data and / or output data during the execution of the program in a first memory coupled to the controller of the computing storage system; Based on the associated information, the corresponding addresses of the input data and / or output data during the program execution process in the first memory are obtained from the host.

28. The operating method according to claim 27, wherein, The command carries first pointer information, as well as a first parameter and / or a second parameter; the first parameter contains the number of input data during the program execution process, and the second parameter contains the number of output data during the program execution process; the first pointer information points to a first area in the cache of the host, the first area stores the corresponding address of each input data in the first memory and the corresponding address of each output data in the first memory, and the corresponding addresses of each input data in the first memory and the corresponding addresses of each output data in the first memory during the program execution process are stored in the first area in a first preset order.

29. The operating method according to claim 28, wherein, The step of obtaining the corresponding addresses of the input data and / or output data during program execution in the first memory from the host according to the associated information includes: Based on the first pointer information, and the first parameter and / or the second parameter, obtain from the host's cache the corresponding address of each input data in the first memory and / or the corresponding address of each output data in the first memory during the program execution process.

30. The operating method according to claim 28, wherein, The step of obtaining the corresponding addresses of the input data and / or output data during program execution in the first memory from the host according to the associated information includes: Based on the capacity of the buffer occupied by each input data and each output data in the first memory, the information of the first preset order, the number of input data and the number of output data, the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory during the program execution process are obtained from the host.

31. The operating method according to claim 28, wherein, The first preset order includes: the corresponding address of the input data in the first memory is stored first, and the corresponding address of the output data in the first memory is stored later; or, the corresponding address of the output data in the first memory is stored first, and the corresponding address of the input data in the first memory is stored later.

32. The operating method according to claim 27, wherein, The command carries second pointer information; the second pointer information points to a second area in the cache of the host; the second area stores the number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory. The number of input data, the corresponding address of each input data in the first memory, the number of output data, and the corresponding address of each output data in the first memory during the program execution process are stored in the second area in a second preset order.

33. The operating method according to claim 32, wherein, The step of obtaining the corresponding addresses of the input data and / or output data during program execution in the first memory from the host according to the associated information includes: Based on the number of input data, the corresponding address of each input data in the first memory, the number of output data, the capacity of the buffer occupied by each corresponding address of each output data in the first memory, the information of the second preset order, the number of input data, and the number of output data, the corresponding addresses of the input data and / or the corresponding addresses of the output data in the first memory during the program execution process are obtained from the host.

34. The operating method according to any one of claims 28 to 33, wherein, The operation method further includes: Based on the functional characteristics of the program, determine the number of input data and / or the number of output data during the program execution process.

35. The operating method according to claim 27, wherein, The command carries third pointer information and / or fourth pointer information; the third pointer information points to a third region in the buffer of the host, the third region storing the corresponding address of each input data in the first memory during the execution of the program; the fourth pointer information points to a fourth region in the buffer, the fourth region storing the corresponding address of each output data in the first memory during the execution of the program; The step of obtaining the corresponding addresses of the input data and / or output data during program execution in the first memory from the host according to the associated information includes: Based on the addresses stored in the third region, the corresponding addresses of the input data during program execution in the first memory are obtained from the host. And / or, based on the address stored in the fourth region, obtain from the host the corresponding address of the output data during program execution in the first memory.

36. The operating method according to claim 28, 32, or 35, wherein, Each input data occupies the same size of the buffer at its corresponding address in the first memory, and both are of the first value. Each output data occupies the same size of the buffer at its corresponding address in the first memory, and both are of the second value. The first value and the second value are equal.

37. The operating method according to claim 28, 32, or 35, wherein, The corresponding address of each input / output data in the first memory includes information about the first memory to which the region storing the corresponding input / output data belongs, the size of the input / output data, and the starting address of the input / output data in the first memory.

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