Semiconductor device

Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes a first memory cell, a sense amplifier, a second memory cell, and an operation block. The first memory cell, the sense amplifier, and the operation block are provided in a first element layer. The second memory cell is provided in a second element layer. The second element layer is provided above the first element layer. The second memory cell is electrically connected to the sense amplifier and the first memory cell through a first bit line. The first memory cell is electrically connected to the operation block through a second bit line. Data transferred to the operation block is data written to the first memory cell by activating data held by the second memory cell in the sense amplifier.

Description

Technical Field

[0001] This manual describes semiconductor devices, etc.

[0002] Note that one aspect of the present invention is not limited to the above-described technical fields. Examples of technical fields for one aspect of the present invention disclosed in this specification include semiconductor devices, imaging devices, display devices, light-emitting devices, energy storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, or manufacturing methods thereof. Background Technology

[0003] In recent years, the importance of measures to combat global warming has increased. Energy consumption continues to rise, and carbon dioxide emissions, one of the causes of global warming, have not yet been reduced. Simply reducing energy consumption can sometimes lead to a decrease in convenience. Therefore, low-power technologies have become crucial for reducing energy consumption without compromising convenience.

[0004] In AI (Artificial Intelligence) technology, as performance increases and power consumption rises, the development of low-power technologies is becoming increasingly active. AI technology involves a repetitive process: sequentially reading data stored in a memory circuit, performing calculations using that data in an arithmetic circuit, and then storing the resulting data in a memory. Therefore, the power consumption of data transfer between the memory and arithmetic circuits is dominant. As a countermeasure, for example, techniques have been proposed that integrate the memory and arithmetic circuits using transistors, including oxide semiconductor transistors (also known as OS transistors), i.e., so-called in-memory computing or near-memory computing technology (e.g., Patent Document 1).

[0005] [Preliminary Technology Documents]

[0006] [Patent Literature]

[0007] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0024083 Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] In computing circuits, when performing a series of computational processes required by AI technology, storage circuits that can read or write large amounts of data at high speed are needed. SRAM (Static Random Access Memory) cells are preferred for such storage circuits; however, SRAM cells are disadvantageous due to their large area per cell and high power consumption when holding data. On the other hand, storage circuits using OS transistors are advantageous because they offer low power consumption when holding data, high flexibility in configuration, and the ability to increase the number of cells per unit area through stacking. However, the data read or write speed of OS transistor-based storage circuits is lower than that of SRAM.

[0010] One objective of this invention is to provide a semiconductor device that operates at high speed, consumes low power, can hold large amounts of data, and is capable of performing a series of computational processes required by AI technology. Furthermore, one objective of this invention is to provide a semiconductor device that achieves miniaturization. Additionally, one objective of this invention is to provide a semiconductor device with a novel structure.

[0011] Note that one embodiment of the present invention does not need to achieve all of the above objectives; achieving at least one objective is sufficient. Furthermore, the description of the above objectives does not preclude the existence of other objectives. Objectives other than those described above can be readily apparent from the description, claims, drawings, etc.

[0012] means of solving technical problems

[0013] One aspect of the present invention is a semiconductor device including a first storage cell, a sense amplifier, a second storage cell, and an arithmetic block, wherein the first storage cell, the sense amplifier, and the arithmetic block are disposed in a first element layer, the second storage cell is disposed in a second element layer, the second element layer is disposed above the first element layer, the second storage cell is electrically connected to the sense amplifier and the first storage cell via a first bit line, the first storage cell is electrically connected to the arithmetic block via a second bit line, and the data transmitted to the arithmetic block is data written to the first storage cell by activating the data held in the second storage cell in the sense amplifier.

[0014] One aspect of the present invention is a semiconductor device including a first storage unit, a sense amplifier, a second storage unit, and an arithmetic block. The first storage unit, sense amplifier, and arithmetic block are disposed in a first element layer, and the second storage unit is disposed in a second element layer. The second element layer is disposed above the first element layer. The second storage unit is electrically connected to the sense amplifier and the first storage unit via a first bit line. The first storage unit is electrically connected to the arithmetic block via a second bit line. The data transmitted to the arithmetic block is data written to the first storage unit by activating the data held in the second storage unit in the sense amplifier. The arithmetic block includes a product summation unit, an activation function arithmetic unit, a data conversion unit, a loading storage unit, and a controller unit.

[0015] In a semiconductor device according to one aspect of the present invention, preferably, the first memory cell includes a first transistor, and the first transistor includes a first semiconductor layer comprising silicon in a channel forming region.

[0016] In one aspect of the semiconductor device of the present invention, it is preferred that the second memory cell includes a second transistor, and the second transistor includes a second semiconductor layer comprising an oxide semiconductor in the channel forming region.

[0017] In one aspect of the semiconductor device of the present invention, the first storage cell is preferably a storage cell of a static random access memory.

[0018] In one aspect of the semiconductor device of the present invention, the first bit line preferably has a portion disposed parallel to a direction perpendicular to the surface of the substrate on which the first element layer is disposed, between the second memory cell and the sense amplifier, and between the second memory cell and the first memory cell.

[0019] In a semiconductor device according to one aspect of the present invention, preferably, the product summation unit includes an arithmetic circuit and an analog-to-digital conversion circuit. The arithmetic circuit includes a cell array for performing product summation operations and an input circuit for converting the input digital signal into an analog signal and inputting it into the cell array. The analog-to-digital conversion circuit has the function of converting the analog signal output by the arithmetic circuit into a digital signal. The input circuit and the analog-to-digital conversion circuit are disposed in a first element layer, and the cell array is disposed in a second element layer.

[0020] Note that other aspects of the present invention are described in the following description and accompanying drawings.

[0021] Invention Effects

[0022] One aspect of the present invention can provide a semiconductor device that operates at high speed, consumes low power, can hold large amounts of data, and is capable of performing a series of computational processes required by AI technology. Furthermore, one aspect of the present invention can provide a miniaturized semiconductor device. Additionally, one aspect of the present invention can provide a semiconductor device with a novel structure.

[0023] The description of multiple effects does not preclude the existence of each other's effects. Furthermore, one aspect of the invention does not necessarily require all of the aforementioned effects. In one aspect of the invention, objectives, effects, and novel features beyond the foregoing can be readily understood from the description and drawings herein.

[0024] Brief description of the attached figures

[0025] Figure 1A and Figure 1B This is a diagram illustrating an example of the structure of a semiconductor device.

[0026] Figure 2 This is a diagram illustrating an example of how a semiconductor device works.

[0027] Figure 3A and Figure 3B This is a diagram illustrating an example of the structure of a semiconductor device.

[0028] Figure 4A and Figure 4B This is a diagram illustrating an example of the structure of a semiconductor device.

[0029] Figure 5A and Figure 5B This is a diagram illustrating an example of the structure of a semiconductor device.

[0030] Figures 6A to 6C This is a diagram illustrating an example of the structure of a semiconductor device.

[0031] Figures 7A to 7G This is a diagram illustrating an example of the structure of a semiconductor device.

[0032] Figures 8A to 8C This is a diagram illustrating an example of the structure of a semiconductor device.

[0033] Figure 9A and Figure 9B This is a diagram illustrating an example of the structure of a semiconductor device.

[0034] Figure 10A and Figure 10B This is a diagram illustrating an example of the structure of a semiconductor device.

[0035] Figure 11 This is a diagram illustrating an example of the structure of a semiconductor device.

[0036] Figures 12A to 12CThis is a diagram illustrating an example of the structure of a semiconductor device.

[0037] Figures 13A to 13D This is a diagram illustrating an example of the structure of a semiconductor device.

[0038] Figure 14 This is a timing diagram illustrating an example of how a semiconductor device works.

[0039] Figure 15 This is a cross-sectional view illustrating an example of the structure of a semiconductor device.

[0040] Figure 16A This is a diagram illustrating an example of the structure of a transistor included in a semiconductor device. Figure 16B It is a diagram illustrating the equivalent circuit of a memory cell.

[0041] Figures 17A to 17C This is a cross-sectional view illustrating an example of the structure of a transistor included in a semiconductor device.

[0042] Figure 18A This is a plan view illustrating an example of the structure of a transistor included in a semiconductor device. Figures 18B to 18D This is a cross-sectional view illustrating an example of the structure of a transistor included in a semiconductor device.

[0043] Figure 19A This is a plan view illustrating an example of the structure of a transistor included in a semiconductor device. Figures 19B to 19D This is a cross-sectional view illustrating an example of the structure of a transistor included in a semiconductor device.

[0044] Figure 20 This is a cross-sectional view illustrating an example of the structure of a semiconductor device.

[0045] Figure 21A This is a diagram illustrating an example of the structure of a transistor included in a semiconductor device. Figure 21B It is a diagram illustrating the equivalent circuit of a memory cell.

[0046] Figure 22A and Figure 22B This is a plan view showing an example of the structure of a transistor included in a semiconductor device. Figure 22C This is a cross-sectional view showing an example of the structure of a transistor included in a semiconductor device.

[0047] Figure 23A and Figure 23B This is a cross-sectional view showing an example of the structure of a transistor included in a semiconductor device.

[0048] Figure 24 This is a cross-sectional view showing an example of the structure of a transistor included in a semiconductor device.

[0049] Figure 25A and Figure 25BThis is a schematic diagram illustrating an example of the structure of a transistor included in a semiconductor device.

[0050] Figure 26A and Figure 26B This is a plan view showing an example of the structure of a transistor included in a semiconductor device. Figure 26C and Figure 26D This is a cross-sectional view showing an example of the structure of a transistor included in a semiconductor device.

[0051] Figures 27A to 27D This is a cross-sectional view illustrating a method for depositing metal oxides according to one aspect of the present invention.

[0052] Figures 28A to 28D This is a cross-sectional view illustrating a method for depositing metal oxides according to one aspect of the present invention.

[0053] Figure 29A and Figure 29B This is a diagram showing an example of an electronic component.

[0054] Figures 30A to 30D This is a diagram illustrating an example of an electronic component.

[0055] Figure 31A and Figure 31B This is a diagram illustrating an example of an electronic device.

[0056] Figures 32A to 32C This is a diagram illustrating an example of an electronic device.

[0057] Figure 33 This is a diagram illustrating an example of a large computer.

[0058] Methods of implementing the invention

[0059] The embodiments will now be described. Note that one embodiment of the present invention is not limited to the following description, and those skilled in the art will readily understand that its manner and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, one aspect of the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0060] Note that in this specification, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Furthermore, these ordinal numbers do not limit the order of the constituent elements. Additionally, for example, in this specification, a constituent element referred to by "first" in one embodiment may be designated as a constituent element referred to by "second" in other embodiments or claims. Furthermore, for example, in this specification, a constituent element referred to by "first" in one embodiment may be omitted in other embodiments or claims.

[0061] In the accompanying drawings, the same symbol is sometimes used to represent the same element or elements with the same function, elements made of the same material or elements formed at the same time, and sometimes repeated descriptions are omitted.

[0062] In this specification, the power supply potential VDD is sometimes simply referred to as potential VDD, VDD, etc. The same applies to other components (e.g., signals, voltages, circuits, components, electrodes, and wiring).

[0063] In addition, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as “_1”, “_2”, “[n]”, “[m,n]” are sometimes added to the symbol for identification. For example, the second wiring GL is represented as wiring GL[2].

[0064] (Implementation Method 1)

[0065] The structure and operation of a semiconductor device according to one aspect of the present invention will be described.

[0066] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the properties of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, and storage devices are also types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc., sometimes include semiconductor devices.

[0067] (Structural example of semiconductor device 100)

[0068] Figure 1AThis is a schematic diagram illustrating one aspect of the semiconductor device 100 of the present invention. The semiconductor device 100 has the function of performing computational processing such as product sum operations used in AI technology. The semiconductor device 100 capable of performing a series of computational processes required by AI technology is called an NPU (Neural-network Processing Unit). The semiconductor device 100 performs computational processing related to neural networks using data stored in a storage circuit section. Specifically, it performs parallel processing accompanying product sum operations, activation function operations, data transformation operations, and loading and storing data for various computational processes.

[0069] Semiconductor device 100 includes a device layer 10 and a device layer 40 stacked on the device layer 10. Figure 1A In the schematic diagram shown, to facilitate understanding of the arrangement of the various components constituting the semiconductor device 100, the element layer 10 and element layer 40 are shown separated from each other. Furthermore, the element layer is a layer on which elements such as transistors or capacitors are disposed.

[0070] The component layer 10 includes an interface section 12, a storage circuit section 11, and an arithmetic block 14. The storage circuit section 11 includes a readout amplifier section 20 and a storage circuit 30. The arithmetic block 14 includes a controller section 15, a product summation section 16, an activation function arithmetic section 17, a data conversion section 18, and a loading storage section 19.

[0071] exist Figure 1A In the schematic diagrams shown, to illustrate the configuration of each structure, the direction perpendicular or substantially perpendicular to the surface of component layer 10 (e.g., the surface where an interlayer insulating layer is provided) is defined as the Z-axis direction. Furthermore, for ease of understanding, the Z-axis direction is sometimes referred to as the direction perpendicular to the surface of component layer 10 in the specification. Note that "substantially perpendicular" refers to a configuration at an angle of 85 degrees or more but less than 95 degrees.

[0072] Note that, in order to illustrate the configuration of the various components, the X, Y, and Z directions are sometimes specified in this specification and accompanying drawings. For example, in Figure 1A In the schematic diagram shown, to illustrate the arrangement of the constituent elements constituting the semiconductor device 100, the X, Y, and Z directions are sometimes specified. The X, Y, and Z directions are each perpendicular or substantially perpendicular to each other.

[0073] The device layer 10 includes a silicon transistor (Si transistor) contained in a semiconductor layer having a channel formation region. The device layer 10 is a device layer in which a semiconductor layer having a channel formation region is disposed within a silicon substrate, or a device layer formed by attaching a silicon semiconductor layer having a channel formation region to a silicon substrate.

[0074] Although the case where the substrate provided in element layer 10 is a silicon substrate has been described, this embodiment is not limited to this. Note that a silicon substrate refers to a substrate with silicon as the semiconductor material, such as a single-crystal silicon substrate. In addition, it is not limited to silicon, and materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc., may also be used as the substrate.

[0075] The Si transistors included in the element layer 10 are made of highly crystalline silicon, such as monocrystalline silicon or polycrystalline silicon. Because the element layer 10 contains highly crystalline silicon, a high field-effect mobility can be achieved, enabling higher-speed operation. Therefore, the interface section 12, the sense amplifier section 20 and storage circuit 30 included in the storage circuit section 11, and the controller section 15, product summation section 16, activation function calculation section 17, data conversion section 18, and loading storage section 19 included in the arithmetic block 14 can be integrated into the element layer 10.

[0076] Component layer 40 includes multiple storage cells 41. Note that, although Figure 1A The element layer 40 is shown only above the storage circuit section 11 included in the element layer 10, but the element layer 40 can be provided at any position that overlaps with the element layer 10.

[0077] Storage unit 41 is used as a storage circuit to hold data. Storage unit 41 is connected to the sense amplifier section 20 and storage circuit 30 included in the storage circuit section 11. Storage unit 41 holds the data used in the computation block 14 by the sense amplifier section 20 and storage circuit 30. The data stored (held) by storage unit 41 is data corresponding to the weight parameters (weight data) used in the product sum operation of the neural network. By converting the weight data into digital data, a semiconductor device with strong noise immunity and high-speed operation can be realized. Alternatively, the weight data can also be analog data.

[0078] Component layer 40 includes an oxide semiconductor transistor (OS transistor) in a semiconductor layer having a channel formation region. Component layer 40, including the OS transistor, can be stacked on component layer 10. By disposing component layer 40 on component layer 10, the transistor density per unit area can be increased. Therefore, the storage capacity in a storage circuit including storage cell 41 disposed in component layer 40 can be increased.

[0079] Examples of metal oxides used in OS transistors include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide). In-Zn oxide can also be used as a metal oxide for OS transistors. Furthermore, the metal oxide preferably contains one or more selected from indium, element M, and zinc. Element M is selected from one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, element M is preferably selected from one or more selected from aluminum, gallium, yttrium, and tin.

[0080] Figure 1B This is a block diagram illustrating the readout amplifier section 20 and the storage circuit 30 included in the storage circuit section 11. Additionally, Figure 1B The driving circuit 71 for the output signal WEN and the driving circuit 72 for the output signal REN are shown. Signal WEN controls the writing of data to the readout amplifier section 20 and the storage circuit 30 included in the storage circuit section 11. Signal REN controls the reading of data from the readout amplifier section 20 and the storage circuit 30 included in the storage circuit section 11.

[0081] In the storage circuit section 11, the readout amplifier section 20 includes a plurality of readout amplifiers 21. The storage circuit 30 includes a plurality of storage cells 31. The storage cells 31 are sometimes referred to as first storage cells. The storage cells 41 disposed in the aforementioned component layer 40 are sometimes referred to as second storage cells.

[0082] Interface unit 12 based on the input write data W DATA The interface section 12 amplifies the potential of the bit line OBL and uses it as the read data R. DATA Output. Write data W DATA In addition to the weight data, there is also input data that is input into the calculation block 14 and used for product and sum operations with the weight data.

[0083] Bit line OBL is a wiring used for bidirectional data input and output between interface section 12 and sense amplifier 21. For example, by supplying data to bit line OBL from interface section 12 and activating the bit line pair (bit line BL) connecting sense amplifier 21 and memory cell 41, weighted data can be written to memory cell 41. Furthermore, bit line OBL can read output data through interface section 12 by selecting memory cell 31 that holds the output data obtained in operation block 14.

[0084] Bit line SBL is used for bidirectional data input and output between storage cell 31 and operation block 14. For example, by selecting storage cell 31 that holds weighted data, data can be output to operation block 14 via bit line SBL. In addition, by selecting the selected storage cell 31, output data obtained in operation block 14 can be stored in the storage cell.

[0085] When the input / output data on bit lines OBL and SBL is multi-bit, multiple wirings are also required. Note that bit line BL, which is connected to memory cell 41, is sometimes referred to as the first bit line. Bit line OBL, which is connected to memory cell 31, is sometimes referred to as the second bit line.

[0086] The sense amplifier 21 is connected to the memory cell 31 via bit line pairs (bit line BL and inverted bit line BLB) arranged in the Z direction. The sense amplifier 21 is configured close to the memory cell 31. The writing and reading of data in the sense amplifier 21 are controlled by drive circuits 71 and 72. Bit line BL and inverted bit line BLB are sometimes referred to as bit line pair BL-BLB. Similarly, bit line OBL and inverted bit line OBLB, and bit line SBL and inverted bit line SBLB are sometimes referred to as bit line pair OBL-OBLB and bit line pair SBL-SBLB, respectively.

[0087] Storage cell 31 can selectively update the stored data by choosing the weight data held in storage cell 41. Alternatively, storage cell 31 can select output data obtained in operation block 14 to update the stored data. Storage cell 31 is connected to storage cell 41 via a bit line pair BL-BLB positioned in the Z direction (parallel to the direction perpendicular to the substrate surface). Storage cell 31 is disposed close to sense amplifier 21. Storage cell 31 is connected to sense amplifier 21. The writing and reading of data in storage cell 31 are controlled by drive circuits 71 and 72.

[0088] Storage cell 31 uses a storage cell with high access speed. For example, storage cell 31 is preferably a storage cell of static random access memory (hereinafter, SRAM). Storage cell 31, which is configured near the operation block 14, is sometimes referred to as a note-type memory. The storage capacity of the storage circuit 30 including storage cell 31 is smaller than that of the storage circuit including storage cell 41, but the access speed is fast, so it is preferred as a memory for holding weighted data in operation block 14.

[0089] The controller unit 15 included in the computation block 14 is a circuit used to control the computational processing performed in the computation block 14. The product sum operation unit 16 included in the computation block 14 is a circuit used to perform product sum operation processing on the weight data input to the computation block 14. The activation function operation unit 17 included in the computation block 14 is a circuit used to process the results obtained in the product sum operation unit 16 within the computation block 14 using activation functions such as the normalized linear function (ReLU). The data conversion unit 18 included in the computation block 14 is a circuit used to perform data conversion for preprocessing based on the results obtained in the activation function operation unit 17 within the computation block 14. The load storage unit 19 included in the computation block 14 is a circuit used to input or output data for the computational processing performed within the computation block 14.

[0090] Thus, in the semiconductor device 100, the computation block 14 is composed of circuitry specifically designed for neural network computation. By employing this structure, the power consumption required for computation can be reduced compared to performing the same computation in general-purpose computing circuits such as CPUs and GPUs.

[0091] Figure 2 It is used to explain Figure 1A and Figure 1B A schematic diagram illustrating the operation of a semiconductor device 100 according to one aspect of the present invention. Figure 2 The diagram illustrates the data held in storage unit 41 that cycles according to the clock, the data held in storage unit 31, the operation processing in product summation unit 16, the operation processing in activation function operation unit 17, the operation processing in data conversion unit 18, and the input or output processing of data in loading storage unit 19.

[0092] As described above, the storage circuit including storage unit 41 has a large storage capacity. Storage unit 41 can hold more data than storage unit 31. Figure 2 In this context, data OS_1 to OS_N (where N is an integer greater than or equal to 2) are shown as such data. Data OS_1 to OS_N are data pre-stored in storage unit 41 before the semiconductor device 100 performs operations. The data held in storage unit 41 is also used as a cache for the data held in storage unit 31.

[0093] At time T01, data is transferred from storage unit 41 to storage unit 31. Figure 2In this process, data SR1 is shown as data transmitted to storage unit 31. Data SR1 is data equivalent to the weight data used in operation block 14. Then, operation processing MAC1 is performed in the product sum operation unit 16, in which the product sum operation of the input data input to operation block 14 and data SR1 is performed. Then, operation processing AF1 is performed on the data obtained in operation processing MAC1 in the activation function operation unit 17. Then, operation processing DC1 is performed on the data obtained in operation processing AF1 in the data conversion unit 18. Then, input or output processing LS1 is performed on the data obtained in operation processing DC1 in the load storage unit 19.

[0094] After time T01, data SR2 to SR9 required for operation block 14 are read from storage unit 41 to storage unit 31. The following is as follows... Figure 2 As shown, the pipelined processing performs operations MAC2 to MAC8, AF2 to AF7, DC2 to DC6, and LS2 to LS5.

[0095] Storage unit 41 is capable of holding a large amount of data equivalent to the weighted data. Therefore, storage unit 41 can store the data required by storage unit 31. Storage unit 31 can update the data SR1 to SR9 required by the computation block 14 based on the data held by storage unit 41 without accessing external storage circuitry. Therefore, a semiconductor device that operates at high speed, consumes low power, can hold a large amount of data, and can perform a series of computational processes required by AI technology can be provided.

[0096] Furthermore, the data stored in storage unit 41 and the data stored in storage unit 31 can be rewritten separately. For example, as... Figure 2 As shown, the held data can be rewritten from data OS_2 to data OS_2x using time sequence T02. Additionally, for example, as... Figure 2 As shown, the held data can be rewritten from data OS_1 to data OS_1x using time sequence T03. Additionally, for example, as... Figure 2 As shown, data can be retained for the OS_N specified period without rewriting.

[0097] According to one aspect of the present invention, a semiconductor device has a structure in which a plurality of sense amplifiers 21 and a plurality of memory cells 31 are arranged directly below a memory cell 41. Therefore, the memory cells 41, sense amplifiers 21, and memory cells 31 can be arranged close to each other, thereby enabling high-speed updates of the data held in the memory cells 31 without accessing external memory circuitry. Furthermore, the memory cells 31 with high access speeds can be arranged near the arithmetic block 14, thereby enabling bidirectional data input and output between the memory cells 31 and the arithmetic block 14. Therefore, near-memory computation can be achieved, thereby reducing the power consumption required for data transfer between circuits.

[0098] Figure 3A This is a schematic diagram illustrating an example of the structure of memory cell 41, readout amplifier 21, and memory cell 31. Figure 3A Shown in Figure 1B The structure described above the area containing the readout amplifier 21 and the memory cell 31 is a component layer 40 including the memory cell 41. Note that, to improve visibility, in Figure 3A The memory cell 41 on the readout amplifier 21 is omitted.

[0099] Storage cell 41 is connected to sense amplifier 21 and storage cell 31 via bit line pair BL-BLB. Sense amplifier 21 is connected to bit line OBL (bit line pair). Storage cell 31 is connected to bit line SBL (bit line pair).

[0100] Figure 3B It is used to explain Figure 1A The schematic diagram shown depicts transistor 53 disposed in component layer 10 and transistor 51 disposed in component layer 40, representing a stacked component layer 10. Additionally, Figure 3B Show connection Figure 3A The bit line pair BL-BLB of memory cell 41, sense amplifier 21 and memory cell 31 are shown.

[0101] The semiconductor layer 52 included in transistor 51 is made of oxide semiconductor (metal oxide), thereby forming the memory cell 41 composed of OS transistors as described above.

[0102] By using silicon as the semiconductor layer 54 included in the transistor 53, a readout amplifier 21 and a memory cell 31 can be provided in the element layer 10 composed of the aforementioned Si transistors.

[0103] By placing the component layer 40 containing the memory cell 41 on the component layer containing the sense amplifier 21 and the memory cell 31, the number of memory circuits per unit area, i.e., the storage capacity, can be increased compared to placing the memory cell 41, sense amplifier 21, and storage cell 31 on the same layer. By increasing the storage capacity, the number of times the external storage device transfers the data required for computation to the semiconductor device can be reduced, thereby achieving low power consumption.

[0104] When the storage circuits such as storage cell 41 and storage cell 31 are made of different chips, the bus width is limited by the number of pins on the chip. On the other hand, as shown in one embodiment of the present invention, in a structure where storage cells 41 and 31 are stacked, the number of parallel data required for computation can be increased by setting the openings of the bit lines to the BL-BLB, thereby enabling efficient computation.

[0105] exist Figure 4A In the middle, as Figure 3A The schematic diagram shows the sense amplifier 21, which includes sense amplifiers 21_P and 21_Q, as... Figure 3A The schematic diagram shows storage cells 31_P and 31_Q. Additionally, as... Figure 3A The schematic diagram shows a storage cell 41, which includes a component layer 40 comprising storage cells 41P and 41Q.

[0106] The sense amplifiers 21_P and 21_Q are connected to the bit lines OBL_P and OBL_Q, respectively. When the interface section 12 is connected to the sense amplifiers 21_P and 21_Q through multiple bit lines OBL_P and OBL_Q, different data can be written or read in the same timing sequence.

[0107] Storage cells 31_P and 31_Q are connected to bit lines SBL_P and SBL_Q, respectively. When the operation block 14 is connected to storage cells 31_P and 31_Q through multiple bit lines SBL_P and SBL_Q, different data can be written or read out in the same timing sequence.

[0108] Storage cell 41P is connected to bit line pairs BL_P and BLB_P. Storage cell 41Q is connected to bit line pairs BL_Q and BLB_Q. Preferably, bit line pairs BL_P and BLB_P are not connected to bit line pairs BL_Q and BLB_Q. By adopting this structure, the sense amplifiers 21_P and 21_Q, as well as storage cells 31_P and 31_Q, can perform different weighted data writing and reading, or weighted data operation processing.

[0109] Figure 4B This is an explanation Figure 4AThe diagram shows the bit line BL_V connecting sense amplifier 21_P and memory cells 31_P and 41P, and sense amplifier 21_Q and memory cells 31_Q and 41Q. Bit line BL_V is as follows... Figure 4A and Figure 4B The bit line shown is set in the Z direction (a direction parallel to the direction perpendicular to the substrate surface).

[0110] in addition, Figure 4B This diagram shows bit lines BL_LD and BL_RD connected to bit line BL_V and disposed in element layer 40. The lengths of bit lines BL_LD and BL_RD are preferably the same. That is, it is preferable to position the opening for bit line BL_V near the center of bit line BL in element layer 40. By employing this structure, the distances between the sense amplifier 21 and the memory cell 31 and the memory cell 41 can be made equal, thereby making the parasitic capacitances between bit line pairs BL-BLB equal.

[0111] Figure 5A The semiconductor device 100A shown is Figure 3A A modified example of the semiconductor device 100 shown. Figure 5A The diagram shown illustrates that Figure 3A The component layer 40 is set up as multiple component layers 40_1 and 40_2 stacked together.

[0112] Figure 5A The semiconductor device 100A shown includes element layers 40_1 and 40_2, each configured with a plurality of memory cells 41. By employing this structure, the same manufacturing process using the same photomask can be used in the plurality of element layers 40_1 and 40_2. Therefore, the same manufacturing process can be reused in the vertical direction to manufacture the memory cells 41, thereby reducing manufacturing costs.

[0113] Figure 5B It is set to include Figure 5A The diagram shows component layers 40_1 to 40_n (n is an integer of 2 or more) of component layers 40_1 and 40_2. Additionally, Figure 5B Show connection Figure 5A The bit line pair BL-BLB of memory cell 41, sense amplifier 21, and memory cell 31 are shown. Figure 5B As shown, in the semiconductor device 100A, multiple element layers 40_1 to 40_n are stacked in a direction perpendicular or substantially perpendicular to the surface of the element layer 10. By adopting this structure, the number of memory cells 41 disposed per unit area can be increased. Therefore, the storage capacity of the memory circuit composed of memory cells 41 can be increased.

[0114] exist Figure 5BIn this structure, the number of memory cells 41 connected to the bit line pairs BL-BLB can be increased while the length of the bit line pairs BL-BLB connecting the memory cells 41, the sense amplifier 21, and the memory cells 31 can be shortened. By stacking the component layer 40, the wiring distance can be shortened, and the parasitic capacitance generated between the bit line pairs BL-BLB can be reduced, thereby achieving low power consumption. In addition, the number of bits of weighted data can be increased while reading the weighted data from the memory cells 41 to the sense amplifier 21 at high speed.

[0115] (Structure example of storage unit 41)

[0116] Next, an example of a circuit structure that can be used as a memory cell 41 will be described. Alternatively, memory cell 41 can be a memory cell including an OS transistor. A memory that includes a memory cell with an OS transistor is sometimes referred to as an "OS memory".

[0117] The off-state current of the OS transistor is extremely small. Therefore, the charge corresponding to the data written to the memory cell 41 can be maintained for a long time. In other words, the written data can be retained in the memory cell 41 for a long time. Therefore, the frequency of data refresh can be reduced, thereby reducing the power consumption of the semiconductor device according to one aspect of the present invention.

[0118] Figure 6A This is a diagram illustrating a memory cell array 42 that includes multiple memory cells 41. Figure 6A The diagram shows word lines WL_1 to WL_m and bit lines BL_1 to BL_n arranged side-by-side in an m-row, n-column configuration (m and n are natural numbers greater than 2). It also shows memory cells 41 connected to each word line WL and bit line BL. Furthermore, signals supplied to the word lines and bit lines to drive the memory cells 41 can be obtained from... Figure 1B The outputs of drive circuit 71 and drive circuit 72 are shown.

[0119] Figure 6B This is a circuit diagram illustrating an example of a circuit structure that can be applied to memory cell 41. Memory cell 41 includes a transistor M1 and a capacitor C1 (also called a capacitor). Transistor M1 is connected to word line WL, bit line BL, and capacitor C1. Additionally, capacitor C1 is connected to wiring PL, which serves as a capacitor line. For example, wiring PL is input to ground potential GND (the low-level power supply potential). Furthermore, Figure 6C It corresponds to Figure 6B The circuit block of the circuit diagram.

[0120] Figure 6BThe shown memory cell 41 can be a 1T1C type DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) memory cell. DOSRAM is RAM that includes 1T (transistor) 1C (capacitor) type memory cells. DOSRAM is DRAM formed using OS transistors, and DOSRAM is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current characteristic of OS transistors. DOSRAM is a 1T1C type memory cell, so a memory cell array 42 with a large storage capacity can be realized. Furthermore, by using OS transistors, the data retention period can be extended compared to DRAM that includes Si transistors.

[0121] The circuit structure that can be used in storage cell 41 is not limited to Figure 6B The 1T1C type DOSRAM. For example. Figure 7A Other structural examples of 1T1C type memory cells that can be used as DOSRAM are shown. Figure 7A The storage cell 41A shown is Figure 6B The difference in the shown memory cell 41 is that, in the former, transistor M1 is an OS transistor including a back gate connected to wiring BGL. By including wiring BGL, transistor M1 can be a transistor with improved electrical characteristics.

[0122] The storage cell 41, including the OS transistor, can be a NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory). NOSRAM storage cells are dual-transistor (2T) or three-transistor (3T) gain cells. NOSRAM rewrites data using the charging and discharging of capacitors, thus theoretically having no limit on the number of write cycles and low energy consumption. Therefore, NOSRAM is a high-speed, low-power, and highly write-resistant memory. Furthermore, NOSRAM allows for non-destructive reading of written data, making it suitable for long-term data retention.

[0123] Figure 7B The illustrated memory cell 41B is a circuit equivalent to a 2T type NOSRAM. Memory cell 41B includes transistor M1, transistor M2, and capacitor C1. Transistors M1 and M2 are the write transistor and read transistor, respectively. Transistors M1 and M2 can be OS transistors with semiconductor layers arranged in different layers, or OS transistors with semiconductor layers arranged in the same layer. Memory cell 41B is shown as an example connected to the write bit line WBL, the read bit line RBL, the write word line WWL, the read word line RWL, and the wiring SL.

[0124] Figure 7C The shown memory cell 41C is a circuit equivalent to a 3T type NOSRAM. Memory cell 41C includes transistors M1, M2, and M3, and a capacitor C1. Transistors M1, M2, and M3 are the write transistor, read transistor, and select transistor, respectively. By employing a structure including transistor M3, the current flowing between the source line and the read bit line RBL can be more reliably blocked regardless of the conduction state of transistor M2. Transistors M1, M2, and M3 can be OS transistors with semiconductor layers disposed on different layers, or OS transistors with semiconductor layers disposed on the same layer.

[0125] Since the write transistor is composed of an OS transistor, the charge corresponding to the data can be maintained by turning off the write transistor. Therefore, memory cells 41B and 41C do not consume power while holding data. Thus, memory cells 41B and 41C can be used as low-power memory cells capable of holding data for extended periods. Note that the gate of the read transistor serves as a node for holding the charge corresponding to the data. The read transistor is a transistor that allows current to flow according to the potential of the node holding the charge corresponding to the data. The select transistor is a transistor that controls the current flowing through the read transistor.

[0126] Figure 7D Other structural examples of the 2T type gain unit are shown. Figure 7D The storage cell 41D shown is Figure 7B The difference in the shown memory cell 41B is that, in the former, transistors M1 and M2 are both OS transistors including a back gate, and this back gate is connected to the wiring BGL. For example, the wiring BGL is input to ground potential GND (low-level side power supply potential). By including the wiring BGL, transistors M1 and M2 can be transistors with improved electrical characteristics.

[0127] Figure 7E Other structural examples of the 3T type gain unit are shown. Figure 7E The storage cell 41E shown is Figure 7C The difference in the shown memory cell 41C is that, in the former, transistors M1, M2, and M3 are all OS transistors including a back gate, and this back gate is connected to the wiring BGL. For example, the wiring BGL is input to ground potential GND (low-level side power supply potential). By including the wiring BGL, transistors M1, M2, and M3 can be transistors with improved electrical characteristics.

[0128] Figure 7F Other structural examples of the 2T type gain unit are shown. Figure 7F The storage cell 41F shown is Figure 7BThe difference in the shown memory cell 41B is that, in the former, capacitor C1 is omitted by using the gate capacitance of the read transistor; and wiring SL is omitted. By omitting capacitor C1, miniaturization of the semiconductor device can be achieved.

[0129] Figure 7F The transistors M1 and M2 included in the 2T-type gain unit shown are preferably vertical transistors, where the source and drain electrodes are located at different heights. In a vertical transistor, current flows along the height direction (Z direction) of the channel formation region of the semiconductor layer. In other words, the channel length direction can be said to include a component in the height direction (vertical direction). Therefore, the above-mentioned vertical transistor can also be called VFET (Vertical Field Effect Transistor), vertical channel transistor, or vertical transistor, etc.

[0130] Compared to lateral transistors (also known as planar transistors or planar structures) where the source and drain electrodes are at the same height, vertical transistors have a structure in which at least a portion of the source region, channel formation region, and drain region overlap when viewed from a plane, thus reducing the occupied area (also known as the footprint). Furthermore, because they have a structure that allows for a shorter channel length and a wider channel width, the on-state resistance can be reduced (and the on-state current increased).

[0131] Figure 7G Other structural examples of the 3T type gain unit are shown. Figure 7G The storage cell 41G shown is Figure 7C The difference in the memory cell 41C shown is that, in the former, capacitor C1 is omitted by using the gate capacitor of the read transistor; and wiring PL is omitted. Figure 7G The transistors M1, M2, and M3 included in the 3T-type gain unit shown can reduce the occupied area (also known as the footprint area) and reduce the on-state resistance (increase the on-state current) by using vertical transistors with the source and drain electrodes located at different heights.

[0132] (Example of the structure of readout amplifier 21)

[0133] An example of the circuit structure of the readout amplifier 21 is explained. Figure 8A This is the circuit diagram of readout amplifier 21. Figure 8B The circuit blocks corresponding to this circuit diagram are shown. Additionally, Figure 8C Show combination Figure 6C The circuit block of the storage cell 41 shown is... Figure 8B The circuit block structure of the readout amplifier 21 is shown as an example.

[0134] Figure 8A The sense amplifier 21 shown includes an amplification circuit 61, a precharge circuit 62, a precharge circuit 63, and a switching circuit 64. The amplification circuit 61, the precharge circuit 62, the precharge circuit 63, and the switching circuit 64 are respectively connected to bit line pairs BL-BLB. Additionally, the signal used to drive the sense amplifier 21 can be obtained from... Figure 1B The outputs of drive circuit 71 and drive circuit 72 are shown.

[0135] Amplifier circuit 61 has the function of supplying a predetermined potential to the bit line BL to output a potential corresponding to one of the two data values ​​and to the inverted bit line BLB to output a potential corresponding to the other of the two data values ​​by supplying a predetermined potential to the wiring SAP and wiring SAN. Amplifier circuit 61 includes transistors 61_1, 61_2, 61_3, and 61_4. Transistors 61_1 and 61_2 are both p-channel transistors. Transistors 61_3 and 61_4 are both n-channel transistors. Transistors 61_1 and 61_3 form an inverter circuit with the inverted bit line BLB as input, the bit line BL as output, the wiring SAP as a high-potential power supply line, and the wiring SAN as a low-potential power supply line. Transistors 61_2 and 61_4 form an inverter circuit with the bit line BL as input, the inverted bit line BLB as output, the wiring SAP as a high-potential power supply line, and the wiring SAN as a low-potential power supply line.

[0136] The pre-charge circuit 62 has the function of pre-charging the bit line pair BL-BLB to potential VPRE according to the signal EQB. Specifically, the pre-charge circuit 62 includes transistors 62_1, 62_2, and 62_3. Transistors 62_1, 62_2, and 62_3 are all p-channel transistors. Transistor 62_1 has the function of turning the bit line pair BL-BLB into an on or off state according to the signal EQB. Transistor 62_2 has the function of pre-charging the bit line BL to potential VPRE according to the signal EQB. Transistor 62_3 has the function of pre-charging the inverted bit line BLB to potential VPRE according to the signal EQB.

[0137] The pre-charge circuit 63 has the function of pre-charging the bit line pair BL-BLB to potential VPRE according to the signal EQ. Specifically, the pre-charge circuit 63 includes transistors 63_1, 63_2, and 63_3. Transistors 63_1, 63_2, and 63_3 are all n-channel transistors. Transistor 63_1 has the function of turning the bit line pair BL-BLB into an on or off state according to the signal EQ. Transistor 63_2 has the function of pre-charging the bit line BL to potential VPRE according to the signal EQ. Transistor 63_3 has the function of pre-charging the inverted bit line BLB to potential VPRE according to the signal EQ.

[0138] The switching circuit 64 has the function of turning the bit line pair BL-BLB and bit line OBL (bit line pair OBL-OBLB) into an on or off state according to the column selection signal CSE. Specifically, the switching circuit 64 includes transistors 64_1 and 64_2. Both transistors 64_1 and 64_2 are n-channel transistors. Transistor 64_1 has the function of turning the bit line pair BL-BLB and bit line BL and bit line OBL into an on or off state according to the column selection signal CSE. Transistor 64_2 has the function of turning the bit line pair BL-BLB and bit line pair OBL-OBLB into an on or off state according to the column selection signal CSE.

[0139] Figure 8B Showing the corresponding Figure 8A The circuit block of the circuit diagram for the readout amplifier 21 is shown below. Additionally, Figure 8C Show combination Figure 8B The circuit block of the readout amplifier 21 shown is... Figure 6C The diagram shows an example of the structure of the circuit block of the storage unit 41.

[0140] exist Figures 8A to 8C In the structure of the sense amplifier 21 shown, by reading data from the memory cell 41, the potential difference between the bit line BL and the inverted bit line BLB, which varies according to the charge held in the memory cell 41, can be amplified, and output to the bit line pair OBL-OBLB according to the column select signal CSE. Furthermore, in Figures 8A to 8C In the structure of the sense amplifier 21 shown, the amplified potential difference can be written into the memory cell 41 connected to the bit line pair BL-BLB by applying the potential difference of the bit line pair OBL-OBLB to the bit line pair BL-BLB according to the column select signal CSE.

[0141] (Structure example of storage unit 31)

[0142] The circuit structure of the memory cell that can be used as memory cell 31 is described. Furthermore, memory cell 31 is a memory cell including Si transistors. As described above, memory cell 31 is a memory cell that can be used for high-speed access to SRAM. Memory cell 31 is particularly preferably a memory cell of multi-port SRAM.

[0143] Figure 9A An example of a storage cell that can be used as storage cell 31 in a multi-port SRAM is shown.

[0144] Figure 9AThe diagram shows a memory cell 31A comprising transistors M1A, M1B, M6A, M6B, inverters INV1 and INV2, bit lines BL and SBL, inverted bit lines BLB and SBLB, and word lines WL1 and WL2. Additionally, signals used to drive the memory cell 31A can be derived from... Figure 1B The outputs of drive circuit 71 and drive circuit 72 are shown.

[0145] Figure 9A The bit lines BL and BLB shown correspond to the bit line pair BL-BLB connected to the aforementioned memory cell 41 and sense amplifier 21. Furthermore, bit lines SBL and SBLB correspond to the bit line pair SBL connected to the aforementioned operational block 14. Word line WL1 is used to control the writing of data supplied to the bit line pair BL-BLB to memory cell 31A and the reading of data held in memory cell 31A from the bit line pair BL-BLB. Word line WL2 is used to control the writing of data supplied to the bit line pair SBL connected to operational block 14 to memory cell 31A and the reading of data held in memory cell 31A from the bit line pair SBL connected to operational block 14.

[0146] Figure 9B An example of a memory cell that can be used as a multi-port SRAM for memory cell 31 is shown. Additionally, signals used to drive memory cell 31B can be derived from... Figure 1B The outputs of drive circuit 71 and drive circuit 72 are shown.

[0147] Figure 9B The diagram shows a memory cell 31B including transistors M1A, M6A, M7, M8, inverters INV1 and INV2, bit line BL, inverted bit line BLB, bit line SBL, and word lines WL1 and WL2.

[0148] Figure 9B The bit line BL and the inverted bit line BLB shown correspond to the bit line pair BL-BLB connected to the aforementioned memory cell 41 and sense amplifier 21. Furthermore, the bit line SBL corresponds to the bit line SBL connected to the aforementioned operational block 14. Word line WL1 is used to control the writing of data supplied to the bit line pair BL-BLB to the memory cell 31B and the reading of data held in the memory cell 31B from the bit line pair BL-BLB. Word line WL2 is used to control the reading of data held in the memory cell 31B from the bit line SBL connected to the operational block 14.

[0149] In one embodiment of the invention, it is preferred to be as follows: Figure 9AThe multi-port SRAM shown allows for separate control of data writing and reading from storage cell 31. This structure improves the access speed from the operational block 14 to the data held in storage cell 31 and allows for rewriting of data in storage cell 31 based on the large amount of data held in storage cell 41.

[0150] As explained above, a semiconductor device according to one aspect of the present invention has a structure in which a plurality of sense amplifiers 21 and a plurality of memory cells 31 are arranged directly below memory cell 41. Therefore, the memory cell 41, sense amplifiers 21, and memory cell 31 can be arranged close to each other, thereby enabling high-speed updates of the data held in memory cell 31. Furthermore, the memory cell 31 with high access speed is arranged near the arithmetic block 14. Therefore, near-memory computation can be implemented, thereby reducing the power consumption required for data transfer between circuits.

[0151] The configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments, etc.

[0152] (Implementation Method 2)

[0153] In this embodiment, an example of a product and arithmetic unit of a semiconductor device that can be used in one aspect of the present invention will be described.

[0154] <Example of the structure of the product summation unit>

[0155] Figure 10A This describes what can be used as the above-described embodiment 1. Figure 1A A block diagram illustrating an example structure of the product sum operation unit 16A in the semiconductor device 100.

[0156] The product and arithmetic unit 16A includes an arithmetic circuit MAC1 and an analog-to-digital conversion circuit 79.

[0157] The arithmetic circuit MAC1 has the function of converting digital signal D IND It converts the data into an analog signal, performs a product operation between the first data (e.g., weighted data) and the second data (e.g., input data), and outputs an analog signal D corresponding to the product operation. MACA The function.

[0158] The analog-to-digital converter circuit 79 has the following function: converting the analog signal D output by the arithmetic circuit MAC1 into digital signal D. MACA Converted to digital signal D MACD It transmits and receives signals with the other circuits (controller unit 15, activation function calculation unit 17, data conversion unit 18, and loading storage unit 19) included in the storage circuit unit 11 and the arithmetic block 14.

[0159] The operational circuit MAC1 includes the input circuit WCS, the input circuit XCS, the control circuit WSD, and the cell array CA.

[0160] The arithmetic circuit MAC1 is a circuit that performs a product and sum operation on the first data (weighted data) corresponding to the potential held by each unit and the second data (input data) that is input. Furthermore, the first data and the second data can be, for example, analog data or multi-valued data (discrete data).

[0161] The input circuits WCS and XCS convert first and second data from externally supplied digital signals into first and second data from analog signals and supply them to the unit included in the arithmetic circuit MAC1 for performing product summation. Additionally, the control circuit WSD outputs a signal controlling the unit included in the arithmetic circuit MAC1 for performing product summation.

[0162] Figure 10B This refers to the implementation method 1 described above. Figure 1A The product summation unit 16 in the structure of the semiconductor device 100 described herein is replaced with... Figure 10A Block diagram of the semiconductor device 100A of the product summation unit 16A described herein.

[0163] The analog-to-digital conversion circuit 79, the input circuit WCS, the input circuit XCS, and the control circuit WSD are circuits located in the component layer 10.

[0164] The cell array CA is a circuit that can be disposed in the same element layer (represented as element layer 40A in the drawings) as the element layer 40 including the memory cell 41 described in Embodiment 1 above. That is, the transistors in the plurality of cells included in the cell array CA can be OS transistors. Therefore, the cell array CA can be disposed on the upper layer of the area where the analog-to-digital converter circuit 79, the input circuit WCS, the input circuit XCS, and the control circuit WSD included in the element layer 10 are disposed. As a result, the cell array CA, the analog-to-digital converter circuit 79, the input circuit WCS, the input circuit XCS, and the control circuit WSD can be arranged close together, thereby reducing the power consumption required for signal input and output.

[0165] The off-state current of an OS transistor is extremely small. Therefore, a cell using an OS transistor can be a cell that holds the first bit of analog data. A cell array CA can hold multiple bits of digital data as analog values. Furthermore, low power consumption can be achieved in a cell array CA by performing a product-sum operation utilizing subthreshold current.

[0166] <Example of the structure of the operational circuit MAC1>

[0167] Figure 11 An example of the structure of the arithmetic circuit MAC1, which performs the product of the first data and the second data, is shown. In addition to the aforementioned input circuits WCS, XCS, WSD, and cell array CA, the arithmetic circuit MAC1 also includes circuits SWS1 and SWS2.

[0168] <<Cellular Array CA>>

[0169] Here, a specific example of a cell array (CA) is explained.

[0170] The cell array CA includes cells 91_1, 1 to 91_m, n and cells 81_1 to 81_m. For example, cells 91_1, 1 to 91_m, n each include transistor 92, transistor 93, transistor 94 and capacitor 95. For example, cells 81_1 to 81_m each include transistor 82, transistor 83, transistor 84 and capacitor 85. Note that in the following description, "one of the source and drain" is sometimes referred to as "first terminal" and "the other of the source and drain" is sometimes referred to as "second terminal". Additionally, in the following description, "one electrode" of the capacitor is sometimes referred to as "first terminal" and "the other electrode" is sometimes referred to as "second terminal".

[0171] like Figure 11 As shown, the transistors and capacitors included in units 91_1,1 to 91_m,n and units 81_1 to 81_m are connected to at least one of the wirings WSL_1 to WSL_m (wiring WSL), wirings XCL_1 to XCL_m (wiring XCL), wiring VBL, wirings WCL_1 to WCL_n (wiring WCL) and wiring supplying ground potential.

[0172] exist Figure 11 In unit 91_1,1, the connection portion of the first terminal of transistor 92, the gate of transistor 94, and the first terminal of capacitor 95 is represented as node NN_11. Similarly, in Figure 11 In units 91_1,n, 91_m,1, and 91_m,n, the same connection parts are represented as nodes NN_1n, NN_m1, and NN_mn. Similarly, in Figure 11 In elements 81_1 and 81_m, the same connection portion is represented as nodes NN_ref1 and NNref_m. Note that nodes NN_11 to NN_mn and nodes NNref_1 to NNref_m are used as the hold nodes (nodes NN and NNref) of each element.

[0173] Unit 81 (units 81_1, 1 and 81_m) has the function of allowing a current set during data writing and reading to flow through and perform the operations of unit 91 (units 91_1, 1 to 91_m, n). Specifically, unit 81 has the following functions: when writing data, a reference current flows through it to maintain a reference voltage within unit 81; and when reading data, it causes the current corresponding to the input data (X) supplied to unit 91 to flow through unit 81, thereby controlling the current flowing through unit 91.

[0174] The connection relationships within unit 81 will be explained.

[0175] The gate of transistor 82 is connected to wiring WSL. One of the sources and drains of transistor 82 is connected to one of the sources and drains of transistor 83 and wiring XCL. The other of the sources and drains of transistor 82 is connected to the gate of transistor 84 and one electrode of capacitor 85. When writing data, transistor 82 is turned on, and the reference voltage is written to the holding node (gate of transistor 84) in cell 81, turning it off, thereby holding the reference voltage in cell 81.

[0176] The gate of transistor 83 is connected to wiring VBL. The back gate of transistor 83 is connected to the other of the source and drain of transistor 84. One of the source and drain of transistor 83 is connected to one of the source and drain of transistor 82 and wiring XCL. The other of the source and drain of transistor 83 is connected to one of the source and drain of transistor 84. Transistor 83 makes the potential of one of the source and drain of transistor 84 the potential corresponding to the gate potential of transistor 83.

[0177] The gate of transistor 84 is connected to the other of the source and drain of transistor 82 and one electrode of capacitor 85. Note that the holding node connecting the gate of transistor 84, the other of the source and drain of transistor 82, and one electrode of capacitor 85 can be set to a potential corresponding to the current flowing through transistor 84. The back gate of transistor 84 is connected to the other of the source and drain of transistor 84. The other of the source and drain of transistor 84 is connected to a wiring supplying a low power supply potential (e.g., ground potential). This ground potential wiring is used to allow current to flow between the source and drain of transistor 84. The other of the source and drain of transistor 84 is connected to the back gate of transistor 83 and the back gate of transistor 84. Since the back gates of transistor 83 and 84 are supplied with a fixed potential, the transistor characteristics of transistors 83 and 84 are stabilized. Transistor 84 allows an output current corresponding to the gate potential of transistor 84 to flow through the other of its source and drain.

[0178] One electrode of capacitor 85 is connected to the source and drain of transistor 82 and the gate of transistor 84. The other electrode of capacitor 85 is connected to wiring XCL. Capacitor 85 has the function of changing the potential of one electrode according to the potential change of the other electrode when one electrode is in a floating state.

[0179] When writing data, unit 91 functions to allow a current corresponding to the weight data (W) held in unit 91 to flow through it, while maintaining a voltage corresponding to that current internally. Furthermore, when reading data, unit 91 functions to boost the voltage held during data writing based on the current flowing through unit 81, thereby allowing a current corresponding to the operation between the weight data and the input data to flow through it. Sometimes the weight data is referred to as the first data, and the input data as the second data. Note that the weight data, for example, is data corresponding to the weight parameters used in the product summation operation of an artificial neural network (weight data).

[0180] The connection relationships within unit 91 will be explained.

[0181] The gate of transistor 92 is connected to wiring WSL. One of the sources and drains of transistor 92 is connected to one of the sources and drains of transistor 93 and wiring WCL. The other source and drain of transistor 92 is connected to the gate of transistor 94 and one electrode of capacitor 95. When writing data, transistor 92 is turned on to write the voltage corresponding to the weighted data into cell 91, and then turned off to maintain the voltage corresponding to the weighted data within cell 91.

[0182] The gate of transistor 93 is connected to wiring VBL. The back gate of transistor 93 is connected to the other of the source and drain of transistor 94. One of the source and drain of transistor 93 is connected to one of the source and drain of transistor 92 and wiring WCL. The other of the source and drain of transistor 93 is connected to one of the source and drain of transistor 94. Transistor 93 makes the potential of one of the source and drain of transistor 94 the potential corresponding to the gate potential of transistor 93.

[0183] The gate of transistor 94 is connected to the other of the source and drain of transistor 92 and one electrode of capacitor 95. The back gate of transistor 94 is connected to the other of the source and drain of transistor 94. The other of the source and drain of transistor 94 is connected to a wiring supplying a low power supply potential (e.g., ground). This ground-supply wiring is used to allow current to flow between the source and drain of transistor 94. The other of the source and drain of transistor 94 is connected to the back gate of transistor 93 and the back gate of transistor 94. Because the back gates of transistors 93 and 94 are supplied with a fixed potential, the transistor characteristics of transistors 93 and 94 are stabilized. Transistor 94 allows an output current corresponding to the gate potential of transistor 94 to flow through the other of its source and drain.

[0184] One electrode of capacitor 95 is connected to the source and drain of transistor 92 and the gate of transistor 94. The other electrode of capacitor 95 is connected to wiring XCL. When one electrode of capacitor 95 is in a floating state, the potential of one electrode changes according to the potential change of the other electrode.

[0185] Next, the transistors included in units 81 and 91 will be described.

[0186] Unless otherwise specified, transistors 84 and 94 operate in the subthreshold region. The drain current Id of the transistors operating in the subthreshold region can be represented by equation (1).

[0187] [Equation 1]

[0188] In formula (1), I0 represents V g =V th Drain current at time, q represents elementary charge, V g V represents the gate voltage. th The threshold voltage is represented by η, which is a coefficient determined by factors such as device structure, and k is the threshold voltage. B Let represent the Boltzmann constant, and T represent the temperature. As shown in equation (1), the drain current Id of the transistor operating in the subthreshold region is independent of the drain voltage. The current flowing through transistors 84 and 94 is the current flowing when operating in the subthreshold region. The current in the subthreshold region of transistors 84 and 94 can reduce the influence of drain voltage deviation. Therefore, the accuracy of the data obtained through calculation can be improved.

[0189] In this specification, the subthreshold region refers to the region in a graph showing the gate voltage (Vg) vs. drain current (Id) characteristics of a transistor where the gate voltage is below the threshold voltage. Furthermore, the subthreshold region refers to the region through which current flows, deviating from the gradually varying channel approximation (a model considering only drift current), accompanied by carrier diffusion. Additionally, the subthreshold region refers to the region where the drain current increases exponentially with respect to an increase in gate voltage. Furthermore, the subthreshold region includes regions that can be considered as described above.

[0190] Furthermore, the drain current of a transistor operating in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with respect to the gate voltage, independent of the drain voltage. In circuits using subthreshold current, the effects of drain voltage non-uniformity can be reduced.

[0191] Furthermore, transistors 92 and 82 have the function of maintaining the potential of the gates of transistors 84 and 94 by turning them off. Specifically, they have the function of maintaining the potential corresponding to the data supplied to the gate of transistor 94 via transistor 92. For example, transistors 92 and 82 are preferably OS transistors.

[0192] When the OS transistor is in the off state, the current flowing between its source and drain is extremely small. By using the OS transistor as transistor 92 and / or transistor 82, the leakage current of transistor 92 and / or transistor 82 can be suppressed, thereby reducing the power consumption of the semiconductor device 100. Specifically, the potential changes maintained by the gates of transistor 84 and 94 can be made very small, thus reducing the refresh operation of this potential. Furthermore, reducing the refresh operation can reduce the power consumption of the semiconductor device 100. In addition, by making the leakage current from the holding node to the wiring WCL or XCL very small, the cell can maintain the potential of the holding node for a longer period of time.

[0193] When the gate voltage of the OS transistor is less than the threshold voltage of the transistor, the channel width of 1μm can be less than 1×10⁻⁶. -20 A. Less than 1×10 -22 A or less than 1×10 -24 A very small drain current flows through it. Furthermore, when the gate voltage of the OS transistor is equal to the transistor's threshold voltage, a channel width of 1 μm can be reduced to 1.0 × 10⁻⁶. -8 Below A, 1.0×10 -12 A or below or 1.0 × 10 -15A drain current of A or less flows through it. Therefore, the OS transistor can allow different magnitudes of subthreshold current to flow within a range of gate voltages operating in the subthreshold region. In other words, the OS transistor can expand the range of gate voltages operating in the subthreshold region. Specifically, when the threshold voltage of the OS transistor is V... th In the case of subthreshold regions, it is possible to utilize (V) th -1.0V and above and V th The following or in (V) th -0.5V and above and V th The circuit operates within the following range of gate voltages.

[0194] On the other hand, Si transistors have large off-state currents and a narrow range of gate voltages operating in the subthreshold region. When utilizing subthreshold currents, OS transistors can operate over a wider range of gate voltages compared to Si transistors.

[0195] OS transistors are accumulation transistors where electrons are the majority carriers. Therefore, compared to inversion transistors with pn junctions, OS transistors are less affected by DIBL (Drain-Induced Barrier Lowering), a short-channel effect. In other words, OS transistors are more resistant to short-channel effects than Si transistors.

[0196] Furthermore, by using OS transistors as transistors 93, 94 and 83, 84, operation can be achieved over a wider current range in the subthreshold region, thereby reducing current consumption. Additionally, by using OS transistors as transistors 93, 94 and 83, 84, transistors 82 and 92, as well as transistors 93, 94 and 83, 84, can be manufactured simultaneously, which can sometimes shorten the manufacturing process of the operational circuit. Moreover, in addition to OS transistors, Si transistors containing silicon in the channel formation region can also be used as transistors 93, 94 and 83, 84. As silicon, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or monocrystalline silicon can be used.

[0197] When using Si transistors as transistors 93, 94, and 83, 84, it is preferable to employ a structure in which an electrode or body electrode, which serves as the back gate of the transistor, is provided, and the potential supplied to the back gate is the same as the ground potential supplied to the other of the source and drain of transistors 94, 84. By employing this structure, the electrical characteristics of transistors 93, 94, and 83, 84 can be stabilized.

[0198] Next, the wiring WSL, wiring XCL, wiring VBL and wiring WCL connected to unit 81 and unit 91 will be described.

[0199] A signal is supplied to the wiring WSL to control the on / off state of transistors 82 and 92, which are used as switches. Wiring WSL is used as the write word line when writing data to cells 81 and 91. Data is written to cells 81 and 91 by supplying current or voltage corresponding to the data to be written to wiring XCL or wiring WCL. This data is written by turning on transistors 82 and 92. At this time, wiring WCL is at H level (high potential). Furthermore, data is retained in cells 81 and 91 by controlling the switching off of transistors 82 and 92. At this time, wiring WCL is at L level (low potential).

[0200] The wiring WCL has a current (weighting current or constant current I) corresponding to the weighted data (also called first data, first input data) directed to cell 91. Wut The function of the drain voltage Vd that supplies current according to the potential held by the arithmetic unit.

[0201] The wiring XCL has cells 81 and 91 to make the current corresponding to the reference data (reference current or constant current I) Xut ) or the current (input current or current I) corresponding to the input data (also known as the second data, second input data). X The function of flowing through.

[0202] Wiring VBL is a wiring supplied with a constant potential Vb. The constant potential Vb is used to fix the potentials of the drain terminals of transistors 84 and 94 in cells 81 and 91, respectively. By supplying a constant potential Vb to the gates of transistors 83 and 93, the transistor characteristics, such as the threshold voltage of transistors 84 and 94, which correspond to the potential variations of wiring WCL, can be stabilized.

[0203] In particular, when transistors 94 and 84 are short-channel transistors with short channel lengths, the threshold voltage decreases due to DIBL, causing the drain current Id to depend on the drain voltage Vd. Therefore, a structure that supplies a constant potential Vb to the gates of transistors 83 and 93 and reduces the variation in the drain voltage of transistors 84 and 94 is effective. By adopting this structure, the accuracy of the data obtained through computation can be improved.

[0204] In addition, although Figure 11 Transistors 82 and 92 shown include a back gate, but other structures can also be used. For example, Figure 11Transistors 82 and 92 shown can be transistors with a structure that does not include a back gate, i.e., a single-gate structure. Furthermore, the potential or signal supplied to the back gate can be a fixed potential such as ground potential or a signal supplied to the gate.

[0205] In addition, although Figure 11 Transistors 92 to 94 and 82 to 84 shown are n-channel transistors, but other structures can also be used. For example, some or all of transistors 92 to 94 and 82 to 84 can be replaced with p-channel transistors. Furthermore, when some or all of transistors 92 to 94 and 82 to 84 are replaced with p-channel transistors, the voltage supplied by the wiring can be changed as needed to make transistors 92 to 94 and 82 to 84 perform the desired operation.

[0206] Note that the dimensions (e.g., channel length, channel width, transistor structure, etc.) of the transistors in each cell of the cell array CA are preferably equal to each other. For example, the dimensions of transistor 82 and transistor 92 are preferably equal to each other. For example, the dimensions of transistor 83 and transistor 93 are preferably equal to each other. For example, the dimensions of transistor 84 and transistor 94 are preferably equal to each other.

[0207] By making the transistors the same size as each other, the electrical characteristics of each transistor can be made approximately the same. Therefore, by making the transistors 92 in units 91_1,1 to 91_m,n each the same size, the transistors 93 in units 91_1,1 to 91_m,n each the same size, and the transistors 94 in units 91_1,1 to 91_m,n each of these units can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials input to the source, drain, and gate of transistor 92; the potentials input to the source, drain, and gate of transistor 93; the potentials input to the source, drain, and gate of transistor 94; the voltage maintained by each of units 91_1,1 to 91_m,n; and so on. Furthermore, by making the transistors 82 in each of units 81_1 to 81_m equal in size, the transistors 83 in each of units 81_1 to 81_m equal in size, and the transistors 84 in each of units 81_1 to 81_m equal in size, units 81_1 to 81_m can, for example, operate in a manner that is substantially identical to the result of such operation. Under identical conditions, substantially identical operations can be performed. Here, identical conditions refer to, for example, the potentials input to the source, drain, and gate of transistor 82; the potentials input to the source, drain, and gate of transistor 83; the potentials input to the source, drain, and gate of transistor 84; the voltage maintained in each of units 81_1 to 81_m; and so on.

[0208] <<Circuit SWS1, Circuit SWS2>>

[0209] Here are specific examples of circuits SWS1 and SWS2.

[0210] Circuit SWS1 includes, for example, transistors F3_1 to F3_n. The first terminal of transistor F3_1 is connected to wiring WCL_1, the second terminal of transistor F3_1 is connected to the input circuit WCS, and the gate of transistor F3_1 is connected to wiring SWL1. The first terminal of transistor F3_n is connected to wiring WCL_n, the second terminal of transistor F3_n is connected to the input circuit WCS, and the gate of transistor F3_n is connected to wiring SWL1.

[0211] Transistors F3_1 to F3_n can be, for example, transistors that can be used in the cell array CA. In particular, OS transistors are preferably used as transistors F3_1 to F3_n.

[0212] Circuit SWS1 is used to keep the input circuit WCS and wirings WCL_1 to WCL_n in an on or off state, respectively.

[0213] Circuit SWS2 includes, for example, transistors F4_1 to F4_n. The first terminal of transistor F4_1 is connected to wiring WCL_1, the second terminal of transistor F4_1 is connected to wiring OL_1, and the gate of transistor F4_1 is connected to wiring SWL2. The first terminal of transistor F4_n is connected to wiring WCL_n, the second terminal of transistor F4_n is connected to wiring OL_n, and the gate of transistor F4_n is connected to wiring SWL2.

[0214] Transistors F4_1 to F4_n can be, for example, transistors that can be used in the cell array CA. In particular, OS transistors are preferably used as transistors F4_1 to F4_n.

[0215] Circuit SWS2 has the function of enabling the connection between wiring WCL_1 and wiring OL_1, and between wiring WCL_n and wiring OL_n, to be in an open or closed state.

[0216] The input circuit WCS has the function of transmitting data stored in each cell of the cell array CA.

[0217] The input circuit XCS is connected to wirings XCL_1 to XCL_m. The input circuit XCS has the function of causing the current corresponding to the reference data described later or the current corresponding to the second data to flow through cells 81_1 to 81_m in the cell array CA.

[0218] The control circuit WSD is connected to wirings WSL_1 to WSL_m. The control circuit WSD has the function of supplying predetermined signals to wirings WSL_1 to WSL_m to select the row of the memory cell CA to which the first data is written when writing first data to cells 91_1,1 to 91_m,n. That is, wirings WSL_1 to WSL_m are used as write word lines.

[0219] Additionally, the control circuit WSD is connected, for example, to wiring SWL1 and wiring SWL2. The control circuit WSD has the function of supplying a specified signal to wiring SWL1 to put the input circuit WCS and the cell array CA into an on or off state, and to supply a specified signal to wiring SWL2 to put wiring OL_1 to wiring OL_n and the cell array CA into an on or off state.

[0220] <<Input Circuit WCS, Input Circuit XCS>>

[0221] Here, specific examples of the input circuit WCS and the input circuit XCS are given.

[0222] First, the input circuit WCS will be explained. Figure 12A This is a block diagram illustrating an example of the input circuit WCS. Figure 12A To illustrate the electrical connections between the input circuit WCS and its surrounding circuitry, circuit SWS1, transistor F3, wiring SWL1, and wiring WCL are also shown. Additionally, transistor F3 is... Figure 11 In the operational circuit MAC1, any one of transistors F3_1 to F3_n, the wiring WCL is Figure 11 Any one of the wirings WCL_1 to WCL_n in the operational circuit MAC1.

[0223] As an example Figure 12A The input circuit WCS shown includes a switch SWW. The first terminal of switch SWW is connected to the second terminal of transistor F3, and the second terminal of switch SWW is connected to wiring VINIL1. Wiring VINIL1 is used to supply an initialization potential to wiring WCL. This initialization potential can be ground (GND), a low-level potential, a high-level potential, etc. Switch SWW is only in the on state when supplying an initialization potential to wiring WCL; otherwise, it is in the off state.

[0224] As a switch SWW, for example, an analog switch or an electrical switch such as a transistor can be used. When a transistor is used as a switch SWW, for example, the transistor can be a transistor that can be used in the cell array CA. In addition, mechanical switches can also be used in addition to electrical switches.

[0225] Additionally, as an example, Figure 12A The input circuit WCS includes multiple current sources CS. Specifically, the input circuit WCS has K-bit (2 K The first data output (where K is an integer greater than or equal to 1) functions as current. At this time, the input circuit WCS includes 2... K -1 current source CS. The input circuit WCS includes one current source CS that outputs current as the information equivalent to the first bit value, two current sources CS that output current as the information equivalent to the second bit value, and 2 K-1 A current source CS outputs information equivalent to the value of the Kth bit as current.

[0226] exist Figure 12A In the circuit SWS1, each current source CS includes terminals T1 and T2. Terminal T1 of each current source CS is connected to the second terminal of transistor F3. Additionally, terminal T2 of one current source CS is connected to wiring DW_1, and terminals T2 of both current sources CS are connected to wiring DW_2. K-1 Terminal T2 of each current source CS is connected to wiring DW_K.

[0227] The multiple current sources CS in the input circuit WCS have the same constant current I Wut The function output from their respective terminals T1: constant current I. Wut Equivalent to the normalized current I Wut Note that during the manufacturing process of the MAC1 operational circuit, errors sometimes occur due to fluctuations in the electrical characteristics of the transistors in each current source CS. Therefore, the constant current I output from each terminal T1 of the multiple current sources CS varies. Wut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, it is assumed that the constant current I output from the terminal T1 of the plurality of current sources CS in the input circuit WCS is... Wut There is no error between them, so this is explained.

[0228] Wiring DW_1 to wiring DW_K is used to transmit a constant current I from the current source CS connected to it. Wut The wiring of the control signal. Specifically, for example, when wiring DW_1 is supplied with a high-level potential, the current source CS connected to wiring DW_1 acts as a constant current to make I... Wut When the current flows through the second terminal of transistor F3 and wiring DW_1 is supplied with a low-level potential, the current source CS connected to wiring DW_1 has no output I. Wut .

[0229] The current supplied by one current source CS connected to wiring DW_1 is equivalent to the first value, the current supplied by two current sources CS connected to wiring DW_2 is equivalent to the second value, and the current supplied by K current sources CS connected to wiring DW_K is equivalent to the Kth value.

[0230] Note that in Figure 12A The diagram shows the input circuit WCS when K is an integer greater than or equal to 3, and when K is 1, it functions as... Figure 12A The input circuit WCS can be constructed without a current source CS connected to wiring DW_2 to wiring DW_K. Additionally, when K is 2, as... Figure 12A The input circuit WCS can be constructed without setting a current source CS connected to wiring DW_3 to wiring DW_K.

[0231] Next, a specific structural example of the current source CS will be described.

[0232] Figure 13A The current source CS1 shown is suitable for use with Figure 12A The circuit of the current source CS in the input circuit WCS, the current source CS1 includes transistor Tr1 and transistor Tr2.

[0233] The first terminal of transistor Tr1 is connected to wiring VDDL. The second terminal of transistor Tr1 is connected to the gate and back gate of transistor Tr1, and the first terminal of transistor Tr2. The second terminal of transistor Tr2 is connected to terminal T1, and the gate of transistor Tr2 is connected to terminal T2. Additionally, terminal T2 is connected to wiring DW.

[0234] DW wiring is Figure 12A Any one of the wiring DW_1 to wiring DW_K.

[0235] The VDDL wiring is used as a wiring to supply a constant voltage. This constant voltage can be, for example, a high-level potential.

[0236] When the constant voltage supplied by wiring VDDL is set to a high level, the first terminal of transistor Tr1 is input with a high level. Meanwhile, the potential of the second terminal of transistor Tr1 is set to a lower level than this high level. At this time, the first terminal of transistor Tr1 is used as the drain, and the second terminal of transistor Tr1 is used as the source. Furthermore, the gate and the second terminal of transistor Tr1 are connected, therefore the gate-source voltage of transistor Tr1 is 0V. Therefore, when the threshold voltage of transistor Tr1 is within an appropriate range, a current (drain current) in the subthreshold region flows between the first and second terminals of transistor Tr1. The amount of this current is preferably, for example, 1.0 × 10⁻⁶. -8 A and below, preferably 1.0 × 10 -12 Below A, 1.0 × 10 is further preferred. -15 Below A. Furthermore, for example, this current is more preferably in a range that increases exponentially with respect to the gate-source voltage. That is, transistor Tr1 is used as a current source to allow current to flow within the current range when operating in the subthreshold region. This current corresponds to the aforementioned I. Wut Or the following I Xut .

[0237] Transistor Tr2 is used as a switching element. Furthermore, when the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal, the first terminal of transistor Tr2 is used as the drain, and the second terminal is used as the source. Additionally, the back gate and the second terminal of transistor Tr2 are connected, therefore the back gate-source voltage is 0V. Thus, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 is in the on state when a high-level potential is input to its gate, and in the off state when a low-level potential is input to its gate. Specifically, when transistor Tr2 is in the on state, the current in the subthreshold current range flows from the second terminal of transistor Tr1 to terminal T1; when transistor Tr2 is in the off state, this current does not flow from the second terminal of transistor Tr1 to terminal T1.

[0238] Note that it can be used Figure 12A The circuit of the current source CS in the input circuit WCS is not limited to Figure 13A The current source CS1. For example, the current source CS1 has a structure that connects the back gate of transistor Tr2 and the second terminal of transistor Tr2, but it can also be a structure in which the back gate of transistor Tr2 is connected to other wiring. Figure 13B An example of such a structure is shown. Figure 13B The current source CS2 shown has a structure where the back gate of transistor Tr2 is connected to the wiring VTHL. In current source CS2, because the wiring VTHL is connected to external circuitry, a predetermined potential can be supplied to the back gate of transistor Tr2 by supplying a predetermined potential to the wiring VTHL using this external circuitry. This allows the threshold voltage of transistor Tr2 to be changed. By increasing the threshold voltage of transistor Tr2, the off-state current of transistor Tr2 can be reduced.

[0239] Alternatively, for example, current source CS1 has a structure that connects the back gate of transistor Tr1 and the second terminal of transistor Tr1, but it can also have a structure in which the voltage between the back gate and the second terminal of transistor Tr2 is maintained by a capacitor. Figure 13C An example of such a structure is shown. Figure 13CThe current source CS3 shown includes transistors Tr1 and Tr2, transistor Tr3, and capacitor C6. Current source CS3 differs from current source CS1 in that capacitor C6 connects the second terminal of transistor Tr1 to its back gate, and the back gate of transistor Tr1 to the first terminal of transistor Tr3. Furthermore, current source CS3 has a structure where the second terminal of transistor Tr3 is connected to wiring VTL, and the gate of transistor Tr3 is connected to wiring VWL. In current source CS3, supplying a high-level potential to wiring VWL turns transistor Tr3 on, thus turning on the connection between wiring VTL and the back gate of transistor Tr1. At this time, a predetermined potential can be input from wiring VTL to the back gate of transistor Tr1. Conversely, supplying a low-level potential to wiring VWL turns transistor Tr3 off, and capacitor C6 maintains the voltage between the second terminal of transistor Tr1 and its back gate. In other words, by determining the voltage supplied to the back gate of transistor Tr1 by wiring VTL, the threshold voltage of transistor Tr1 can be changed, while the threshold voltage of transistor Tr1 can be fixed by transistor Tr3 and capacitor C6.

[0240] Additionally, for example, as can be used Figure 12A The circuit of the current source CS in the input circuit WCS can also be used Figure 13D The current source CS4 is shown. Current source CS4 has the function of... Figure 13C The back gate of transistor Tr2, the current source CS3, is connected to the wiring VTHL but not to the second terminal of transistor Tr2. That is, with... Figure 13B Similarly, in current source CS4, the threshold voltage of transistor Tr2 can be changed according to the potential supplied by wiring VTHL.

[0241] When a large current flows through the first and second terminals of transistor Tr1 in current source CS4, the on-state current of transistor Tr2 needs to be increased in order for this current to flow from terminal T1 to the outside of current source CS4. At this time, by supplying a high-level potential to wiring VTHL in current source CS4 to lower the threshold voltage of transistor Tr2 and increase the on-state current of transistor Tr2, the large current flowing through the first and second terminals of transistor Tr1 can be made to flow from terminal T1 to the outside of current source CS4.

[0242] As Figure 12A The current source CS in the input circuit WCS uses Figures 13A to 13DThe current sources CS1 to CS4 shown enable the input circuit WCS to output a current corresponding to the first data of bit K. Alternatively, the amount of this current can be, for example, the current flowing between the first and second terminals within the subthreshold region of transistor 94.

[0243] In addition, as Figure 12A The input circuit WCS can also be used Figure 12B The input circuit WCS is shown. Figure 12B The input circuit WCS has wiring DW_1 to wiring DW_K respectively connected to a Figure 13A The structure of the current source CS. Furthermore, when the channel width of transistor Tr1_1 is w_1, the channel width of transistor Tr1_2 is w_2, and the channel width of transistor Tr1_K is w_K, the ratio of the channel widths is w_1:w_2:w_K = 1:2:2. K-1 The current flowing through the source-drain junction of a transistor operating in the subthreshold region is proportional to the channel width, and therefore... Figure 12A The input circuit WCS is the same. Figure 12B The input circuit WCS shown can output the current corresponding to the first data of the K-bit.

[0244] Transistors Tr1 (including transistors Tr1_1 to Tr1_K), Tr2 (including transistors Tr2_1 to Tr2_K), and Tr3 may, for example, be transistors that can be used in the cell array CA. In particular, transistors Tr1 (including transistors Tr1_1 to Tr1_K), Tr2 (including transistors Tr2_1 to Tr2_K), and Tr3 are preferably OS transistors.

[0245] Next, a specific example of the input circuit XCS will be explained.

[0246] Figure 12C This is a block diagram illustrating an example of the input circuit XCS. Note that in Figure 12C To illustrate the electrical connection between the input circuit XCS and its surrounding circuitry, wiring XCL is also shown. Furthermore, wiring XCL is... Figure 11 Any one of the wirings XCL_1 to XCL_m in the operational circuit MAC1.

[0247] As an example Figure 12CThe input circuit XCS shown includes a switch SWX. The first terminal of switch SWX is connected to wiring XCL and multiple current sources CS, and the second terminal of switch SWX is connected to wiring VINIL2. Wiring VINIL2 is used to supply an initialization potential to wiring XCL; this initialization potential can be ground (GND), a low-level potential, a high-level potential, etc. Alternatively, the initialization potential supplied by wiring VINIL2 can be made equal to the potential supplied by wiring VINIL1. Switch SWX is only in the open state when supplying an initialization potential to wiring XCL; otherwise, it is in the closed state.

[0248] For example, a switch SWX can be a switch that can be used to switch SWW.

[0249] In addition, as Figure 12C The input circuit XCS circuit structure can be adopted with Figure 12A The input circuit WCS has almost the same structure. Specifically, the input circuit XCS has the function of outputting reference data as current and outputting L-bit (2 L The second data output (where L is an integer greater than or equal to 1) functions as current. In this case, the input circuit XCS includes 2... L -1 current source CS. The input circuit XCS includes one current source CS that outputs current as the information equivalent to the first bit value, two current sources CS that output current as the information equivalent to the second bit value, and 2 L-1 A current source CS outputs information equivalent to the value of the Lth bit as current.

[0250] In addition, the input circuit XCS, as the reference data for the current output, can be, for example, information where the first bit is "1" and the subsequent bits are "0".

[0251] exist Figure 12C In the diagram, terminal T2 of one current source CS is connected to wiring DX_1, and terminal T2 of both current sources CS is connected to wiring DX_2. L-1 Terminal T2 of each current source CS is connected to wiring DX_L.

[0252] The multiple current sources CS in the input circuit XCS have I as the same constant current. Xut The function is output from their respective terminals T1. Wiring DX_1 to DX_L is used to transmit I from the current source CS connected to them. Xut The control signal is routed. That is, the input circuit XCS has the function of causing the current corresponding to the L bits of information sent by the wirings DX_1 to DX_L to flow through the wiring XCL.

[0253] When errors occur due to fluctuations in the electrical characteristics of the transistors in the current sources CS of the input circuit XCS, the constant current I output from the terminals T1 of the multiple current sources CS will change. Xut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, it is assumed that the constant current I output from the terminal T1 of the plurality of current sources CS in the input circuit XCS is... Xut There is no error between them, so this is explained.

[0254] In addition, similar to the current source CS of the input circuit WCS, the current source CS of the input circuit XCS can be... Figures 13A to 13D Any one of the current sources CS1 to CS4. In this case, wiring DX can be used instead. Figures 13A to 13D The wiring DW is shown. Therefore, the input circuit XCS can be used as reference data or L-bit second data to allow current to flow through the wiring XCL within the subthreshold current range.

[0255] in addition, Figure 12C The input circuit XCS can have the same characteristics as... Figure 12B The input circuit WCS shown has the same circuit structure. This time, the input circuit XCS is used instead. Figure 12B The input circuit WCS shown can be considered by replacing wiring DW_1 with wiring DX_1, replacing wiring DW_2 with wiring DX_2, replacing wiring DW_K with wiring DX_L, replacing switch SWW with switch SWX, and replacing wiring VINIL1 with wiring VINIL2.

[0256] <Examples of operational circuits>

[0257] Next, an example of how the operational circuit MAC1 works will be explained.

[0258] Figure 14 This is a timing diagram of an example of the operation of the operational circuit MAC1. Figure 14 The timing diagram shows the potential changes of routing SWL1, SWL2, WSL_i (i is an integer greater than or equal to 1 and less than m-1), WSL_i+1, XCL_i, XCL_i+1, nodes NN_i,j (j is an integer greater than or equal to 1 and less than n-1), nodes NN_i+1,j, NNref_i, and NNref_i+1 during and near time T11 to time T23. Figure 14 The timing diagram also shows the current I flowing between the first and second terminals of transistors 93 and 94 in cell 91_i,j. 94 _i,j, the current I flowing between the first and second terminals of transistors 83 and 84 in unit 81_i 84The current I flowing through the first and second terminals of transistors 93 and 94 in unit 91_i+1,j is... 94 _i+1, j and the current I flowing between the first and second terminals of transistors 83 and 84 in unit 81_i+1. 84 The changes of _i+1.

[0259] WCS is used as the input circuit of the arithmetic circuit MAC1. Figure 12A The input circuit WCS is used as the input circuit XCS of the arithmetic circuit MAC1. Figure 12C The input circuit XCS.

[0260] Note that in this example, the source potentials of transistors 84 and 94 are ground potential GND. Additionally, before time T11, as an initial setting, the potentials of nodes NN_i,j, NN_i+1,j, NNref_i, and NNref_i+1 are each set to ground potential GND. Specifically, for example, ... Figure 12A The initialization potential of wiring VINIL1 is set to ground potential GND, which turns on switch SWW, transistor F3, and transistors 92 in units 91_i,j and 91_i+1,j. This allows nodes NN_i,j and NN_i+1,j to have the ground potential GND. Alternatively, for example, [the following text is incomplete and requires further context]. Figure 12C The initialization potential of the wiring VINIL2 is set to ground potential GND, which puts the switch SWX and each transistor 82 in unit 91_i,j and unit 91_i+1,j into the on state, thereby making the potential of node NNref_i,j and node NNref_i+1,j the ground potential GND.

[0261] Note that in this example, the gate potentials of transistors 83 and 93 are set to a constant potential Vb. By setting the gate potentials of transistors 83 and 93 to a constant potential Vb, the first terminals of transistors 83 and 93 can be set to a voltage Vb-Vth, which is the constant potential Vb minus the threshold voltage. Therefore, the rise of the second terminals (drain side) of transistors 84 and 94 can be suppressed.

[0262] <<Time T11 to Time T12>>

[0263] During the period from time T11 to time T12, a high-level potential is applied to wiring SWL1 (in Figure 14 (Note: High) Apply a low-level potential to wiring SWL2 (in) Figure 14(This is denoted as Low). Therefore, when a high-level potential is applied to the gates of transistors F3_1 to F3_n, each transistor F3_1 to F3_n becomes turned on, and when a low-level potential is applied to the gates of transistors F4_1 to F4_n, each transistor F4_1 to F4_n becomes turned off.

[0264] Additionally, during time T11 to time T12, a low-level potential is applied to wiring WSL_i and wiring WSL_i+1. Therefore, a low-level potential is applied to the gates of transistor 92 in cells 91_i, 1 to 91_i, n in the i-th row of cell array CA, and to the gate of transistor 82 in cell 81_i, causing transistors 92 and 82 to turn off. Furthermore, a low-level potential is applied to the gates of transistor 92 in cells 91_i+1, 1 to 91_i+1, n in the (i+1)-th row of cell array CA, and to the gate of transistor 82 in cell 81_i+1, causing transistors 92 and 82 to turn off.

[0265] Additionally, during the period from time T11 to time T12, a ground potential GND is applied to wiring XCL_i and wiring XCL_i+1. Specifically, for example, when Figure 12C When the wiring XCL is wiring XCL_i and wiring XCL_i+1, by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on the switch SWX, the potential of wiring XCL_i and wiring XCL_i+1 can be the ground potential GND.

[0266] Additionally, during the period from time T11 to time T12, Figure 12A In each case where the routing WCL is routing WCL_1 to routing WCL_K, routing DW_1 to routing DW_K are not input with the first data. Additionally, in... Figure 12C In the case where the routing XCL is each of routing XCL_1 to routing XCL_K, routing DX_1 to routing DX_L are not input with second data. Figure 12A In the input circuit WCS, wirings DW_1 to DW_K are all input with a low-level potential, and Figure 12C In the input circuit XCS, wiring DX_1 to wiring DX_L are all input with a low level potential.

[0267] Furthermore, during the period from time T11 to time T12, current does not flow through wiring WCL_j, wiring XCL_i, and wiring XCL_i+1. Therefore, I 94 _i, j, I 84 _i、I 94 _i+1, j, I 84_i+1 is 0.

[0268] <<Time T12 to Time T13>>

[0269] During time T12 to time T13, a high-level potential is applied to wiring WSL_i. Therefore, a high-level potential is applied to the gates of transistor 92 in cells 91_i,1 to 91_i,n in the i-th row of cell array CA, and to the gate of transistor 82 in cell 81_i, turning transistors 92 and 82 on. Conversely, during time T12 to time T13, a low-level potential is applied to wirings WSL_1 to WSL_m (excluding wiring WSL_i), turning off transistors 92 in cells 91_1,1 to 91_m,n (excluding the i-th row) and transistors 82 in cells 81_1 to 81_m (excluding the i-th row).

[0270] Furthermore, continuing from time T12, wiring XCL_1 to wiring XCL_m is given a ground potential GND.

[0271] <<Time T13 to Time T14>>

[0272] During the period from time T13 to time T14, the current I0_i,j flows as the first data from the input circuit WCS through transistor F3_j to the cell array CA. Specifically, when Figure 12A When the wiring WCL is wiring WCL_j, each of the wirings DW_1 to DW_K is input with a signal corresponding to the first data, thereby the current I0_i,j flows from the input circuit WCS to the second terminal of transistor F3_j. That is, when the value of the K-bit signal input as the first data is w_i,j (w_i,j is 0 or above and 2...), the current I0_i,j flows from the input circuit WCS to the second terminal of transistor F3_j. K When the integer is less than or equal to -1, the following holds true: I0_i,j = w_i,j × I Wut .

[0273] Furthermore, when w_i,j is 0, I0_i,j=0 holds true. Therefore, strictly speaking, the current does not flow from the input circuit WCS through the transistor F3_j to the cell array CA. However, in this specification, it is sometimes written as "the current with I0_i,j=0 flows through", etc.

[0274] During the period from time T13 to time T14, transistor 92 in cell 91_i,j of the i-th row of cell array CA is in the on state, and transistor 92 in cells 91_1,j to 91_m,j of cell array CA other than the i-th row is in the off state. Therefore, current I0_i,j flows from wiring WCL_j to cell 91_i,j.

[0275] When transistor 92, included in unit 91_i,j, is turned on, current I0_i,j flows through transistor 94. The current I0_i,j is set as the current flowing between the first and second terminals of transistor 94. The gate-source voltage of transistor 94 becomes V. g _i,j-GND flows through with current I0_i,j.

[0276] Additionally, during the period from time T13 to time T14, the current I ref0 Reference data flows from the input circuit XCS to the wiring XCL_i. Specifically, when Figure 12C When the routing XCL is XCL_i, routing DX_1 is input with a high-level potential, and routings DX_2 to DX_K are input with a low-level potential, and the current I... ref0 =I Xut The flow from the input circuit XCS to the wiring XCL_i.

[0277] During the period from time T13 to time T14, since transistor 82 in unit 81_i turns on, the current I... ref0 The routing flow is from XCL_i to cell 81_i. 84 _i becomes I ref0 Due to the establishment of I ref0 =I Xut Therefore I 94 _i,j become I0_i,j=w_i,j×I ref0 (In the attached diagram, the "j×I" in the instruction manual will be replaced with "j×I".) ref0 " is represented as "j I ref0 (”).

[0278] Similar to units 91_i,j, when transistor 82 included in unit 81_i is turned on, the current I... ref0 The current flows through transistor 84. As the current flowing between the first and second terminals of transistor 84, the current I is set. ref0 The gate-source voltage of transistor 84 is V. gm _i-GND with current I ref0 It flowed by.

[0279] <<Time T14 to Time T15>>

[0280] During time T14 to time T15, a low-level potential is applied to the wiring WSL_i. Therefore, a low-level potential is applied to the gates of transistors 92 in cells 91_i,1 to 91_i,n in the i-th row of cell array CA and the gate of transistor 82 in cell 81_i, turning each transistor 92 and transistor 82 off.

[0281] When transistor 92 in cell 91_i,j turns off, capacitor 95 maintains the potential difference between the gate potential of transistor 94 (node ​​NN_i,j) and the potential of wiring XCL_i by V. g _i, jV gm _i. In addition, when transistor 92 in cell 91_i is turned off, capacitor 95 maintains the potential difference between the gate of transistor 84 (node ​​NNref_i) and the potential of wiring XCL_i at 0.

[0282] <<Time T15 to Time T16>>

[0283] During the period from time T15 to time T16, the wiring XCL_i is given GND. Specifically, for example, when Figure 12C When the wiring XCL is wiring XCL_i, the potential of wiring XCL_i can be made to the ground potential GND by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on the switch SWX.

[0284] Therefore, the potential changes of nodes NN_i,1 to NN_i,n are due to the capacitive coupling of capacitors 95 in each of the units 91_i,1 to 91_i,n in the i-th row, and the potential changes of node NNref_i are due to the capacitive coupling of capacitors 85 in unit 81_i.

[0285] The potential change of nodes NN_i,1 to NN_i,n is the potential change of wiring XCL_i multiplied by the potential of the capacitive coupling coefficient, which depends on the structure of each cell 91_i,1 to 91_i,n in the cell array CA. This capacitive coupling coefficient is calculated based on the capacitance of capacitor 95, the gate capacitance of transistor 94, parasitic capacitance, etc. In each of cells 91_i,1 to 91_i,n, when the capacitive coupling coefficient through capacitor 95 is p, the potential of node NN_i,j of cell 91_i,j decreases by p (V) during the period from time T14 to time T15. gm _i-GND).

[0286] Similarly, when the potential of wiring XCL_i changes, the potential of node NNref_i also changes due to the capacitive coupling through capacitor 85 in cell 81_i. When the capacitive coupling coefficient through capacitor 85 is the same as that of capacitor 95, the potential of node NNref_i in cell 81_i decreases by p (V) during the period from time T14 to time T15. gm (_i-GND). In Figure 14In the timing diagram, p=1 is used as an example. Therefore, the potential of node NNref_i during the period from time T15 to time T16 is GND.

[0287] Therefore, the potential of node NN_i,j of unit 91_i,j decreases, so transistor 94 becomes off. Similarly, the potential of node NNref_i of unit 81_i decreases, so transistor 84 also becomes off. Therefore, during the period from time T15 to time T16, I 94 _i, j and I 84 Each _i is 0.

[0288] <<Time T16 to Time T17>>

[0289] During time T16 to time T17, a high-level potential is applied to wiring WSL_i+1. Therefore, a high-level potential is applied to the gates of transistors 92 in cells 91_i+1, 1 to 91_i+1, n of the (i+1)th row of cell array CA, and to the gate of transistor 82 in cell 81_i+1, turning each transistor 92 and 82 on. Conversely, during time T16 to time T17, a low-level potential is applied to wirings WSL_1 to WSL_m (excluding wiring WSL_i+1), turning off transistors 92 in cells 91_1, 1 to 91_m, n of cell array CA (excluding the (i+1)th row) and transistors 82 in cells 81_1 to 81_m (excluding the (i+1)th row).

[0290] Furthermore, continuing from time T16, wiring XCL_1 to wiring XCL_m is given a ground potential GND.

[0291] <<Time T17 to Time T18>>

[0292] During the period from time T17 to time T18, the current I0_i+1,j flows as the first data from the input circuit WCS through transistor F3_j to the cell array CA. Specifically, when Figure 12A When the wiring WCL is set to WCL_j+1, each of the wirings DW_1 to DW_K is input with a signal corresponding to the first data, thereby causing the current I0_i+1,j to flow from the input circuit WCS to the second terminal of transistor F3_j. That is, when the value of the K-bit signal input as the first data is w_i+1,j (w_i+1,j is 0 or greater and 2...), the current I0_i+1,j flows from the input circuit WCS to the second terminal of transistor F3_j. K When the integer is less than -1, the following holds true: I0_i+1, j=w_i+1, j×I Wut .

[0293] Furthermore, when w_i+1,j is 0, I0_i+1,j=0 holds true. Therefore, strictly speaking, the current does not flow from the input circuit WCS through the transistor F3_j to the cell array CA. However, in this specification, the same situation as I0_i,j=0 is sometimes described as "the current flows through I0_i+1,j=0".

[0294] At this time, transistor 92 in cell 91_i+1,j of cell array CA in row i+1 is turned on, and transistor 92 in cells 91_1,j to cell 91_m,j of cell array CA except for row i+1 is turned off. Therefore, current I0_i+1,j flows from wiring WCL_j to cell 91_i+1,j.

[0295] When transistor 92, included in unit 91_i+1,j, is turned on, current I0_i+1,j flows through transistor 94. The current I0_i+1,j is set as the current flowing between the first and second terminals of transistor 94. The gate-source voltage of transistor 94 becomes V. g _i+1,j-GND flows through with current I0_i+1,j.

[0296] Additionally, during the period from time T17 to time T18, the current I... ref0 Reference data flows from the input circuit XCS to the wiring XCL_i+1. Specifically, similar to the period from time T13 to time T14, when Figure 12C When the routing XCL is XCL_i+1, routing DX_1 is input with a high-level potential, and routings DX_2 to DX_K are input with a low-level potential, and the current I... ref0 =I Xut The flow originates from the input circuit XCS and flows to the wiring XCL_i+1.

[0297] During the period from time T17 to time T18, since transistor 82 in cell 81_i+1 turns on, the current I... ref0 The flow originates from wiring XCL_i+1 to cell 81_i+1. 84 _i+1 becomes I ref0 Due to the establishment of I ref0 =I Xut Therefore I 94 _i+1, j becomes I0_i+1, j=w_i+1, j×I ref0 (In the attached diagram, "×" represents " (”).

[0298] Similar to unit 91_i+1,j, when transistor 82 included in unit 81_i+1 is turned on, the current I ref0The current flows through transistor 84. As the current flowing between the first and second terminals of transistor 84, the current I is set. ref0 The gate-source voltage of transistor 84 is V. gm _i+1-GND with current I ref0 It flowed by.

[0299] <<Time T18 to Time T19>>

[0300] During the period from time T18 to time T19, a low-level potential is applied to wiring WSL_i+1. Therefore, a low-level potential is applied to the gates of transistors 92 in cells 91_i+1, 1 to 91_i+1, n in the (i+1)th row of cell array CA, and to the gate of transistor 82 in cell 81_i+1, turning each transistor 92 and transistor 82 off.

[0301] When transistor 92 in cell 91_i+1,j turns off, capacitor 95 maintains the potential difference between the gate of transistor 94 (node ​​NN_i+1,j) and the potential of wiring XCL_i+1 by V. g _i+1, jV gm _i+1. Additionally, when transistor 92 in cell 81_i+1 is turned off, capacitor 85 maintains a voltage difference of 0 between the gate potential of transistor 84 (node ​​NNref_i+1) and the potential of wiring XCL_i+1. Note that during the operation from time T18 to time T19, the voltage maintained by capacitor 85 is sometimes not zero (e.g., V) depending on the transistor characteristics of transistors 82 and 84. ds At this point, the potential of node NNref_i+1 is considered as the potential of wiring XCL_i+1 plus V. ds The potential is sufficient.

[0302] <<Time T19 to Time T20>>

[0303] During the period from time T19 to time T20, wiring XCL_i+1 is given a ground potential GND. Specifically, for example, when Figure 12C When the wiring XCL is wiring XCL_i+1, by setting the initialization potential of wiring VINIL2 to ground potential GND and putting switch SWX in the open state, the potential of wiring XCL_i+1 can be made to ground potential GND.

[0304] Therefore, the potential changes of nodes NN_i,1 to NN_i+1,n are due to the capacitive coupling of capacitors 95 in each of the units 91_i+1,1 to 91_i+1,n in the i+1th row, and the potential changes of node NNref_i+1 are due to the capacitive coupling of capacitor 85 in unit 81_i+1.

[0305] The potential change of nodes NN_i+1,1 to NN_i+1,n is the potential change of wiring XCL_i+1 multiplied by the potential depending on the capacitive coupling coefficient of the structure of each cell 91_i+1,1 to 91_i+1,n in the cell array CA. This capacitive coupling coefficient is calculated based on the capacitance of capacitor 95, the gate capacitance of transistor 94, parasitic capacitance, etc. In each cell 91_i+1,1 to 91_i+1,n, when the capacitive coupling coefficient through capacitor 95 is the same as that of each cell 91_i,1 to 91_i,n, and the capacitive coupling coefficient through capacitor 95 is p, the potential of node NN_i+1,j of cell 91_i+1,j decreases by p (V) during the period from time T18 to time T19. gm _i+1-GND).

[0306] Similarly, when the potential of the wiring XCL_i+1 changes, the potential of the node NNref_i+1 also changes due to the capacitive coupling through capacitor 85 in cell 81_i+1. When the capacitive coupling coefficient through capacitor 85 is the same as that of capacitor 95, the potential of the node NNref_i+1 in cell 81_i+1 decreases by p (V) during the period from time T18 to time T19. gm (_i+1-GND). In Figure 14 In the timing diagram, p=1 as an example. Therefore, the potential of node NNref_i+1 during the period from time T20 to time T21 is GND.

[0307] Therefore, the potential of node NN_i+1,j in unit 91_i+1 decreases, so transistor 94 becomes off. Similarly, the potential of node NNref_i+1 in unit 81_i+1 decreases, so transistor 84 also becomes off. Therefore, during the period from time T19 to time T20, I 94 _i+1, j and I 84 Each of _i+1 is 0.

[0308] <<Time T20 to Time T21>>

[0309] During the period from time T20 to time T21, a low-level potential is applied to wiring SWL1. Therefore, a low-level potential is applied to the gates of transistors F3_1 to F3_n, and each of transistors F3_1 to F3_n becomes off.

[0310] <<Time T21 to Time T22>>

[0311] During the period from time T21 to time T22, a high-level potential is applied to wiring SWL2. Therefore, a high-level potential is applied to the gates of transistors F4_1 to F4_n, and each of transistors F4_1 to F4_n becomes turned on.

[0312] <<Time T22 to Time T23>>

[0313] During the period from time T22 to time T23, the current I ref0 x_i times x_iI ref0 The current flows as the second data from the input circuit XCS to the wiring XCL_i. Specifically, for example, when Figure 12C When the wiring XCL is XCL_i, the wirings DX_1 to DX_K are respectively input with a high-level potential or a low-level potential according to the value of x_i, which serves as the current x_iI. ref0 =x_iI Xut The current flows from the input circuit XCS to the wiring XCL_i. Note that in this example, x_i corresponds to the value of the second data. At this point, the potential of the wiring XCL_i changes from 0 to V. gm _i+ΔV_i.

[0314] When the potential of the wiring XCL_i changes, the potential of nodes NN_i,1 to NN_i,n also changes due to the capacitive coupling of capacitors 95 in each of the cells 91_i,1 to 91_i,n in the i-th row of the cell array CA. Therefore, the potential of node NN_i,j of cell 91_i,j becomes V. g _i,j+pΔV_i.

[0315] Similarly, when the potential of wiring XCL_i changes, the potential of node NNref_i also changes due to the capacitive coupling through capacitor 85 in cell 81_i. Therefore, the potential of node NNref_i in cell 81_i becomes V. gm _i+pΔV_i.

[0316] Therefore, the current flowing through the first terminal and the second terminal of the transistor 94 in cell 91_i,j is proportional to the product of the first data w_i,j and the second data x_i.

[0317] During the period from time T22 to time T23, the current I ref0 x_i+1 times x_i+1I ref0 The current flows as the second data from the input circuit XCS to the wiring XCL_i+1. Specifically, for example, when Figure 12C When the routing XCL is XCL_i+1, the routing DX_1 to DX_K are respectively input with a high-level potential or a low-level potential according to the value of x_i+1, as the current x_i+1I. ref0 =x_i+1I Xut The current flows from the input circuit XCS to the wiring XCL_i+1. Note that in this example, x_i+1 corresponds to the value of the second data. At this point, the potential of the wiring XCL_i+1 changes from 0 to V. gm _i+1+ΔV_i+1.

[0318] When the potential of XCL_i+1 changes, the potential of nodes NN_i+1,1 to NN_i+1,n also changes due to the capacitive coupling of capacitor 95 in each of the cells 91_i+1,1 to 91_i+1,n in the (i+1)th row of the cell array CA. Therefore, the potential of node NN_i+1,j of cell 91_i+1,j becomes V. g _i+1, j+pΔV_i+1.

[0319] Similarly, when the potential of the wiring XCL_i+1 changes, the potential of the node NNref_i+1 also changes due to the capacitive coupling through the capacitor 85 in cell 81_i+1. Therefore, the potential of the node NNref_i+1 in cell 81_i+1 becomes V. gm _i+1+pΔV_i+1.

[0320] Therefore, the current flowing through the first terminal and the second terminal of the transistor 94 in cell 91_i+1,j is proportional to the product of w_i+1,j as the first data and x_i+1 as the second data.

[0321] Therefore, the current output from wiring OL_j can be a current proportional to the sum of the weighting coefficients w_i,j and w_i+1,j (as the first data) and the values ​​x_i and x_i+1 (as the second data) of the input signal. This current can be converted into an analog signal D with an analog voltage value by a current-to-voltage conversion circuit, etc. MACA It is then output to the analog-to-digital converter circuit 79.

[0322] Therefore, the arithmetic circuit MAC1, which includes a cell array CA with 3 or more rows and 2 or more columns, can also perform the product summation operation as described above. In this case, the cells of one column of the multiple columns in the arithmetic circuit MAC1 are used as the holding current I.ref0 and xI ref0 The units of ref0 can simultaneously perform the product-sum operation processing for the remaining number of columns in multiple columns. In other words, by increasing the number of columns of the memory cell array, a semiconductor device capable of achieving high-speed product-sum operation processing can be provided. Therefore, a product-sum operation unit with excellent operation processing ability per unit power can be provided.

[0323] In addition, although the case where the transistors in the operation circuit MAC1 are OS transistors or Si transistors has been described in the present embodiment, one aspect of the present invention is not limited thereto. As the transistors in the operation circuit MAC1, for example, transistors including Ge or the like in the channel formation region, transistors including compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. in the channel formation region, transistors including carbon nanotubes in the channel formation region, transistors including organic semiconductors in the channel formation region, etc. can be used.

[0324] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0325] (Embodiment 3)

[0326] In the present embodiment, an example of the cross-sectional structure of an element layer having OS transistors that can be used for stacking in semiconductor devices and the like is described. In the present embodiment, an example of a cross-sectional schematic diagram of a circuit structure applicable to NOSRAM, DOSRAM, etc. is described.

[0327] <Example of the structure of NOSRAM 1>

[0328] Figure 15 An example of the cross-sectional structure when a circuit structure of a three-transistor type NOSRAM is adopted is shown. Figure 15 An example of the case where element layers UF[1] to UF[3] are stacked on the element layer LF is shown. In addition, Figure 16A An example of the cross-sectional structure of the element layer UF[k] is shown. In addition, Figure 16B is Figure 16A the equivalent circuit diagram of.

[0329] The element layer LF is the element layer 10 described in the above Embodiment 1. Elements such as Si transistors are provided in the element layer LF. The element layer UF is the element layer 40 described in the above Embodiment 1. Elements such as OS transistors are provided in the element layer UF.

[0330] In addition, Figure 15An example of a transistor 550 included in the element layer LF is shown. The transistor 550 is disposed on the substrate 311 and includes a conductive layer 316 used as a gate electrode, an insulating layer 315, a semiconductor region 313 formed by a portion of the substrate 311, and low-resistance regions 314a and 314b used as source or drain regions.

[0331] Furthermore, the transistor 550 can be either a p-channel transistor or an n-channel transistor.

[0332] In the low resistance regions 314a and 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements such as arsenic and phosphorus that impart n-type conductivity or elements such as boron that impart p-type conductivity are also included.

[0333] also, Figure 15 The transistor 550 shown is just an example; appropriate transistors may be used depending on the circuit structure or driving method, and the structure is not limited to it.

[0334] A wiring layer, including interlayer films, wiring, and connectors, may be provided between component layer LF and component layer UF, or between the k-th component layer UF and the (k+1)-th component layer UF. Furthermore, in this embodiment, the k-th component layer UF is sometimes denoted as component layer UF[k], and the (k+1)-th component layer UF is denoted as component layer UF[k+1]. Here, k is an integer greater than or equal to 1 and less than N. Additionally, in this embodiment, when denoted as "k+α (α is an integer greater than or equal to 1)" or "k-α", the solutions for "k+α" and "k-α" are each integer greater than or equal to 1 and less than N.

[0335] Furthermore, the wiring layer can be configured as multiple layers depending on the design. Additionally, in this specification and other materials, wiring and connectors for connecting to wiring can also be considered components. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a connector.

[0336] For example, in transistor 550, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 are embedded in insulating layers 320 and 322. Furthermore, conductive layers 330 are embedded in insulating layers 324 and 326. Furthermore, conductive layers 328 and 330 are used as contact plugs or wiring.

[0337] Alternatively, a wiring layer can be provided on the insulating layer 326 and the conductive layer 330. For example, in Figure 15In this structure, insulating layers 350, 357, 352, and 354 are sequentially stacked on insulating layer 326 and conductive layer 330. Furthermore, a conductive layer 356 is formed within insulating layers 350, 357, and 352. The conductive layer 356 is used as a contact plug or wiring.

[0338] An insulating layer 514, characteristic of the component layer UF, is provided on the insulating layer 354. Furthermore, a conductive layer 358 is embedded in the insulating layer 514 and the insulating layer 354. The conductive layer 358 is used as a contact plug or wiring. For example, wiring used as bit lines is connected to the transistor 550 via conductive layers 358, 356, and 330.

[0339] like Figure 16A As shown, Figure 15 The storage cell 41E shown includes transistors M2, M3 and M1 on the insulating layer 514.

[0340] Figure 15 and Figure 16A Transistors M2 and M3 shown share a single island-shaped semiconductor layer 530. In other words, a portion of the island-shaped semiconductor layer 530 is used as the channel formation region for transistor M2, and another portion is used as the channel formation region for transistor M3. Furthermore, the source of transistor M2 and the drain of transistor M3, or vice versa, are shared. Therefore, compared to the case where transistors M2 and M3 are disposed independently, the transistors occupy a smaller area.

[0341] Note that in Figure 15 and Figure 16A The memory cell 41E shown can be configured without transistor M1. The memory cell 41E with the configuration of not having transistor M1 can be a dual-transistor type NOSRAM, which is equivalent to... Figure 7D The storage unit 41D shown is shown.

[0342] Here, refer to Figures 17A to 17C Explain the OS transistor. Figure 17A and Figure 17B This is a cross-sectional schematic diagram of transistor 500, which can be used as transistors M1 to M3.

[0343] like Figure 17A and Figure 17BAs shown, an insulating layer 516 is disposed on an insulating layer 514. The transistor 500 includes: a conductive layer 503 disposed in the insulating layer 516; an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 503; an insulating layer 524 disposed on the insulating layer 522; a semiconductor layer 530 disposed on the insulating layer 524; conductive layers 542a and 542b disposed on the semiconductor layer 530 spaced apart from each other; an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening that overlaps between the conductive layers 542a and 542b; an insulating layer 545 disposed on the bottom and side surfaces of the opening; and a conductive layer 560 disposed on the insulating layer 545. The conductive layer 560 includes a conductive layer 560a disposed inside the insulating layer 545 and a conductive layer 560b disposed on the conductive layer 560a in a manner that embeds into the opening.

[0344] In addition, such as Figure 17A and Figure 17B As shown, insulating layer 544 is disposed between semiconductor layer 530, conductive layer 542a and conductive layer 542b and insulating layer 580. Furthermore, insulating layer 574 is disposed on insulating layer 580, conductive layer 560 and insulating layer 545, and insulating layer 581 is disposed on insulating layer 574.

[0345] In transistor 500, conductive layer 560 is used as the gate electrode, insulating layer 545 is used as the gate insulating film, and conductive layers 542a and 542b are used as the source electrode or drain electrode, respectively. Conductive layer 560 is sometimes used as the first gate electrode. Conductive layer 503 is sometimes used as the second gate electrode. Insulating layers 522 and 524 are used as the second gate insulating film.

[0346] In addition, Figure 17A and Figure 17B In the transistor 500 shown, insulating layer 522 and insulating layer 524 are shown as the second gate insulating film, which is a two-layer stacked structure. However, the second gate insulating film may also have a single-layer structure or a stacked structure of three or more layers. In this case, it is not limited to using a stacked structure made of the same material, and a stacked structure made of different materials may also be used.

[0347] In transistor 500, an oxide semiconductor layer is preferably used as the semiconductor layer 530 including the channel formation region. The oxide semiconductor layer that can be used as semiconductor layer 530 will be described in Embodiment 4 described later.

[0348] In the channel formation region of a transistor where an oxide semiconductor is used as the semiconductor layer, it is preferable that the number of oxygen vacancies (V0) is higher than that of the source and drain regions. OThe concentration of impurities such as hydrogen, nitrogen, and metal elements is low. Additionally, hydrogen near oxygen vacancies sometimes forms defects (hereinafter sometimes referred to as V0) that allow hydrogen to enter oxygen vacancies. O H) generates electrons that become charge carriers, so V is generated in the channel formation region. O H is also preferably reduced. Thus, the channel formation region of the transistor is a high-resistivity region with low carrier concentration. Therefore, the channel formation region of the transistor can be described as i-type (intrinsic) or substantially i-type.

[0349] Furthermore, the source and drain regions of transistors using oxide semiconductors as semiconductor layers are as follows: Due to the higher number of oxygen vacancies compared to the channel formation region, V... O High concentrations of impurities such as hydrogen, nitrogen, and metals increase carrier concentration, resulting in lower resistance. In other words, compared to the channel region, the source and drain regions of a transistor are n-type regions with higher carrier concentration and lower resistance.

[0350] The bandgap of the oxide semiconductor is preferably 2 eV or higher, more preferably 2.5 eV or higher. By using an oxide semiconductor with a large bandgap as the semiconductor layer, the off-state current of the transistor can be reduced. By using transistors with low off-state current in the memory cells, the stored content can be retained for a long time. In other words, refresh operations are not required or the refresh frequency is extremely low, thereby significantly reducing the power consumption of the semiconductor device.

[0351] Figure 17A and Figure 17B The semiconductor layer 530 is shown as a single layer, but the invention is not limited thereto. For example, the semiconductor layer 530 may also be a stacked structure of two or more layers.

[0352] When an oxide semiconductor is used as the semiconductor layer 530, such as Figure 17A As shown, sometimes a region 543a is formed at and near the interface between the semiconductor layer 530 and the conductive layer 542a as a low-resistance region. Similarly, sometimes a region 543b is formed at and near the interface between the semiconductor layer 530 and the conductive layer 542b as a low-resistance region. In this case, regions 543a and 543b are used as source regions or drain regions, respectively. Furthermore, a channel forming region is formed in the region sandwiched between regions 543a and 543b.

[0353] Note that the semiconductor material that can be used for semiconductor layer 530 is not limited to oxide semiconductor. Semiconductor materials other than oxide semiconductors can also be used as semiconductor layer 530. Other semiconductor materials that can be used for semiconductor layer 530 will be described later in the section on [Other Semiconductor Materials].

[0354] exist Figure 17AThe conductive layers 542a and 542b are single-layer structures, but the present invention is not limited thereto. For example, the conductive layers 542a and 542b can also be stacked structures of two or more layers.

[0355] exist Figure 17A and Figure 17B The conductive layer 560 and the conductive layer 503 are two-layer structures, but the present invention is not limited thereto. For example, the conductive layer 560 and the conductive layer 503 can also be single-layer structures or stacked structures of three or more layers.

[0356] The insulating layer 580 is preferably disposed on the conductive layers 542a and 542b, with the insulating layer 544 as a buffer. The opening of the insulating layer 580 is formed to overlap with the area between the conductive layers 542a and 542b. Thus, the conductive layer 560 is disposed such that it is embedded in the opening of the insulating layer 580 and sandwiched in the area between the conductive layers 542a and 542b.

[0357] When an oxide semiconductor is used as the semiconductor layer 530, an insulator containing oxygen (hereinafter sometimes referred to as excess oxygen) that has been removed by heating is preferably used as the insulating layer 580. By heat-treating the insulating layer 580 containing excess oxygen, oxygen can be supplied from the insulating layer 580 to the channel formation region of the semiconductor layer 530, thereby reducing oxygen vacancies and Vo. O H. This allows the electrical characteristics of transistor 500 to be stabilized, thereby improving its reliability.

[0358] exist Figure 17A and Figure 17B The insulating layer 545 is a single-layer structure, but the present invention is not limited thereto. For example, the insulating layer 545 may also be a stacked structure of two or more layers.

[0359] The insulating layer 544 is provided to cover the conductive layers 542a and 542b. The insulating layer 544 preferably has oxygen-barrier properties. By employing this structure, oxidation of the conductive layers 542a and 542b can be suppressed.

[0360] An insulating layer 571a is disposed on a conductive layer 542a, and an insulating layer 571b is disposed on a conductive layer 542b. By providing insulating layers 571a and 571b, over-etching of the ends of conductive layers 542a and 542b can be prevented when the semiconductor film that will become semiconductor layer 530 and the conductive films that will become conductive layers 542a and 542b are processed into island shapes in one step. As a result, miniature transistors can be fabricated with high precision.

[0361] The insulating layer 574 preferably has the function of suppressing the diffusion of impurities such as hydrogen. Furthermore, the insulating layer 574 preferably has the function of trapping or fixing impurities such as hydrogen. By employing this structure, hydrogen diffusion into the semiconductor layer 530 can be suppressed. In addition, the hydrogen concentration in the semiconductor layer 530 can be reduced.

[0362] A conductive layer 540a is disposed in the openings of insulating layers 581, 574, 580, 544, and 571a, and a conductive layer 540b is disposed in the openings of insulating layers 581, 574, 580, 544, and 571b. The conductive layers 540a and 540b are disposed opposite to each other with a conductive layer 560 between them. The conductive layers 540a and 540b are used as through holes, contact plugs, or wiring.

[0363] exist Figure 17A The conductive layer 540a and conductive layer 540b are two-layer stacked structures, but the present invention is not limited thereto. For example, the conductive layer 540a and conductive layer 540b can be single-layer structures or stacked structures of three or more layers, respectively.

[0364] Figure 17A and Figure 17B The structure of transistor 500 shown is just an example and is not limited to the structure described above. Appropriate transistors can be used depending on the circuit structure, driving method, etc.

[0365] Note that the transistors that can be used in this invention are not limited to those in the present invention. Figure 17A and Figure 17B The transistor 500 is shown. For example, it can also be used... Figure 17C The transistor 500 shown has the following structure. Figure 17C The transistor 500 shown is Figure 17A and Figure 17B The difference of the transistor 500 shown is that, in the former, conductive layers 542a and 542b have a stacked structure; and insulating layers 520 and 555 are provided.

[0366] Figure 17CThe transistor 500 shown has a conductive layer 542a with a stacked structure of conductive layer 542a1 and conductive layer 542a2 on conductive layer 542a1, and a conductive layer 542b with a stacked structure of conductive layer 542b1 and conductive layer 542b2 on conductive layer 542b1. The conductive layers 542a1 and 542b1, which are in contact with the semiconductor layer 530, are preferably made of conductive materials that are not easily oxidized, such as metal nitrides. This prevents excessive oxidation of the conductive layers 542a and 542b due to oxygen contained in the semiconductor layer 530. Furthermore, the conductive layers 542a2 and 542b2 are preferably made of conductive materials with higher conductivity than the conductive layers 542a1 and 542b1. Therefore, the conductive layers 542a and 542b can be used as highly conductive wiring or electrodes. Thus, a semiconductor device can be provided in which conductive layers 542a and 542b, used as wiring or electrodes, are disposed in a manner that contacts the top surface of the semiconductor layer 530.

[0367] like Figure 17C As shown, when viewed in cross-section along the channel length of transistor 500, the distance between conductive layers 542a1 and 542b1 is smaller than the distance between conductive layers 542a2 and 542b2. By employing this structure, the distance between the source and drain can be further shortened, and correspondingly, the channel length can be shortened. Furthermore, by employing a stacked structure of conductive layers 542a2 and 542b1, and a stacked structure of conductive layers 542b1 and 542b2, non-uniformity in the manufacturing process of transistor 500 can be reduced. More specifically, by processing conductive layers 542a1 and 542b1 after processing conductive layers 542a2 and 542b2, non-uniformity in the manufacturing process of transistor 500 can be reduced. Therefore, the frequency characteristics of transistor 500 can be improved, and a semiconductor device with high yield can be achieved. Thus, by miniaturizing the semiconductor device, a semiconductor device with increased operating speed can be provided.

[0368] The insulating layer 555 is disposed in contact with the sides of the conductive layer 542a2 and the sides of the conductive layer 542b2. The insulating layer 555 preferably has the function of inhibiting oxygen diffusion. By employing this structure, oxidation of the sides of the conductive layer 542a2 and the sides of the conductive layer 542b2 can be suppressed.

[0369] The insulating layer 520 preferably has hydrogen-barrier properties. This can suppress hydrogen diffusion into the semiconductor layer 530 and reduce the hydrogen concentration in the semiconductor layer 530.

[0370] By adopting this structure, miniaturization or high integration of semiconductor devices using transistors containing oxide semiconductors can be achieved.

[0371] Note that the transistors that can be used in this invention are not limited to those in the present invention. Figure 17A and Figure 17C The transistor 500 is shown. Figures 18A to 18D Explanation and Figures 17A to 17C The transistors shown have different structures. Figure 18A This is a plan view of transistor 500A, which can be used in transistors M1 to M3 mentioned above. Furthermore, Figures 18B to 18D This is a cross-sectional view of the 500A transistor.

[0372] Figure 18B It is along Figure 18A The cross-sectional view of the section with dotted lines A1-A2 is also a cross-sectional view of the channel width direction of transistor 500A. Figure 18C It is along Figure 18A The cross-sectional view of the dashed lines A3-A4 in the figure is equivalent to the cross-sectional view of the transistor 500A in the channel width direction. Figure 18D It is along Figure 18A The cross-sectional view of the section marked with dotted lines A5-A6 is also a cross-sectional view along the channel length of transistor 500A. Here, the dotted lines A5-A6 are orthogonal to the dotted lines A1-A2 and A3-A4, and the dotted lines A1-A2 are parallel to the dotted lines A3-A4. Note that in... Figure 18A In the plan view, for clarity, some constituent elements are omitted and shown in a transparent manner.

[0373] Transistor 500A includes an insulating layer 516 on a substrate (not shown), an insulator 521 on the insulating layer 516, an insulating layer 522 on the insulator 521, a semiconductor layer 530 on the insulating layer 522, conductive layers 542a and 542b on the semiconductor layer 530 and the insulating layer 522, an insulating layer 545 on the semiconductor layer 530, and conductive layers 560 (conductive layers 560a and 560b) on the insulating layer 545. Note that conductive layers 542a and 542b are sometimes collectively referred to as conductive layer 542 below.

[0374] An insulator 575 is disposed on the conductive layer 542, and an insulating layer 580 is disposed on the insulator 575. The insulating layer 545 and the conductive layer 560 are disposed inside an opening disposed in the insulating layer 580 and the insulator 575. This opening reaches the semiconductor layer 530, and the insulating layer 545 is in contact with the semiconductor layer 530 within this opening. In addition, an insulating layer 574 is disposed on the insulating layer 580 and the conductive layer 560. Furthermore, an insulator 583 is disposed on the insulating layer 574. In addition, an insulator 515 is disposed below the insulating layer 516.

[0375] An insulator 541a is provided in contact with the inner wall of an opening in an insulating layer 580, etc., and a conductive layer 540a is provided in contact with the side surface of the insulator 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulator 541b is provided in contact with the inner wall of an opening in an insulating layer 580, etc., and a conductive layer 540b is provided in contact with the side surface of the insulator 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Hereinafter, conductive layers 540a and 540b are sometimes collectively referred to as conductive layer 540. Furthermore, insulators 541a and 541b are sometimes collectively referred to as insulator 541.

[0376] Semiconductor layer 530 has a region serving as a channel formation region for transistor 500A. Additionally, conductive layer 560 has a region serving as a first gate electrode (upper gate electrode) for transistor 500A. Insulating layer 545 has a region serving as a first gate insulator for transistor 500A.

[0377] Conductive layer 542a has a region that serves as one of the source and drain electrodes of transistor 500A. Conductive layer 540a is used as a connector to conductive layer 542a. Conductive layer 542b has a region that serves as the other of the source and drain electrodes of transistor 500A. Conductive layer 540b is used as a connector to conductive layer 542b.

[0378] The semiconductor layer 530 is formed in contact with the insulating layer 522. The semiconductor layer 530 has a high aspect ratio shape when viewed in cross-section along the channel width direction (a shape where the length (H) in the height direction is greater than or equal to the length (W) of the base side (H≥W)). The semiconductor layer 530 with its high aspect ratio shape can sometimes be described as having a fin-like shape.

[0379] Here, the aspect ratio of the semiconductor layer 530 when viewed in cross-section along the channel width direction refers to the ratio of the width L of the semiconductor layer 530 to the height H of the semiconductor layer 530. The aspect ratio of the semiconductor layer 530 is preferably as large as possible within a range that will not cause the semiconductor layer 530 to collapse during the manufacturing process of the transistor 500A. In the semiconductor layer 530, the height H is at least greater than the width L. The height H of the semiconductor layer 530 is set to be greater than 1 times and less than 400 times the width L, preferably more than 2 times and less than 100 times, more preferably more than 5 times and less than 40 times, and even more preferably more than 10 times and less than 20 times. Alternatively, for example, the height H may also be more than 2 times and less than 10 times the width L. For example, the width L is set to 5 nm and less than 100 nm, preferably 5 nm and less than 50 nm, and more preferably 10 nm and less than 30 nm. Alternatively, for example, the height H can be set to 50 nm or more and 2000 nm or less, preferably 100 nm or more and 1000 nm or less. Furthermore, for example, the height H can also be 50 nm or more and 100 nm or less.

[0380] Furthermore, when viewed in cross-section along the channel width, the angle formed by the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably a right angle or approximately a right angle. For example, the angle formed by the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably 80° or more and 100° or less, more preferably 85° or more and 95° or less.

[0381] An insulating layer 545, a conductive layer 560, and a conductive layer 542 are provided to cover the high aspect ratio semiconductor layer 530 described above. In the transistor 500A, a portion of the insulating layer 545 and the conductive layer 560 are provided in a folded state, sandwiching the semiconductor layer 530. Thus, when viewed in cross-section along the channel width direction, the semiconductor layer 530 and the conductive layer 560 are disposed opposite each other, sandwiching the insulating layer 545 on the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530. In other words, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530 are all used as channel formation regions. Therefore, compared to the case where the semiconductor layer 530 is formed as a flat plate, the channel width of the transistor 500A is increased by the size of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 530.

[0382] As described above, increasing the channel width improves the on-state current, transconductance, and frequency characteristics of transistor 500A. This allows for the provision of a transistor with high operating speed. Furthermore, it increases the operating speed of memory devices using this transistor. Additionally, in the above structure, by providing the semiconductor layer 530, the channel width can be increased without expanding the occupied area of ​​transistor 500A. This enables miniaturization or high integration of semiconductor devices. Moreover, by adopting the above structure, the area of ​​the sides of the conductive layer 560 and the semiconductor layer 530 relative to each other is increased, thus allowing for threshold control to keep transistor 500A in a normally off state.

[0383] Furthermore, the upper part of the semiconductor layer 530 may also have a curved shape. By having this curved shape, defects such as voids can be prevented from forming in the insulating layer 545 and the conductive layer 542 near the upper part of the semiconductor layer 530.

[0384] Since the semiconductor layer 530 has a high aspect ratio shape, it is preferably formed as a sidewall on the side of the pillar made of insulator. Therefore, the semiconductor layer 530 is preferably formed using the ALD method, which provides good coverage. Furthermore, when the semiconductor layer 530 has a stacked structure, it is preferable to deposit at least one layer using the ALD method, preferably the layer in contact with the pillar.

[0385] The semiconductor layer 530 is formed into a sidewall shape by contacting the sides of multiple pillars, such as... Figure 18A As shown, multiple semiconductor layers 530 can be formed simultaneously. Thus, by forming multiple semiconductor layers 530, the distance between each semiconductor layer 530 can be set according to the size and shape of the pillar. This reduces the distance between the semiconductor layers 530 and decreases the area occupied by the transistor 500A, thereby achieving high integration of the transistor.

[0386] Because the semiconductor layer 530 is formed as a sidewall in a manner that contacts the pillar, therefore... Figure 18A As shown, the top surface of semiconductor layer 530 has a circumferential shape (also referred to as a frame, ring, donut, or closed curve) with both ends aligned. Alternatively, semiconductor layer 530 can be described as having a shape including an opening in the central portion. Note that in... Figure 18A In this invention, the top surface of semiconductor layer 530 has a linearly symmetrical shape centered on A1-A2, but the invention is not limited to this. For example, the top surface of semiconductor layer 530 can also be an asymmetrical shape.

[0387] exist Figure 18A In the structure shown, two pillars are arranged along the dotted line A1-A2, and a circumferential semiconductor layer 530 is formed in contact with the side of each pillar. For example... Figure 18AAs shown, the semiconductor layer 530 preferably overlaps with the conductive layer 560 in two or more locations when viewed from a planar perspective. That is, the structure has two or more regions where the semiconductor layer 530 and the conductive layer 560 overlap. By adopting this structure, as... Figure 18B As shown, multiple fin-shaped semiconductor layers 530 are formed when viewed in cross-section along the channel width direction. Each of the multiple fin-shaped semiconductor layers 530 serves as a channel formation region. In other words, transistor 500A is used as a multi-channel transistor. Therefore, the channel width can be further increased in transistor 500A.

[0388] In addition, such as Figures 19A to 19D The transistor 500B shown in the figure can be used for Figures 18A to 18D The transistor 500A of transistors M1 to M3 described above can also adopt a structure in which a conductive layer 503 is provided under the insulator 521. The conductive layer 503 has a region that serves as the second gate electrode (lower gate electrode) of transistor 500B. Furthermore, the insulating layer 522 and the insulator 521 each have a region that serves as the second gate insulator of transistor 500B. Here, Figures 19A to 19D Corresponding to Figures 18A to 18D Therefore, for details about the structure, please refer to the above description.

[0389] In transistor 500B, conductive layer 503 is disposed in a manner that overlaps with semiconductor layer 530 and conductive layer 560. Here, conductive layer 503 is preferably disposed in a manner that embeds it within an opening in insulating layer 516. Furthermore, as... Figure 19A and Figure 19B As shown, the conductive layer 503 is preferably provided extending in the channel width direction. By adopting this structure, the conductive layer 503 is used as wiring when multiple transistors are disposed.

[0390] like Figure 19B and Figure 19D As shown, the conductive layer 503 preferably includes a conductive layer 503a and a conductive layer 503b. The conductive layer 503a is disposed in contact with the bottom surface and sidewall of the opening. The conductive layer 503b is disposed in a recess of the conductive layer 503a formed along the opening. Here, the height of the top surface of the conductive layer 503 is the same as or approximately the same as the height of the top surface of the insulating layer 516.

[0391] Here, the conductive layer 503a preferably comprises a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to comprise a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0392] By using a conductive material having a function of suppressing hydrogen diffusion as the conductive layer 503a, impurities such as hydrogen contained in the conductive layer 503b can be prevented from diffusing into the semiconductor layer 530 through the insulating layer 516 or the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion as the conductive layer 503a, oxidation of the conductive layer 503b can be suppressed and the conductivity can be prevented from decreasing. Examples of the conductive material having a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 503a may have a single-layer structure or a laminated structure of the above-mentioned conductive materials. For example, the conductive layer 503a preferably contains titanium nitride.

[0393] In addition, the conductive layer 503b preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. For example, the conductive layer 503b preferably contains tungsten.

[0394] The conductive layer 503 can be used as a second gate electrode. In this case, by independently changing the potential applied to the conductive layer 503 without linking it to the potential applied to the conductive layer 560, the threshold voltage (Vth) of the transistor 500B can be controlled. In particular, by applying a negative potential to the conductive layer 503, the Vth of the transistor 500B can be further increased to reduce the off-state current. Therefore, compared with the case where no negative potential is applied to the conductive layer 503, the drain current when the potential applied to the conductive layer 560 is 0V can be reduced in the case where a negative potential is applied to the conductive layer 503.

[0395] In addition, the resistivity of the conductive layer 503 is designed in consideration of the potential applied to the conductive layer 503 as described above, and the thickness of the conductive layer 503 is set according to this resistivity. In addition, the thickness of the insulating layer 516 is substantially the same as that of the conductive layer 503. Here, it is preferable to reduce the thicknesses of the conductive layer 503 and the insulating layer 516 within the range allowed by the design of the conductive layer 503. By reducing the thickness of the insulating layer 516, the absolute amount of impurities such as hydrogen contained in the insulating layer 516 can be reduced, so that the diffusion of the impurities into the semiconductor layer 530 can be suppressed.

[0396] Note that in the above structure, a laminated structure of the conductive layer 503a and the conductive layer 503b is shown, but the present invention is not limited thereto, and the conductive layer 503 may have a single-layer structure or a laminated structure of three or more layers. For example, when the conductive layer 503 has a three-layer laminated structure, the above-mentioned laminated structure of the conductive layer 503a and the conductive layer 503b can be adopted and a conductive layer containing the same material as the conductive layer 503a can be further provided on the conductive layer 503b. At this time, the conductive body may also be formed in such a manner that the top surface of the conductive layer 503b is lower than the uppermost part of the conductive layer 503a and is embedded in the recess formed by the conductive layer 503a and the conductive layer 503b.

[0397] <Structural example of DOSRAM>

[0398] Figure 20 An example of a cross-sectional structure is shown when using a circuit structure with DOSRAM. Figure 20 An example is shown where component layers UF[1] to UF[3] are stacked on component layer LF. Furthermore, Figure 21A An example of the cross-sectional structure of the element layer UF[k] is shown. Furthermore, Figure 21B yes Figure 21A The equivalent circuit diagram.

[0399] exist Figure 20 In the middle, each of the multiple component layers UF includes multiple storage units 41. Figure 20 An example is shown in which one bit line BL in each of the element layers UF[1] to UF[3] is connected to two memory cells 41. Figure 20 The storage cell 41 shown includes a transistor M1 and a capacitor C1. Figure 20 In the storage cell 41 shown, capacitor C1 is positioned below transistor M1. Transistor M1 can be an OS transistor.

[0400] Furthermore, conductive layers 363a, 363b, and 363c are embedded in the interlayer film between element layer LF and element layer UF[1]. Furthermore, in each of the multiple element layers UF, conductive layer 365 is embedded in insulating layer 180 (described later). Furthermore, in each of the multiple element layers UF, conductive layer 366 is embedded in insulating layer 180 and insulating layer 280 (described later). Furthermore, in each of the multiple element layers UF, conductive layer 367 is embedded in semiconductor layer 270, insulating layer 250, and insulating layer 285 (described later). Conductive layers 363a, 363b, 363c, 365, 366, and 367 are used as through-holes, contact plugs, or wiring.

[0401] Next, the explanation Figure 20 The diagram shows a structural example of the storage unit 41 included in the multiple element layers UF.

[0402] Figure 22A This is a plan view showing an example of the structure of the memory cells 41 included in each of the multiple element layers UF and their vicinity. Figure 22B It is an omission Figure 22A A plan view of a portion of the constituent elements shown. Figure 22C It is along Figure 22A The cross-sectional view shown is the dotted-dotted line A1-A2. Note, for example, in... Figure 22A In the diagram, some components of transistor VM1, such as the insulating layer 250, are omitted. Furthermore, in subsequent transistor planar diagrams, some components such as the insulating layer are also omitted.

[0403] exist Figures 22A to 22CIn the diagram, transistor VM1 is equivalent to... Figure 20 In the transistor M1, capacitor VC1 is equivalent to Figure 20 Capacitor C1 in the middle.

[0404] exist Figure 22C In the figure, insulating layer 160 is disposed on substrate (not shown), insulating layer 180 is disposed on insulating layer 160, insulating layer 280 is disposed on insulating layer 180, and insulating layer 285 is disposed on insulating layer 280.

[0405] A conductive layer 110 is disposed on the insulating layer 160. As an example, the conductive layer 110 may be a wiring PL extending in the Y direction.

[0406] An opening 601 is provided in the region where the insulating layer 180 overlaps with the conductive layer 110. A conductive layer 115 is provided in contact with the bottom surface and sidewalls of the opening 601. That is, the conductive layer 115 has a region in the opening 601 that contacts the top surface of the conductive layer 110 and a region that contacts the side surface of the insulating layer 180. Note that in Figure 22C The intermediate conductive layer 115 has a region that contacts the top surface of the insulating layer 180.

[0407] An insulating layer 130 is provided on the insulating layer 180 and the conductive layer 115. Furthermore, a conductive layer 220 is provided on the insulating layer 130. The conductive layer 220 is provided in a manner that it is embedded in the opening 601.

[0408] The capacitor VC1 includes a conductive layer 115, a conductive layer 220, and an insulating layer 130.

[0409] In capacitor VC1, conductive layer 115 is used as one of a pair of electrodes, conductive layer 220 is used as the other of a pair of electrodes, and insulating layer 130 is used as a dielectric material sandwiched between the pair of electrodes.

[0410] A transistor VM1 is disposed above the capacitor VC1. The transistor VM1 includes a conductive layer 220, a conductive layer 240, a semiconductor layer 270, an insulating layer 250, and a conductive layer 260.

[0411] In transistor VM1, conductive layer 260 is used as the gate electrode, and insulating layer 250 is used as the gate insulating film. Conductive layers 220 and 240 are used as the source electrode or drain electrode, respectively. Note that, as mentioned above, conductive layer 220 is also used as the other of a pair of electrodes in capacitor VC1.

[0412] In semiconductor layer 270, the entire area between the source electrode and the drain electrode, separated by a gate insulating film and opposite to the gate electrode, is used as a channel forming region. Furthermore, in semiconductor layer 270, the region in contact with the source electrode is used as the source region, and the region in contact with the drain electrode is used as the drain region.

[0413] Insulating layer 280 can be used as an interlayer insulating layer. Here, interlayer insulating layer can refer to the interlayer film used to separate the source electrode and drain electrode in transistor VM1.

[0414] An insulating layer 280 is provided with a conductive layer 240. The insulating layer 280 is provided with an opening 602 that reaches the conductive layer 220. The conductive layer 240 is provided with an opening 603 that reaches the opening 602. That is, the opening 603 has a region that overlaps with the opening 602.

[0415] Figure 22A The conductive layer 220, conductive layer 240, conductive layer 260, opening 602, and opening 603 are shown. Here, Figure 22B Shown in Figure 22A The structural example shown omits the conductive layer 260 in the constituent elements. That is to say, Figure 22B The conductive layer 220, conductive layer 240, opening 602, and opening 603 are shown.

[0416] Figure 22A and Figure 22B An example is shown where the shapes of openings 602 and 603 are both circular when viewed from a plane. By making the planar shapes (shapes and edges of the object when viewed from a plane) of openings 602 and 603 circular, the processing precision during the formation of openings 602 and 603 can be improved, allowing for the formation of fine openings 602 and 603. This enables miniaturization or high integration of memory cells. Note that in this specification, the circle is not limited to a perfect circle. For example, the planar shapes of openings 602 and 603 can also be elliptical or curved. Alternatively, they can be polygonal or polygonal with rounded corners.

[0417] The description of the shapes of openings 602 and 603 can be applied to opening 601.

[0418] The conductive layer 240 is preferably not disposed inside the opening 602. That is, the conductive layer 240 preferably does not contact the side of the insulating layer 280 on the side of the opening 602. By adopting this structure, the opening 603 and the opening 602 can be formed in one step, thereby simplifying the process.

[0419] Figure 22C An example is shown where the bottom end of the conductive layer 240 in the opening 603 coincides with or substantially coincides with the top end of the insulating layer 280 in the opening 602. Note that in this specification, the bottom surface of the conductive layer 240 refers to the surface on one side of the insulating layer 280. The top surface of the insulating layer 280 refers to the surface on one side of the conductive layer 240.

[0420] Note that "end-to-end alignment" or "approximate alignment" can also be described as "end-to-end alignment" or "approximate alignment." In cases of end-to-end alignment or approximate alignment, and in cases of consistent or approximate planar shapes, it can be said that, when viewed in a plane, at least a portion of the edges overlap between the stacked layers. For example, this includes cases where the upper and lower layers are processed from the same mask pattern or a portion thereof. However, there are actually cases where the edges do not overlap, sometimes with the upper layer located inside or outside the lower layer; in these cases, it can also be described as "approximately aligned ends" or "approximately consistent planar shapes."

[0421] Hereinafter, the opening including opening 602 and opening 603 will sometimes be referred to as opening 290. That is, the insulating layer 280 and the conductive layer 240 are provided with opening 290 that leads to the conductive layer 220. Furthermore, opening 602 is a part of opening 290 and opening 603 is another part of opening 290.

[0422] At least a portion of the semiconductor layer 270 is disposed in the opening 290. The semiconductor layer 270 has a region in the opening 290 that contacts the side surface of the conductive layer 240, a region that contacts the side surface of the insulating layer 280, and a region that contacts the top surface of the conductive layer 220. The semiconductor layer 270 has a region that contacts the top surface of the conductive layer 240.

[0423] At least a portion of the insulating layer 250 is disposed in the opening 290. The insulating layer 250 is disposed on the semiconductor layer 270 and the insulating layer 280. The insulating layer 250 has a region that contacts the top surface of the semiconductor layer 270, a region that contacts the side surface of the semiconductor layer 270, a region that contacts the side surface of the conductive layer 240, and a region that contacts the top surface of the insulating layer 280.

[0424] A conductive layer 260 is disposed on an insulating layer 250 and has a region that contacts the top surface of the insulating layer 250. The conductive layer 260 is disposed such that it is embedded in an opening 290. The conductive layer 260 is disposed such that it is embedded in a recess in the insulating layer 250 that reflects the shape of the opening 290. The conductive layer 260 has a region that overlaps with the semiconductor layer 270 across the insulating layer 250.

[0425] Figure 22C An example is shown where the conductive layer 260 overlaps with the conductive layer 240 across the insulating layer 250 and the semiconductor layer 270, but the invention is not limited thereto. For example, the conductive layer 260 may also be disposed without overlapping the conductive layer 240. By employing this structure, the parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be reduced. Therefore, the operating speed of the memory cell can be further improved.

[0426] Transistor VM1 has the following structure: the direction of the channel length is not approximately parallel to the substrate (not shown) but along the sidewall of the opening 602 provided in the insulating layer 280. Therefore, transistor VM1 is a vertical transistor.

[0427] Figure 22A An example is shown where the conductive layer 240 extends in a direction perpendicular to the conductive layers 110 and 260.

[0428] Here, Figure 23A Show Figure 22C An enlarged view of the semiconductor layer 270 and its vicinity is shown. Furthermore, Figure 23B A cross-sectional view of the XY plane including the conductive layer 240 is shown.

[0429] like Figure 23A As shown, the semiconductor layer 270 has region 270i, region 270na and region 270nb disposed in a manner that sandwiches region 270i.

[0430] Region 270na is the region in semiconductor layer 270 that contacts conductive layer 220. Region 270nb is the region in semiconductor layer 270 that contacts conductive layer 240. Regions 270na and 270nb each serve as the source or drain region of transistor VM1. Figure 23B As shown, the conductive layer 240 contacts the entire outer periphery of the semiconductor layer 270. Therefore, the source or drain region of the transistor VM1 may be formed on the entire outer periphery of the portion of the semiconductor layer 270 formed in the same layer as the conductive layer 240.

[0431] Region 270i is the region in semiconductor layer 270 sandwiched between regions 270na and 270nb. Region 270i is used as the channel formation region of transistor VM1. That is, the channel formation region of transistor VM1 is formed in a portion of semiconductor layer 270 located between conductive layer 220 and conductive layer 240. Alternatively, it can be said that the channel formation region of transistor VM1 is located in or near the region of semiconductor layer 270 that is in contact with insulating layer 280.

[0432] The channel length of transistor VM1 is the distance between the source and drain regions. In other words, the channel length of transistor VM1 can be said to be determined by the thickness of the insulating layer 280 on the conductive layer 220. Figure 23A In the diagram, the channel length L of transistor VM1 is represented by a dashed double arrow. Viewed in cross-section, the channel length L is the distance from the end of the region where semiconductor layer 270 contacts conductive layer 220 to the end of the region where semiconductor layer 270 contacts conductive layer 240. In other words, the channel length L is equivalent to the length of the side surface of the opening 602 of insulating layer 280 when viewed in cross-section.

[0433] In planar transistors, the channel length is determined based on the exposure limit of photolithography. However, in this invention, the channel length can be determined based on the thickness of the insulating layer 280. Therefore, the channel length of transistor VM1 can be set to a very fine structure below the exposure limit of photolithography. This increases the on-state current of transistor VM1, improving its frequency characteristics. Consequently, a semiconductor device with high operating speed can be provided.

[0434] Furthermore, as described above, a channel forming region, a source region, and a drain region can be formed in the opening 290. Therefore, compared to a planar transistor where the channel forming region, source region, and drain region are respectively provided on the XY plane, the occupied area of ​​the transistor VM1 can be reduced. As a result, the semiconductor device can be highly integrated, thus increasing the storage capacity per unit area.

[0435] In addition, with Figure 23B Similarly, on the XY plane including the channel formation region of semiconductor layer 270, semiconductor layer 270, insulating layer 250, and conductive layer 260 are arranged in a concentric circle. Therefore, the side of the conductive layer 260 located at the center faces the side of semiconductor layer 270 across insulating layer 250. In other words, when viewed from the plane, the entire outer periphery of semiconductor layer 270 forms the channel formation region. At this time, for example, the channel width of transistor VM1 is determined by the length of the outer periphery of semiconductor layer 270. That is, the channel width of transistor VM1 is determined by the maximum width of opening 602. Figure 23A and Figure 23B In the diagram, the double-headed arrow with a double dotted line represents the maximum width D of the opening 602. Figure 23B The double-headed dotted arrow represents the channel width W of transistor VM1. By increasing the maximum width D of the opening 602, the channel width per unit area can be increased, thereby increasing the on-state current.

[0436] When forming the opening 602 using photolithography, the maximum width D of the opening 602 is set according to the exposure limit of the photolithography method. Furthermore, the maximum width D of the opening 602 is set according to the thickness of each of the semiconductor layer 270, insulating layer 250, and conductive layer 260 disposed in the opening 602. Note that when the shape of the opening 602 is circular when viewed from a plane, the maximum width D of the opening 602 is equivalent to the diameter of the opening 602, and the channel width W can be calculated as "D×π".

[0437] At this point, the maximum width D of the opening 602 can be appropriately calculated based on the shape of the opening 602 when viewed from a plane. For example, when the opening 602 is a quadrilateral when viewed from a plane, the maximum width of the opening 602 is preferably the length of the diagonal of the quadrilateral. Alternatively, for example, when the shape of the opening 602 when viewed from a plane is an ellipse, a polygon, or a polygon with rounded corners, the maximum width of the opening 602 is preferably the diameter of the smallest circle (also called the smallest containing circle) that includes the shape of the opening 602 when viewed from a plane.

[0438] Furthermore, in one embodiment of the semiconductor device of the present invention, the channel length L of transistor VM1 is preferably at least smaller than the channel width W of transistor VM1. In one embodiment of the present invention, the channel length L of transistor VM1 is at least 0.1 times and less than 0.99 times the channel width W of transistor VM1, preferably at least 0.5 times and less than 0.8 times. By employing this structure, a transistor with good electrical characteristics and high reliability can be realized.

[0439] Furthermore, by forming the opening 602 in a manner that is approximately circular when viewed from a plane, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are arranged in a concentric circle. As a result, the distance between the conductive layer 260 and the semiconductor layer 270 is approximately uniform, so a gate electric field can be applied to the semiconductor layer 270 approximately uniformly.

[0440] Note that in Figure 23A In the example, the opening 602 is provided such that the side surface of the opening 602 is perpendicular to the top surface of the conductive layer 220, but the present invention is not limited to this. For example, the side surface of the opening 602 may also be tapered.

[0441] In this specification and the like, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is disposed at an angle relative to the substrate surface. For example, it is preferable to have a region having an angle (also called a cone angle) of less than 90° formed by the inclined side surface and the substrate surface.

[0442] like Figure 22C As shown, a portion of the insulating layer 250 is located outside the opening 603, i.e., on the insulating layer 280. In this case, the insulating layer 250 preferably covers the side end of the conductive layer 240. This prevents a short circuit between the conductive layer 260 and the conductive layer 240.

[0443] As semiconductor layer 270, a single layer or a stack of semiconductors that can be used in semiconductor layer 530 can be used. Furthermore, the structure of semiconductor layer 270 can also refer to the structure of semiconductor layer 530 described above.

[0444] Semiconductor layer 270 preferably has layered crystals that are substantially parallel to the sides of insulating layer 280 in opening 602. By adopting this structure, the layered crystals of semiconductor layer 270 are substantially parallel to the channel length direction of transistor VM1, thus increasing the on-state current of transistor.

[0445] When the semiconductor layer 270 contacts the conductive layer 220, metal compounds or oxygen vacancies are formed, and region 270na of the semiconductor layer 270 is reduced in resistance. By reducing the resistance of the semiconductor layer 270 in contact with the conductive layer 220, the contact resistance between the semiconductor layer 270 and the conductive layer 220 can be reduced. Similarly, when the semiconductor layer 270 contacts the conductive layer 240, region 270nb of the semiconductor layer 270 is reduced in resistance. This reduces the contact resistance between the semiconductor layer 270 and the conductive layer 240.

[0446] The conductive layer 240 can be a stacked structure of a first conductive layer and a second conductive layer on the first conductive layer. In this case, a highly conductive material can be used to form the first conductive layer, and an oxygen-containing conductive material can be used to form the second conductive layer. When an oxide semiconductor is used as the semiconductor layer 270, by using an oxygen-containing conductive material as the second conductive layer of the conductive layer 240 that contacts the semiconductor layer 270, the contact resistance between the second conductive layer of the conductive layer 240 and the semiconductor layer 270 can be reduced, thereby suppressing the decrease in the on-state current of the transistor VM1 caused by this contact resistance. For example, it is preferable to use tungsten as the first conductive layer of the conductive layer 240 and indium tin oxide containing silicon as the second conductive layer of the conductive layer 240.

[0447] The conductive layer 220 has a recess at a position overlapping with the opening 602. Furthermore, the semiconductor layer 270 contacts the bottom and side surfaces of the recess in the conductive layer 220. Note that the recess in the conductive layer 220 can also be considered part of the opening 290.

[0448] By having a recess in the conductive layer 220 at the location overlapping with the opening 602, compared to the case without the recess, the height of the bottom surface of the insulating layer 250 and the bottom surface of the conductive layer 260 within the opening 290 can be lower than the height of the top surface of the conductive layer 220 that contacts the insulating layer 280, when the top surface of the insulating layer 160 is used as a reference. Here, the height of each surface can be determined based on the surface where the memory cell or transistor is formed. Here, the top surface of the insulating layer 160 is used as the reference. There is no particular limitation on the surface used as the reference; for example, the top surface of the substrate on which the memory cell or transistor is disposed can also be used as the reference.

[0449] This increases the contact area between the conductive layer 220 and the semiconductor layer 270, thereby reducing their contact resistance. Consequently, the decrease in the on-state current of transistor VM1 caused by the contact resistance between the conductive layer 220 and the semiconductor layer 270 can be suppressed. Furthermore, a gate electric field can be easily applied to the channel formation region of the semiconductor layer 270, thereby improving the electrical characteristics of transistor VM1. Moreover, a gate electric field can also be easily applied to the region of the semiconductor layer 270 that contacts the conductive layer 220, thus increasing the on-state current of transistor VM1. Additionally, regardless of whether either the conductive layer 220 or the conductive layer 240 is used as the drain electrode, transistor VM1 can possess excellent electrical characteristics.

[0450] Furthermore, an oxygen-containing conductive material is preferably used as the conductive layer 220. When an oxide semiconductor is used as the semiconductor layer 270, the contact resistance between the semiconductor layer 270 and the conductive layer 220 can be reduced by using an oxygen-containing conductive material as the conductive layer 220.

[0451] Furthermore, the conductive layer 220 can be constructed by stacking tungsten beneath an oxygen-containing conductive material. This stacking of tungsten improves the conductivity of the conductive layer 220.

[0452] Insulating layers 280 and 285 are used as interlayer films, so their relative permittivity is preferably low. By using a material with a low relative permittivity for the interlayer film, the capacitance value of parasitic capacitance generated between the wirings can be reduced.

[0453] Furthermore, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulating layer 280. This can suppress the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 270.

[0454] Furthermore, the insulating layer 280 preferably uses an insulator containing excess oxygen. By heat-treating the insulating layer 280 containing excess oxygen, oxygen can be supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 270, thereby reducing oxygen vacancies and V. O H. This stabilizes the electrical characteristics of transistor VM1 and improves its reliability.

[0455] Note that the transistors that can be used in this invention are not limited to those in the present invention. Figure 22C The transistor VM1 shown. For example, it can also be used Figure 24 The transistor VM2 is shown in the diagram. Figure 24 The transistor VM2 shown is Figure 22C The difference between the transistor VM1 shown is that the former has a conductive layer 215 and an insulating layer 225.

[0456] Figure 24 The structure shown is equivalent to Figure 7AThe storage unit 41A is shown. In Figure 24 In the storage cell 41A shown, transistor VM2 is positioned above capacitor VC1.

[0457] like Figure 24 As shown, a conductive layer 215 is provided on the insulating layer 280. Furthermore, an insulating layer 281 is disposed on both the insulating layer 280 and the conductive layer 215. Additionally, a conductive layer 240 is provided on the insulating layer 281.

[0458] An opening 604 leading to the conductive layer 220 is provided in the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240. The opening 604 includes openings in the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240. The sidewalls of the opening 604 include the sidewalls of the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240.

[0459] At least a portion of each of the insulating layer 225, semiconductor layer 270, insulating layer 250, and conductive layer 260 is located in the opening 604. Specifically, the insulating layer 225 is disposed such that it covers a portion of the bottom and sidewalls of the opening 604; the semiconductor layer 270 is disposed such that it covers the remaining portion of the bottom of the opening 604 and the insulating layer 225; and the insulating layer 250 is disposed such that it covers the semiconductor layer 270. Furthermore, the conductive layer 260 is disposed such that it is embedded in a recess of the insulating layer 250 that reflects the shape of the opening 604.

[0460] The insulating layer 225 contacts a portion of the top surface of the conductive layer 220, the side surface of the insulating layer 280, the side surface of the conductive layer 215, the side surface of the insulating layer 281, and the side surface of the conductive layer 240 in the opening 604.

[0461] exist Figure 24 In the transistor VM2 shown, semiconductor layer 270 is used as semiconductor layer, conductive layer 260 is used as first gate electrode, insulating layer 250 is used as first gate insulating film, conductive layer 215 is used as second gate electrode, insulating layer 225 is used as second gate insulating film, and conductive layer 220 and conductive layer 240 are used as source electrode or drain electrode, respectively.

[0462] The threshold voltage V of the transistor can be controlled by independently changing the potential applied to the conductive layer 215 without linking it to the potential applied to the conductive layer 260. th In particular, by applying a negative potential to the conductive layer 215, the Vt of the transistor can be further increased. thTo reduce the off-state current. Therefore, compared with the case where no negative potential is applied to the conductive layer 215, the drain current when the potential applied to the conductive layer 260 is 0V can be reduced in the case where a negative potential is applied to the conductive layer 215. In addition, the conductive layer 260 can also be used as the second gate electrode and the conductive layer 215 can be used as the first gate electrode.

[0463] Alternatively, the conductive layer 215 can also be connected to the conductive layer 260. By connecting the conductive layer 215 and the conductive layer 260 and applying the same potential to them, the on-state current can be increased, the initial characteristic non-uniformity can be reduced, the deterioration of electrical characteristics under the negative GBT (Gate Bias-Temperature) stress test can be suppressed, and the variation of the rising voltage of the on-state current under different drain voltages can be suppressed.

[0464] As described above, Figure 24 The transistor VM2 shown includes a first gate electrode and a second gate electrode, whereby the electrical characteristics of the transistors included in the semiconductor device can be improved.

[0465] <Example structure 2 of NOSRAM>

[0466] Figure 25A and Figure 25B Shows an example structure of a transistor that can be used in the circuit structure of a dual-transistor type NOSRAM. Figure 25A Is an example of a perspective view of a semiconductor device in which a plurality of memory cells 41F including the transistor VT1 and the transistor VT2 arranged in a stacked manner are arranged. Both the transistor VT1 and the transistor VT2 are vertical transistors. The memory cell 41F is connected to the conductive layer 220a, the conductive layer 240a, the conductive layer 240b, and the conductive layer 210. Note that in Figure 25A For clarity, insulating layers such as interlayer films are not shown and the conductive layer 210 located at the top is represented by a dashed line.

[0467] Figure 25A The conductive layer 220a shown is used as Figure 7F The read bit line RBL shown, etc. Figure 25A The conductive layer 240a shown is used as Figure 7F The read word line RWL shown, etc. Figure 25A The conductive layer 240b shown is used as Figure 7F The write bit line WBL shown, etc. Figure 25A The conductive layer 210 shown is used as Figure 7F The write word line WWL shown, etc.

[0468] In Figure 25A The memory cell 41F shown, the transistor VT2 is provided above the transistor VT1. Figure 25A The transistor VT2 shown corresponds to Figure 7F The transistor M1 of the memory cell 41F shown. Figure 25A The transistor VT1 shown is equivalent to Figure 7F The transistor M2 of the memory cell 41F shown.

[0469] Notice, Figure 25A An example is shown in which the storage cells 41F are arranged at equal intervals in the X and Y directions. An interleaved configuration in which the storage cells 41F are arranged alternately can also be used.

[0470] Transistor VT1 includes conductive layers 220a, 240a, and 260a as constituent elements. Transistor VT2 includes conductive layers 260a, 240b, and 260b as constituent elements.

[0471] Next, an example of the structure of storage cell 41F will be described. Figure 25B This is a perspective view illustrating an example of the structure of memory cell 41F. Note that, for clarity, insulating layers such as interlayer films are not shown; portions of conductive layers 220a, 240a, 240b, and 210 are indicated by dashed lines.

[0472] Figure 25B The memory cell 41F shown has the following structure: In transistor VT1, a semiconductor layer 270a is disposed in the opening of conductive layer 240a, and the side of conductive layer 240a in the opening is in contact with semiconductor layer 270a.

[0473] Figure 26A This is a plan view illustrating transistor VT1. Figure 26B This is a plan view illustrating transistor VT2. Note that some components have been omitted in the plan view for clarity.

[0474] Figure 26C It is equivalent to Figure 26A , Figure 26B The diagram shows the cross-section of line segment A1-A2. Figure 26D It is equivalent to Figure 26A , Figure 26B The diagram shows the cross-section of line segment B1-B2.

[0475] The memory cell 41F includes an insulating layer 160 on a substrate (not shown), a transistor VT1 disposed on the insulating layer 160, and a transistor VT2 disposed on the transistor VT1. In addition, insulating layers 280a, 280b, and 285, which serve as interlayer films, can be disposed between the transistors and between various wirings.

[0476] Transistor VT1 includes a conductive layer 220a, a conductive layer 240a, a semiconductor layer 270a, an insulating layer 250a, and a conductive layer 260a. In transistor VT1, the semiconductor layer 270a is used as the semiconductor layer, the conductive layer 260a is used as the gate electrode, and the insulating layer 250a is used as the gate insulating film. Furthermore, the conductive layers 220a and 240a are used as the source electrode and drain electrode, respectively.

[0477] In other words, transistor VT1 has the same characteristics as... Figure 22C The diagram shows the structure corresponding to that of transistor VM1. Therefore, in the accompanying drawings, corresponding components in transistors VM1 and VT1 are generally assigned the same three-digit number as symbols. Furthermore, unless otherwise specified, transistor VT1 can be referred to in the description of transistor VM1.

[0478] Transistor VT2 includes a conductive layer 260a, a conductive layer 240b, a semiconductor layer 270b, and an insulating layer 250b. In transistor VT2, the semiconductor layer 270b is used as the semiconductor layer, the conductive layer 260b is used as the gate electrode, and the insulating layer 250b is used as the gate insulating film. Furthermore, the conductive layers 260a and 240b are used as source electrodes or drain electrodes.

[0479] In other words, transistor VT2 has the same characteristics as... Figure 22C The structure shown corresponds to the structure of transistor VM1. Therefore, in the accompanying drawings, corresponding components in transistors VM1 and VT2 are generally assigned the same three-digit number as symbols. Furthermore, unless otherwise specified, transistor VT2 can be referred to in the description of transistor VM1. Note that conductive layer 260a corresponds to conductive layer 220 in transistor VM1. Therefore, conductive layer 260a can be referred to in the description of conductive layer 220 described above.

[0480] Note that you can Figure 24 The transistor VM2 shown is used as one or both of transistors VT1 and VT2.

[0481] The conductive layer 260a can be said to have a region that serves as both the gate electrode of transistor VT1 and one of the source and drain electrodes of transistor VT2.

[0482] The conductive layer 260b is connected to the conductive layer 210 formed on the conductive layer 260b. Note that the conductive layer 260b and the conductive layer 210 may also be formed as a single component.

[0483] The top surfaces of both conductive layers 260a and 260b are preferably approximately circular. This structure improves the integration density of the memory cell 41F. Note that the top surface shapes of conductive layers 260a and 260b can be referenced to the description of the shape of the opening 602, etc., described above.

[0484] In order to increase the overlap area of ​​transistor VT2 and transistor VT1, it is preferable that the top surface shape of the opening 290b has the same or similar shape as the top surface shape of the opening 290a forming transistor VT1.

[0485] Materials Constituting Semiconductor Devices

[0486] The following describes the constituent materials that can be used in semiconductor devices.

[0487] [Substrate]

[0488] Substrates suitable for use in semiconductor devices can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switches, light-emitting elements, and memory elements.

[0489] [Insulator]

[0490] As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0491] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, low voltage can be achieved during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using a material with a low relative permittivity as the insulator used as the interlayer film, the capacitance value of parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material based on the function of the insulator. Additionally, materials with a low relative permittivity are also materials with high dielectric strength.

[0492] Materials with relatively high permittivity (high-k) include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0493] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorinated silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Additionally, porous silicon oxides can be cited. Moreover, these silicon oxides may also contain nitrogen.

[0494] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. Examples of insulators that suppress the permeation of impurities and oxygen include single layers or stacks of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride, can be used as insulators that suppress the permeation of impurities and oxygen.

[0495] Furthermore, the insulating layer in contact with the semiconductor layer, or the insulating layer disposed near the semiconductor layer, such as a gate insulating film, preferably has regions containing excess oxygen. For example, when an insulating layer having regions containing excess oxygen is in contact with the semiconductor layer, or when an insulating layer having regions containing excess oxygen is disposed near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or porous silicon oxide.

[0496] In addition, examples of oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon oxynitride are examples of oxides containing one or both of aluminum and hafnium.

[0497] In addition, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon oxynitride are examples of insulators that have hydrogen-blocking properties.

[0498] An oxygen-blocking insulator and a hydrogen-blocking insulator can be described as an insulator that blocks one or both of oxygen and hydrogen.

[0499] Furthermore, as insulators capable of trapping or fixing hydrogen, examples include oxides containing magnesium or oxides containing one or both of aluminum and hafnium. Moreover, these oxides are more preferably amorphous. Oxides with amorphous structures sometimes possess the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. Furthermore, while these metal oxides are preferably amorphous, some may also have crystalline regions.

[0500] Note that in this specification, etc., "barrier insulating film" refers to an insulating film with barrier properties. Furthermore, barrier property refers to the property that makes it difficult for the corresponding substance to diffuse (also referred to as the property that makes it difficult for the corresponding substance to pass through, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Additionally, the function of trapping or fixing (also called gettering) the corresponding substance can be referred to as barrier property. Furthermore, hydrogen, denoted as the corresponding substance, refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms, oxygen molecules, etc., does not readily diffuse.

[0501] [Conductor]

[0502] As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. As an alloy containing the above-mentioned metallic elements, a nitride or an oxide of the alloy may also be used. For example, tantalum nitride, titanium nitride, tungsten nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0503] Furthermore, conductive materials containing nitrogen, such as tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, ruthenium nitrides, tantalum and aluminum nitrides, or titanium and aluminum nitrides; conductive materials containing oxygen, such as ruthenium oxide, strontium and ruthenium oxides, or lanthanum and nickel oxides; and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Note that examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0504] In addition, conductive materials with tungsten, copper or aluminum as the main components have high conductivity and are therefore preferred.

[0505] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0506] Furthermore, when using oxide semiconductors in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0507] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the oxide semiconductor in which the channel is formed is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, can be used. Furthermore, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon can also be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the oxide semiconductor in which the channel is formed can sometimes be trapped. Alternatively, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0508] [Other Semiconductor Materials]

[0509] Semiconductor materials that can be used as semiconductor layers are not limited to oxide semiconductors. Semiconductor materials with band gaps (semiconductor materials that are not zero-bandgap semiconductors) can also be used as semiconductor layers. For example, it is preferable to use single-element semiconductors, compound semiconductors, or layered materials (also known as atomic layer materials, two-dimensional materials, etc.) as semiconductor materials.

[0510] In this specification and other materials, layered materials are a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together by bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using materials that are semiconductors and have high two-dimensional conductivity in the channel formation region, transistors with large on-state currents can be provided.

[0511] Examples of semiconductors that can be used as single-element semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include, for instance, low-temperature polycrystalline silicon (LTPS).

[0512] Compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride suitable for use in semiconductor layers preferably has an amorphous structure. Boron arsenide suitable for use in semiconductor layers preferably comprises crystals with a cubic crystal structure.

[0513] As layered materials, examples include graphene, silicene, boron carbonitride, and chalcogenides. In boron carbonitride, a layered material, carbon, nitrogen, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. Furthermore, chalcogen elements are a collective term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and protium. Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0514] As a semiconductor layer, transition metal chalcogenides, which are typically used as semiconductors, are preferred, for example. Examples of transition metal chalcogenides suitable for use in semiconductor layers include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2). By using the aforementioned transition metal chalcogenides as semiconductor layers, semiconductor devices with high on-state currents can be provided.

[0515] According to one aspect of the present invention, a novel transistor and a novel semiconductor device can be provided. Furthermore, a semiconductor device capable of miniaturization or high integration can be provided. Additionally, a semiconductor device with excellent frequency characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a low-power semiconductor device can be provided. Furthermore, a semiconductor device including a transistor with a large on-state current can be provided. Furthermore, a semiconductor device with less non-uniformity in transistor characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided.

[0516] The configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments, etc.

[0517] (Implementation Method 4)

[0518] In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer for a transistor is described.

[0519] [Oxide semiconductor layer]

[0520] In one aspect of the present invention, the oxide semiconductor layer preferably comprises a crystalline metal oxide. Examples of structures with crystalline metal oxides include the CAAC (c-axis aligned crystal) structure, the poly-crystal structure, and the nano-crystal (nc: nano-crystal) structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. This improves the reliability of transistors using the oxide semiconductor layer of one aspect of the present invention, and consequently improves the reliability of semiconductor devices including transistors.

[0521] In one embodiment of the present invention, the oxide semiconductor layer preferably comprises a metal oxide having a CAAC structure. A CAAC structure refers to a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) are oriented along the c-axis and connected on the ab plane in a manner where the multiple microcrystals are not oriented. Furthermore, when a cross-section of the oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that the metal atoms are arranged in layers within the crystalline regions. Therefore, the oxide semiconductor layer having a CAAC structure can also be described as a structure with layered crystalline regions.

[0522] The crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, it can be analyzed by combining several of the above methods.

[0523] Furthermore, there are no particular restrictions on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. For example, the oxide semiconductor layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and crystalline semiconductors other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in a portion thereof). When the oxide semiconductor layer is crystalline, it can sometimes suppress the degradation of transistor characteristics.

[0524] The metal oxide comprising the oxide semiconductor layer of one aspect of the present invention can include, for example, indium oxide, gallium oxide, and zinc oxide. Preferably, the metal oxide of one aspect of the present invention comprises at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably comprises two or three elements selected from indium, element M, and zinc. Additionally, element M is a metallic or semi-metallic element with a high bonding energy with oxygen, for example, a metallic or semi-metallic element with a higher bonding energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide of one aspect of the present invention preferably comprises one or more elements selected from indium, gallium, and zinc. Note that in this specification and other documents, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification and other documents sometimes include half-metallic elements.

[0525] As one embodiment of the present invention, the metal oxide may be indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also denoted as ITO), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. In addition, examples include indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide), which contain silicon.

[0526] By increasing the proportion of indium atoms in a metal oxide relative to the total number of atoms of all metal elements, transistors can achieve large on-state current and high frequency characteristics.

[0527] In addition, metal oxides can also contain one or more of the periodically numbered metals in the periodic table instead of indium. Alternatively, metal oxides can contain one or more of the periodically numbered metals in the periodic table besides indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including periodically numbered metals, the field-effect mobility of transistors can sometimes be improved. Examples of periodically numbered metals include those belonging to the fifth period and those belonging to the sixth period. Specific examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are referred to as light rare earth elements.

[0528] In addition, metal oxides may also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0529] Furthermore, by increasing the proportion of zinc atoms relative to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. As a result, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0530] Furthermore, by increasing the proportion of element M atoms in the metal oxide relative to the total number of atoms of all metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. In addition, variations in the transistor's electrical characteristics are suppressed, thereby improving reliability.

[0531] In this embodiment, In-Ga-Zn oxides are sometimes used as examples to illustrate metal oxides.

[0532] In one embodiment of the present invention, the oxide semiconductor layer is crystalline. Furthermore, in another embodiment of the present invention, the oxide semiconductor layer preferably has a CAAC structure.

[0533] An oxide semiconductor layer according to one aspect of the present invention can be fabricated by forming a metal oxide using at least two deposition methods. For example, an oxide semiconductor layer according to one aspect of the present invention can be fabricated by forming a metal oxide using a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed using at least two deposition methods can also be referred to as a Hybrid OS.

[0534] An oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, and then forming a metal oxide as a second layer on the first layer using a second deposition method. In this case, as the first deposition method, it is preferable to use a deposition method that causes less damage to the surface to be formed compared to the second deposition method. When a deposition method that causes less damage to the surface to be formed is used as the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on the surface to be formed of the oxide semiconductor layer can be suppressed. Furthermore, the incorporation of impurities such as silicon into the second layer can be suppressed, thereby improving the crystallinity of the oxide semiconductor layer.

[0535] Examples of first deposition methods include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet deposition methods. Examples of CVD methods include plasma-enhanced CVD (PECVD), thermal CVD, photochemical CVD, and metal-organic CVD (MOCVD). Examples of wet deposition methods include spraying. Compared to sputtering methods described later, ALD and CVD methods can suppress damage to the surface being formed, making them suitable as first deposition methods.

[0536] Examples of ALD methods include thermal ALD (thermal ALD) which uses only thermal energy to react precursors and reactants, and plasma ALD (PEALD) which uses reactants excited by plasma.

[0537] The ALD method allows for atomic deposition layer by layer, resulting in advantages such as: extremely thin deposition; the ability to deposit on structures with high aspect ratios or surfaces with large steps; deposition with fewer defects such as pinholes; high coverage; and the ability to deposit at low temperatures. Furthermore, the PEALD method, utilizing plasma, allows for deposition at even lower temperatures, making it sometimes preferred. Note that precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films deposited using the ALD method sometimes contain more carbon or chlorine than films deposited using other methods. It should be noted that the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Furthermore, in a metal oxide deposition method according to one aspect of the present invention, the ALD method employs one or both of the following conditions: a high substrate temperature during deposition and an impurity removal process. Compared to the case where the ALD method is used without employing the aforementioned conditions and processes, the carbon and chlorine content in the film is sometimes lower.

[0538] Unlike deposition methods that deposit particles released from a target or similar material, the ALD (Advanced Layer Deposition) method forms a film through a reaction on the surface of the workpiece. Therefore, the ALD method is a deposition method with good step coverage, less affected by the shape of the workpiece. In particular, the ALD method exhibits good step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings, etc.

[0539] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, thermal CVD, because it does not use plasma, is a deposition method that reduces plasma damage to the workpiece. Moreover, since no plasma damage occurs during deposition in thermal CVD, films with fewer defects can be obtained.

[0540] Examples of secondary deposition methods include sputtering and pulsed laser deposition (PLD). Metal oxides formed using these secondary deposition methods tend to have a CAAC structure.

[0541] Furthermore, as the first layer, a metal oxide with a microcrystalline or amorphous structure, for example, having a lower crystallinity than the CAAC structure, is sometimes formed. By forming a second layer with higher crystallinity on the first layer with lower crystallinity, or by performing heat treatment after forming the second layer, the crystallinity of the first layer is sometimes improved with the second layer as the nucleus. As a result, the crystallinity of the oxide semiconductor layer as a whole, including the interface with the surface to which it is formed, can be improved.

[0542] Furthermore, a third layer can also be formed on the second layer. Because the second layer has high crystallinity, the third layer can crystallize and grow using the crystals of the second layer as nuclei or seeds. Thus, even if the deposition method for the third layer does not utilize a deposition method that readily produces crystals, the third layer can still be crystallized. Here, for example, when the third layer is formed using a deposition method with higher coverage than the second layer, both high crystallinity and high coverage can be achieved throughout the oxide semiconductor layer.

[0543] As an example, an oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, forming a metal oxide as a second layer using a second deposition method, and then forming a metal oxide as a third layer using the first deposition method. Specifically, the first deposition method can be the ALD method, and the second deposition method can be the sputtering method. Compared with the sputtering method, the ALD method is a deposition method with excellent coverage. When the ALD method is used as the deposition method for the first and third layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with high aspect ratios.

[0544] [Manufacturing method of oxide semiconductor layer]

[0545] The oxide semiconductor 230 of the oxide semiconductor layer can be manufactured, for example, by the following steps: forming oxide semiconductor 230a on layer 229 of the surface to be formed using the ALD method, forming oxide semiconductor 230b on oxide semiconductor 230a using the sputtering method, and forming oxide semiconductor 230c on oxide semiconductor 230b using the ALD method. Furthermore, it is preferable to perform heat treatment after forming the oxide semiconductor 230. By performing heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. The heat treatment described herein is not limited to heating treatment. For example, it can also be heat applied during the manufacturing process.

[0546] The oxide semiconductor 230 can be used in the semiconductor layer 530 and semiconductor layer 270 described in the above embodiments. In addition, layer 229 is equivalent to the insulating layer 524, insulating layer 280, insulating layer 225 or conductive layer 220 described in the above embodiments.

[0547] Layer 229 may also be non-crystalline. Furthermore, if layer 229 is crystalline, it may have a crystal structure with low lattice integration with the metal oxide contained in the oxide semiconductor 230.

[0548] Reference Figures 27A to 28D An example illustrating the manufacturing method of oxide semiconductor 230.

[0549] First, oxide semiconductor 230a is formed on layer 229 using the ALD method. Figure 27A Next, oxide semiconductor 230b is formed on oxide semiconductor 230a using a sputtering method. Figure 27B ).

[0550] When depositing metal oxide films using sputtering, alloying sometimes occurs between the components contained in the metal oxide film and the components contained in the layer on the surface being formed, due to damage to the surface being formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even after the heat treatment described later. When using an oxide semiconductor layer with alloyed regions in a transistor, there are concerns about negatively impacting the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying between the components contained in the metal oxide film and the components contained in the layer on the surface being formed.

[0551] In one embodiment of the present invention, an oxide semiconductor layer manufacturing method is used to form an oxide semiconductor 230a between an oxide semiconductor 230b and a layer 229 using a deposition method that causes minimal damage to the surface to be formed. This suppresses the alloying of the components contained in the oxide semiconductor 230 with the components contained in the layer 229, thereby further improving the crystallinity of the oxide semiconductor 230.

[0552] By employing the above structure, the thickness of the alloyed region can be reduced to a point where it is not observable. For example, the thickness of the alloyed region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that... Figure 27A and Figure 27B An example is shown where no alloying region is formed between layer 229 and oxide semiconductor 230a.

[0553] Note that the thickness of the alloyed region can sometimes be calculated by performing a linear analysis of the composition of the region and its surroundings using SIMS or Energy Dispersive X-ray Spectroscopy (EDX).

[0554] For example, using the direction perpendicular to the surface to which the oxide semiconductor 230a is formed as the depth direction, a linear EDX analysis is performed on the aforementioned region and its surrounding area. Next, in the distribution of quantitative values ​​of each element relative to the depth direction obtained through this analysis, the depth at which the quantitative value of a metal that is a major component of the oxide semiconductor 230a but not a major component of the layer forming the surface (here, layer 229) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element that is a major component of the layer forming the surface but not a major component of the oxide semiconductor 230a (e.g., Si) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the layer forming the surface. Through these steps, the thickness of the alloyed region can be calculated.

[0555] In one aspect of the oxide semiconductor layer of the present invention, when the thickness of the alloyed region is observed using EDX analysis, for example, its thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0556] Additionally, for example, when using a silicon oxide layer as layer 229 and performing SIMS analysis on the oxide semiconductor 230 formed on layer 229, the interface is defined as the depth at which the silicon concentration reaches 50% of the maximum concentration in layer 229, and the silicon concentration is reduced to 1.0 × 10⁻⁶. 21 atoms / cm 3 Preferably 5.0×10 20 atoms / cm 3 More preferably 1.0×10 20 atoms / cm 3 The distance between the depth and the interface is the thickness t_s2. The thickness t_s2 is preferably less than 3 nm, and more preferably less than 2 nm.

[0557] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the range mentioned above.

[0558] Furthermore, by thinning the alloyed region, a CAAC structure can be formed near the surface to be formed. Here, "near the surface to be formed" refers, for example, to a region in a substantially perpendicular direction that is greater than 0 nm and less than 3 nm from the surface to be formed of the oxide semiconductor 230, preferably greater than 0 nm and less than 2 nm, and more preferably more than 1 nm and less than 2 nm.

[0559] Note that CAAC structures near the formed surface can sometimes be identified during TEM observation. For example, when performing cross-sectional observation of oxide semiconductor 230 using high-resolution TEM, layered bright spots arranged in a direction parallel to the formed surface were identified near the formed surface.

[0560] Furthermore, when forming oxide semiconductor 230a using the ALD method, sometimes oxide semiconductor layers with microcrystalline or amorphous structures that have lower crystallinity than the CAAC structure are formed. That is, in Figure 27A In the manufacturing stages shown, oxide semiconductor 230a sometimes includes regions whose crystallinity is lower than that of oxide semiconductor 230b.

[0561] The oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure.

[0562] When forming the oxide semiconductor 230b using a sputtering method, a mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, due to sputtered particles during the formation of the oxide semiconductor 230b, or energy supplied to the substrate side by sputtered particles, small crystalline regions may sometimes form in the mixed layer 231. In subsequent heat treatment processes, at least a portion of the oxide semiconductor 230a may crystallize by using the mixed layer 231 or the small crystalline regions formed in the mixed layer 231 as nuclei.

[0563] When depositing oxide semiconductor 230b using sputtering, it is preferable to heat the substrate. When forming metal oxides, by increasing the substrate temperature (stage temperature) during metal oxide formation, it is sometimes possible to form highly crystalline metal oxides.

[0564] Next, oxide semiconductor 230c is formed on oxide semiconductor 230b using the ALD method. Figure 27C For the formation of oxide semiconductor 230c using the ALD method, please refer to the formation method of oxide semiconductor 230a.

[0565] When forming oxide semiconductor 230c on oxide semiconductor 230b having a CAAC structure using the ALD method, oxide semiconductor 230c is sometimes epitaxially grown with oxide semiconductor 230b as the core. Therefore, when forming oxide semiconductor 230c, oxide semiconductor 230c sometimes includes a region having a CAAC structure. Furthermore, this region having a CAAC structure is preferably formed throughout oxide semiconductor 230c.

[0566] Next, a heat treatment process can be performed. Through this heat treatment process, the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c is sometimes improved. Furthermore, after deposition using the ALD method, when this region is only formed below the oxide semiconductor 230c, it sometimes extends upwards due to this heat treatment process. Figure 27D In other words, by performing this heat treatment, regions with CAAC structures are sometimes formed throughout the oxide semiconductor 230c.

[0567] Furthermore, it is preferable that at least a portion of the oxide semiconductor 230a undergoes CAAC treatment via this heat treatment process. Figure 27D CAAC formation is expected to readily occur using the mixed layer 231 formed in the oxide semiconductor 230a during the deposition of oxide semiconductor 230b as a core or seed. The CAAC formation region in the oxide semiconductor 230a is preferably large, and preferably extends to the vicinity of layer 229.

[0568] Furthermore, since CAAC formation occurs from the upper to the lower portion of the oxide semiconductor 230a, it is not limited by the material or crystallinity of layer 229 and can reach the vicinity of layer 229. For example, even if layer 229 has an amorphous structure, a highly crystalline oxide semiconductor 230a can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one aspect of the present invention is particularly suitable for cases where the layer to be formed has an amorphous structure.

[0569] Notice, Figures 27A to 27D This is a cross-sectional view illustrating a method for depositing metal oxides according to one aspect of the present invention. Furthermore, Figures 27A to 27D This can also be viewed as a conceptual diagram illustrating a metal oxide deposition model of one aspect of the present invention. For example... Figures 27A to 27D As shown, oxide semiconductors 230a and 230c respectively enhance their crystallinity by using highly crystallinity oxide semiconductor 230b as a core or seed. Specifically, the crystallinity of oxide semiconductor 230a is sometimes improved by heat treatment during or after the deposition of oxide semiconductor 230b. Furthermore, the crystallinity of oxide semiconductor 230c is sometimes improved by heat treatment during or after the deposition of oxide semiconductor 230c. Note that the aforementioned heat treatment plays an auxiliary role in improving crystallinity.

[0570] Thus, in one aspect of the metal oxide deposition method of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, oxide semiconductors 230a and 230c) can be improved by using a highly crystalline oxide semiconductor 230b (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor. In other words, by using oxide semiconductor 230b as a nucleus or seed to grow the upper and lower oxide semiconductors in a solid phase, a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed using the above deposition method, i.e., the CAAC film, can be referred to as axially grown CAAC (AG CAAC).

[0571] In oxide semiconductor 230, regions with CAAC structures are preferably widely present throughout the entire layer. Figure 28A The diagram shows a state where oxide semiconductors 230a, 230b, and 230c are all crystallized. In this state, sometimes the boundary between oxide semiconductors 230a and 230b is not observed. Furthermore, sometimes the boundary between oxide semiconductors 230b and 230c is not observed. Sometimes oxide semiconductor 230 can be described as a layer without a clearly observed interface. Sometimes oxide semiconductor 230 can be described as a single layer. Note that although... Figure 27D An example of a three-layer stacked structure of oxide semiconductor 230, comprising oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c, is shown, but the example is not limited thereto. For instance, oxide semiconductor 230 may also have a two-layer stacked structure comprising oxide semiconductor 230b and oxide semiconductor 230c.

[0572] In addition, sometimes a portion of oxide semiconductor 230a or oxide semiconductor 230c is not crystallized. Figure 28B This illustrates the case where the interface between the oxide semiconductor 230a and layer 229 is not crystallized. Figure 28C This illustrates the case where the surface of an oxide semiconductor 230c is not crystallized. Figure 28D This illustrates the case where the area near the interface between oxide semiconductor 230a and layer 229, and the area near the surface of oxide semiconductor 230c, are not crystallized.

[0573] By improving the crystallinity of the oxide semiconductor layer, the increase in semiconductor layer resistance in transistors using oxide semiconductor layers is suppressed, or the initial characteristics of the transistor (especially the on-state current) are improved, thereby making it possible to realize transistors suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0574] In one embodiment of the present invention, the oxide semiconductor layer exhibits high overall crystallinity. Therefore, in oxide semiconductor 230, the boundaries between the stacked films in oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are sometimes not identified. In particular, after heat treatment, it is sometimes difficult to identify the boundaries between the stacked films. For example, cross-sectional TEM, cross-sectional STEM, etc., can be used to confirm the presence or absence of boundaries between the stacked films.

[0575] As described above, using metal oxides with a high In content ratio in transistors can improve the transistor's field-effect mobility. On the other hand, oxide semiconductors with a high In content ratio tend to polycrystalline. When using metal oxides with polycrystalline structures in transistors, it negatively impacts the transistor's initial characteristics or reliability. Therefore, by using oxide semiconductors with a high In content ratio in one or both of oxide semiconductors 230a and 230c, forming a crystal that reflects the orientation of the crystals contained in oxide semiconductor 230b, polycrystalline formation can be suppressed.

[0576] Furthermore, the lattice mismatch between the crystal contained in oxide semiconductor 230b and the crystal contained in oxide semiconductor 230a or oxide semiconductor 230c is preferably small. Therefore, oxide semiconductor 230a or oxide semiconductor 230c can form a crystal that reflects the orientation of the crystal contained in oxide semiconductor 230b. At this time, for example, when observing a cross-section of oxide semiconductor 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in oxide semiconductor 230a or oxide semiconductor 230c.

[0577] There are no particular restrictions on the crystal structure of oxide semiconductor 230a or oxide semiconductor 230c, provided that the lattice mismatch between the crystal contained in oxide semiconductor 230b and the crystal contained in oxide semiconductor 230a or oxide semiconductor 230c is small. The crystal structure of oxide semiconductor 230a or oxide semiconductor 230c can also be any of the cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal crystal systems.

[0578] [Composition of the oxide semiconductor layer]

[0579] As described above, the composition of the oxide semiconductor 230b is preferably suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed, for example, using a sputtering method. The oxide semiconductor 230b preferably contains zinc, for example. By including zinc, a highly crystalline metal oxide can be obtained. Furthermore, the oxide semiconductor 230b preferably contains element M in addition to zinc. By including element M in the oxide semiconductor 230b, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of transistors using the oxide semiconductor layer can be improved. Specifically, as an oxide semiconductor 230b, metal oxides with the following compositions can be used: In:M:Zn = 1:1:1 [atomic ratio] or similar, In:M:Zn = 1:1:1.2 [atomic ratio] or similar, In:M:Zn = 1:1:0.5 [atomic ratio] or similar, In:M:Zn = 1:1:2 [atomic ratio] or similar, In:M:Zn = 4:2:3 [atomic ratio] or similar, In:M:Zn = 1:3:2 [atomic ratio] or similar, In:M:Zn = 1:3:4 [atomic ratio] or similar. Note that "similar" includes a range of ±30% of the desired atomic ratio. Furthermore, one or more of gallium, aluminum, and tin are preferably used as element M.

[0580] The oxide semiconductor 230b may also not contain element M. For example, In-Zn oxide may be used. Specifically, it may be an In:Zn composition of 1:1 (atomic ratio) or near, In:Zn composition of 2:1 (atomic ratio) or near, or In:Zn composition of 4:1 (atomic ratio) or near. Alternatively, indium oxide may be used. Furthermore, it may contain trace amounts of element M. For example, it may be an In:Ga:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Ga:Zn composition of 2:0.1:1 (atomic ratio) or near. Additionally, it may be an In:Sn:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Sn:Zn composition of 2:0.1:1 (atomic ratio) or near.

[0581] Oxide semiconductors 230a and 230c can use metal oxides with a high In content. Oxide semiconductors 230a and 230c can be formed, for example, using the ALD method. Furthermore, metal oxides with a higher In content than element M are particularly preferred. By using metal oxides with a high In content, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics improved.

[0582] Alternatively, oxide semiconductors 230a and 230c may not contain element M. For example, In-Zn oxide may also be used. Specifically, it may be an In:Zn ratio of 1:1 or similar, an In:Zn ratio of 2:1 or similar, or an In:Zn ratio of 4:1 or similar. Alternatively, indium oxide may also be used. Furthermore, oxide semiconductors 230a and 230c may also contain trace amounts of element M. Specifically, it may be an In:Ga:Zn ratio of 4:0.1:1 or similar, an In:Ga:Zn ratio of 2:0.1:1 or similar, an In:Sn:Zn ratio of 4:0.1:1 or similar, or an In:Sn:Zn ratio of 2:0.1:1 or similar.

[0583] Furthermore, oxide semiconductors 230a and 230c can use metal oxides with a higher proportion of In than oxide semiconductor 230b.

[0584] Furthermore, for example, metal oxides with a higher Ga content than oxide semiconductor 230b can be used as oxide semiconductors 230a and 230c. For example, oxide semiconductors 230a and 230c preferably use metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar. By increasing the Ga content, the band gap of oxide semiconductors 230a and 230c can sometimes be made larger than that of oxide semiconductor 230b. Thus, oxide semiconductor 230b is sandwiched between oxide semiconductors 230a and 230c with larger band gaps, and oxide semiconductor 230b is primarily used as a current path (channel). By sandwiching oxide semiconductor 230b between oxide semiconductors 230a and 230c, the trap levels at and near the interface of oxide semiconductor 230b can be reduced. This allows for the creation of buried-channel transistors with the channel located far from the insulating layer interface, thereby improving field-effect mobility.

[0585] Furthermore, in one embodiment of the oxide semiconductor layer of the present invention, even if the oxide semiconductors 230a and 230c employ a composition that makes it difficult to form a CAAC structure when forming a monolayer, the entire oxide semiconductor layer including oxide semiconductors 230a and 230c can have a CAAC structure by crystal growth with oxide semiconductor 230b as the nucleus. Alternatively, regions including at least a portion of each of oxide semiconductors 230a and 230c extending to the region of oxide semiconductor 230b can have a CAAC structure.

[0586] In particular, when the oxide semiconductors 230a and 230c employ a high In ratio, a crystallinity suitable for transistors can be obtained. In one embodiment of the oxide semiconductor layer of the present invention, while increasing the In ratio to improve the transistor's turn-on characteristics, reliability can be improved by employing a highly crystallinity CAAC structure.

[0587] Note that the composition of oxide semiconductor 230a can also be different from that of oxide semiconductor 230c.

[0588] In addition, oxide semiconductors 230a and 230c can also use metal oxides with the same composition as oxide semiconductor 230b.

[0589] By using the oxide semiconductor layer with CAAC structure formed by the above two deposition methods to form the channel region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0590] The composition of the metal oxides used in oxide semiconductor 230 can be analyzed using methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these methods can be used. Note that the actual content ratio of elements with low abundance can differ from the analytically obtained ratio due to the limitations of analytical precision. For example, when the abundance ratio of element M is low, the analytically obtained content ratio of element M may sometimes be lower than the actual content ratio.

[0591] [c-axis orientation]

[0592] One embodiment of the present invention has an oxide semiconductor layer with a CAAC structure. For example, crystal orientation can be used to evaluate the crystallinity of the oxide semiconductor layer of one embodiment of the present invention.

[0593] Crystal orientation can be obtained from TEM images by performing a Fast Fourier Transform (FFT). Specifically, the crystal axis orientation can be obtained from the FFT pattern. The FFT pattern obtained through FFT processing reflects the same reciprocal lattice space information as the electron diffraction pattern.

[0594] By performing FFT processing on each region within a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region over a certain area, a map showing the crystal orientation can be formed. Specifically, two high-intensity spots are observed in the FFT pattern of a region with layered crystals. The crystal axis orientation of this region can be obtained from the angle of the line segment connecting these two spots.

[0595] The degree of c-axis orientation can be calculated by determining the proportion of the c-axis orientation region in a diagram showing crystal orientation. Note that here, the c-axis orientation region refers to the region whose orientation coincides with the c-axis and whose difference from the c-axis is within 20°.

[0596] In one embodiment of the present invention, the c-axis orientation rate can be calculated, for example, by performing cross-sectional or planar TEM observation of the oxide semiconductor layer. Furthermore, the region for performing the FFT (also called the FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region for performing the FFT is not limited to a circle.

[0597] In one embodiment of the oxide semiconductor layer of the present invention, the c-axis orientation is preferably 60% or more, more preferably 70% or more, even more preferably 80% or more, even more preferably 90% or more, and still more preferably 95% or more.

[0598] Furthermore, the c-axis orientation degrees of the regions deposited as oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are preferably 60% or more, more preferably 70% or more, further preferably 80% or more, even more preferably 90% or more, and still more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Furthermore, Rc2 / Rc1 is preferably greater than 1.

[0599] Note that sometimes the boundaries of oxide semiconductors 230a, 230b and 230c are not clearly observed after the oxide semiconductor 230 is manufactured.

[0600] In one embodiment of the present invention, the oxide semiconductor 230 can be sequentially divided into three regions—a first region, a second region, and a third region—from one side of layer 229. Each region is a layered region.

[0601] The first, second, and third regions all have a CAAC structure. Furthermore, the c-axis orientation degree of the third region is preferably higher than that of the first region. Similarly, the c-axis orientation degree of the second region is preferably higher than that of the first region. Moreover, the c-axis orientation degree of both the second and third regions is preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0602] The first region is located 0 nm above and 3 nm below the top surface of layer 229, and the third region is located 0 nm above and 3 nm below the top surface of oxide semiconductor 230.

[0603] Alternatively, the thickness of the layers in each region may be approximately the same.

[0604] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0605] (Implementation Method 5)

[0606] In this embodiment, electronic components, electronic devices, and mainframe computers that can use the semiconductor devices described in the above embodiments will be described. Electronic components, electronic devices, and mainframe computers using a semiconductor device according to one aspect of the present invention are highly effective for achieving high performance, such as low power consumption.

[0607] [Electronic Components]

[0608] Figure 29A A perspective view of a substrate (circuit board 704) on which electronic components 709 are mounted is shown. Figure 29A The electronic component 709 shown includes a semiconductor device 710 within the mold 711. Figure 29A In this description, a portion of the electronic component 709 is omitted to indicate its internal structure. The electronic component 709 includes a connecting pad 712 on the outside of the mold 711. The connecting pad 712 is connected to an electrode pad 713, which is connected to a semiconductor device 710 via a lead 714. The electronic component 709 is mounted, for example, on a printed circuit board 702. By combining multiple such electronic components and connecting them individually on the printed circuit board 702, a circuit board 704 is completed.

[0609] Furthermore, the semiconductor device 710 includes a layer 715 with a computing core and a layer 716 with memory. Note that the memory layer 716 has a structure with multiple memory cell arrays stacked on top of each other. The structure of the stacked computing core layer 715 and memory layer 716 can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without through-hole electrode technologies such as TSVs (Through Silicon Vias) or bonding technologies such as Cu-Cu direct bonding. When the computing core layer 715 and memory layer 716 have a monolithic stacked structure, for example, a so-called on-chip memory structure where memory is directly formed on the processor can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0610] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to through-electrode techniques such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving the memory bandwidth.

[0611] Furthermore, it is preferable to use OS transistors to form the multiple memory cell arrays included in the memory layer 716, and to stack these multiple memory cell arrays monolithically. When the multiple memory cell arrays adopt a monolithic stacked structure, one or both of the memory bandwidth and memory access latency can be improved. Note that bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange. In addition, when Si transistors are used in the memory layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0612] Alternatively, the semiconductor device 710 may be referred to as a bare die. In this specification, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0613] then, Figure 29BA perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is disposed on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple semiconductor devices 710 are disposed on the interposer 731.

[0614] The packaging substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The through-hole plate 731 can be, for example, a silicon through-hole plate or a resin through-hole plate.

[0615] The through-hole board 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal spacings. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 functions to connect the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the packaging substrate 732. Therefore, the through-hole board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuit is connected to the packaging substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0616] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0617] Furthermore, in SiP and MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally side-by-side on the interposer.

[0618] On the other hand, when multiple integrated circuits with different terminal pitches are connected using silicon interposers and TSVs, space is required for the width of these terminal pitches. Therefore, when the size of the electronic component 730 is to be reduced, the width of the aforementioned terminal pitch becomes a problem, and it is sometimes difficult to set to achieve the required amount of wiring to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a memory cell array stacked monolithically can also be used.

[0619] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the insert 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 735.

[0620] In order to mount the electronic component 730 on other substrates, an electrode 733 may also be provided on the bottom of the package substrate 732. Figure 29B An example of forming electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0621] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0622] Figures 30A to 30D This is an explanation of the above. Figure 29A and Figure 29B The diagram shows different structural examples of the electronic components 709 and 730. Figures 30A to 30D The electronic components 730A to 730D shown have the following structure: a layer 715 having a computing core and a layer 716 having a memory are provided in a mold 711 on a plate 731 on which the above-mentioned electrodes 733 are provided.

[0623] exist Figure 30AIn the structure of the electronic component 730A shown, a layer 715 with a processing core is disposed on a connector 731 and connected to electrode pads (not shown) via leads 714. A memory layer 716 formed on the processing core layer 715 has the aforementioned monolithic stacked structure. In the monolithic stacked structure, the memory layer 716 is connected to the processing core layer 715. Therefore, since the leads 714 between the connector 731 and the processing core layer 715 can also serve as wiring between the memory layers 716 of each layer and the connector 731, the number of leads can be reduced.

[0624] Note that in Figure 30A The structural example illustrates a single monolithic stacked structure, but it's also possible to use a structure where monolithic stacked electronic components overlap with other electronic components. For example, as... Figure 30B As shown, the following structure can also be adopted: multiple layers 716A (containing memory) and 715A (containing computational core), as well as layers 716B (containing memory) and 715B (containing computational core), are stacked to form a monolithic stacked structure. The monolithic stacked structure, overlapping with other electronic components, is fixed to a resin sheet 744 by an adhesive layer 743. By adopting this structure, it is possible to realize a structure that stacks multiple memory cell arrays with different circuit structures. By having different circuit structures, semiconductor devices with different memory bandwidths and memory access delays can be realized, and this is preferably applied to structures with layered structures, such as cache memories.

[0625] also, Figure 30A The structural examples can be stacked with other electronic components. For example, such as... Figure 30C As shown, an electronic component 730C can be used, wherein the aforementioned electronic component 730A and a layer 715C containing a processing core, such as a processor, are stacked within a mold 711 located between insert plates 731A and 731B. The circuit layers are connected via conductive materials such as electrodes 733. This structure enables high-speed operation of the interface between the processor and memory. Furthermore, a gap (space) can be provided between the mold containing the processing core layer 715C and the mold containing the electronic component 730A, thereby preventing heat generated in the processing core layer 715C from easily transferring to the electronic component 730A.

[0626] In addition, Figure 30C In structural examples, a structure can also be adopted where a memory layer including OS transistors is set on the 715C layer containing processing cores such as processors. For example, as... Figure 30DAs shown, a memory layer 716C can be disposed on a layer 715C having a computing core and stacked with an electronic component 730A. By adopting this structure, high-speed operation of the interface portion between a structure of so-called on-chip memory, in which memory is directly formed on the processor, and a structure of a semiconductor device including stacked memory layers, can be achieved.

[0627] [Electronic Devices]

[0628] Figure 31A This is an external image showing an example of a portable electronic device. Figure 31B This is a simplified diagram of data delivery within a portable electronic device. The portable electronic device 595 includes a printed circuit board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0629] In the portable electronic device 595, the aforementioned electronic component 709 can be mounted on the printed circuit board 596. By utilizing the electronic component 709, the portable electronic device 595 can process and analyze multiple data obtained through the speaker 597, camera 598, microphone 599, etc., thereby improving user convenience. Furthermore, the electronic component 709 can also be used in systems such as voice guidance and image retrieval.

[0630] In electronic component 709, the obtained image data is processed by neural network operations, such as image resolution, image noise reduction, face recognition (for security purposes), object recognition (for autonomous driving purposes), image compression, image correction (wide dynamic range), image restoration of lensless image sensors, position alignment, text recognition, and reduction of reflected glare.

[0631] Figure 32A The portable game console 1100 shown includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connector 1105, and operation keys 1107. Housings 1101, 1102, and 1103 are detachable. By mounting the connector 1105 provided on housing 1101 to housing 1108, the image output to display unit 1104 can be output to other video display devices. Alternatively, by mounting housings 1102 and 1103 to housing 1109, housings 1102 and 1103 can be integrated and used as an operation unit. The aforementioned electronic components 709 can be combined with chips or the like provided on the substrates of housings 1102 and 1103.

[0632] Figure 32BThis is a USB-connected, strip-shaped electronic device 1120. The electronic device 1120 includes a housing 1121, a cover 1122, a USB connector 1123, and a substrate 1124. The substrate 1124 is housed within the housing 1121. For example, a memory chip 1125 and a control chip 1126 are mounted on the substrate 1124. The aforementioned electronic components 709 can be integrated with the controller chip 1126, etc., on the substrate 1124.

[0633] Figure 32C It is a humanoid robot 1130. Robot 1130 includes sensors 2101 to 2106 and control circuitry 2110. For example, the aforementioned electronic component 709 can be integrated into control circuitry 2110.

[0634] [Mainframe Computer]

[0635] The aforementioned electronic component 709 can be used in a system 3000 that includes a large computer that communicates with the electronic device, without being housed within the electronic device. In this case, the electronic device and the large computer constitute a computing system. Figure 33 This shows a structural example of System 3000.

[0636] System 3000 consists of electronic device 3001 and mainframe computer 3002. Communication between electronic device 3001 and mainframe computer 3002 can be carried out via Internet cable 3003.

[0637] The mainframe computer 3002 has multiple racks 3004. Multiple substrates 3005 are arranged on these racks, and the electronic components 709 described in the above embodiments can be mounted on these substrates 3005. Thus, a neural network is formed in the mainframe computer 3002. Furthermore, the mainframe computer 3002 can perform neural network operations using data input from the electronic device 3001 via the Internet cable 3003. The operation results of the mainframe computer 3002 can be transmitted to the electronic device 3001 via the Internet cable 3003 as needed. This reduces the computational burden on the electronic device 3001.

[0638] This embodiment can be appropriately combined with descriptions of other embodiments.

[0639] <Notes regarding the contents of this instruction manual, etc.>

[0640] Below, additional notes are added to the descriptions of the above embodiments and the structures in those embodiments.

[0641] The structures shown in each embodiment can be appropriately combined with the structures shown in other embodiments to constitute a mode of the present invention. Furthermore, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0642] Furthermore, the content (or a portion thereof) described in one embodiment may be applied, combined, or replaced with other content (or a portion thereof) described in that embodiment and / or content (or a portion thereof) described in one or more other embodiments.

[0643] The content described in the embodiments refers to the content described in each embodiment using various accompanying drawings or the content described in the instruction manual.

[0644] Furthermore, more figures can be formed by combining the figures (or portions thereof) shown in one embodiment with other portions of the figures, other figures (or portions thereof) shown in that embodiment, and / or figures (or portions thereof) shown in one or more other embodiments.

[0645] In this specification, components are categorized according to function and represented by independent boxes in block diagrams. However, in actual circuits, it is difficult to categorize components according to function; sometimes a circuit involves multiple functions or multiple circuits involve a single function. Therefore, the division of boxes in block diagrams is not limited to the components described in the specification and can vary appropriately.

[0646] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not necessarily limited to the dimensions described above. The drawings are shown in arbitrary sizes for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, non-uniformity of signals, voltages, or currents caused by noise or timing deviations may be included.

[0647] In this specification and other materials, when describing the connection relationship of transistors, the terms "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. This is because the source and drain of a transistor are interchangeable depending on the transistor's structure or operating conditions. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminals or source (drain) electrodes, etc.

[0648] Furthermore, in this specification and the like, the terms "electrode" or "wiring" do not limit the function of the constituent elements. For example, sometimes an "electrode" is used as part of a "wiring," and vice versa. Moreover, "electrode" and "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0649] Furthermore, voltage and potential can be interchanged appropriately in this instruction manual and other documents. Voltage refers to the potential difference between the voltage and a reference potential. For example, when the reference potential is ground voltage (grounding voltage), voltage can be replaced with potential. Grounding potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied for wiring, etc., sometimes varies according to the reference potential.

[0650] In this instruction manual and other documents, terms such as "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Additionally, "insulating film" may sometimes be replaced with "insulating layer."

[0651] In this specification and the like, a switch refers to a component that controls whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to a component that selects and switches current paths.

[0652] In this specification, for example, the channel length of a planar transistor refers to the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate overlap or in the region forming the channel in a planar view of the transistor.

[0653] In this specification, for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is turned on) and the gate electrode overlap, or the length of the portion of the region in which the source and drain electrodes of the channel are opposite each other.

[0654] In this specification and other materials, nodes may also be referred to as terminals, wiring, electrodes, conductive layers, conductors, or impurity regions, depending on the circuit structure or device structure. Alternatively, terminals, wiring, etc., may also be referred to as nodes.

[0655] In this specification, the "on state" of a transistor refers, for example, to a state in which the source and drain of the transistor are short-circuited. For example, the following states are sometimes referred to as the "on state": in an n-channel transistor, the voltage between the gate and source is higher than the threshold voltage; or in a p-channel transistor, the voltage between the gate and source is lower than the threshold voltage, etc. Note that the "on state" of a transistor refers to a state that allows current to flow between the source and drain. Therefore, sometimes a transistor being in the "on state" is referred to as a transistor being in the "conduction state."

[0656] In this specification and other materials, the "off state" of a transistor refers to a state in which the source and drain of the transistor are disconnected. For example, the following states are sometimes referred to as the "off state": in an n-channel transistor, the voltage between the gate and source is lower than the threshold voltage; or in a p-channel transistor, the voltage between the gate and source is higher than the threshold voltage, etc. Furthermore, sometimes the transistor being in the "off state" is referred to as the transistor being in the "non-conducting state".

[0657] In this specification and other materials, the voltage between the gate and the source (gate-source) is sometimes referred to as the "gate voltage," the voltage between the drain and the source (drain-source) is sometimes referred to as the "drain voltage," and the voltage between the back gate and the source (back gate-source) is sometimes referred to as the "back gate voltage." In addition, the current flowing from the drain to the source is sometimes referred to as the "drain current."

[0658] In this specification, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in the off state. Note that in this specification, the off-state current and the current flowing from the gate to the source and drain (also called gate leakage current) are sometimes referred to as leakage current.

[0659] In this specification, the term "connection" includes, for example, "electrical connection." When "electrical connection" is used to describe the connection relationship of circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." "A and B directly connected" means, for example, that A and B are connected without being connected by circuit elements (e.g., transistors or switches, rather than wiring). On the other hand, "A and B indirectly connected" means, for example, that A and B are connected through more than one circuit element.

[0660] Here, the term "indirectly connected between A and B" refers to a connection relationship in the following ways: That is, when it is assumed that the circuit is operating, and there is a sequence of events such as the exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, such a circuit can be defined as an object "indirectly connected between A and B." Furthermore, even if there is no sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B, but there is still a sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, it can still be defined as "indirectly connected between A and B." Note that the expression "indirectly connected between A and B" defines the connection relationship of circuit elements as an object. Therefore, for example, even if the circuit is not operating because it is not supplied with a power supply voltage, the circuit can still be defined as an object "indirectly connected between A and B" (however, this is limited, for example, to the case where, when the circuit is operating because it is supplied with a power supply voltage, there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation).

[0661] The following are specific examples of "indirect connection". First, as an example of "A and B indirect connection", there are cases where A and B are connected through the source and drain of more than one transistor. Other examples of "A and B indirect connection" include cases where A and B are connected through more than one switch. In the case of "A and B indirect connection", assuming the circuit is operational, at least once, one transistor between A and B is in an on-state, a conducting state, or a state where current can flow. Furthermore, in the case of "A and B indirect connection", there are cases where one transistor between A and B is in a off-state or a non-conducting state. In the case of "A and B indirect connection", if multiple transistors are connected between A and B, assuming the circuit is operational, at least once, each of the multiple transistors between A and B is in an on-state, a conducting state, or a state where current can flow. That is, in the case of "A and B indirect connection", multiple transistors do not necessarily need to be in an on-state, a conducting state, or a state where current can flow simultaneously. Therefore, the case of "A and B being indirectly connected" includes situations where multiple transistors between A and B simultaneously or at different times become off or non-conducting. As another example, when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C being indirectly connected," "B and C being indirectly connected," or "A and B being indirectly connected." Note that, as described below, when a fixed potential V is supplied to C from a power source or GND, etc., while it is possible to say "A and C being indirectly connected" or "B and C being indirectly connected," it is not possible to say "A and B being indirectly connected."

[0662] The above examples illustrate situations where "indirect connection" can or cannot be described. However, the following examples illustrate other situations where "indirect connection" cannot be described. Even when there is signal exchange or potential interaction between A and B during circuit operation, there are exceptions where "A and B are indirectly connected" cannot be described. An example of such an exception is when A and B are connected through an insulator. That is, when A and B are connected through an insulator, "A and B are indirectly connected" cannot be described. A concrete example of A and B being connected through an insulator is when a capacitor is connected between A and B. Another example of A and B being connected through an insulator is when a gate insulating film of a transistor is sandwiched between A and B. In this case, "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected" cannot be described.

[0663] As another example where it's inappropriate to say "A and B are indirectly connected," cases where there is no signal exchange or potential interaction between A and B can be cited. For instance, consider the following situation: along the path from A to B, multiple transistors are connected through their source and drain, and a fixed potential V is supplied from the power supply or GND at the nodes between the transistors. In this case, while it's not appropriate to say "A and B are indirectly connected," it's possible to say "A and V are indirectly connected" or "B and V are indirectly connected." Similarly, if A and C are connected through the source and drain of transistor TrP, and B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from the power supply or GND, it's inappropriate to say "A and B are indirectly connected," but rather "A and C are indirectly connected" or "B and C are indirectly connected."

[0664] Although the above examples of "indirect connection" are shown, the provisions of "indirect connection" are included in the provisions of "electrical connection", so in the case of "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0665] Next, specific examples of the "direct connection" case are shown. As examples of "A and B directly connected," there are cases where A and B are not connected through circuit elements. Furthermore, when A and B are connected to a power supply or GND (which provides a fixed potential V) without circuit elements, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Furthermore, even when A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A and B are directly connected." However, since A and V, or B and V, are connected through the source and drain of a transistor, it cannot be said that they are directly connected; instead, it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0666] Although the above examples show "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", so in the case of "A and B are directly connected", it can be said that "A and B are electrically connected".

[0667] [Symbol Explanation]

[0668] 10: Component layer; 11: Storage circuit section; 12: Interface section; 14: Operation block; 15: Controller section; 16: Product summation section; 17: Activation function operation section; 18: Data conversion section; 19: Load memory section; 20: Readout amplifier section; 21: Readout amplifier; 30: Storage circuit; 31: Storage cell; 40: Component layer; 41: Storage cell; 42: Storage cell array; 51: Transistor; 52: Semiconductor layer; 53: Transistor

Claims

1. A semiconductor device, comprising: First storage unit; Readout amplifier; Second storage unit; as well as computation block, The first storage unit, the sense amplifier, and the arithmetic block are disposed in the first element layer. The second storage cell is disposed in the second element layer. The second component layer is disposed on top of the first component layer. The second storage unit is electrically connected to the sense amplifier and the first storage unit via the first bit line. The first storage unit is electrically connected to the computation block via a second bit line. Furthermore, the data transmitted to the computation block is the data written to the first storage cell by activating the data held in the second storage cell in the sense amplifier.

2. The semiconductor device according to claim 1, The first memory cell includes a first transistor. The first transistor includes a first semiconductor layer containing silicon in the channel formation region.

3. The semiconductor device according to claim 1 or 2, The second memory cell includes a second transistor. The second transistor includes a second semiconductor layer comprising an oxide semiconductor in the channel forming region.

4. The semiconductor device according to claim 1, The first storage unit is a storage unit of a static random access memory.

5. The semiconductor device according to claim 1, The first line has a portion between the second memory cell and the sense amplifier, and between the second memory cell and the first memory cell, that is parallel to a direction perpendicular to the surface of the substrate on which the first element layer is disposed.

6. A semiconductor device, comprising: First storage unit; Readout amplifier; Second storage unit; as well as computation block, The first storage unit, the sense amplifier, and the arithmetic block are disposed in the first element layer. The second storage cell is disposed in the second element layer. The second component layer is disposed on top of the first component layer. The second storage unit is electrically connected to the sense amplifier and the first storage unit via the first bit line. The first storage unit is electrically connected to the computation block via a second bit line. The data transmitted to the computation block is the data written to the first memory cell by activating the data held in the second memory cell in the sense amplifier. Furthermore, the computation block includes a product sum computation unit, an activation function computation unit, a data conversion unit, a loading and storage unit, and a controller unit.

7. The semiconductor device according to claim 6, The first memory cell includes a first transistor. The first transistor includes a first semiconductor layer containing silicon in the channel formation region.

8. The semiconductor device according to claim 6 or 7, The second memory cell includes a second transistor. The second transistor includes a second semiconductor layer comprising an oxide semiconductor in the channel forming region.

9. The semiconductor device according to claim 6, The first storage unit is a storage unit of a static random access memory.

10. The semiconductor device according to claim 6, The first line has a portion between the second memory cell and the sense amplifier, and between the second memory cell and the first memory cell, that is parallel to a direction perpendicular to the surface of the substrate on which the first element layer is disposed.

11. The semiconductor device according to claim 6, The product and arithmetic unit includes an arithmetic circuit and an analog-to-digital converter circuit. The arithmetic circuit includes a cell array for performing product summation operations and an input circuit that converts the input digital signal into an analog signal and inputs it into the cell array. The analog-to-digital converter circuit has the function of converting the analog signal output by the arithmetic circuit into a digital signal. The input circuit and the analog-to-digital conversion circuit are disposed in the first component layer. Furthermore, the cell array is disposed in the second element layer.

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