Metallized structure having an outer metallization layer comprising a nickel layer and a platinum layer for reducing intermetallic compound formation

Abstract

A metallization structure having an outer metallization layer including a copper (Cu) layer, a nickel (Ni) layer, and a platinum (Pt) layer to reduce intermetallic compound formation due to high temperature exposure. The copper (Cu) layer includes a plurality of interconnects. The metallization structure includes a plurality of interconnect bumps, where each bump is coupled to a Cu interconnect of the plurality of Cu interconnects. The Pt layer is adjacent to the Ni layer such that the Pt layer is between the Ni layer and the plurality of interconnect bumps. In this regard, any intermetallic compound (IMC) formation due to the material of the interconnect bumps (e.g., due to a reflow process) coupling to the Cu interconnects is reduced, resulting in an outer metallization layer that is mechanically stronger.

Description

background

[0001] I. Technical Field

[0002] This disclosure relates to integrated circuit (IC) dies, and more specifically to the design and fabrication of external metallization to address the problem of intermetallic compound formation.

[0003] II. Background Technology

[0004] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages, also known as “semiconductor packages” or “chip packages.” An IC package includes one or more semiconductor dies that serve as the IC, which are mounted on and electrically coupled to a package substrate to provide physical support and electrical interfaces for the dies. The package substrate also includes one or more metallization layers comprising metal interconnects (e.g., metal traces, metal lines), wherein vertical interconnect channels (vias) couple the metal interconnects between adjacent metallization layers together to provide electrical interfaces between the dies. The package substrate also includes an outer metallization layer comprising metal interconnects coupled to external metal interconnects (e.g., ball grid array (BGA) interconnects) to provide external interfaces between the dies in the IC package. The external metal interconnects may also be coupled (e.g., soldered) to traces in a printed circuit board (PCB) to attach the package to the PCB and electrically interconnect its dies with the circuitry of the PCB. The die also includes one or more metallization layers, which include metal interconnects (e.g., metal pads, metal traces, metal lines). The outer metallization layer in the one or more metallization layers typically electrically couples the metal interconnects in the die to metal interconnects (e.g., metal traces) exposed in the outer metallization layer of the package substrate via interconnect balls. Summary of the Invention

[0005] The aspects disclosed in the detailed description include a metallization structure having an outer metallization layer comprising nickel (Ni) and platinum (Pt) to reduce the formation of intermetallic compounds (IMCs). As an example, this metallization structure may be part of a back-end process (BEOL) interconnect structure for a semiconductor die or a packaging substrate for an IC package. The metallization structure includes multiple metal layers, including an outer metallization layer. The outer metallization layer is the last metal layer fabricated on the die and is coupled to interconnect bumps. The outer metallization layer includes a copper (Cu) layer comprising multiple interconnects for conducting electronic signals, and multiple interconnect bumps, wherein each bump is coupled to a Cu interconnect among the multiple Cu interconnects. The outer metallization layer also includes a Ni layer located between the Cu layer and the multiple interconnect bumps, and a Pt layer adjacent to the Ni layer, such that the Pt layer is located between the Ni layer and the multiple interconnect bumps. In this respect, any IMC formation caused by the material of the interconnect bumps (e.g., due to reflow processes) coupling to the Cu interconnects is reduced. Interconnect chromatic aberration (IMC) can degrade the mechanical properties of the coupling between Cu interconnects and interconnect bumps, thus posing a risk of reduced yield and / or increased interconnect resistance. Furthermore, repeated exposure of the metallization structure to high temperatures, such as when coupling interconnect bumps to an outer metallization layer, can lead to further IMC formation. When the metallization structure is formed on the die and / or substrate, subsequent exposure during integrated circuit (IC) packaging assembly, such as attaching the die to the IC package and attaching the IC package to the printed circuit board (PCB), can also result in further IMC formation. Reducing IMC formation leads to higher mechanical strength of the outer metallization layer.

[0006] In this regard, in one aspect, the metallization structure includes interconnect spheres and a plurality of metallization layers, each extending in a first direction. The outer metallization layer of the plurality of metallization layers includes a copper (Cu) interconnect. The Cu interconnect includes a first surface and a first Cu layer, wherein the interconnect spheres are coupled to the first surface. The Cu interconnect further includes: a first nickel (Ni) layer located between the first Cu layer and the interconnect spheres in a second direction orthogonal to the first direction; and a platinum (Pt) layer adjacent to the first Ni layer, such that the Pt layer is located between the first Ni layer and the interconnect spheres in the second direction.

[0007] In another aspect, a method for fabricating a metallized structure to reduce the formation of intermetallic compounds (IMCs) includes: forming a plurality of metallized layers including an outer metallized layer, and forming copper (Cu) interconnects in the outer metallized layers. The Cu interconnects have a first surface. Forming the Cu interconnects includes: depositing a first Cu layer extending along a first direction, depositing a first nickel (Ni) layer adjacent to the first Cu layer extending along the first direction, and depositing a platinum (Pt) layer adjacent to the first Ni layer extending along the first direction. The method further includes coupling interconnect balls to the first surface of the Cu interconnects. Attached Figure Description

[0008] Figure 1 This is a side view of an exemplary IC package, in which the IC package is a three-dimensional (3D) integrated circuit (IC) (3DIC) package, which includes a metallization structure with an outer metallization layer using nickel (Ni) and platinum (Pt) to reduce the formation of intermetallic compounds (IMC);

[0009] Figure 2A yes Figure 1 The side view of the exemplary metallization structure of the exemplary die shown has an outer metallization layer using Ni and Pt to reduce the formation of intermetallic compound (IMC);

[0010] Figure 2B yes Figure 2A A close-up view of a portion of the copper (Cu) interconnects and passivation layer formed using Ni and Pt to reduce the intermetallic compound (IMC) formation;

[0011] Figure 2C yes Figure 2A A close-up view of this portion of the Cu interconnect after the interconnect balls have been deposited on the surface of the Cu interconnect and exposed to the high temperature required to form the IMC;

[0012] Figure 2D yes Figure 2A A close-up view of another embodiment that uses Ni and Pt to reduce the formation of intermetallic compound (IMC) in Cu interconnects and a portion of the passivation layer;

[0013] Figure 3A yes Figure 1 A side view of a portion of an exemplary substrate shown, the substrate including a metallization structure employing Ni and Pt layers to reduce the formation of intermetallic compound (IMC);

[0014] Figure 3B yes Figure 3A The use of Ni and Pt to reduce the metal pads formed by IMC (Integrated Molding Complex) is shown in a close-up view.

[0015] Figure 3C yes Figure 3A A close-up view of the metal pads after the interconnect balls have been deposited on the surface of the metal pads and exposed to the high temperatures required to form the IMC;

[0016] Figure 4 This is a flowchart illustrating an exemplary manufacturing process for fabricating a metallized structure, wherein the metallized structure employs Ni and Pt layers to reduce IMC formation, including but not limited to... Figures 2A to 2D and Figures 3A to 3C Exemplary metallization structures in;

[0017] Figures 5A to 5C This is a flowchart illustrating another exemplary manufacturing process for fabricating a metallized structure, wherein the metallized structure employs Ni and Pt layers to reduce IMC formation, including but not limited to... Figures 2A to 2D and Figures 3A to 3C Exemplary metallization structures in;

[0018] Figures 6A to 6G It is based on Figures 5A to 5C An exemplary manufacturing stage during the manufacturing of a metallized structure in the manufacturing process;

[0019] Figure 7 This is a block diagram of an exemplary processor-based system that may include components deployed in an IC package, wherein the IC package includes metallization structures employing Ni and Pt layers to reduce IMC formation, including but not limited to... Figures 2A to 2D and Figures 3A to 3C And according to Figure 4 and Figures 5A to 5C An exemplary metallized structure manufactured using an exemplary manufacturing process; and

[0020] Figure 8 This is a block diagram of an exemplary wireless communication device, which includes a radio frequency (RF) component deployed in an IC package, wherein the IC package includes a metallization structure employing Ni and Pt layers to reduce IMC formation, including but not limited to... Figures 2A to 2D and Figures 3A to 3C And according to Figure 4 and Figures 5A to 5C An exemplary metallized structure manufactured using an exemplary manufacturing process. Detailed Implementation

[0021] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects. Unless otherwise specifically stated, the term “adjacent” as used herein means spatially adjacent but not necessarily adjacent to something, as shown in the accompanying drawings.

[0022] The aspects disclosed in the detailed description include a metallization structure having an outer metallization layer comprising nickel (Ni) and platinum (Pt) to reduce the formation of intermetallic compounds (IMCs). As an example, this metallization structure may be part of a back-end process (BEOL) interconnect structure for a semiconductor die or a packaging substrate for an IC package. The metallization structure includes multiple metal layers, including an outer metallization layer. The outer metallization layer is the last metal layer fabricated on the die and is coupled to interconnect bumps. The outer metallization layer includes a copper (Cu) layer comprising multiple interconnects for conducting electronic signals, and multiple interconnect bumps, wherein each bump is coupled to a Cu interconnect among the multiple Cu interconnects. The outer metallization layer also includes a Ni layer located between the Cu layer and the multiple interconnect bumps, and a Pt layer adjacent to the Ni layer, such that the Pt layer is located between the Ni layer and the multiple interconnect bumps. In this respect, any IMC formation caused by the material of the interconnect bumps (e.g., due to reflow processes) coupling to the Cu interconnects is reduced. Interconnect chromatic aberration (IMC) can degrade the mechanical properties of the coupling between Cu interconnects and interconnect bumps, thus posing a risk of reduced yield and / or increased interconnect resistance. Furthermore, repeated exposure of the metallization structure to high temperatures, such as when coupling interconnect bumps to an outer metallization layer, can lead to further IMC formation. When the metallization structure is formed on the die and / or substrate, subsequent exposure during integrated circuit (IC) packaging assembly, such as attaching the die to the IC package and attaching the IC package to the printed circuit board (PCB), can also result in further IMC formation. Reducing IMC formation leads to higher mechanical strength of the outer metallization layer.

[0023] In this respect, Figure 1 This is a side view of an exemplary IC package 100, in which the IC package is a three-dimensional (3D) integrated circuit (IC) (3DIC) package 100, which includes metallization structures 101A to 101B, 102A to 102B with an outer metallization layer using Ni and Pt to reduce IMC formation. The IC package 100 includes a package substrate 103 and an interposer substrate 104. The package substrate 103 and the interposer substrate 104 share signal and power routing, and for convenience, both may be simply referred to as substrate 106.

[0024] In this example, the IC package 100 includes a first die 108(1) and a second die 108(2), which are included in respective first die packages 112(1) and second die packages 112(2), and these die packages are stacked on top of each other in the vertical direction (Z-axis direction). The first die package 112(1) of the IC package 100 includes a first die 108(1) coupled to a package substrate 103. In this example, the package substrate 103 includes a first upper outer metallization layer 114. The first upper outer metallization layer 114 provides an electrical interface for routing signals to the first die 108(1). The first die 108(1) is coupled to die interconnects 118 (e.g., bumped metal bumps, pillars), which are electrically coupled to metal interconnects 120 in the first upper outer metallization layer 114. The first die 108(1) includes a metallization structure 101A, which couples the die interconnects 118 to a circuit within the first die 108(1) and reduces the IMC formed by the metals in the metallization structure 101A. The metallization structures 101A to 101B will be discussed in more detail in conjunction with Figures 2A to 2D The metallization structures 101A to 101B will be discussed in more detail in conjunction with Figure 3A Figures 3D. The metal interconnects 120 in the first upper metallization layer 114 are coupled to metal vias 122 (not visible) in the package substrate 103, which are coupled to metal interconnects 124 in a second bottom outer metallization layer 116. In this way, the package substrate 103 provides an interconnection between its first metallization layer 114 and the second metallization layer 116, thereby providing signal routing to the first die 108(1). Both the first metallization layer 114 and the second metallization layer 116 will respectively include metallization structures 102A and 102B, and will be discussed in more detail in conjunction with

[0025] In Figure 1In the exemplary IC package 100, an additional optional second die package 112 (2) is provided and coupled to the first die package 112 (1) to support a plurality of dies. For example, the first die 108 (1) in the first die package 112 (1) may include an application processor, and the second die 108 (2) may be a memory die, such as a dynamic random access memory (DRAM) die that provides memory support for the application processor. In this respect, in this example, the first die package 112 (1) also includes an interposer substrate 104 disposed on a package mold 130 that covers the first die 108 (1) and is adjacent to a second non-functional side 128 (2) of the first die 108 (1). The interposer substrate 104 also includes one or more metallization layers 132, each metallization layer including a metal interconnect 134 to provide interconnection to the second die 108 (2) in the second die package 112 (2). The second die package 112(2) is physically coupled and electrically coupled to the first die package 112(1) by means of external interconnects 136 (e.g., solder bumps, BGA interconnects) coupled to the interposer substrate 104. The external interconnects 136 are coupled to metal interconnects 134 in the interposer substrate 104 through metal vias 138 (not visible). The first die package 112(1) includes vertical interconnects 140 to couple the second die 108(2) to the external interconnects 126 and to the first die 108(1) through the package substrate 103. The second die 108(2) also includes a metallization structure 101B that couples the external interconnects 136 to the circuitry within the second die 108(2) and reduces the IMC formed by the metal in the metallization structure 101B.

[0026] Figure 2A This is a side view of an exemplary metallization structure 200 of an exemplary die 108 (1), such as Figure 1 The metallization structure 101A shown employs Ni and Pt to reduce IMC formation. An exemplary die 108(1) is shown relative to... Figure 1The die 108(1) shown is oriented by a 180° rotation. The metallization structure 200 includes multiple metallization layers 202 and 204, including an outer metallization layer 202. The metallization layers 202 and 204 extend in a first horizontal direction (X-axis direction, Y-axis direction). In this example, the outer metallization layer 202 includes a redistribution layer (RDL) 206 and a dielectric 208. The metallization layer 204 includes the dielectric 208 and a metal pad 210 electrically coupled to the RDL 206 in a second vertical direction (Z-axis direction). The RDL 206 includes multiple interconnects, including copper (Cu) interconnects 212. The metal pads 210 are also electrically coupled to circuitry (not shown) within the die 108(1). A passivation layer 214 extends in the first horizontal direction (X-axis direction, Y-axis direction) and is adjacent to the RDL 206 and the Cu interconnects 212. Passivation layer 214 protects the underlying metallized structure from chemical corrosion. Figure 2B and Figure 2C Let's discuss part 216 of RDL 206.

[0027] Figure 2B yes Figure 2A A close-up view of portion 216 of the Cu interconnect 212 and passivation layer 214 formed by using Ni and Pt to reduce IMC formation. The Cu interconnect 212 has a surface 218 and includes a Cu layer 220 extending in a first horizontal direction (X-axis direction, Y-axis direction), a first Ni layer 222 disposed directly adjacent to the first Cu layer 220, and a Pt layer 224 disposed directly adjacent to the first Ni layer 222. In other words, the first Ni layer 222 is located in a second vertical (Z-axis) direction orthogonal to the first horizontal direction between the first Cu layer 220 and the interconnect sphere (see...). Figure 2C Between the first Ni layer 222 and the interconnect sphere (see [link]). The Pt layer 224 is located in the second vertical direction between the first Ni layer 222 and the interconnect sphere (see [link]). Figure 2C The first Cu layer 220 has a thickness h1 ranging from 1,000 nanometers (nm) to 5,000 nm, depending on the desired conductivity. If a portion 216 of RDL 206 requires high-power processing, the thickness h1 may exceed this range. The first Ni layer 222 has a thickness h2 ranging from 500 nm to 1,000 nm. The Pt layer 224 has a thickness h3 ranging from 50 nm to 150 nm. The passivation layer 214 is disposed directly adjacent to the Pt layer 224 and has a thickness h4 ranging from 10 nm to 100 nm. The ratio of h1 to h2 is between 2 and 5. The ratio of h2 to h3 is between 6 and 10.

[0028] Figure 2C yes Figure 2AA close-up view of portion 216 of the Cu interconnect 212 and passivation layer 214 after interconnect balls 226 have been deposited on surface 218 of Cu interconnect 212 and exposed to the high temperatures of forming IMC 228. Interconnect balls 226 may include solder balls. IMC 228 is coupled to interconnect balls 226 and includes diffusion products of the material of interconnect balls 226 and the material of the first Cu layer 220. In this example, h1 is 1,550 nm, h2 is 400 nm, h3 is 80 nm, and Cu interconnect 212 has been exposed to high temperatures in three separate instances: reflowing interconnect balls 226, connecting die 108 (1) to interposer substrate 104, and connecting package substrate 103 to printed circuit board (PCB). In this example, the maximum thickness h5 of IMC 228 is approximately 1,600 nm and is defined within Ni layer 222, thereby maintaining the integrity of Cu layer 220 and Cu interconnect 212 as a whole.

[0029] Figure 2D yes Figure 2A A close-up view of another embodiment of Cu interconnect 230 and passivation layer 214 portion 216, which uses Ni and Pt to reduce the formation of IMC. Figure 2D Cu interconnect 230 and Figure 2BCommon elements between the elements of Cu interconnect 212 are shown by common element numbers. Cu interconnect 230 includes a first Cu layer 232 extending in a first horizontal direction (X-axis direction, Y-axis direction), a first Ni layer 234 disposed directly adjacent to the first Cu layer 232, a second Cu layer 236 disposed directly adjacent to the first Ni layer 234 and located between the Pt layer 224 and the first Ni layer 234 in a second vertical (Z-axis) direction, a second Ni layer 238 disposed directly adjacent to the second Cu layer 236 and located between the second Cu layer 236 and the Pt layer 224 in the second vertical (Z-axis) direction, and a Pt layer 224 disposed directly adjacent to the second Ni layer 238. The first Cu layer 232 has a thickness h6 in the range of at least 1,000 nanometers (nm) to 5,000 nm, depending on the desired conductivity. The first Ni layer 234 has a thickness h7 in the range of 200 nm to 500 nm. The second Cu layer 236 has a thickness h8 ranging from 500 nanometers (nm) to 1,000 nm. The second Ni layer 238 has a thickness h9 ranging from 200 nm to 500 nm. The Pt layer 224 has a thickness h3 ranging from 50 nm to 150 nm. The passivation layer 214 is disposed directly adjacent to the Pt layer 224 and has a thickness h4 ranging from at least 10 nm to 100 nm. The ratio of h7 to h8 is between 1.5 and 4.0. The ratio of h7+h8+h9 to h3 is between 9 and 18. Note that if the pad is suitable for bump formation, a pad similar to the metal pad 210 may consist of Cu, Ni, and Pt layers having the same configuration and ratio as the Cu interconnects 212 and 230, such as a pad directly electrically coupled to an interconnect ball without an RDL layer (such as RDL layer 206).

[0030] Figure 3A yes Figure 1 The shown is a side view of a portion of a packaging substrate 103, which includes metallization structures such as metallization structures 102A and 102B that employ Ni and Pt layers to reduce IMC formation. The packaging substrate 103 is shown relative to... Figure 1 The orientation of the package substrate 103 shown is rotated by 180°. The package substrate 103 includes multiple metallization layers 301, including outer metallization layers 114 and 116. The outer metallization layers 114 and 116 respectively include multiple Cu interconnects (metal pads, traces) 302 and 304. As one of the multiple Cu interconnects 304, the metal pad 306 is adapted to couple to an interconnect ball and will bond... Figure 3B and Figure 3C Describe it.

[0031] Figure 3B yes Figure 3AA close-up view of the metal pad 306 used to reduce IMC formation by employing Ni and Pt. The metal pad 306 has a surface 308 and includes a first Cu layer 310 extending in a first horizontal direction (X-axis direction, Y-axis direction), a first Ni layer 312 disposed directly adjacent to the first Cu layer 310, and a Pt layer 314 disposed directly adjacent to the first Ni layer 312. In other words, the first Ni layer 312 is located in a second vertical direction (Z-axis direction) orthogonal to the first direction between the first Cu layer 310 and the interconnect ball (see...). Figure 3C Between the first Ni layer 312 and the interconnect sphere (see [link]). The Pt layer 314 is located in the second vertical direction between the first Ni layer 312 and the interconnect sphere (see [link]). Figure 3C The first Cu layer 310 has a thickness h10 ranging from 5,000 nm to 25,000 nm. The first Ni layer 312 has a thickness h11 ranging from 500 nm to 1,000 nm. The Pt layer 314 has a thickness h12 of at least 50 nm to 150 nm. The ratio of h11 to h12 is between 6 and 10.

[0032] Figure 3C yes Figure 3A A close-up view of the metal pad 306 after the interconnect ball 316 has been deposited on the surface 308 of the metal pad 306 and has been exposed to the high temperature of the formation of the IMC 318. The IMC 318 is coupled to the interconnect ball 316 and comprises diffusion products of the material of the interconnect ball 316 and the material of the first Cu layer 310. In this example, the metal pad 306 has been exposed to high temperature. Given the range of Ni and Pt... Figure 2B Given the similar scope, the maximum thickness h13 of IMC 318 will be similar to h5.

[0033] Metallization structures with an outer metallization layer employing Ni and Pt to reduce IMC formation can be manufactured using various manufacturing processes, including but not limited to... Figure 1 The related IC package 100 includes Figures 2A to 2D and Figures 3A to 3C The outer metallization layers of Cu interconnects 212, 230, 302 and 304 in the process. Figure 4 This is a flowchart illustrating an exemplary manufacturing process 400 for fabricating a metallized structure, which includes Cu interconnects, such as... Figure 1 In the relevant IC package 100 Figures 2A to 2D and Figures 3A to 3C Cu interconnects 212, 230, 302, and 304 in which the outer metallization layer employs Ni and Pt layers to reduce IMC formation, including but not limited to... Figure 1 , Figures 2A to 2D and Figures 3A to 3C In the outer metallization layer.

[0034] In this respect, Figure 4 A first exemplary step in the manufacturing process 400 may include: forming a plurality of metallization layers 202, 204, 301 including outer metallization layers 114, 116, 202. Figure 4 (See box 402 in the text). The next step in manufacturing process 400 may include: forming Cu interconnects 212, 230, 306 in outer metallization layers 114, 116, 202, these Cu interconnects 212, 230, 306 having first surfaces 218, 308 (…). Figure 4 (See box 404 in the image). The manufacturing process for forming Cu interconnects 212, 230, and 306 includes the following three steps. The first step includes: depositing first Cu layers 220, 232, and 310 to extend in a first direction (…). Figure 4 (Box 406 in the middle). The next step in the manufacturing process of forming Cu interconnects 212, 230, 306 may include: depositing a first Ni layer 222, 312 adjacent to the first Cu layer 220, 232, 310 to extend in the first direction ( Figure 4 (Box 408 in the middle). The next step in the manufacturing process of forming Cu interconnects 212, 230, 306 may include: depositing Pt layers (24, 314) adjacent to the first Ni layers 222, 312 to extend in the first direction ( Figure 4 (Box 410 in the middle). When performing the first three steps on the die, the corresponding steps can be performed by placing the die in an evaporation chamber to deposit the three metals. When performing the first three steps on the substrate, the corresponding steps can be performed by placing the substrate in an evaporation chamber to deposit the three metals. The next step in the manufacturing process 400 may include: coupling interconnect balls 226, 316 to the first surfaces 218, 308 of Cu interconnects 212, 230, 306 ( Figure 4 (See box 412 in the text). This step in the manufacturing process may be performed by a different company than the one that performed the previous manufacturing steps, and is typically performed by a packaging company that can deploy bump forming services.

[0035] Other manufacturing processes can also be used to fabricate metallized structures that include Cu interconnects, such as Figure 1 In the relevant IC package 100 Figures 2A to 2D and Figures 3A to 3C Cu interconnects 212, 230, 302, and 304 in which the outer metallization layer employs Ni and Pt layers to reduce IMC formation, including but not limited to... Figure 1 , Figures 2A to 2D and Figures 3A to 3C In the outer metallization layer. In this respect, Figures 5A to 5C This is a flowchart illustrating another exemplary manufacturing process for fabricating a metallized structure, which includes Cu interconnects, such as... Figure 1 In the relevant IC package 100 Figures 2A to 2D and Figures 3A to 3C Cu interconnects 212, 230, 302, and 304 in which the outer metallization layer uses Ni and Pt layers to reduce IMC formation, including but not limited to... Figure 1 , Figures 2A to 2D and Figures 3A to 3C The outer metallization layer in the middle. Figure 6A Figure 6H is based on Figures 5A to 5C An exemplary manufacturing stage during the fabrication of a metallized structure in a manufacturing process. For example... Figures 6A to 6G The manufacturing process 500 shown in manufacturing stages 600A to 600G is referenced in the manufacturing process 500. Figure 2A Metallization structure 200 and Figure 1 The relevant IC package 100 in the reference, and therefore will be referenced Figures 2A to 2C Let's discuss the metallization structure 200, which is deployed on existing dies, such as... Figure 1 The die 108 (1) in the related IC package 100.

[0036] In this respect, such as Figure 6A As shown in manufacturing stage 600A, an exemplary step in manufacturing process 500 is to pattern die 108 (1) using conventional photolithography to expose metal pads 210 through solder mask layer 602. Figure 5A (See box 502 in the figure). As shown, die 108 (1) and metal pad 210 have been manufactured using conventional techniques to have multiple metallization layers. Figure 6B As shown in manufacturing stage 600B, the next step in manufacturing process 500 may include forming Cu interconnect 212. Forming Cu interconnect 212 includes depositing first Cu layers 220, 232, 310 extending in a first direction, depositing first Ni layers 222, 312 adjacent to the first Cu layers 220, 232, 310 extending in the first direction, and depositing Pt layers 224, 314 adjacent to the first Ni layers 222, 312 extending in the first direction. Figure 5A (Box 504 in the text). For clarity, Figures 6B to 6G Individual Cu, Ni, and Pt layers are not shown. For example... Figure 6C As shown in manufacturing stage 600C, the next step in manufacturing process 500 may include: applying a passivation layer 214, such as silicon nitride (SiN), to the surface 218 of Cu interconnect 212. Figure 5A (Box 506 in the middle). Figure 6DAs shown in manufacturing stage 600D, the next step in manufacturing process 500 may include: patterning die 108 (1) using conventional photolithography, including adding a photoresist layer 604 and a passivation layer 214 that exposes opening 606 over Cu interconnect 212, to begin adapting die 108 (1) to a subprocess for receiving interconnect balls. Figure 5B (Box 508 in the middle). Figure 6E As shown in manufacturing stage 600E, the next step in manufacturing process 500 may include: dry etching the passivation layer 214 in opening 606 to expose surface 218 ( Figure 5B (Box 510 in the middle). Figure 6F As shown in manufacturing stage 600F, the next step in manufacturing process 500 may include: stripping the remaining photoresist layer 604 on die 108 (1). Figure 5B (Box 512 in the middle). Figure 6G As shown in manufacturing stage 600G, the next step in manufacturing process 500 may include: forming interconnect balls, such as interconnect balls 226, in the openings 606 of the passivation layer 214. Figure 5C (Box 514 in the middle).

[0037] Electronic devices including IC packages can be provided or integrated into any processor-based device, wherein the IC package has a metallized structure having an outer metallization layer employing Ni and Pt to reduce IMC formation, including but not limited to... Figure 1 In the relevant IC package 100 Figures 2A to 2D and Figures 3A to 3C The outer metallization layer in the middle includes Cu interconnects 212, 230, 302 and 304, and may be based on, but is not limited to, [the following]. Figure 4 and Figures 5A to 5C The exemplary manufacturing processes described herein and manufactured according to any aspect disclosed herein. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, and multirotor aircraft.

[0038] In this respect, Figure 7 This is a block diagram of an exemplary processor-based system that may include components deployed in an IC package, wherein the IC package includes metallization structures employing Ni and Pt layers to reduce IMC formation, including but not limited to... Figures 2A to 2D and Figures 3A to 3C And according to Figure 4 and Figures 5A to 5C The exemplary metallization structure is manufactured using an exemplary manufacturing process and according to any exemplary aspect disclosed herein. In this example, the processor-based system 700 may be formed as an IC package 702, such as... Figure 1 The IC package 100 is included. The processor-based system 700 includes a central processing unit (CPU) 708, which includes one or more processors 710, which may also be referred to as a CPU core or processor core. The CPU 708 may have a cache memory 712 coupled to the CPU 708 for fast access to temporarily stored data. The CPU 708 is coupled to a system bus 714 and may be coupled to master and slave devices included in the processor-based system 700. As is well known, the CPU 708 communicates with these other devices by exchanging address, control, and data information via the system bus 714. For example, the CPU 708 may communicate a bus transaction request to a memory controller 716, which is an example of a slave device. Although in Figure 7 Not illustrated, but multiple system buses 714 may be provided, each of which constitutes a different interconnect architecture.

[0039] Other master and slave devices can be connected to system bus 714. For example... Figure 7As illustrated, these devices may include a memory system 720, one or more input devices 722, one or more output devices 724, one or more network interface devices 726, and one or more display controllers 728, the memory system including a memory controller 716 and a memory array 718. Each of the memory system 720, one or more input devices 722, one or more output devices 724, one or more network interface devices 726, and one or more display controllers 728 may be located in the same or different electronic devices. Input devices 722 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 724 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 726 may be any device configured to allow the exchange of data to and from network 730. Network 730 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth. ™ Networks and the Internet. The network interface device 726 can be configured to support any type of communication protocol desired.

[0040] CPU 708 can also be configured to access display controller 728 via system bus 714 to control information transmitted to one or more displays 732. Display controller 728 transmits information to be displayed to display 732 via one or more video processors 734, which process the information to be displayed into a format suitable for display 732. As an example, display controller 728 and video processor 734 can be included as ICs in the same or different electronic devices, and in the same or different electronic devices containing CPU 708. Display 732 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0041] Figure 8 An exemplary wireless communication device 800 is illustrated, which includes a radio frequency (RF) component formed by one or more ICs 802, wherein any IC 802 may be deployed in an IC package 803, wherein the IC package 803 includes a metallization structure employing Ni and Pt layers to reduce the formation of the IMC, including but not limited to... Figures 2A to 2D and Figures 3A to 3C And according to Figure 4 and Figures 5A to 5CThe metallized structure is manufactured using exemplary manufacturing processes and according to any exemplary aspect disclosed herein. As an example, wireless communication device 800 may include or be provided in any of the devices mentioned above. Figure 8 As shown, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 supporting bidirectional communication. Generally, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0042] The transmitter 808 or receiver 810 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages; for example, it is converted from RF to intermediate frequency (IF) in one stage of receiver 810, and subsequently from IF to baseband in another stage of the same receiver. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 8 In the wireless communication device 800, the transmitter 808 and receiver 810 are implemented using a direct frequency conversion architecture.

[0043] In the transmission path, the data processor 806 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1) and 812(2) to convert digital signals generated by the data processor 806 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0044] Within transmitter 808, low-pass filters 814(1) and 814(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 816(1) and 816(2) amplify the signals from low-pass filters 814(1) and 814(2), respectively, and provide I and Q baseband signals. Upconverter 818 upconverts the I and Q baseband signals from transmit (TX) local oscillator (LO) signal generator 822 using mixers 820(1) and 820(2) to provide upconverted signal 824. Filter 826 filters the upconverted signal 824 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 828 amplifies the upconverted signal 824 from filter 826 to obtain the desired output power level and provide the transmit RF signal. The RF signal is routed through the duplexer or switch 830 and transmitted via the antenna 832.

[0045] In the receiving path, antenna 832 receives signals transmitted by the base station and provides received RF signals, which are routed through duplexer or switch 830 and provided to low-noise amplifier (LNA) 834. Duplexer or switch 830 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Downconversion mixers 838(1) and 838(2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMP 842(1) and 842(2) and further filtered by low-pass filters 844(1) and 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. In this example, the data processor 806 includes analog-to-digital converters (ADCs) 846(1) and 846(2) to convert analog input signals into digital signals to be further processed by the data processor 806.

[0046] exist Figure 8In the wireless communication device 800, a TX LO signal generator 822 generates I and Q TX LO signals for up-conversion, while an RX LO signal generator 840 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 848 receives timing information from a data processor 806 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 822. Similarly, an RXILL circuit 850 receives timing information from a data processor 806 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 840.

[0047] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory, or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of both. As an example, the devices and components described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0048] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0049] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0050] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0051] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0052] Specific implementation examples are described in the following numbered clauses:

[0053] 1. A metallized structure, the metallized structure comprising:

[0054] Interconnected spheres; and

[0055] Multiple metallization layers, each extending in the first direction;

[0056] The outer metallization layer among the plurality of metallization layers includes copper (Cu) interconnects, wherein the Cu interconnects include:

[0057] First surface;

[0058] First Cu layer;

[0059] The interconnecting spheres are coupled to the first surface;

[0060] A first nickel (Ni) layer is located between the first Cu layer and the interconnect spheres in a second direction orthogonal to the first direction; and

[0061] A platinum (Pt) layer is adjacent to the first Ni layer, such that the Pt layer is located between the first Ni layer and the interconnect sphere in the second direction.

[0062] 2. The metallization structure according to Clause 1, further comprising:

[0063] A second Cu layer located between the Pt layer and the first Ni layer in the second direction; and

[0064] The second Ni layer is located between the second Cu layer and the Pt layer in the second direction.

[0065] 3. The metallization structure according to clause 1 or 2, further comprising:

[0066] Intermetallic compound (IMC) coupled to the interconnect ball, the IMC comprising diffusion products of the material of the interconnect ball and the material of the Cu interconnect.

[0067] 4. The metallized structure according to any one of clauses 1 to 3, wherein:

[0068] The first Cu layer has a first thickness extending in a second direction orthogonal to the first direction;

[0069] The first Ni layer has a second thickness extending in the second direction; and

[0070] The Pt layer has a third thickness extending in the second direction.

[0071] 5. The metallization structure according to Clause 4, wherein the first thickness is in the range of 1,000 nanometers (nm) to 5,000 nm.

[0072] 6. The metallization structure according to clause 4 or 5, wherein the second thickness is in the range of 500 nm to 1,000 nm.

[0073] 7. The metallization structure according to any one of clauses 4 to 6, wherein the third thickness is in the range of 50 nm to 150 nm.

[0074] 8. The metallized structure according to any one of clauses 4 to 7, wherein the ratio of the first thickness to the second thickness is between 2 and 5.

[0075] 9. The metallized structure according to any one of clauses 4 to 8, wherein the ratio of the second thickness to the third thickness is between 6 and 10.

[0076] 10. The metallization structure according to Clause 1, further comprising:

[0077] A substrate, the substrate including metal pads, the substrate being coupled to the Cu interconnect via the interconnect balls.

[0078] 11. The metallized structure according to Clause 10, wherein the substrate comprises:

[0079] The metal pads include:

[0080] Second Cu layer;

[0081] A second Ni layer is disposed adjacent to the second Cu layer; and

[0082] A second Pt layer is disposed adjacent to the second Ni layer.

[0083] 12. The metallization structure according to any one of Clauses 1 to 11, wherein the metallization structure is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; and multirotor aircraft.

[0084] 13. A method for fabricating metallized structures to reduce the formation of intermetallic compounds (IMCs), the method comprising:

[0085] Multiple metallization layers, including an outer metallization layer, are formed;

[0086] A copper (Cu) interconnect is formed in the outer metallization layer, the Cu interconnect having a first surface, and forming the Cu interconnect includes:

[0087] A first Cu layer is deposited to extend in a first direction;

[0088] Deposit a first nickel (Ni) layer adjacent to the first Cu layer to extend in the first direction; and

[0089] Deposit a platinum (Pt) layer adjacent to the first Ni layer to extend in the first direction; and

[0090] Interconnect balls are coupled to the first surface of the Cu interconnect.

[0091] 14. The method according to Clause 13, further comprising:

[0092] A second Cu layer is deposited between the Pt layer and the first Ni layer in a second direction orthogonal to the first direction; and

[0093] A second Ni layer is deposited between the second Cu layer and the Pt layer in the second direction.

[0094] 15. The method according to clause 13 or 14, further comprising:

[0095] An IMC is formed coupled to the interconnect spheres, the IMC comprising diffusion products of the material of the interconnect spheres and the material of the first Cu layer.

[0096] 16. The method according to any one of clauses 13 to 15, wherein:

[0097] The first Cu layer has a first thickness extending in the second direction;

[0098] The first Ni layer has a second thickness extending in the second direction; and

[0099] The Pt layer has a third thickness extending in the second direction.

[0100] 17. The method according to Clause 16, wherein the first thickness is in the range of 1,000 nanometers (nm) to 5,000 nm.

[0101] 18. The method according to clause 16 or 17, wherein the second thickness is in the range of 500 nm to 1,000 nm.

[0102] 19. The method according to any one of clauses 16 to 18, wherein the third thickness is in the range of 50 nm to 150 nm.

[0103] 20. The method according to any one of clauses 16 to 19, wherein the ratio of the second thickness to the third thickness is between 6 and 10.

Claims

1. A metallized structure, the metallized structure comprising: Interconnected spheres; and Multiple metallization layers, each extending in the first direction; The outer metallization layer among the plurality of metallization layers includes copper (Cu) interconnects, wherein the Cu interconnects include: First surface; First Cu layer; The interconnecting spheres are coupled to the first surface; A first nickel (Ni) layer is located between the first Cu layer and the interconnect spheres in a second direction orthogonal to the first direction; and A platinum (Pt) layer is adjacent to the first Ni layer, such that the Pt layer is located between the first Ni layer and the interconnect sphere in the second direction.

2. The metallized structure according to claim 1, further comprising: A second Cu layer located between the Pt layer and the first Ni layer in the second direction; and The second Ni layer is located between the second Cu layer and the Pt layer in the second direction.

3. The metallization structure according to claim 1, further comprising: Intermetallic compound (IMC) coupled to the interconnect ball, the IMC comprising diffusion products of the material of the interconnect ball and the material of the Cu interconnect.

4. The metallized structure according to claim 1, wherein: The first Cu layer has a first thickness extending in a second direction orthogonal to the first direction; The first Ni layer has a second thickness extending in the second direction; and The Pt layer has a third thickness extending in the second direction.

5. The metallized structure according to claim 4, wherein the first thickness is in the range of 1,000 nanometers (nm) to 5,000 nm.

6. The metallized structure according to claim 5, wherein the second thickness is in the range of 500 nm to 1,000 nm.

7. The metallization structure according to claim 5, wherein the third thickness is in the range of 50 nm to 150 nm.

8. The metallized structure according to claim 4, wherein the ratio of the first thickness to the second thickness is between 2 and 5.

9. The metallized structure according to claim 4, wherein the ratio of the second thickness to the third thickness is between 6 and 10.

10. The metallization structure according to claim 1, further comprising: A substrate, the substrate including metal pads, the substrate being coupled to the Cu interconnect via the interconnect balls.

11. The metallized structure of claim 10, wherein the substrate comprises: The metal pads include: Second Cu layer; A second Ni layer is disposed adjacent to the second Cu layer; and A second Pt layer is disposed adjacent to the second Ni layer.

12. The metallized structure of claim 1, wherein the metallized structure is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; and multirotor aircraft.

13. A method for fabricating metallized structures to reduce the formation of intermetallic compounds (IMCs), the method comprising: Multiple metallization layers, including an outer metallization layer, are formed; A copper (Cu) interconnect is formed in the outer metallization layer, the Cu interconnect having a first surface, and forming the Cu interconnect includes: A first Cu layer is deposited to extend in a first direction; Deposit a first nickel (Ni) layer adjacent to the first Cu layer to extend in the first direction; and Deposit a platinum (Pt) layer adjacent to the first Ni layer to extend in the first direction; and Interconnect balls are coupled to the first surface of the Cu interconnect.

14. The method according to claim 13, further comprising: A second Cu layer is deposited between the Pt layer and the first Ni layer in a second direction orthogonal to the first direction; as well as A second Ni layer is deposited between the second Cu layer and the Pt layer in the second direction.

15. The method according to claim 13, further comprising: An IMC is formed coupled to the interconnect spheres, the IMC comprising diffusion products of the material of the interconnect spheres and the material of the first Cu layer.

16. The method of claim 13, wherein: The first Cu layer has a first thickness extending in the second direction; The first Ni layer has a second thickness extending in the second direction; and The Pt layer has a third thickness extending in the second direction.

17. The method of claim 16, wherein the first thickness is in the range of 1,000 nanometers (nm) to 5,000 nm.

18. The method of claim 17, wherein the second thickness is in the range of 500 nm to 1,000 nm.

19. The method of claim 17, wherein the third thickness is in the range of 50 nm to 150 nm.

20. The method of claim 16, wherein the ratio of the second thickness to the third thickness is between 6 and 10.

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