Configuring memory units

Abstract

An apparatus can include a configuration memory cell. The configuration memory cell can include a first connection point to control access to one or more storage nodes of the configuration memory cell, a second connection point to manage stability of the one or more storage nodes of the configuration memory cell during the access to the configuration memory cell, and a third connection point to control a voltage transition at one or more of the storage nodes of the configuration memory cell during the access to the configuration memory cell.

Description

Cross-referencing

[0001] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 603,988, filed November 29, 2023, entitled "CONFIGURATION MEMORY CELL," the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more examples collectively relate to a configuration memory cell. One or more examples involve an additional NMOS transistor in the bit line (BL) path—which enables more reliable cell write operations under both BL high and BL low conditions compared to traditional configuration memory cells used in FPGAs. Background Technology

[0003] Storage elements (e.g., volatile storage elements, but not limited thereto) are used in a variety of operating environments. Attached Figure Description

[0004] To facilitate the identification of any particular element or action in the discussion, the most important number in the figure labels refers to the figure number of the element when it was first introduced.

[0005] Figure 1 It is a schematic diagram depicting the layout of a configured memory cell designed to provide single-event flip-flop (SEU) immunity when operating reliably in the high voltage (HV) domain, according to one or more examples.

[0006] Figure 2 It is a block diagram depicting a memory system, including the configuration of memory cells and their associated driver circuitry, according to one or more examples.

[0007] Figure 3 It is a voltage bias and status table that describes the operating state of a configured memory cell or system according to one or more examples.

[0008] Figure 4 It is a flowchart depicting a process for controlling the configuration of memory cells during an access operation, based on one or more examples.

[0009] Figure 5 It is a flowchart depicting a two-stage process for writing "0" to an example configuration memory cell, based on one or more examples.

[0010] Figure 6 It is a flowchart depicting a two-stage process for writing "1" to an example memory cell, based on one or more examples.

[0011] Figure 7It is a flowchart depicting a two-stage example process for reading “0” from an example configured memory cell, based on one or more examples.

[0012] Figure 8 It is a flowchart depicting a two-stage example process for reading "1" from an example configuration memory cell, based on one or more examples.

[0013] Figure 9 It is a block diagram of a circuit that can be used in some examples to implement the various functions, operations, actions, processes or methods disclosed herein. Detailed Implementation

[0014] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure, and specific examples of embodiments in which this disclosure may be practiced are shown by way of example. These embodiments have been described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other embodiments may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of this disclosure.

[0015] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe embodiments of this disclosure. The figures presented herein are not necessarily drawn to scale. For the reader's convenience, similar structures or components in the figures may retain the same or similar designations; however, similar designations do not imply that the structure or component must be identical in size, composition, configuration, or any other attribute.

[0016] The following description may include examples to assist those skilled in the art in practicing the embodiments disclosed herein. The use of the terms “exemplary,” “by example,” and “for example” indicates that the related descriptions are illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of this disclosure to the specified parts, steps, features, or functions, etc.

[0017] It should be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of this disclosure, but rather to represent various embodiments only. While various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0018] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure this disclosure with unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc., have been omitted, as such details are not necessary for obtaining a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0019] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and description, some figures may illustrate a signal as a single signal. It should be understood by those skilled in the art that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure can be implemented on any number of data signals, including a single data signal.

[0020] The various exemplary logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply host) may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. When a general-purpose computer including a processor executes computational instructions (e.g., software code) related to the embodiments of this disclosure, the general-purpose computer is considered a special-purpose computer.

[0021] The implementation scheme can be described based on a process depicted as a flowchart, schematic diagram, structural diagram, or block diagram. While a flowchart can describe operable actions as a continuous process, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. A process can correspond to a method, thread, function, procedure, subroutine, or subroutine, but is not limited thereto. Furthermore, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, functions can be stored or transmitted as one or more instructions or code onto a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another.

[0022] Any reference to elements in this document using names such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, referring to a first element and a second element does not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0023] As used herein, the term “substantially” means, and includes, the degree to which a given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0024] As used herein, any relational terms (such as "above", "below", "on", "under", "upper", "lower", etc., but not limited thereto) are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and such relational terms do not imply or depend on any particular preference, orientation or order unless the context clearly indicates otherwise.

[0025] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, then the element may be in direct physical or electrical contact, or there may be an intermediary element or layer. In contrast, when an element is described as "directly coupled" to another element, then there is no intermediary element or layer. The term "connection" is used interchangeably with the term "coupled" in this specification and has the same meaning unless otherwise expressly indicated or the context will otherwise indicate to a person skilled in the art.

[0026] As used herein, the terms “assert,” “deassert,” and their derivatives used with respect to the pin and the component are referred to respectively to assert or deassert the signal associated with the pin (e.g., a signal specifically assigned to or to the pin, but not limited thereto).

[0027] A "volatile memory cell" is a type of data storage that requires continuous power to maintain the information stored within it. A volatile memory cell represents information through its state (e.g., charged or not charged, high voltage or low voltage, but not limited to these), and requires continuous power to maintain its state. If the power supply to the cell is interrupted or turned off, the volatile memory cell loses its state and the information stored in it is lost.

[0028] Examples of volatile memory cells include, but are not limited to, latch circuits, flip-flop circuits, and circuits including cross-coupled inverters. Some field-programmable gate arrays (FPGAs) include configuration memory cells that include volatile memory cells. Additionally, static random access memory (SRAM) cells include volatile memory cells.

[0029] The terms "memory cell" and "volatile memory cell" are used interchangeably herein to refer to "volatile memory cell". When used in an FPGA, the example memory cell discussed herein may be referred to as a "configuration memory cell" or simply as a "configuration memory cell".

[0030] Due to transistor stress limitations and specific internal connections, conventional configuration memory cells used in FPGAs cannot perform read or write operations (cannot be written to or read) when powered on in a high-voltage domain (a voltage condition higher than the positive supply voltage). In some implementations, conventional configuration memory cells powered by a high-voltage supply are powered off, powered on with a lower-voltage supply, various access operations are performed in the lower-voltage domain, powered off again, and then powered on again with a higher-voltage supply. Power-off and power-on consume power and degrade performance. Here, "positive supply voltage" refers to the standard positive supply voltage (e.g., VDD, but not limited to) used to represent a standard logic high level (logic "1") for low-voltage components. Non-limiting examples of VDD voltage levels include 1.2V logic, 1.8V logic, 2.5V logic, 3.3V logic, and 5V logic.

[0031] As a non-limiting example, an FPGA can use 1.2V VDD for the standard logic level of low-voltage components and 9V positive high voltage (VPHV) for programming or configuration operations.

[0032] One or more examples in general relate to a configuration memory cell and an FPGA including the configuration memory cell. The configuration memory cell is designed to withstand single-event switching (SEU) (“SEU immunity”) in a high-voltage (HV) environment. More specifically, the configuration memory cell may include a high-resistance element (HRE) for SEU immunity. Non-limiting examples of HREs include various physical configurations: capacitors with layered dielectrics, high-impedance resistors, transistors configured for high resistance, and multilayer dielectric structures.

[0033] One or more examples involve including additional NMOS transistors in the bit line (BL) path—compared to traditional configuration memory cells used in FPGAs. NMOS transistors enable more reliable cell write operations under both BL high and low conditions.

[0034] In one or more examples, the configuration memory cell may include word lines (WLs) (which may be additional word lines compared to traditional configuration memory cells used in FPGAs) to enable the configuration memory cell to be written to and read at high voltages without exposing any individual device to excessive stress that could lead to a SEU. Notably, this avoids VPHV (high-voltage supply) sag during write operations and damage to the associated logic system.

[0035] In one or more examples, biasing via dedicated word lines (e.g., WL2 and WL3) allows for precise control during writing, ensuring that the correct state is set while maintaining robustness.

[0036] Various examples support multiple latch structures, such as cross-coupled inverters, NAND / NOR gates, or SRAM cells with variations such as stacking or separate power supply domains.

[0037] Various examples support both single and multiple bit lines and word lines, thus providing flexibility in FPGA integration.

[0038] Figure 1 This is a schematic diagram depicting the layout of a configuration memory cell 100, according to one or more examples, designed to provide single-event flip-flop (SEU) immunity when operating reliably in the high-voltage (HV) domain. The configuration memory cell 100 includes PMOS transistors and NMOS transistors arranged in a configuration defining cell states.

[0039] Specifically, the configuration memory cell 100 includes a pair of cross-coupled inverters (first inverter 102 and second inverter 104), wherein the corresponding output of each inverter is coupled (e.g., electrically coupled, but not limited to) to the corresponding input of the other inverter. It is noteworthy that when the signal state of the configuration memory cell 100 is configuration data (e.g., data whose values ​​determine the behavior of logic elements of the FPGA, but not limited to), the signal on the output OUT can carry the configuration data stored in the configuration memory cell 100. The configuration memory cell 100 has two stable states, here logic low "0" and logic high "1". The cross-coupled inverters are state-holding elements of the configuration memory cell 100. The cross-coupled inverters, first inverter 102 and second inverter 104, form a configuration that allows the configuration memory cell 100 to define and maintain a stable state during operation. This configuration enables the configuration memory cell 100 to hold either logic "0" or logic "1" according to the input signal.

[0040] The state of the configuration memory cell 100 is stored at storage nodes S1 and S2, which use voltage values ​​corresponding to VPHV and VSS to store the signal state of the configuration memory cell 100. The cross-coupled configuration of the first inverter 102 and the second inverter 104 strengthens the voltage levels at nodes S1 and S2 to ensure that the cell maintains a stable state.

[0041] The respective positive voltage power supply inputs of both the first inverter 102 and the second inverter 104 are coupled to a first voltage power supply VPHV, and the respective ground inputs of the two inverters are coupled to a second voltage power supply VSS. VPHV is used to represent a logic high signal state (logic "1") within the configuration memory cell 100, and VSS is used to represent a logic low signal state (logic "0") within the configuration memory cell. The respective inputs for receiving the first power supply voltage VPHV are operable to be coupled only to the first voltage power supply. In one or more examples, the respective inputs for receiving the first power supply voltage VPHV are directly coupled to the voltage power supply without any intermediate element that could switch the power supply to a lower voltage level.

[0042] The first inverter 102 includes two PMOS transistors P1A and P1B connected in series, and two NMOS transistors N1A and N1B connected in series. Similarly, the second inverter 104 includes two PMOS transistors P2A and P2B connected in series, and two NMOS transistors N2A and N2B connected in series. The PMOS transistors P1A and P1B of the first inverter 102 and P2A and P2B of the second inverter 104 respectively act as pull-up networks.

[0043] NMOS transistors N1B and N2B are controlled by word lines WL3 and WL2, respectively. When NMOS transistors N1B and N2B are turned on, NMOS transistors N1A and N1B of the first inverter 102 and NMOS transistors N2A and N2B of the second inverter 104 act as pull-down networks, as discussed below.

[0044] In the first inverter 102 and the second inverter 104, the sources of N1A and N2A are connected to the voltage power supply line VSS associated with a logic low level (0V), and the drains of N1A and N2A are connected to the sources of NMOS transistors N1B and N2B. The drain of N1B is connected to nodes S1 and OUTB, and the drain of N2B is connected to OUT and then to node S2 via a Hi-Res element.

[0045] In the first inverter 102 and the second inverter 104, the sources of P1A and P2A are connected to a first voltage power supply line VPHV associated with a logic high level. The drains of P1A and P2A are connected to the sources of PMOS transistors P1B and P2B, respectively. The drain of P1B is connected to OUTB and node S1. The drain of P2B is connected to OUT and then to node S2 via a Hi-Res element.

[0046] Figure 1 The document depicts a single instance of PMOS transistors P1A, P1B, P2A, and P2B, and a single instance of NMOS transistors N1A, N1B, N2A, and N2B. The number of NMOS and PMOS transistors used in the cross-coupled inverters, first inverter 102 and second inverter 104, can be selected to balance performance, area, and power consumption. Multiple transistors can be stacked in the presence of one or more of PMOS transistors P1A, P1B, P2A, and P2B or NMOS transistors N1A, N1B, N2A, and N2B. In a stacked configuration, the transistors are arranged such that the drain of one transistor is connected to the source of another transistor. This stacking allows for voltage division across the transistors, thereby helping to manage voltage stress within the device (e.g., ensuring that the voltage across the terminal nodes of the transistors is within tolerances, but not limited thereto), including during access operations discussed herein (e.g., read operations and two-stage write operations discussed herein, but not limited thereto).

[0047] Access devices and drive control transistors

[0048] The output terminal OUTB is connected to access device 110, which is controlled by word lines WL1 and WL2. Access device 110 selectively transmits signal states between memory node S1 of configuration memory cell 100 and bit line (BL). During a write operation, access device 110 allows signal states to be transmitted from bit line BL to configuration memory cell 100 (or more specifically, memory node S1). During a read operation, access device 110 allows signal states to be transmitted from configuration memory cell 100 (or more specifically, memory node S1) to bit line BL.

[0049] Configuration memory cell 100 may optionally include a high-resistance element (optional "Hi-Res element"). A Hi-Res element is an element (e.g., a material, structure, device, circuit, or combination / subcombination thereof, but not limited thereto) characterized by resistance to the inducement of charge flow through it, which is adapted to changes in the state of configuration memory cell 100.

[0050] Pull-up and pull-down networks of the first inverter 102

[0051] Pull-down network 106 is used to at least partially set the voltage level at output OUTB and node S1 to VSS, as discussed herein. Pull-up network 108 is used to set the voltage level at output OUTB and node S1 to VPHV, as discussed herein.

[0052] The pull-down network 106 has an NMOS cascode structure. Specifically, the pull-down network 106 includes NMOS transistors N1A and N1B arranged as cascode voltage switches (the pull-down network 106 may also be referred to as "cascode voltage switch 106"). When the cascode voltage switch is turned on, it acts as a switch to VSS.

[0053] The NMOS transistor N1B provides fine-grained control over the state of memory nodes S1 / OUTB during write and read operations. By modulating WL3, the NMOS transistor N1B adjusts how strongly memory nodes S1 / OUTB are driven to ensure smoother transitions and improved write and read margins, as discussed below. The NMOS transistor N1B may also be referred to herein as the "fine-control transistor N1B".

[0054] The fine-control transistor N1B provides stability and precise control over the voltage transitions at S1 / OUTB during read and write operations, for example, by modulating the current to / from the memory node S1 / OUTB. When the NMOS transistor N1B is turned on (e.g., WL3 is activated / set to a voltage such as 1.1V), the NMOS transistor N1B creates an additional path to the VSS power line, which helps stabilize the voltage at S1 / OUTB. When WL3 is activated, the NMOS transistor N1B provides an additional control path. Control over voltage transitions may include control over the state in which the voltage stops during a transition (e.g., start state, end state, intermediate state, but not limited thereto), control over the time taken to perform a voltage transition or intermediate transition (e.g., rise time, fall time, signal propagation time, but not limited thereto), and control over the stability of the voltage transitions (e.g., one or more of the following: smoothing voltage changes to prevent overshoot or undershoot, maintaining consistent rise and fall times, minimizing noise-induced fluctuations, or ensuring predictable stability, but not limited thereto).

[0055] This precision helps ensure that the voltage at S1 / OUTB effectively reaches its target level (e.g., VPHV or 0V) without overshoot or undershoot. By reducing the possibility of incorrect or incomplete state transitions, the NMOS transistor N1B enhances the ability to reliably write the desired logic level into memory cells. The NMOS transistor N1B may also be referred to herein as the "stable transistor N1B".

[0056] The pull-up network 108 has a PMOS cascode structure. Specifically, the pull-up network 108 includes transistors P1A and P1B arranged as cascode voltage switches (therefore, the pull-up network 108 can also be referred to as "cascode voltage switch 108"). When the cascode voltage switch 108 is turned on, it acts as a switch to VPHV.

[0057] The transistor N1A of the pull-down network 114 and the transistor P1A of the pull-up network 112 are in a common-gate configuration (their respective gates are coupled). The internal node between the respective gates of N1A and P1A serves as the input of the first inverter 102.

[0058] The stabilizing transistor N1B of pull-down network 106 and the transistor P1B of pull-up network 108 are in a common-gate configuration (the respective gates are coupled). The internal node between the respective gates of the stabilizing transistor N1B and the transistor P1B serves as the input of the first inverter 102.

[0059] Pull-up and pull-down networks of the second inverter 104

[0060] Pull-down network 114 is used to at least partially set the voltage level at output OUT and node S2 to VSS, as discussed herein. Pull-up network 112 is used to set the voltage level at output OUT and node S2 to VPHV, as discussed herein.

[0061] The pull-down network 114 has an NMOS cascode structure. Specifically, the pull-down network 114 includes N2B and N2A arranged as cascode voltage switches (therefore, the pull-down network 114 can also be referred to as "cascode voltage switch 114"), which acts as a switch to VSS when the cascode voltage switch 114 is turned on.

[0062] N2A acts as a transconductance voltage amplifier. NMOS transistor N2B acts as a buffer / voltage protection device for NMOS transistor N2A as discussed herein. Specifically, NMOS transistor N2B acts as a buffer / voltage protection between the output OUT and N2A. NMOS transistor N2B may also be referred to herein as "stabilizing transistor N2B".

[0063] In one or more examples, the protection provided by NMOS transistors N2B and N1B may be different and can be controlled individually via different signals (such as signals WL3 and WL2), but is not limited thereto. In one or more examples, configuration memory cell 100 or a device or circuit including the configuration memory cell may include corresponding connection points for receiving corresponding signals in signals WL1, WL2, or WL3. As a non-limiting example, configuration memory cell 100 or a device or circuit including the configuration memory cell may include corresponding connection points (e.g., logical and / or physical interfaces facilitating signal exchange between components, such as pads or terminals, but not limited thereto) to receive signals WL1, WL2, and WL3 and route these signals to corresponding control points (nodes or terminals) of configuration memory cell 100, wherein signals are applied to influence (e.g., control, but not limited thereto) the operation or behavior of configuration memory cell 100 or its corresponding components or subsystems).

[0064] Pull-up network 112 has a PMOS cascode structure. Specifically, pull-up network 112 includes P2A and P2B arranged as cascode voltage switches (therefore, pull-up network 108 can also be referred to as "cascode voltage switch 112"), which acts as a switch to VPHV when cascode voltage switch 112 is turned on.

[0065] The NMOS transistor N2A of pull-down network 114 and P2A of pull-up network 112 are in a common-gate configuration (their respective gates are coupled). The internal node between the respective gates of N2A and P2A serves as the input of the second inverter 104.

[0066] The transistor N2B of the pull-down network 114 and the P2B of the pull-up network 112 are in a common-source configuration (the corresponding sources are coupled). The internal node between the corresponding sources of N2B and P2B is used as the output terminal OUTB of the second inverter 104.

[0067] Optional Hi-Res elements

[0068] The terms "single event flip" and "SEU" refer to a state change at the source or drain node of a transistor caused by one or more ionized particles affecting the transistor. For example, the source or drain node of a transistor may be bombarded by heavy ions, which can cause an influx of electron-hole pairs that can drive the voltage at the source or drain node to be higher or lower. The higher or lower voltage at the source or drain node of the transistor can cause a state change in the transistor (e.g., "on" to "off" or "off" to "on"). The term SEU can be applied to a transistor to indicate that the transistor has changed state based on an SEU. The term SEU can also be applied to a device (e.g., a volatile memory element, but not limited to this) to indicate that the device has changed state based on an SEU; for example, data bits stored by a volatile memory element can be changed due to an SEU.

[0069] The terms "Single Event Flip-Intolerant" or "SEU-resistant" can refer to a state that is more resistant to SEU than another system, circuit, or device. Specifically, an SEU-resistant system, circuit, or device may include one or more elements that allow the SEU-resistant system, circuit, or device to be less likely to experience SEU than a system, circuit, or device that does not include the one or more of these elements.

[0070] Additionally or alternatively, SEU tolerance can improve a system, circuit, or device by making it more resistant to events that may interfere with the state of the latches in the system, circuit, or device. For example, SEU tolerance can improve how a system, circuit, or device responds to events that enable word lines for short periods of time. Examples of events that can enable word lines for short periods of time include, but are not limited to, user errors or malfunctions in the control system that drives the word lines.

[0071] Generally, volatile memory elements can be affected by SEUs. As a non-limiting example, the transistor nodes of the inverters in a pair of cross-coupled inverters of a volatile memory element can change state in response to an SEU, and therefore, the data bits stored by the volatile memory element can be changed.

[0072] The configuration memory cell 100 may include one or more optional high-resistance elements (“Hi-Res elements”) in the circuit, particularly in paths that include components susceptible to SEUs. For example, adding a Hi-Res element in the loop between cross-coupled inverters increases the circuit’s time constant (e.g., RC time). This increased time constant makes the circuit less susceptible to SEUs, which are typically short-duration events. SEUs can cause rapid voltage changes that can alter (e.g., flip) the state of a cross-coupled inverter. Hi-Res elements resist rapid voltage changes across the transistor, thus helping the inverter maintain or recover to its pre-SEU state before an incorrect state is fully established. Hi-Res elements, characterized by their appropriate resistance to the charge flow that may alter the state of a volatile storage device, may include components such as: resistive random access memory (ReRAM), antifuse, vertical resistor, capacitors made of one or more element layers in which the dielectric region is composed of a single or multiple layers of dielectric or semi-dielectric material, transistors coupled to behave as high-impedance elements (the transistor may be a thin-film device), high-impedance resistors, devices having dielectrics between the same metal layers including a metal gate and a contact layer, or devices having multiple dielectric layers across multiple metal layers including a metal gate and a contact layer.

[0073] In one or more examples, including Hi-Res elements in the path of the loop between cross-coupled inverters (e.g., first inverter 102 and second inverter 104) can set a higher time constant for the circuit including Hi-Res elements compared to a circuit without Hi-Res elements. This higher time constant can set a higher resistance to changes in the state of cross-coupled nodes S1 and S2 (and more generally, the configuration of memory cell 100 and compared to a circuit without Hi-Res elements) caused by relatively short-duration events. Therefore, the Hi-Res elements stabilize the state of memory cell 100.

[0074] Hi-Res elements are resistant to changes caused by both desired events (e.g., write pulses, but not limited to) and unwanted events (e.g., single-event toggle (SEU), but not limited to). Because Hi-Res elements are resistant to state changes in response to write pulses, longer write pulses can be used in instances where Hi-Res elements are present than in instances where Hi-Res elements are absent.

[0075] In one or more examples, the Hi-Res element may be coupled to the left side (first inverter 102) and the right side (second inverter 104, e.g.) of the latch structure. Figure 1(As depicted) or on both sides (a Hi-Res element coupled at the first inverter 102, and another Hi-Res element coupled at the second inverter 104). In one or more examples, multiple Hi-Res elements of the same or different types may be coupled in series, in parallel, or in any other suitable circuit topology. Hi-Res elements may be coupled (or may be coupled between) the output of one or more inverter / NAND / NOR gate implementations to the input of one or more inverter / NAND / NOR gate implementations.

[0076] As mentioned above, Hi-Res elements are optional, not required. For example, a configuration memory cell 100 without Hi-Res elements may be suitable for operating conditions in which the SEU is not expected or is processed differently.

[0077] WL1 and WL2

[0078] Access device 110 is controlled by word lines WL1 and WL2. WL1 and WL2 are received at the gates of access transistor N3 and drive control transistor N4 of access device 110, respectively. When both access transistor N3 and drive control transistor N4 are turned on, they connect bit line BL to memory node S1 / OUTB and allow bit line BL to affect the state of memory node S1 / OUTB (for write operations) or allow the state of memory node S1 / OUTB to be sensed on bit line BL (for read operations).

[0079] The stabilizing transistor N2B of the second inverter 104 is also controlled by word line WL2. When turned on, the stabilizing transistor N2B creates at least a portion of a selective path to ground (VSS) through its series connection with N2A. The stabilizing transistor N2B stabilizes the memory node S2 / OUT by providing a controlled discharge path to VSS when activated by WL2. As discussed below, modulation of WL2 determines how effectively the stabilizing transistor N2B pulls the memory node S2 / OUT to ground (VSS), thereby stabilizing the complementary state of the cross-coupled inverter during both read and write operations.

[0080] WL2 controls the gate voltages of both the stabilizing transistor N2B and the drive control transistor N4. By modulating the level of WL2, the gate-to-source voltage (Vgs) of transistors N4 and N2B is adjusted, which in turn sets their active drive strength. A higher WL2 voltage (exceeding the threshold voltage Vth) increases the drive strength, thus allowing more current to flow. Conversely, lowering WL2 reduces the drive strength, thereby limiting the current.

[0081] "Active drive strength" refers to a characterization or measure of how strongly a transistor can drive current through a load when it is turned on. In the case of field-effect transistors (FETs) such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or FinFETs (Fin Field-Effect Transistors), increasing the gate-to-source voltage (Vgs) above the threshold voltage (Vth) enhances the channel conductivity, thereby increasing the drive strength, until there is a point where additional increases have diminishing returns. In one or more examples, the modulation level of signal WL2 can be used to set the Vgs of access transistors N4 and N2B.

[0082] As used herein, “write margin” refers to a characterization or measure of how easily the state of configuration memory cell 100 can be changed. Therefore, “increasing” the write margin of configuration memory cell 100 means making it easier to change the state of configuration memory cell 100.

[0083] The active drive strength of the drive control transistor N4 and the stabilizing transistor N2B determines how strongly the drive control transistor N4 and the stabilizing transistor N2B can "pull" their respective nodes. For example, the drive control transistor N4 pulls S1 / OUTB towards BL during access, and the stabilizing transistor N2B pulls S2 / OUT towards VSS to achieve stabilization. Therefore, in the case of writing, WL2 modulation can make it easier or more difficult to change the state of the memory cell during a write operation by adjusting how effectively the drive control transistor N4 and the stabilizing transistor N2B drive current into or away from the memory node. Furthermore, in the case of reading, WL2 modulation helps ensure that the state of the configuration memory cell can be reliably read without interfering with the stability of the storage state of the configuration memory cell (e.g., avoiding accidental state flips caused by disturbances caused by read operations, but not limited to this).

[0084] Active drive strength also affects power consumption. Higher drive strength (with increased WL2 level) results in stronger current but also higher power dissipation. Lower drive strength reduces power consumption but may compromise margin reliability. Adjustable WL2 levels allow for fine-tuning of memory cell performance configurations for different operating conditions: high WL2 voltage: increases write / read margin at the cost of higher power consumption; lower WL2 voltage: reduces power consumption but may slightly reduce margin. As a non-limiting example, an acceptable trade-off between power consumption and write margin can be determined based on specific operating conditions.

[0085] Therefore, WL2 provides a single signal to modulate the gate voltages of both the drive control transistor N4 and the stabilizing transistor N2B. With the drive control transistor N4 in the case, WL2 controls how strongly the bit line (BL) influences memory node S1 / OUTB based on the active drive strength setting of the drive control transistor N4. With the stabilizing transistor N2B in the case, WL2 controls how effectively memory node S2 / OUT is stabilized by providing a discharge path to VSS.

[0086] WL3

[0087] As mentioned above, the fine control transistor N1B provides fine control over the state of memory nodes S1 / OUTB during write and read operations. By modulating WL3, the fine control transistor N1B adjusts how strongly memory nodes S1 / OUTB are driven to ensure smoother transitions and improved write and read margins. The gate of the fine control transistor N1B is connected to the word line WL3. The modulation level of signal WL3 sets the state of N1B (on or off) and the active drive strength. When N1B is off, this increases the write and read margins at configured memory cell 100 (relative to when N1B is on) and reduces power consumption.

[0088] signal PBIAS

[0089] The respective gates of P1B and P2B are connected to the PBIAS line, which supplies the bias voltage Vpbias (a voltage not depicted). Transistors P1B and P2B are biased PMOS transistors. PBIAS sets the gate-source voltage of the PMOS transistors (here, P1B and P2B). By setting PBIAS at an appropriate level, the gate-source voltage (Vgs) of the PMOS transistors is managed, allowing the transistors to operate within their safe operating regions. While PBIAS directly controls Vgs, it indirectly controls Vds by ensuring that the respective PMOS transistors remain within the region where the drain-source voltage does not exceed tolerance. PBIAS ensures that the drain of P1B or P2B does not rise too high relative to the source, thus keeping Vds within tolerance. Therefore, the PBIAS line effectively regulates P1B and P2B such that their respective drain voltages Vd are constrained to be a portion of their respective source voltages VS, thereby limiting the voltage stress across them.

[0090] In one or more examples, the bias level of the bias voltage PBIAS applied to the gate of the PMOS transistor and the set of corresponding PMOS transistors to which the PBIAS voltage is applied are selected to ensure that the drain-source voltage remains within limits (e.g., limits defined at least in part by specific voltage tolerances across a particular node of the transistor, which may be non-uniform, but are not limited thereto), including for operating the configuration memory cell 100 in the high voltage domain VPHV. In one or more examples, the bias amount may be selected to provide sufficient gate control while reducing the effect of voltage stress on the transistor. This ensures that the transistor operates reliably without exceeding the corresponding voltage tolerances.

[0091] In one or more examples, voltage tolerances of transistors, particularly their drain-source (Vds) limits, may be considered in the design of the configuration memory cell 100. The PMOS and NMOS transistors in the configuration memory cell 100 are partially breakdown voltages and therefore can withstand higher Vgs and Vgd voltages, but their Vds must be kept below a certain threshold (e.g., 1.2V) that is below the thresholds that Vgs and Vg can tolerate.

[0092] As described above, the various designs envisioned herein ensure, at least in part, that the corresponding tolerances are met (e.g., not exceeding, but not limited to) by allocating voltages across multiple transistors (e.g., in a stacked configuration, but not limited to) and by careful biasing.

[0093] In one or more examples, one or more parameters (transistor count, bias voltage, and voltage tolerance) can be predetermined during the design phase to ensure that the memory cell 100 is configured to meet various specifications for read and write operations (including two-stage read and write operations) and tolerance to SEUs. Process variations and operating conditions can also be considered during optimization to ensure consistent design execution across different manufacturing batches and various operating environments.

[0094] PMOS transistors P1B and P2B can be optionally coupled to receive the signal PBIAS. The modulation level of the signal PBIAS can be used to increase or decrease the bias conditions at PMOS transistors P1B and P2B based on specific operating conditions, as discussed below.

[0095] Patterns and characteristics set via signals WL2, WL3 and PBIAS

[0096] The modulation levels of signals WL2, WL3, and PBIAS can be used to set various different modes or features at the configuration memory cell 100, such as write assist (the bias condition is weakened for a finite duration to increase write margin) and reduced read interference (the bias condition is strengthened for a finite duration to reduce read interference and thus increase read margin).

[0097] Uneven voltage tolerance

[0098] One or more of the NMOS access transistor N3, drive control transistor N4, PMOS transistors P1A, P1B, P2A, and P2B, and NMOS transistors N1A, N1B, N2A, and N2B can exhibit non-uniform voltage tolerances. Non-uniform breakdown transistors can withstand different voltage levels across their different terminals (e.g., gate-drain (Vgd), gate-source (Vgs), drain-source (Vds)). In one or more examples, such transistors can handle higher voltages across Vgs and Vgd, and have a lower voltage tolerance across Vds. If the Vds voltage exceeds a tolerance threshold (the amount of time the transistor can withstand), the transistor may be damaged over time, potentially leading to breakdown, short circuit, or leakage current.

[0099] Here, access transistor N3, drive control transistor N4, PMOS transistors P1A, P1B, P2A, and P2B, and NMOS transistors N1A, N1B, N2A, and stabilizing transistor N2B are not tolerant of high voltages across their drain-source nodes. These transistors can withstand voltages up to VDD across their drain-source nodes, but not higher than VDD (e.g., not VPHV). These transistors can withstand voltages at least up to VPHV and optionally exceeding VPHV across their gate-drain nodes and their gate-source nodes.

[0100] Leakage control in programmable switches of an FPGA switch matrix

[0101] In the FPGA version, configuration memory cell 100 and transmission gates (e.g., transistors, but not limited to) form a programmable switch. The output of the configuration memory cell drives the transmission gates that provide connectivity. The programmable switch is connected when the transmission gate is on and disconnected when the transmission gate is off.

[0102] The gate of the drive transmission gate is used in conjunction with a 1.8V power supply voltage.

[0103] When the configuration memory cell generates 1.8V at its output and adjusts the transmission gate to conduct, it exhibits reliable overdrive from transmission signals at logic levels (typically 0.9V or lower).

[0104] Bias modulation of PMOS transistors driven by PBIAS and NMOS transistors driven by WL2 and WL3, using partially voltage-rated transistors, suppresses gate leakage.

[0105] Bias modulation of PMOS transistors driven by PBIAS and NMOS transistors driven by WL2 and WL3, along with cascode arrangement (as a supplement or alternative to gate leakage), suppress other types of leakage.

[0106] Other power domains

[0107] It is worth noting that the configuration memory cell 100 is designed to support coupling to an alternative voltage supply instead of one or both of VPHV and VSS, depending on specific operating conditions (e.g., application requirements, but not limited thereto). For example, the configuration memory cell 100 may be coupled to a VDD power supply instead of a VPHV high-voltage power supply.

[0108] Figure 2 This is a block diagram depicting a memory system 200 including a configuration memory cell 210 and its associated driver circuitry, according to one or more examples. The system is designed to manage high-voltage operating and low-voltage control signals for read and write operations.

[0109] The memory system 200 includes a BL driver 202, a WL1 driver 204, a WL2 driver 206, a WL3 driver 208, and a configuration memory unit 210.

[0110] Configuration memory cell 210 is a configuration memory cell operating in the high voltage (HV) domain according to the examples discussed herein, such as configuration memory cell 100, but not limited thereto. Configuration memory cell 210 is connected to both a high voltage (VPHV) and a low voltage (VSS / 0V) power supply. Furthermore, configuration memory cell 210 is connected to a power supply of the PBIAS voltage discussed above. Additionally, configuration memory cell 210 is connected to BL driver 202, WL1 driver 204, WL2 driver 206, and WL3 driver 208 via BL, WL1, WL2, and WL3, respectively.

[0111] VPHV is a high-voltage power supply connected to the configuration memory cell 210, ensuring its operation in the high-voltage domain. VSS / 0V is a low-voltage (ground) power supply connected to both the configuration memory cell 210 and the associated driver circuitry (here, BL driver 202, WL1 driver 204, WL2 driver 206, and WL3 driver 208). The drivers can use VSS / 0V as a reference voltage for their low-voltage operation.

[0112] The BL driver 202 controls the bit line (BL), which interfaces with the configuration memory cell 210 for read and write (R / W) operations. The BL driver 202 is powered by VDD and VSS / 0V, indicating that it operates in the low-voltage domain. The BL driver 202 receives read commands / write commands and generates appropriate signals to drive the bit line (BL), thereby enabling data to be written to or read from the configuration memory cell 210.

[0113] WL1 driver 204 controls (e.g., activates / deactivates, but is not limited to) word line 1 (WL1), which allows access to configuration memory cell 210 during read and write operations. In the case of configuration memory cell 100 and access device 110, WL1 enables or disables the access transistor N3 of access device 110. Similar to BL driver 202, WL1 driver 204 is powered by VDD and VSS / 0V, indicating that it operates in the low voltage domain. WL1 driver 204 receives read commands / write commands and drives WL1 control to access configuration memory cell 210.

[0114] WL2 driver 206 controls (e.g., activates / deactivates, but is not limited to) word line 2 (WL2), which, together with word line WL1, allows access to configuration memory cell 210 during read and write operations. With configuration memory cell 100 and access device 110 present, WL2 enables or disables drive control transistor N4 and stabilizing transistor N2B. Furthermore, modulation of WL2 sets the corresponding active drive strength of drive control transistor N4 and stabilizing transistor N2B. Similar to BL driver 202 and WL1 driver 204, WL2 driver 206 is powered by VDD and VSS / 0V, indicating its operation in the low-voltage domain. WL2 driver 206 receives read commands / write commands and drives WL2 to control access to configuration memory cell 210.

[0115] WL3 driver 208 controls (e.g., activates / deactivates, but is not limited to) word line 3 (WL3), which provides additional control over one or both of memory nodes S1 and S2 during read and write operations, for example, facilitating precise transitions during phases of the read and write sequences, as discussed below. WL3 driver 208 is powered by VDD and VSS / 0V, indicating its operation in the low-voltage domain. WL3 enables or disables the fine control transistor N1B. Furthermore, modulation of WL3 sets the active drive strength of the fine control transistor N1B.

[0116] In one or more examples, WL3 driver 208, WL1 driver 204 and WL2 driver 206 are coordinated to ensure proper access to configuration memory cell 210 during access operations (e.g., read and write, but not limited to).

[0117] Here, the term "activated" when used in conjunction with a word line means applying a voltage to the word line that turns on the access transistor connected to that word line. The term "deactivated" when used in conjunction with a word line means applying a voltage (typically 0V or another suitable level) to the word line that turns off the access transistor connected to that word line. Both activated and deactivated word lines can be modulated to set the active drive strength, as discussed herein.

[0118] The read / write control lines carry commands that manage the operation of BL driver 202, WL1 driver 204, WL2 driver 206, and WL3 driver 208. The control lines (e.g., the commands on them, but not limited to) determine whether the memory system 200 is performing a read or write operation and adjust the driver outputs accordingly (e.g., the outputs of BL driver 202, WL1 driver 204, WL2 driver 206, or WL3 driver 208, but not limited to). The driver outputs can directly or indirectly cause the states on BL, WL1, WL2, WL3, OUT, and OUTB, such as... Figure 7 As depicted in the state table.

[0119] In one or more examples, the configuration memory unit 210 may support write operations that include two write phases (phase 1 and phase 2), as discussed below.

[0120] Figure 3 It is a voltage bias and status table 300 that describes the operating states of a configuration memory cell or system (such as configuration memory cell 100 or memory system 200) according to one or more examples.

[0121] Figure 3 The voltage bias and state table 300 depicted provides a detailed breakdown of the voltage levels on various signals in the configuration memory cell (e.g., configuration memory cell 100 or configuration memory cell 210, but not limited thereto) during different operating states. Table 300 shows how the voltages on the bit line (BL), word line 1 (WL1), word line 2 (WL2), word line 3 (WL3), and outputs OUT and OUTB change during idle, write, and read operations, particularly using two-stage write and two-stage read processes. These two-stage processes ensure reliable operation of the configuration memory cell under high voltage conditions while minimizing the risk of erroneous state changes due to SEU.

[0122] Regarding the columns in Table 300: BL (Bit Line) includes the voltage on BL, which is responsible for transferring data to and from memory cells during read and write operations. Column WL1 (Word Line 1) includes the voltage on WL1, which controls the first access transistor directly connected to the bit line. Column WL2 (Word Line 2) includes the voltage on WL2, which controls the connection of the first access transistor to the drive control transistor of memory node S1. Column WL3 (Word Line 3) includes the voltage on WL3, which controls the connection of memory node S1 and output OUT (and optionally, memory node S2, if the optional Hi-Res element is not present) to pull-down transistors (e.g., ...). Figure 1 NMOS transistors N1A and N2A, but not limited to these) transistors (e.g., Figure 1 The NMOS transistors N1B and N2B are connected to the negative or ground power supply line VSS.

[0123] The status column lists example states for configuring memory cells. For Idle State 0 and Idle State 1: BL is at 0.9V, WL1 is at 0V, WL2 and WL3 are at 1V; PBIAS is at 0.8V; and OUT and OUTB maintain stable logic levels, where OUT is at 0V and OUTB is at VPHV (1.8V) during Idle 0, and vice versa during Idle 1; and the memory cell retains its state without any active read or write operations.

[0124] In a two-phase access, word lines WL1, WL2, and WL3 are activated sequentially during the access operation to the configuration memory cell. In one or more examples, in the two-phase operation discussed herein for writing 0 or writing 1, the circuitry pre-tunes the memory nodes S1 and S2 by setting them to the opposite state (pre-tuning state) of the desired final value (write state). This ensures that the correct logic level can be determined more robustly in subsequent phases. The circuitry then completes the state by switching the memory nodes from the pre-tuning state to the state of the desired final value (write state).

[0125] By employing an access transistor controlled by WL1, a drive control transistor controlled by WL2, a stabilization transistor controlled by WL2, and a fine control transistor N1B controlled by WL3, BL can selectively and directly influence specific memory nodes S1 and S2 during the corresponding phases of an access operation. This direct influence on the memory nodes allows for more precise setting of the desired logic levels.

[0126] Pre-tuning of write or read operations in the first phase (phase 0) makes it easier to achieve the correct final state in phase 2, thereby reducing the risk of errors due to transient events such as SEU.

[0127] Write 0: Phases 0 and 1 involve writing logic "0" to the configuration memory cells; this is a two-phase operation. During Phase 1, BL sets the initial conditions of memory nodes S1 and S2 to logic "1" at the memory cells, and the NMOS and PMOS transistors of the cross-coupled inverters stabilize the voltage levels at S1 / OUTB and S2 / OUT at 0V and VPHV, respectively. In Phase 2, BL sets the full write conditions of memory nodes S1 / OUTB and S2 / OUT to logic "0" at the memory cells, and the NMOS and PMOS transistors of the cross-coupled inverters stabilize the voltage levels at S1 / OUTB and S2 / OUT at VPHV and 0, respectively, thus completing the write 0 operation.

[0128] In the first stage (stage 0), BL is set to VDD (1.1V), such that initially, a logic "1" is written to the configuration memory cell. WL1 is set to VPHV (1.8V) to enable the first access transistor. WL2 is set to 1.5V to enable the drive control transistor N4 and the stabilizing transistor N2B. With all of the first access transistor, drive control transistor, and stabilizing transistor enabled, BL can coarsely affect S2 / OUT and S1 / OUTB. Specifically, the PMOS and NMOS transistors in the cross-coupled inverter ensure that in response to BL, S2 / OUT reaches VPHV and S1 / OUTB reaches 0V. WL3 is set to 0V to turn off the fine control transistor N1B, thereby isolating the secondary control path. This isolation ensures that the state transition to 0V at S1 / OUTB occurs gradually and under controlled conditions.

[0129] In the second phase (phase 2) of the write-0 operation, the configuration memory cell transitions from the pre-adjustment state in phase 1 to the write state to complete the writing of logic "0".

[0130] BL is maintained at VDD (1.1V), thus continuing to provide the logic "1" preconditioning required for stable operation and influencing the memory node via the cross-coupled inverter. WL1 is set to VPHV (1.8V), thus enabling the first access transistor. WL2 is maintained at 1.5V, thus ensuring that the drive control transistor N4 and the stabilizing transistor N2B remain on. Keeping the access transistor N3, drive control transistor N4, and stabilizing transistor N2B all on allows BL to complete its influence on S1 / OUTB and S2 / OUT. WL3 is set to 1.1V, thus turning on the fine control transistor N1B. This provides fine control over the voltage transitions at S1 / OUTB, thus helping to stabilize the logic "0" state being written.

[0131] Write operation

[0132] Write 1: Phases 1 and 2 involve writing a logic "1" to a configuration memory cell; this is a two-phase operation. During Phase 1, BL sets the initial conditions of memory nodes S1 / OUTB and S2 / OUT to logic "0" at the memory cell, and the NMOS and PMOS transistors of the cross-coupled inverters stabilize the voltage levels at S1 / OUTB and S2 / OUT at VPHV and 0V, respectively. In Phase 2, BL sets the full write conditions of memory nodes S1 / OUTB and S2 / OUT to logic "1" at the memory cell, and the NMOS and PMOS transistors of the cross-coupled inverters stabilize the voltage levels at S1 / OUTB and S2 / OUT at 0V and VPHV, respectively, thus completing the Write 1 operation.

[0133] In the first stage (stage 0) of the write "1" operation, the configuration memory cell is pre-tuned to begin writing a logic "1". BL is set to 0V (VSS) to provide the initial conditions necessary to write a logic "1" to the memory cell. WL1 is set to 1.8V (VPHV), thereby enabling access transistor N3. This creates a path between the bit line (BL) and memory node S1 / OUTB. WL2 is set to 1.5V, thereby activating drive control transistor N4 and stabilizing transistor N2B. This configuration allows controlled interaction between memory nodes and their complementary states. WL3 is set to 0V, thereby keeping fine control transistor N1B off. This isolates the secondary path and prevents interaction with memory node S1 / OUTB during stage 0. PBIAS is set to 1.1V, thereby ensuring stable operation of the PMOS transistor in the cross-coupled inverter by controlling the gate-source voltage and preventing overvoltage stress. Memory node S2 / OUT transitions to 1.8V (VPHV), influenced by the PMOS transistor in the cross-coupled inverter. Storage node S1 / OUTB transitions to 0V (VSS) to pre-tune the memory cell for the logic "1" state.

[0134] In the second phase (phase 1) of the write-to-"-"""""" operation), the configuration memory cell transitions from the pre-tuned state in phase 0 to complete the logic "1". BL is held at 0V (VSS), thus reinforcing the logic "1" condition being written to the memory cell. WL1 is held at 1.8V (VPHV), thus keeping access transistor N3 active and maintaining part of the connection between the bit line (BL) and memory node S1 / OUTB. WL2 is held at 1.5V, thus ensuring that drive control transistor N4 remains active to maintain another part of the connection between BL and memory node S1 / OUTB and ensuring that stabilization transistor N2B remains active to provide stability to the memory node. WL3 is raised to 1.1V, thus activating fine control transistor N1B. This ensures precise stabilization of memory node S2 / OUT at 0V. PBIAS is held at 1.1V, thus maintaining stable operation of the PMOS transistors in the cross-coupled inverter and protecting them from voltage stress. Memory node S2 / OUT is pulled to 0V (VSS) by the NMOS transistors in the cross-coupled inverter. Storage node S1 / OUTB is pulled to 1.8V (VPHV) to complete the logical "1" state.

[0135] Read operation

[0136] Reading "0": The read 0 operation involves phases 0 and 1, which involve reading the stored logic "0" from the configuration memory cell and is performed in two phases. During phase 0, the bit line is pre-tuned to sense the memory node, and the first access transistor connects the bit line to the memory node S1 / OUTB. The NMOS and PMOS transistors of the cross-coupled inverter maintain the voltage levels at S1 / OUTB and S2 / OUT at VPHV and 0V, respectively. In phase 1, the bit line completes sensing the memory state as logic "0", where the NMOS and PMOS transistors ensure stable complementary voltage levels at S1 / OUTB and S2 / OUT, thereby confirming the logic "0" stored in the memory cell.

[0137] In the first stage (stage 0) of a read-0 operation, the memory cell is pre-tuned to read the stored logic "0" by enabling access to the bit lines. BL is set to 1.1V (VDD) to prepare it to sense the voltage levels at S2 / OUT and S1 / OUTB. WL1 is set to 1.8V (VPHV) to enable the first access transistor, connecting BL to S1 / OUTB. WL2 is set to 1.5V to maintain the activity of the drive control transistor and the stabilizing transistor. This ensures the stability of the memory node during the read operation. WL3 is set to 1V to maintain the activity of the fine control transistor N1B to provide fine-grained control over S2 / OUT. PBIAS is maintained at 0.8V to stabilize the PMOS transistor in the cross-coupled inverter to prevent excessive voltage stress. S2 / OUT: The primary memory node is maintained at 0V (VSS) to represent the stored logic "0". S1 / OUTB: The complementary memory node is maintained at 1.8V (VPHV).

[0138] In the second phase (phase 1) of the read-0 operation, the bit line voltages are finalized to ensure reliable sensing of the stored logic "0". BL is set to 0V (VSS) to allow it to sense voltage transitions. WL1 is maintained at 1.8V (VPHV) to keep the first access transistor active. WL2 is maintained at 1.5V to ensure the continued stability of the drive control transistor and the stabilizing transistor. WL3 is maintained at 1V to keep the fine control transistor N1B active for stability. PBIAS is maintained at 0.8V to stabilize the PMOS transistor. The voltages at S2 / OUT and S1 / OUTB are maintained complementary, with S2 / OUT = 0V and S1 / OUTB = 1.8V, thus confirming the stored logic "0".

[0139] Reading "1": The read 1 operation involves phases 0 and 1, which involve reading a stored logic "1" from a configuration memory cell and is performed in two phases. During phase 0, the bit line is pre-tuned to sense the memory node, and the first access transistor connects the bit line to the memory node S1 / OUTB. The NMOS and PMOS transistors of the cross-coupled inverter maintain the voltage levels at S1 / OUTB and S2 / OUT at 0V and VPHV, respectively. In phase 1, the bit line completes the sensing of the memory state as a logic "1", where the NMOS and PMOS transistors ensure stable complementary voltage levels at S1 / OUTB and S2 / OUT, thereby confirming the logic "1" stored in the memory cell.

[0140] In the first stage (stage 0) of the read-1 operation, the memory cell is pre-tuned to read the stored logic "1". BL is set to 1.1V (VDD) to prepare it for sensing. WL1 is set to 1.8V (VPHV), thereby enabling the first access transistor. WL2 is set to 1.5V, thereby activating the drive control transistor N4 and the stabilizing transistor N2B to stabilize the memory node. WL3 is set to 1V, thereby keeping the fine control transistor N1B active to stabilize the complementary node. PBIAS is maintained at 0.8V, thereby ensuring the correct operation of the PMOS transistors in the cross-coupled inverter. S2 / OUT: The primary memory node is maintained at 1.8V (VPHV), representing the stored logic "1". S1 / OUTB: The complementary memory node is maintained at 0V (VSS).

[0141] In the second phase (phase 1) of the read-1 operation, the bit line voltages are maintained to ensure reliable sensing of the stored logic "1". BL is maintained at 1.1V to enhance sensing of the stored logic "1". WL1 is maintained at 1.8V to keep the first access transistor active. WL2 is maintained at 1.5V to ensure the continued stability of the drive control transistor N4 and the stabilizing transistor N2B. WL3 is maintained at 1V to keep the fine control transistor N1B active for stability. PBIAS is maintained at 0.8V to maintain stable operation of the PMOS transistor. The voltages at S2 / OUT and S1 / OUTB are maintained complementaryly, with S2 / OUT = 1.8V and S1 / OUTB = 0V, thus confirming the stored logic "1".

[0142] In one or more examples, writing and reading (whether 0 or 1) each consist of two phases, and each such phase occurs within a single clock cycle. Therefore, writing and reading to configuration memory cell 100 occur within two clock cycles.

[0143] Figure 4 It is a flowchart depicting an example process 400 for controlling a configuration memory unit (such as configuration memory unit 100 or configuration memory unit 210, but not limited thereto) according to one or more examples.

[0144] Although example process 500 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not substantially affect the functionality of process 500. In other examples, different components of the example device or system implementing process 500 may perform their functions substantially simultaneously or in a specific order. In one or more examples, some or all of the operations of process 700 may be performed by memory system 200 or a system incorporating configuration memory units 100.

[0145] In one or more examples, some or all of the operations in process 400 may be performed cooperatively by logic circuitry with one or more drivers of BL, WL1, WL2, and WL3 discussed herein. As a non-limiting example, the logic circuitry may be integrated with a controller (e.g., but not limited to, a microcontroller, microprocessor, DSP, or other processor) that issues read / write commands to instruct the drivers of BL, WL1, WL2, and WL3 according to some or all of the operations in process 500. Additionally or alternatively, multiple logic circuits may be integrated with the respective drivers of BL, WL1, WL2, and WL3 to cause the drivers to operate according to some or all of the operations in process 400.

[0146] According to one or more examples, process 400 may include, at operation 402, controlling selective coupling of a bit line to a memory node of the configured memory cell via a first connection point of the configured memory cell. In various examples, process 400 may activate a word line that controls an access transistor (e.g., access transistor N3, but not limited to) for switchably coupling a memory node (e.g., memory node S1 / OUTB, but not limited to) to a bit line (e.g., bit line BL, but not limited to). In various examples, process 400 may modulate the drive strength of the access transistor by modulating the respective voltage levels of one or both of WL1 or WL2.

[0147] According to one or more examples, process 400 may include, at operation 404, controlling voltage transitions at one or more memory nodes of the configuration memory cell via a second connection point of the configuration memory cell during access to the configuration memory cell. In various examples, process 400 may modulate the voltage level of WL2 to control voltage transitions at memory nodes (e.g., memory node S1 / OUTB). For example, during a write operation, WL2 modulates the gate voltage and therefore the current at the drive control transistor N4 to ensure that the voltage at S1 / OUTB transitions to its final value without overshoot, undershoot, or unexpected fluctuations. Furthermore, during a read operation, WL2 modulates the gate voltage and therefore the current at the drive control transistor N4 to prevent transient disturbances that could disrupt the memory state. In various examples, WL2 also controls a stabilizing transistor N2B connected to S2 / OUT. Through the adjustment of WL2, the stabilizing transistor N2B ensures that the complementary memory node (S2 / OUT) transitions or maintains its state as needed, thereby indirectly stabilizing the overall behavior of the cross-coupled inverter.

[0148] Figure 5This is a flowchart depicting an example process 500 for writing “0” to example configuration memory cells (e.g., configuration memory cell 100, configuration memory cell 210, but not limited thereto) according to one or more examples.

[0149] Although example process 500 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not substantially affect the functionality of process 500. In other examples, different components of the example device or system implementing process 500 may perform their functions substantially simultaneously or in a specific order. In one or more examples, some or all of the operations of process 700 may be performed by memory system 200 or a system incorporating configuration memory units 100.

[0150] In one or more examples, some or all of the operations of process 500 may be performed cooperatively by logic circuitry with one or more drivers of BL, WL1, WL2, and WL3 discussed herein. As a non-limiting example, such logic circuitry may be integrated with a controller (e.g., but not limited to, a microcontroller, microprocessor, DSP, or other processor) that issues read / write commands to instruct the drivers of BL, WL1, WL2, and WL3 according to some or all of the operations of process 500. Additionally or alternatively, multiple logic circuits may be integrated with the respective drivers of BL, WL1, WL2, and WL3 to cause the drivers to operate according to some or all of the operations of process 500.

[0151] According to one or more examples, process 500 may include: at operation 502, setting BL to VDD (1.1V or logic "1"). This pre-tunes the storage node and sets the configuration memory cell to an intermediate state.

[0152] According to one or more examples, process 500 may include: at operation 504, setting write line WL1 to VPHV (1.8V) to enable access transistor (e.g., access transistor N3).

[0153] According to one or more examples, process 500 may include: at operation 506, setting write line WL2 to 1.5V to enable the drive control transistor (e.g., drive control transistor N4) and stabilizing transistor N2B. Both the drive control transistor and the stabilizing transistor are turned on simultaneously. Additionally, both access transistor N3 and drive control transistor N4 are turned on simultaneously. When both access transistor N3 and drive control transistor N4 are enabled, this connects BL to memory node S1 / OUTB. Furthermore, when access transistor N3, drive control transistor N4, and stabilizing transistor N2B are all active, it allows BL to affect both S1 / OUTB and S2 / OUT.

[0154] According to one or more examples, process 500 may include: at operation 508, waiting to allow the storage node to stabilize at a value corresponding to a logic "1" at the configuration memory cell.

[0155] According to one or more examples, process 500 may include: at operation 510, setting BL to 0V (logic 0) to complete the transition of the configuration memory cell to a write state.

[0156] According to one or more examples, process 500 may include: at operation 512, maintaining WL1 at VPHV (1.8V) and maintaining WL2 at 1.5V, thereby keeping the access control transistor and drive control transistor active and keeping the control transistor active to stabilize S2 / OUT at VPHV (1.8V) via the complementary inverter.

[0157] According to one or more examples, process 500 may include: at operation 514, waiting to allow the storage node to stabilize at a value corresponding to a logic "0" at the memory cell.

[0158] Figure 6 It is a flowchart depicting an example process 600 for writing “1” to example memory cells (e.g., configuration memory cell 100 or configuration memory cell 210) discussed herein, based on one or more examples.

[0159] Although example process 600 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the operations depicted may be performed in parallel or in a different order that does not substantially affect the functionality of process 600. In other examples, different components of the example device or system implementing process 600 may perform their functions substantially simultaneously or in a specific order.

[0160] In one or more examples, some or all of the operations of process 600 may be performed by logic circuitry in cooperation with one or more drivers of BL, WL1, WL2, and WL3 discussed herein. As a non-limiting example, the logic circuitry may be integrated with a controller (e.g., but not limited to, a microcontroller, microprocessor, DSP, or other processor) that issues read / write commands to instruct the drivers of BL, WL1, WL2, and WL3 according to some or all of the operations of process 600. Additionally or alternatively, multiple logic circuits may be integrated with the respective drivers of BL, WL1, WL2, and WL3 to cause the drivers to operate according to some or all of the operations of process 600.

[0161] According to one or more examples, process 600 may include: at operation 602, setting BL to 0V (logic 0). This pre-tunes the memory node and sets the memory cell to an intermediate state.

[0162] According to one or more examples, process 600 may include: at operation 604, setting WL1 to VPHV (1.8V) to enable access transistor N3. This at least partially connects bit line BL to memory node S1 / OUTB.

[0163] According to one or more examples, process 600 may include: at operation 606, setting WL2 to 1.5V, which activates both drive control transistor N4 and stabilizing transistor N2B. Activation of access transistor N3, drive control transistor N4, and stabilizing transistor N2B allows bit line BL to affect S1 / OUTB and node S2 / OUT.

[0164] According to one or more examples, process 600 may include: at operation 608, setting WL3 to 0V, which keeps fine control transistor N1B off to avoid interference during preconditioning.

[0165] According to one or more examples, process 600 may include: at operation 610, waiting for the storage node to stabilize to a value corresponding to logic "0". In this stage, the cross-coupled inverter stabilizes S1 / OUTB at 0V (VSS), and S2 / OUT is driven to VPHV (1.8V), thereby completing the pre-conditioning.

[0166] According to one or more examples, process 600 may include: at operation 612, setting BL to VDD (1.1V) to complete the transition of the memory cell state.

[0167] According to one or more examples, process 600 may include: at operation 614, setting WL3 to 1.1V to activate fine control transistor N1B. This transistor ensures a smooth voltage transition at S1 / OUTB, thereby preventing unexpected fluctuations.

[0168] According to one or more examples, process 600 may include: at operation 616, maintaining WL1 at VPHV (1.8V) and maintaining WL2 at 1.5V, which maintains the activity of the access transistor and the drive control transistor, and maintains the activity of the stabilizing transistor to stabilize S2 / OUT at 0V via the complementary inverter.

[0169] According to one or more examples, process 600 may include: at operation 618, waiting to allow the storage node to stabilize at a value corresponding to a logical "1", which is a write state.

[0170] Figure 7 It is a flowchart depicting an example process 700 for reading “0” from example configuration memory cells discussed herein (e.g., configuration memory cell 100 or configuration memory cell 210, but not limited thereto), according to one or more examples.

[0171] Although example process 700 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the operations depicted may be performed in parallel or in a different order that does not substantially affect the functionality of process 700. In other examples, different components of the example device or system implementing process 700 may perform their functions substantially simultaneously or in a specific order.

[0172] In one or more examples, some or all of the operations of process 700 may be performed by logic circuitry in cooperation with one or more drivers of BL, WL1, WL2, and WL3 discussed herein. As a non-limiting example, such logic circuitry may be integrated with a controller (e.g., but not limited to, a microcontroller, microprocessor, DSP, or other processor) that issues read / write commands to instruct the drivers of BL, WL1, WL2, and WL3 according to some or all of the operations of process 700. Additionally or alternatively, multiple logic circuits may be integrated with the respective drivers of BL, WL1, WL2, and WL3 to cause the drivers to operate according to some or all of the operations of process 700.

[0173] According to one or more examples, process 700 may include: at operation 702, BL is set to 1.1V (VDD) to prepare it to sense logic levels stored in memory cells.

[0174] According to one or more examples, process 700 may include: at operation 704, WL1 is set to 1.8V (VPHV) to enable access transistor N3. This connects BL to storage node S1 / OUTB.

[0175] According to one or more examples, process 700 may include: at operation 706, WL2 is set to 1.5V, which activates both drive control transistor N4 and stabilizing transistor NB2. This ensures that S1 / OUTB is stabilized via drive control transistor N4 and S2 / OUT is stabilized via stabilizing transistor N2B to ensure no interference during sensing.

[0176] According to one or more examples, process 700 may include: at operation 708, WL3 is set to 1.1V, thereby activating fine control transistor N1B to provide additional stability to S1 / OUTB.

[0177] According to one or more examples, process 700 may include: at operation 710, waiting to ensure that BL can sense the voltage corresponding to logic "0" (VPHV or 1.8V) at S1 / OUTB. It is VPHV or 1.8V because OUTB is the complementary output of cross-coupled inverters 102 and 104.

[0178] According to one or more examples, process 700 may include: at operation 712, setting BL to 0V (VSS) to allow it to sense voltage transitions.

[0179] According to one or more examples, process 700 may include: at operation 714, maintaining WL1 at 1.8V (VPHV), which keeps the first access transistor active.

[0180] According to one or more examples, process 700 may include: at operation 716, maintaining WL2 at 1.5V, which ensures the continued stability of the drive control transistor and the stabilizing transistor.

[0181] According to one or more examples, process 700 may include: at operation 718, maintaining WL3 at 1.1V, which keeps fine control transistor activity to stabilize S1 / OUTB.

[0182] According to one or more examples, process 700 may include: at operation 720, waiting to allow the storage node to stabilize at a value corresponding to a logic "1" at the configuration memory cell.

[0183] Figure 8 It is a flowchart depicting an example process 800 for reading “1” from example configuration memory units discussed herein (e.g., configuration memory unit 100 or configuration memory unit 210, but not limited thereto) in two stages, according to one or more examples.

[0184] Although example process 800 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the operations depicted may be performed in parallel or in a different order that does not substantially affect the functionality of process 800. In other examples, different components of the example device or system implementing process 800 may perform their functions substantially simultaneously or in a specific order.

[0185] In one or more examples, some or all of the operations of process 800 may be performed by logic circuitry in cooperation with one or more drivers of BL, WL1, WL2, and WL3 discussed herein. As a non-limiting example, such logic circuitry may be integrated with a controller (e.g., but not limited to, a microcontroller, microprocessor, DSP, or other processor) that issues read / write commands to instruct the drivers of BL, WL1, WL2, and WL3 according to some or all of the operations of process 800. Additionally or alternatively, multiple logic circuits may be integrated with the respective drivers of BL, WL1, WL2, and WL3 to cause the drivers to operate according to some or all of the operations of process 800.

[0186] According to one or more examples, process 800 may include: at operation 802, setting BL to 1.1V (VDD) to prepare it to sense logic levels stored in the configuration memory cell.

[0187] According to one or more examples, process 800 may include: at operation 804, setting WL1 to 1.8V (VPHV) to enable the access transistor and connecting BL to the storage node S1 / OUTB.

[0188] According to one or more examples, process 800 may include: at operation 806, setting WL2 to 1.5V to enable the drive control transistor and the stabilizing transistor. This ensures that S1 / OUTB is stabilized via 112 and S2 / OUT is stabilized via 112, thereby ensuring no interference during sensing.

[0189] According to one or more examples, process 800 may include: at operation 808, setting WL3 to 1.1V, which enables fine control transistors, providing additional stability for S1 / OUTB.

[0190] According to one or more examples, process 800 may include: at operation 810, waiting to ensure that BL can sense the voltage corresponding to logic "1" (0V) at S1 / OUTB.

[0191] According to one or more examples, process 800 may include: at operation 812, maintaining BL at 1.1V (VDD) to complete sensing.

[0192] According to one or more examples, process 800 may include: at operation 814, maintaining WL1 at 1.8V (VPHV), which keeps the first access transistor active.

[0193] According to one or more examples, process 800 may include: at operation 816, maintaining WL2 at 1.5V, which ensures the continued stability of the drive control transistor and the stabilizing transistor.

[0194] According to one or more examples, process 800 may include: at operation 818, maintaining WL3 at 1.1V, which keeps fine control transistor activity to stabilize S1 / OUTB.

[0195] According to one or more examples, process 800 may include: at operation 820, waiting to allow the storage node to stabilize at a value corresponding to a logic "1" at the configuration memory cell.

[0196] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, or methods) of the examples disclosed herein can be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 9 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated. In some examples, some or all portions of the functional elements disclosed herein may be executed by hardware capable of performing the functional elements.

[0197] Figure 9 This is a block diagram of circuitry 900 that, in some examples, can be used to implement the various functions, operations, actions, processes, or methods disclosed herein. Circuitry 900 includes one or more processors 902 (sometimes referred to herein as "processor 902") operatively coupled to one or more data storage devices 904 (sometimes referred to herein as "storage device 904"). Storage device 904 includes machine-executable code 906 stored thereon, and processor 902 includes logic circuitry 908. Machine-executable code 906 includes information describing functional elements that can be implemented (e.g., executed) by logic circuitry 908. Logic circuitry 908 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 906. When executing the functional elements described by machine-executable code 906, circuitry 900 should be considered as dedicated hardware for executing the functional elements disclosed herein. In one or more examples, processor 902 may execute the functional elements described by machine-executable code 906 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0198] When implemented by the logic circuitry 908 of the processor 902, the machine-executable code 906 adapts the processor 902 to be or perform some or all of the features, functions, or operations disclosed herein for one or more of the following: configuration memory cell 100 of memory system 200, or BL driver 202, WL1 driver 204, WL2 driver 206, WL3 driver 208, or configuration memory cell 210 of memory system 200; the status and bias voltage of table 300; or system 200; process 400, process 500, process 600, process 700, or process 800.

[0199] Processor 902 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic components, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer is considered a special-purpose computer at least when it includes one or more processors 902 (including the general-purpose processor) executing functional elements corresponding to machine-executable code 906 (e.g., software code, firmware code, configuration data, hardware description, but not limited thereto) associated with the examples of this disclosure. It should be noted that the general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in alternatives, the general-purpose processor of processor 902 may include any conventional processor, controller, microcontroller, or state machine. The FPGA or other PLD of processor 902 may be configured (e.g., programmed, but not limited thereto) with configuration data to perform the functions disclosed herein, or additionally or alternatively, may be configured or reconfigured (e.g., programmable or reprogrammable, but not limited thereto) with configuration data to perform the functions disclosed herein. Processor 902 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0200] In one or more examples, storage device 904 includes volatile data storage devices (e.g., random access memory (RAM), static RAM (SRAM), but not limited thereto) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 902 and storage device 904 may be implemented as a single device (e.g., semiconductor device product, system-on-a-chip (SoC), but not limited thereto). In some examples, processor 902 and storage device 904 may be implemented as separate devices.

[0201] In one or more examples, machine-executable code 906 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored in storage device 904, directly accessed by processor 902, and executed by processor 902 using at least logic circuitry 908. Also as a non-limiting example, the computer-readable instructions may be stored on storage device 904, passed to a memory device (not shown) for execution, and executed by processor 902 using at least logic circuitry 908. Processor 902 or its logic circuitry 908 may be coupled to or include such memory devices (e.g., configuring memory cells, but not limited thereto). Thus, in some examples, logic circuitry 908 includes electrically configurable logic circuitry 908.

[0202] In one or more examples, machine-executable code 906 may describe the hardware (e.g., circuitry) to be implemented in logic circuitry 908 to perform functional elements. This hardware can be described from any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), can be used. As a non-limiting example, Verilog can be used. ® SystemVerilog ™ Or, the Very Large Scale Integration (VLSI) Hardware Description Language (VHDL).

[0203] HDL descriptions can be transformed into descriptions at any of a variety of other levels of abstraction as needed. As a non-limiting example, a high-level description can be transformed into a logic-level description such as Register Pass Language (RTL), Gate-level (GL) description, Placement-level description, or Mask-level description. As a non-limiting example, micro-operations to be performed by the hardware logic circuitry of logic circuitry 908 (e.g., gates, flip-flops, registers, but not limited thereto) can be described in RTL, then transformed into a GL description by a synthesis tool, and the GL description can be transformed into a placement-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or combinations thereof. Therefore, in some examples, machine-executable code 906 may include HDL, RTL, GL descriptions, Mask-level descriptions, other hardware descriptions, or any combination thereof.

[0204] In an example where machine-executable code 906 includes a hardware description (at any level of abstraction), the system (not shown, but including storage device 904) implements the hardware description described by machine-executable code 906. As a non-limiting example, processor 902 may include programmable logic devices (e.g., FPGA or PLC, but not limited thereto), and logic circuitry 908 may be electrically controlled (e.g., via configuration data, but not limited thereto) to implement circuitry corresponding to the hardware description into logic circuitry 908. Again, as a non-limiting example, logic circuitry 908 may include hardwired logic components manufactured by a manufacturing system (not shown, but including storage device 904) according to the hardware description of machine-executable code 906.

[0205] Regardless of whether the machine-executable code 906 includes computer-readable instructions or a hardware description, the logic circuit 908 is adapted to execute the functional elements described by the machine-executable code 906 when implementing the functional elements of the machine-executable code 906. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0206] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation that performs actions of a module or component and / or software object or software routine that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, but not limited thereto) of a computing system. In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and conceivable.

[0207] As used in this disclosure, the term "combination" referring to multiple elements can include a combination of all elements or any one of various different sub-combinations of certain elements. For example, the phrase "A, B, C, D or combinations thereof" can refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0208] The terminology used in this disclosure, and particularly in the appended claims (e.g., in the body of the appended claims, but not limited thereto), is generally intended to be “open-ended” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, and the term “having” should be interpreted as “at least having, but not limited to”). As used herein, the term “each” means “some or all”. As used herein, the term “each and every” means “all”.

[0209] Furthermore, if a specific number of introduced claim statements are anticipated, such an intent will be explicitly stated in the claims, and without such statements, no such intent exists. For example, as an aid to understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” can be interpreted as referring to “at least one” or “one or more”, but is not limited thereto); the same applies to the use of definite articles to introduce claim statements.

[0210] Furthermore, even when a specific number of the introduced claim statements are explicitly stated, those skilled in the art will recognize that such statements should be interpreted as meaning at least the number stated (e.g., the unmodified statement "two statements" means, in the absence of other modifying elements, at least two statements, or two or more statements, but not limited thereto). Additionally, in instances where conventions such as "at least one of A, B, and C, but not limited thereto" or "one or more of A, B, and C, but not limited thereto" are used, such constructions are generally intended to include, but are not limited to, a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together.

[0211] Furthermore, any separate word or phrase presenting two or more alternative terms in the specification, claims, or drawings should be understood to contemplate the possibility of including one term, any one term, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0212] Additional non-limiting embodiments include:

[0213] Example 1: An apparatus comprising: a configuration memory unit, the configuration memory unit including: a first connection point for controlling access to one or more memory nodes of the configuration memory unit; a second connection point for managing the stability of one or more memory nodes of the configuration memory unit during access to the configuration memory unit; and a third connection point for controlling voltage transitions at one or more memory nodes of the configuration memory unit during access to the configuration memory unit.

[0214] Example 2: The apparatus according to Example 1, wherein the configuration memory cell includes a transistor for selectively coupling a bit line to one or more memory nodes of the configuration memory cell in response to the first connection point.

[0215] Example 3: The apparatus according to Examples 1 and 2, wherein the configuration memory cell includes a transistor for controlling how bit lines strongly influence one or more memory nodes of the configuration memory cell in response to the third connection point.

[0216] Example 4: An apparatus according to any one of Examples 1 to 3, wherein the transistor exhibits an active drive strength at least in part based on a signal received via the third connection point, and how strongly the bit line affects one or more memory nodes of the configured memory cell is at least in part based on the active drive strength exhibited by the transistor.

[0217] Example 5: An apparatus according to any one of Examples 1 to 4, wherein the configuration memory cell includes an additional transistor for providing stability to the one or more memory nodes of the configuration memory cell by selectively coupling one or more memory nodes of the configuration memory cell to a voltage power supply in response to the third connection point.

[0218] Example 6: The apparatus according to any one of Examples 1 to 5, wherein the additional transistor exhibits an active drive strength at least in part based on a signal received via the third connection point, and the responsiveness of one or more memory nodes of the configured memory cell to the coupled voltage power supply is at least in part based on the active drive strength exhibited by the additional transistor.

[0219] Example 7: An apparatus according to any one of Examples 1 to 6, wherein the configuration memory cell includes a transistor for providing stability to one or more memory nodes of the configuration memory cell by selectively modulating currents to or from the memory nodes of the configuration memory cell, the modulation of the currents being at least partially based on a signal received via the second connection point.

[0220] Example 8: An apparatus according to any one of Examples 1 to 7, the apparatus comprising: a high-resistance element coupled between a storage node in one or more storage nodes and the output of the configuration memory cell to enhance single event flip (SEU) tolerance.

[0221] Example 9: The apparatus according to any one of Examples 1 to 8, wherein the configuration memory unit includes a first inverter and a second inverter, the first inverter and the second inverter being cross-coupled between a first node and a second node to store state information represented by complementary voltages at the first node and the second node.

[0222] Example 10: The apparatus according to any one of Examples 1 to 9, wherein the transistors of one or more of the first inverter or the second inverter exhibit non-uniform voltage tolerance.

[0223] Example 11: A method comprising: selectively coupling bit lines to memory nodes of the configuration memory cell via a first connection point of the configuration memory cell; and controlling voltage transitions at one or more memory nodes of the configuration memory cell via a second connection point of the configuration memory cell during access to the configuration memory cell.

[0224] Example 12: According to the method described in Example 11, during access to the configuration memory unit, the stability of one or more memory nodes of the configuration memory unit is controlled via a third connection point of the configuration memory unit.

[0225] Example 13: The method according to Examples 11 and 12, the method includes: selectively coupling the storage node of the configured memory cell to a voltage power supply to enhance the stability of the storage node.

[0226] Example 14: The method according to any one of Examples 11 to 13, the method comprising: selectively modulating current to or from the storage node to enhance the stability of the storage node.

[0227] Example 15: The method according to any one of Examples 11 to 14, the method comprising: adjusting the responsiveness of the coupling voltage of the storage node of the configured memory cell, the adjusted responsiveness being associated with the enhanced stability of the storage node.

[0228] Example 16: A system comprising: a configuration memory cell; a bit line driver for driving a bit line coupled to a first connection point of the configuration memory cell; a first write line driver for driving a first write line coupled to a second connection point of the configuration memory cell; a second write line driver for driving a second write line coupled to a third connection point of the configuration memory cell; a third write line driver for driving a third write line coupled to a fourth connection point of the configuration memory cell; and logic circuitry for coordinating the bit line driver, the first word line driver, the second word line driver, and the third write line driver to perform an access operation to the configuration memory cell, wherein the logic circuitry is configured to dynamically control the configuration memory cell during the access operation via adjustments to signals generated by the first write line driver, the second write line driver, and the third write line driver to ensure stable and reliable state transitions.

[0229] Example 17: The system according to Example 16, wherein the bit line driver, the first write line driver, the second write line driver and the third write line driver are used to generate signals in at least part of response to instructions received from the logic circuit.

[0230] While this disclosure has been described with respect to certain exemplary embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the exemplary and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. An apparatus, the apparatus comprising: Configuration memory unit, the configuration memory unit comprising: A first connection point, wherein the first connection point is used to control access to one or more storage nodes of the configuration memory unit; A second connection point, configured to manage the stability of one or more storage nodes among the storage nodes of the configuration memory unit during access to the configuration memory unit; and A third connection point is used to control voltage transitions at one or more memory nodes of the configuration memory cell during access to the configuration memory cell.

2. The apparatus of claim 1, wherein the configuration memory cell includes a transistor configured to selectively couple a bit line to one or more memory nodes of the configuration memory cell in response to the first connection point.

3. The apparatus of claim 1, wherein the configuration memory cell includes a transistor configured to control, in response to the third connection point, how a bit line strongly influences one or more memory nodes of the configuration memory cell.

4. The apparatus of claim 3, wherein the transistor exhibits an active drive strength at least in part based on a signal received via the third connection point, and how strongly the bit line affects one or more memory nodes of the configured memory cell is at least in part based on the active drive strength exhibited by the transistor.

5. The apparatus of claim 3, wherein the configuration memory cell includes an additional transistor configured to provide stability to the one or more memory nodes of the configuration memory cell by selectively coupling one or more memory nodes of the configuration memory cell to a voltage power supply in response to the third connection point.

6. The apparatus of claim 5, wherein the additional transistor exhibits an active drive strength at least in part based on a signal received via the third connection point, and the responsiveness of one or more memory nodes of the configured memory cells to the coupled voltage supply is at least in part based on the active drive strength exhibited by the additional transistor.

7. The apparatus of claim 1, wherein the configuration memory cell includes a transistor configured to provide stability to one or more memory nodes by selectively modulating currents to or from one or more memory nodes of the configuration memory cell, the modulation of the currents being at least partially based on a signal received via the second connection point.

8. The apparatus according to claim 1, wherein the apparatus comprises: A high-resistance element is coupled between the storage node in one or more storage nodes and the output of the configuration memory cell to enhance single event flip (SEU) tolerance.

9. The apparatus of claim 1, wherein the configuration memory unit includes a first inverter and a second inverter, the first inverter and the second inverter being cross-coupled between a first node and a second node to store state information represented by complementary voltages at the first node and the second node.

10. The apparatus of claim 9, wherein the transistors of one or more of the first inverter or the second inverter exhibit non-uniform voltage tolerances.

11. A method, the method comprising: Selective coupling from the first connection point of the configuration memory cell to the memory node of the configuration memory cell is controlled via the bit line. as well as During access to the configuration memory cell, voltage transitions at one or more memory nodes of the configuration memory cell are controlled via a second connection point of the configuration memory cell.

12. The method of claim 11, wherein during access to the configuration memory unit, the stability of one or more memory nodes of the configuration memory unit is controlled via a third connection point of the configuration memory unit.

13. The method according to claim 12, wherein the method comprises: The memory nodes of the configured memory cells are selectively coupled to a voltage power supply to enhance the stability of the memory nodes.

14. The method according to claim 13, wherein the method comprises: Selectively modulate the current going to or from the storage node to enhance the stability of the storage node.

15. The method according to claim 11, wherein the method comprises: The responsiveness of the coupling voltage of the memory node of the configured memory cell is adjusted, and the adjusted responsiveness is associated with the enhanced stability of the memory node.

16. A system comprising: Configure memory units; Bit line driver, the bit line driver being used to drive bit lines coupled to a first connection point of the configuration memory cell; A first write line driver is used to drive a first write line coupled to a second connection point of the configuration memory cell; A second write line driver is used to drive a second write line coupled to a third connection point of the configuration memory cell; A third write line driver is used to drive a third write line coupled to a fourth connection of the configured memory cell; and A logic circuit is provided for coordinating the bit line driver, the first word line driver, the second word line driver, and the third write line driver to perform access operations to the configuration memory cell, wherein the logic circuit is used to dynamically control the configuration memory cell during the access operation via adjusting signals generated by the first write line driver, the second write line driver, and the third write line driver to ensure stable and reliable state transitions.

17. The system of claim 16, wherein the bit line driver, the first write line driver, the second write line driver, and the third write line driver are configured to generate signals in at least a portion of response to an instruction received from the logic circuitry.

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