Silicon carbide driver using high voltage capacitor for isolation and signaling

Abstract

A gate driver circuit for receiving an input drive signal and outputting an output drive signal is provided. The gate driver circuit can include a first capacitor having a first terminal and a second terminal, a second capacitor having a first terminal and a second terminal, a first set of switches to selectively couple the first terminals of the first and second capacitors to the input drive signal and a supply voltage, a second set of switches to selectively couple the second terminals of the first and second capacitors to a reference voltage and a high impedance node, and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high impedance node. The comparator can output the output drive signal based on a comparison of the reference voltage to a voltage at the high impedance node.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Nonprovisional Patent Application No. 18 / 966,025, filed December 2, 2024, and U.S. Provisional Patent Application No. 63 / 605,292, filed December 1, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates generally to silicon carbide (SiC) drivers, and more specifically to SiC drivers that use capacitor coupling and charging to transfer input drive signals from a high voltage domain to a low voltage domain. Summary of the Invention

[0003] According to one or more examples, a gate driver circuit is provided for receiving an input drive signal and outputting an output drive signal. The gate driver circuit may include: a first capacitor having a first terminal and a second terminal; a second capacitor having a first terminal and a second terminal; a first set of switches for selectively coupling the first terminals of the first and second capacitors to the input drive signal and a power supply voltage; a second set of switches for selectively coupling the second terminals of the first and second capacitors to a reference voltage and a high-impedance node; and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high-impedance node. The comparator may output the output drive signal based on a comparison of the reference voltage with a voltage at the high-impedance node. The first set of switches may be high-voltage domain switches, and the second set of switches may be low-voltage domain switches. The first set of switches may selectively couple the first terminals of the first and second capacitors to the input drive signal and the power supply voltage based on a clock signal, and the second set of switches may selectively couple the second terminals of the first and second capacitors to the reference voltage and the high-impedance node based on a clock signal. When the clock signal is low, the first set of switches couples the first terminal of the first capacitor to the input drive signal and the first terminal of the second capacitor to the power supply voltage. When the clock signal is low, the second set of switches couples the second terminal of the first capacitor to a high-impedance node and the second terminal of the second capacitor to a reference voltage. When the clock signal is low, the second capacitor can be charged by the difference between the power supply voltage and the reference voltage. When the clock signal is high, the first set of switches couples the first terminal of the first capacitor to the power supply voltage and the first terminal of the second capacitor to the input drive signal. When the clock signal is high, the second set of switches couples the second terminal of the first capacitor to the reference voltage and the second terminal of the second capacitor to a high-impedance node. When the clock signal is high, the first capacitor can be charged by the difference between the power supply voltage and the reference voltage. The voltage at the high-impedance node can be in the range of approximately -0.5V to approximately 4.5V. The reference voltage can be approximately 2V. The input drive signal can be approximately 2005V, and the power supply voltage can be approximately 2002.5V. The input drive signal can be approximately 2000V, and the supply voltage can be approximately 2002.5V. When the voltage at the high-impedance node is approximately 4.5V, the output drive signal can be approximately 5V. When the voltage at the high-impedance node is approximately -0.5V, the output drive signal can be approximately 0V.

[0004] According to one aspect of one or more examples, an integrated circuit (IC) is provided. The IC may include a primary side comprising: a first capacitor having a first terminal and a second terminal; a second capacitor having a first terminal and a second terminal; and a first set of switches for receiving an input drive signal and a power supply voltage, and selectively coupling the first terminals of the first and second capacitors to the input drive signal and the power supply voltage. The IC may include a secondary side comprising: a second set of switches for selectively coupling the second terminals of the first and second capacitors to a reference voltage and a high-impedance node; and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high-impedance node, the comparator comparing the reference voltage with a voltage at the high-impedance node to generate an output drive signal based on the comparison. The primary side may also include an input logic block for receiving the input drive signal and outputting a modified input drive signal to the first set of switches. The first and second capacitors may be 2000V lateral capacitors. The input drive signal may be sampled at a clock frequency of approximately 100MHz.

[0005] According to one aspect of one or more examples, a method for driving a silicon carbide (SiC) transistor is provided. The method may include: using a first set of switches to selectively couple first terminals of a first capacitor and a second capacitor to an input drive signal and a power supply voltage; using a second set of switches to selectively couple second terminals of the first capacitor and the second capacitor to a reference voltage and a high-impedance node; coupling a first terminal of a comparator to the reference voltage and a second terminal of the comparator to the high-impedance node; and using the comparator to output an output drive signal based on a comparison of the reference voltage with a voltage at the high-impedance node. The first set of switches may be high-voltage domain switches, and the second set of switches may be low-voltage domain switches. The selective coupling of the first terminals of the first capacitor and the second capacitor to the input drive signal and the power supply voltage using the first set of switches, and the selective coupling of the second terminals of the first capacitor and the second capacitor to the reference voltage and the high-impedance node using the second set of switches, may be based on a clock signal. Attached Figure Description

[0006] Figure 1 A functional block diagram of a silicon carbide driver according to the prior art is shown.

[0007] Figure 2 It shows the result of Figure 1 The silicon carbide driver uses a modulation scheme based on on-off keying.

[0008] Figure 3 A circuit diagram of a gate driver circuit according to one or more examples is shown.

[0009] Figure 4 The diagram illustrates, based on one or more examples, a high input drive signal. Figure 3 Functional diagram of the switching functionality of the gate driver circuit.

[0010] Figure 5 The diagram illustrates a low input drive signal based on one or more examples. Figure 3 Functional diagram of the switching functionality of the gate driver circuit.

[0011] Figure 6A This illustrates, according to one or more examples, when the input drive signal is high. Figure 3 A diagram of a comparator in a gate driver circuit.

[0012] Figure 6B This illustrates, according to one or more examples, when the input drive signal is low. Figure 3 A diagram of a comparator in a gate driver circuit.

[0013] Figure 7 A diagram of an integrated circuit including gate driver circuitry, according to one or more examples, is shown. Detailed Implementation

[0014] Reference will now be made in detail to the various examples illustrated in the accompanying drawings, wherein the same reference numerals always denote the same elements. These examples may be presented in various forms, and are not limited to those described herein.

[0015] In a silicon carbide gate driver, it is necessary to receive a high-voltage input drive signal (e.g., about 2,000V) and output a low-voltage output drive signal (e.g., about 5V). Figure 1 A functional block diagram of a silicon carbide driver 100 according to the prior art is shown. Figure 2 It shows the result of Figure 1 The silicon carbide driver 100 uses a modulation scheme 200 based on on-keying. (In the description...) Figure 1 When describing the functionality, descriptions of certain components have been omitted to avoid obscuring the concept of the invention. References Figure 1 and Figure 2 The input signal TXIN 101 is input to the transmitter 102, and the output signal RXOUT 103 is output from the receiver 104. The input signal TXIN 101 and the output signal RXOUT 103 can be digital signals, such as... Figure 2 As shown. Figure 1 The transmitter 102 includes a TX signal conditioning circuit 105, which can generate and modulate an AC carrier signal based on the input signal TX IN 101. For example, as Figure 2As shown, the TX signal conditioning circuit 105 can modulate the frequency of the AC carrier signal 201 to correspond to the digital high and low levels of the input signal TXIN 101. For example... Figure 1 As shown, transmitter 102 and receiver 104 can be separated by a capacitive isolation barrier 106 (such as a silicon dioxide (SiO2) barrier). The AC carrier signal 201 can propagate through the capacitive isolation barrier 106 and can be received by an RX signal conditioning circuit 107, which demodulates the AC carrier signal 201 to generate a digital output signal RX OUT 103. The TX signal conditioning circuit 105 and the RX signal conditioning circuit 107 can be modulated at approximately 250MHz to 300MHz, which consumes a significant amount of current. The steps of modulating and demodulating the input signal TX IN 101 require modulation and demodulation components, which occupy space and delay the output signal RX OUT 103. Therefore, a circuit is needed that can address one or more of these problems.

[0016] Figure 3 A circuit diagram of a gate driver circuit 300 according to one or more examples is shown. Figure 3 One or more examples of the gate driver circuit 300 may include: a first capacitor C1 301 having a first terminal 302 and a second terminal 303; and a second capacitor C2 304 having a first terminal 305 and a second terminal 306. The first terminal 302 of the first capacitor C1 301 and the first terminal 305 of the second capacitor C2 304 may be coupled to a first set of switches 307, which may selectively couple the first terminals 302 and 305 of the first capacitor C1 301 and the second capacitor C2 304 to an input drive signal IN+ 308 and a power supply voltage VDD / 2 309. According to one or more examples, the power supply voltage VDD / 2 309 coupled to the first set of switches 307 may be supplied to an integrated circuit containing the gate driver circuit 300 (e.g., Figure 7 The power supply voltage VDD / 2 309 of the integrated circuit 700 in the circuit, or may be a representation of the power supply voltage VDD / 2 309 supplied to the integrated circuit, such as Figure 3 As shown in the figure, the power supply voltage VDD / 2 309 supplied to the gate driver circuit 300 is half the voltage supplied to the integrated circuit VDD. Although supplied to... Figure 3 The power supply voltage VDD / 2 309 of the gate driver circuit 300 shown in the example is half of the voltage supplied to the integrated circuit, but other representations of the voltage supplied to the integrated circuit (e.g., 1 / 3, 1 / 4, etc.) can be used.

[0017] according to Figure 3One or more examples of the gate driver circuit 300 may further include a second set of switches 310 that can selectively couple the second terminals 303, 306 of the first capacitor C1 301 and the second capacitor C2 304 to a reference voltage Vref 311 and a high-impedance node 312. The first set of switches 307 and the second set of switches 310 may be coupled to a clock signal and may selectively couple the first terminals 302, 305 of the first capacitor C1 301 and the second capacitor C2 304 to an input drive signal IN+ 308 and a power supply voltage VDD / 2 309 based on the clock signal, and selectively couple the second terminals 303, 306 of the first capacitor C1 301 and the second capacitor C2 304 to the reference voltage Vref 311 and the high-impedance node 312 based on the clock signal. Figure 3 The gate driver circuit 300 may further include a comparator 313 having a first terminal 314 coupled to a reference voltage Vref 311 and a second terminal 315 coupled to a high-impedance node 312. The comparator 313 may output an output drive signal VOUT 316 based on a comparison between the reference voltage Vref 311 and the voltage at the high-impedance node 312.

[0018] Figure 4 The diagram illustrates a 308 with a high input drive signal IN+, based on one or more examples. Figure 3 The functional diagram of the switches 307 and 310 of the gate driver circuit 300 is shown in Figure 400. As explained above, the first set of switches 307 and the second set of switches 310 can be controlled in response to a clock signal oscillating between high and low states. Figure 4 The operation of the first set of switches 307 and the second set of switches 310 at three times 400A, 400B and 400C is shown. Figure 4 The left portion 400A shows the first set of switches 307 and the second set of switches 310 when the clock signal is high. Figure 4 The central portion 400B shows the first set of switches 307 and the second set of switches 310 when the clock signal is low, and Figure 4 The right part 400C shows the first set of switches 307 and the second set of switches 310 when the clock signal is high. Figure 4 All three sections, 400A, 400B, and 400C, demonstrate when the input drive signal IN+ 308 is high. Figure 3 The operation of the gate driver circuit 300. In Figure 4In the example shown, the high state of the input drive signal IN+ 308 is represented as 2005V, and the supply voltage VDD / 2 309 is 2002.5V, although these values ​​assume a common-mode signal of 2000V. Other values ​​for the input drive signal IN+ 308, the supply voltage VDD / 2 309, and the common-mode signal can be selected.

[0019] refer to Figure 4 In the central portion 400B, when the clock signal is low, the first set of switches 307 couples the first terminal 305 of the second capacitor C2 304 to the power supply voltage VDD / 2 309 (which is 2002.5V), and the second set of switches 310 couples the second terminal 306 of the second capacitor C2 304 to the reference voltage Vref 311 (which is set to 2V, but other reference voltages can be used). Therefore, the second capacitor C2 304 is charged with the difference between the power supply voltage VDD / 2 309 (e.g., 2002.5V) and the reference voltage Vref 311 (e.g., 2V), which is 2000.5V. When the clock signal is low, the first set of switches 307 also couples the first terminal 302 of the first capacitor C1 301 to the input drive signal IN+ 308, and the second set of switches 310 couples the second terminal 303 of the first capacitor C1 301 to the high-impedance node 312.

[0020] When the clock signal goes high, the first set of switches 307 couples the first terminal 305 of the second capacitor C2 304 to the input drive signal IN+ 308, which is 2005V, and couples the second terminal 306 of the second capacitor C2 304 to the high-impedance node 312. To maintain a voltage of 2000.5V across the second capacitor C2 304 from when the clock signal is low, the voltage at the high-impedance node 312 becomes 4.5V because the voltage at the first terminal 305 of the second capacitor C2 304 has increased from 2002.5V (when the clock signal is low) to 2005V. When the clock signal is high, the first set of switches 307 also couples the first terminal 302 of the first capacitor C1 301 to the power supply voltage VDD / 2 309 (which is 2002.5V), and the second set of switches 310 couples the second terminal 303 of the first capacitor C1 301 to the reference voltage Vref 311 (which is 2V). By maintaining 4.5V at the high-impedance node 312 of the second terminal 306 coupled to the second capacitor C2 304, the high input drive signal IN+ 308 is passed to comparator 313, as explained below. During the high clock cycle, the first capacitor C1 301 is charged at 2000.5V (i.e., the difference between the supply voltage VDD / 2 309 and the reference voltage Vref 311). When the clock signal returns to the low clock cycle ( Figure 4When the first set of switches 307 couples the first terminal 302 of the first capacitor C1 301 to the input drive signal IN+ 308 (e.g., 2005V), and the second set of switches 310 couples the second terminal 303 of the first capacitor C1 301 to the high-impedance node 312. To maintain 2000.5V across the first capacitor C1 301, the voltage at the high-impedance node 312 is maintained at 4.5V, thereby passing the high input drive signal IN+ 308 to the comparator 313. By repeating this process as the clock signal cycles between high and low states, the input drive signal IN+ 308 is accurately and quickly provided to the comparator 313 to output the output drive signal VOUT 316, as explained below. Furthermore, the gate driver circuit 300 is capable of shifting the 2005V input drive signal IN+ 308 from the high voltage domain to the low voltage domain (e.g., 4.5V).

[0021] Figure 5 The diagram illustrates a 308 with a low input drive signal IN+, based on one or more examples. Figure 3 The functional diagram 500 shows the switches 307 and 310 of the gate driver circuit 300. Similar to... Figure 4 , Figure 5 The operation of the first set of switches 307 and the second set of switches 310 at three times 500A, 500B and 500C is shown. Figure 5 The left portion 500A shows the first set of switches 307 and the second set of switches 310 when the clock signal is high. Figure 5 The central portion 500B shows the first set of switches 307 and the second set of switches 310 when the clock signal is low, and Figure 5 The right part 500C shows the first set of switches 307 and the second set of switches 310 when the clock signal is high. Figure 5 All three sections, 500A, 500B, and 500C, demonstrate when the input drive signal IN+ 308 is low. Figure 3 The operation of the gate driver circuit 300. In Figure 5 In the example shown, the low state of the input drive signal IN+ 308 is represented as 2000V, and the supply voltage VDD / 2 309 is 2002.5V, although these values ​​assume a common-mode signal of 2000V. Other values ​​for the input drive signal IN+ 308, the supply voltage VDD / 2 309, and the common-mode signal can be selected.

[0022] refer to Figure 5In the central portion 500B, when the clock signal is low, the first set of switches 307 couples the first terminal 305 of the second capacitor C2 304 to the power supply voltage VDD / 2 309 (which is 2002.5V), and the second set of switches 310 couples the second terminal 306 of the second capacitor C2 304 to the reference voltage Vref 311 (which is set to 2V). Therefore, the second capacitor C2 304 is charged with the difference between the power supply voltage VDD / 2 309 (e.g., 2002.5V) and the reference voltage Vref 311 (e.g., 2V), which is 2000.5V. When the clock signal is low, the first set of switches 307 also couples the first terminal 302 of the first capacitor C1 301 to the input drive signal IN+ 308, and the second set of switches 310 couples the second terminal 303 of the first capacitor C1 301 to the high-impedance node 312.

[0023] When the clock signal goes high, the first set of switches 307 couples the first terminal 305 of the second capacitor C2 304 to the 2000V input drive signal IN+ 308, and couples the second terminal 306 of the second capacitor C2 304 to the high-impedance node 312. To maintain a voltage of 2000.5V across the second capacitor C2 304 from when the clock signal is low, the voltage at the high-impedance node 312 becomes -0.5V, because the voltage at the first terminal 305 of the second capacitor C2 304 has decreased from 2002.5V (when the clock signal is low) to 2000V. When the clock signal is high, the first set of switches 307 also couples the first terminal 302 of the first capacitor C1 301 to the power supply voltage VDD / 2 309 (which is 2002.5V), and the second set of switches 310 couples the second terminal 303 of the first capacitor C1 301 to the reference voltage Vref 311 (which is 2V). By maintaining -0.5V at the high-impedance node 312 of the second terminal 306 coupled to the second capacitor C2 304, the low input drive signal IN+ 308 is passed to comparator 313, as explained below. During the high clock cycle, the first capacitor C1 301 is charged at 2000.5V (i.e., the difference between the supply voltage VDD / 2 309 and the reference voltage Vref 311). When the clock signal returns to the low clock cycle ( Figure 5When the first set of switches 307 couples the first terminal 302 of the first capacitor C1 301 to the input drive signal IN+ 308 (e.g., 2000V), and the second set of switches 310 couples the second terminal 303 of the first capacitor C1 301 to the high-impedance node 312. To maintain 2000.5V across the first capacitor C1 301, the voltage at the high-impedance node 312 remains at -0.5V, thereby passing the low input drive signal IN+ 308 to the comparator 313. By repeating this process as the clock signal cycles between high and low states, the input drive signal IN+ 308 is accurately and quickly provided to the comparator 313 to output the output drive signal VOUT 316, as explained below. Furthermore, the gate driver circuit 300 is capable of shifting the 2000V input drive signal IN+ 308 from the high voltage domain to the low voltage domain (e.g., -0.5V).

[0024] Figure 6A This illustrates, according to one or more examples, when the input drive signal IN+ 308 is high. Figure 3 The comparator 313 of the gate driver circuit 300 is shown in Figure 600A. Figure 6B This illustrates, according to one or more examples, when the input drive signal IN+ 308 is low. Figure 3 The comparator 313 of the gate driver circuit 300 is shown in Figure 600B. Figure 6A In the above text, when the input drive signal IN+ 308 is high, the voltage at the high impedance node 312 is 4.5V, as explained above. Figure 3 The comparator 313 of the gate driver circuit 300 has a first terminal 314 coupled to a reference voltage Vref 311, which in this example is 2V. A high-impedance node 312 is coupled to a second terminal 315 of the comparator 313 such that when the input drive signal IN+ 308 is high, the second terminal 315 of the comparator 313 receives 4.5V at the high-impedance node 312. The comparator 313 outputs an output drive signal VOUT 316 based on a comparison of the reference voltage Vref 311 (e.g., 2V) with the voltage at the high-impedance node 312 (e.g., 4.5V). For example, the comparator 313 may output a 5V output drive signal VOUT 316 based on a comparison of the 4.5V signal at the high-impedance node 312 with the 2V reference voltage Vref 311.

[0025] exist Figure 6BIn this configuration, when the input drive signal IN+ 308 is low, the voltage at the high-impedance node 312 is -0.5V, as explained above. The first terminal 314 of comparator 313 is coupled to a reference voltage Vref 311, which in this example is set to 2V. The second terminal 315 of comparator 313 is coupled to the high-impedance node 312 such that when the input drive signal IN+ 308 is low, the second terminal 315 of comparator 313 receives -0.5V. Comparator 313 outputs an output drive signal VOUT 316 based on a comparison of the reference voltage Vref 311 (e.g., 2V) with the voltage at the high-impedance node 312 (e.g., -0.5V). For example, comparator 313 could output a 0V output drive signal VOUT 316 based on a comparison of the -0.5V signal at the high-impedance node 312 with the 2V reference voltage Vref 311.

[0026] Figure 7 A diagram of an integrated circuit 700 including a gate driver circuit 300 according to one or more examples is shown. Figure 7 The diagram illustrates multiple components that can be used to implement the gate driver circuit 300 according to one or more examples; for clarity, a discussion of these components is omitted. Figure 7 The circuit 700 may have a primary side 701 and a secondary side 702. The primary side 701 may include a first set of switches 307 for receiving an input drive signal IN+ 308 and a power supply voltage VDD / 2 309. According to one or more examples, the input drive signal IN+ 308 may be received by an input logic block 703 that can output a modified input drive signal MOD_IN 704 to the first set of switches 307. The primary side 701 may also include a first capacitor C1 301 and a second capacitor C2 304, which, according to one or more examples, may be 2000V lateral capacitors. The secondary side 702 may include a second set of switches 310, a reference voltage source, and a comparator 313 that compares a reference voltage Vref 311 with the voltage at a high-impedance node 312 to generate an output drive signal VOUT 316 based on the comparison. By using capacitor coupling and charging to transfer the high-voltage input drive signal IN+ 308 to the low-voltage output drive signal VOUT 316, the gate drive circuit 300, according to one or more examples, can be faster than relying on modulation and demodulation of the input drive signal, uses less space by eliminating the need for modulation and demodulation circuitry, and consumes less current than using an ultrafast oscillator for modulation and demodulation. The input drive signal IN+ 308 can be sampled frequently, for example, at a clock frequency of 100 MHz, which allows for accurate readouts with reduced glitches.

[0027] Various examples have been disclosed herein in conjunction with the foregoing description and accompanying drawings. It should be understood that describing and illustrating each combination and sub-combination of these examples literally would be an undue repetition. Therefore, all examples can be combined in any manner and / or combination, and this specification (including the accompanying drawings) should be construed as constituting a complete written description of all combinations and sub-combinations of the examples described herein, as well as the ways and processes of preparing and using them, and should support any claims to any such combinations or sub-combinations.

[0028] Those skilled in the art will understand that the examples described herein are not limited to those specifically shown and described above. Furthermore, unless the contrary is mentioned above, it should be noted that all figures are not drawn to scale. Various modifications and variations are possible in accordance with the above teachings.

Claims

1. A gate driver circuit, the gate driver circuit being configured to receive an input drive signal and output an output drive signal, the gate driver circuit comprising: A first capacitor, the first capacitor having a first terminal and a second terminal; A second capacitor, the second capacitor having a first terminal and a second terminal; A first set of switches is used to selectively couple the first terminals of the first capacitor and the second capacitor to the input drive signal and the power supply voltage. The second set of switches is used to selectively couple the second terminals of the first capacitor and the second capacitor to a reference voltage and a high-impedance node; and A comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high-impedance node; The comparator outputs the output drive signal based on a comparison between the reference voltage and the voltage at the high-impedance node.

2. The gate driver circuit according to claim 1, wherein the first set of switches is a high-voltage domain switch and the second set of switches is a low-voltage domain switch.

3. The gate driver circuit of claim 1, wherein the first set of switches selectively couples the first terminals of the first capacitor and the second capacitor to the input drive signal and the power supply voltage based on a clock signal, and the second set of switches selectively couples the second terminals of the first capacitor and the second capacitor to the reference voltage and the high impedance node based on the clock signal.

4. The gate driver circuit of claim 3, wherein when the clock signal is low, the first set of switches couples the first terminal of the first capacitor to the input drive signal and couples the first terminal of the second capacitor to the power supply voltage; and When the clock signal is low, the second set of switches couples the second terminal of the first capacitor to the high-impedance node and couples the second terminal of the second capacitor to the reference voltage.

5. The gate driver circuit of claim 4, wherein when the clock signal is low, the second capacitor is charged with the difference between the power supply voltage and the reference voltage.

6. The gate driver circuit of claim 3, wherein when the clock signal is high, the first set of switches couples the first terminal of the first capacitor to the power supply voltage and couples the first terminal of the second capacitor to the input drive signal; and When the clock signal is high, the second set of switches couples the second terminal of the first capacitor to the reference voltage and the second terminal of the second capacitor to the high impedance node.

7. The gate driver circuit of claim 6, wherein when the clock signal is high, the first capacitor is charged with the difference between the power supply voltage and the reference voltage.

8. The gate driver circuit of claim 1, wherein the voltage at the high-impedance node is in the range of approximately -0.5V to approximately 4.5V.

9. The gate driver circuit of claim 1, wherein the reference voltage is approximately 2V.

10. The gate driver circuit of claim 1, wherein the input drive signal is approximately 2005V and the power supply voltage is approximately 2002.5V.

11. The gate driver circuit of claim 1, wherein the input drive signal is approximately 2000V and the power supply voltage is approximately 2002.5V.

12. The gate driver circuit of claim 1, wherein the output drive signal is approximately 5V when the voltage at the high-impedance node is approximately 4.5V.

13. The gate driver circuit of claim 1, wherein the output drive signal is approximately 0V when the voltage at the high-impedance node is approximately -0.5V.

14. An integrated circuit (IC), said integrated circuit (IC) comprising: The primary side includes: A first capacitor, the first capacitor having a first terminal and a second terminal; A second capacitor, the second capacitor having a first terminal and a second terminal; and A first set of switches is used to receive an input drive signal and a power supply voltage, and to selectively couple the first terminals of the first capacitor and the second capacitor to the input drive signal and the power supply voltage. The secondary side includes: A second set of switches is used to selectively couple the second terminals of the first capacitor and the second capacitor to a reference voltage and a high-impedance node; and A comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high-impedance node, the comparator being used to compare the reference voltage with the voltage at the high-impedance node to generate an output drive signal based on the comparison.

15. The IC of claim 14, wherein the primary side further includes an input logic block for receiving the input drive signal and outputting a modified input drive signal to the first set of switches.

16. The IC according to claim 14, wherein the first capacitor and the second capacitor are 2000V lateral capacitors.

17. The IC of claim 14, wherein the input drive signal is sampled at a clock frequency of approximately 100 MHz.

18. A method for driving a silicon carbide (SiC) transistor, the method comprising: The first set of switches is used to selectively couple the first terminals of the first capacitor and the second capacitor to the input drive signal and the power supply voltage. A second set of switches is used to selectively couple the second terminals of the first capacitor and the second capacitor to the reference voltage and the high-impedance node; The first terminal of the comparator is coupled to the reference voltage, and the second terminal of the comparator is coupled to the high-impedance node; as well as The comparator is used to output a drive signal based on a comparison between the reference voltage and the voltage at the high-impedance node.

19. The method of claim 18, wherein the first set of switches is a high-voltage domain switch and the second set of switches is a low-voltage domain switch.

20. The method of claim 18, wherein the first set of switches is used to selectively couple the first terminals of the first capacitor and the second capacitor to the input drive signal and the power supply voltage, and the second set of switches is used to selectively couple the second terminals of the first capacitor and the second capacitor to the reference voltage and the high-impedance node based on the clock signal.

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