OFDM communication with dynamic frequency hopping

Abstract

In one embodiment, a method includes transmitting (2802), by a first device (202), a first synchronization sequence in a single first synchronization channel of a plurality of channels, transmitting (2804), by the first device (202), first data (2504, 2506, 2508) associated with the first synchronization sequence using a single channel of the plurality of channels according to a first frequency hopping sequence each time after transmitting the first synchronization sequence, transmitting (2802), by the first device (202), a second synchronization sequence in a single second synchronization channel of the plurality of channels after transmitting the first data, and transmitting (2804), by the first device (202), second data (2504, 2506, 2508) associated with the second synchronization sequence using a single channel of the plurality of channels according to a second frequency hopping sequence each time after transmitting the second synchronization sequence.

Description

Technical Field

[0001] This disclosure generally relates to an electronic system and method, and in certain embodiments, to orthogonal frequency division multiplexing (OFDM) communication with dynamic frequency hopping. Background Technology

[0002] In Frequency Division Multiplexing (FDM), a transmitter can encode data across multiple frequency bands and transmit a radio frequency (RF) signal that combines signals from those bands. The RF signal is a combination of multiple subcarrier signals, each of which encodes information. Because unique information can be encoded in each frequency band, FDM systems typically have higher data throughput than other systems that use only a single carrier frequency.

[0003] In orthogonal FDM (OFDM) systems, each frequency band is orthogonal to its adjacent bands (e.g., the center frequency of the first band is aligned with the zero frequency of each adjacent band). This orthogonality of the bands leads to reduced interference between cross-carrier signals. Therefore, in OFDM systems, which lack orthogonality (where sub-channels do not overlap in frequency), the spacing between the center frequencies of each sub-channel (also called a channel, subcarrier band, or frequency band) can be much closer to each other (e.g., sub-channels may overlap in frequency), such as... Figure 1 As shown in the diagram. Furthermore, orthogonality allows OFDM receivers to more easily extract information from each frequency band of the combined RF signals. Summary of the Invention

[0004] According to one embodiment, a method includes: transmitting a first synchronization sequence by a first device in a single synchronization channel among a plurality of channels; and after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence by the first device each time using a single channel among the plurality of channels according to a frequency hopping sequence.

[0005] According to one embodiment, a method includes: a first device monitoring a single synchronization channel among a plurality of channels for detecting a first synchronization sequence; and in response to detecting the first synchronization sequence, the first device using the single channel among the plurality of channels each time to extract a first data symbol associated with the first synchronization sequence according to a frequency hopping sequence.

[0006] According to one embodiment, a method includes: generating a first plurality of chip spread spectrums corresponding to a synchronization sequence of a packet by a first means; generating a second plurality of chip spread spectrums corresponding to a header field of the packet by the first means; generating a first plurality of binary phase shift keying (BPSK) symbol pairs by the first means based on the first plurality of chip spread spectrums; generating a second plurality of BPSK symbol pairs by the first means based on the second plurality of chip spread spectrums; transmitting the first plurality of BPSK symbol pairs by the first means in a single synchronization channel among a plurality of channels; and after transmitting the first plurality of BPSK symbol pairs, transmitting the second plurality of BPSK symbol pairs by the first means in corresponding channels among the plurality of channels according to a frequency hopping sequence, wherein only a single channel among the plurality of channels is used for transmission at a time.

[0007] According to one embodiment, an apparatus includes: a transceiver; and a controller configured to: transmit a first synchronization sequence via the transceiver in a single synchronization channel among a plurality of channels; and after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence each time using a single channel among the plurality of channels according to a frequency hopping sequence.

[0008] According to one embodiment, an apparatus includes: a transceiver; and a controller configured to: use the transceiver to monitor a single synchronization channel among a plurality of channels for detecting a first synchronization sequence; and in response to detecting the first synchronization sequence, use the single channel among the plurality of channels each time to extract a first data symbol associated with the first synchronization sequence according to a frequency hopping sequence.

[0009] According to one embodiment, an apparatus includes: a transceiver; and a controller configured to: generate a first plurality of chip spreads corresponding to a plurality of bits of a synchronization sequence of a packet; generate a second plurality of chip spreads corresponding to a plurality of bits of a header field of a packet; generate a first plurality of binary phase shift keying (BPSK) symbol pairs based on the first plurality of chip spreads; generate a second plurality of BPSK symbol pairs based on the second plurality of chip spreads; transmit the first plurality of BPSK symbol pairs via the transceiver in a single synchronization channel among a plurality of channels; and after transmitting the first plurality of BPSK symbol pairs, transmit the second plurality of BPSK symbol pairs via the transceiver in corresponding channels among the plurality of channels according to a frequency hopping sequence, wherein only a single channel among the plurality of channels is used for transmission at a time.

[0010] According to one embodiment, a method includes: transmitting a first synchronization sequence by a first device in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence by the first device each time using a single channel among the plurality of channels according to a first frequency hopping sequence; after transmitting the first data, transmitting a second synchronization sequence by the first device in a single second synchronization channel among the plurality of channels; and after transmitting the second synchronization sequence, transmitting second data associated with the second synchronization sequence by the first device each time using a single channel among the plurality of channels according to a second frequency hopping sequence, wherein: the first synchronization channel is different from the second synchronization channel, or the first synchronization sequence is different from the second synchronization sequence, or the second frequency hopping sequence is different from the first frequency hopping sequence.

[0011] According to one embodiment, a method includes: transmitting a first synchronization sequence by a first device in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence by the first device each time using a single channel among the plurality of channels according to a first frequency hopping sequence; and after transmitting the first data, monitoring a single second synchronization channel by the first device for detecting a second synchronization sequence, wherein the first synchronization channel is different from the second synchronization channel.

[0012] According to one embodiment, a method includes: generating a plurality of chip spread spectrums corresponding to a plurality of bits of a first group; generating a plurality of binary phase shift keying (BPSK) symbols based on the plurality of chip spread spectrums; repeating a portion of the corresponding BPSK symbol before each of the plurality of BPSK symbols; applying a windowed filter during a first portion of the repeated portion of each BPSK symbol to generate a second plurality of BPSK symbols; and transmitting the second plurality of BPSK symbols in symbol pairs in corresponding channels of a plurality of channels according to a frequency hopping sequence, wherein only a single channel of the plurality of channels is used each time to transmit the second plurality of BPSK symbols.

[0013] According to one embodiment, a method includes: transmitting a first synchronization sequence by a first device in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence each time using a single channel among the plurality of channels according to a first frequency hopping sequence; and after transmitting the first data: monitoring a single second synchronization channel by the first device to detect a second synchronization sequence associated with a second device, and monitoring a single second synchronization channel by the first device to detect a third synchronization sequence associated with a third device.

[0014] According to one embodiment, a method includes: generating a first plurality of chip spread spectrums corresponding to a plurality of bits of a first group; generating a first plurality of binary phase shift keying (BPSK) symbol pairs based on the first plurality of chip spread spectrums; transmitting the first plurality of BPSK symbol pairs in corresponding channels of a plurality of channels according to a first frequency hopping sequence; generating a second plurality of chip spread spectrums corresponding to a plurality of bits of a second group; generating a second plurality of BPSK symbol pairs based on the second plurality of chip spread spectrums; and transmitting the second plurality of BPSK symbol pairs in corresponding channels of a plurality of channels according to a second frequency hopping sequence, wherein the second frequency hopping sequence is different from the first frequency hopping sequence, and wherein only a single channel of the plurality of channels is used for transmission at a time.

[0015] According to one embodiment, a method includes: negotiating a first symbol duration with a second device; transmitting a first synchronization sequence in a single synchronization channel among a plurality of channels using the negotiated first symbol duration; and after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence in a single channel among the plurality of channels according to a frequency hopping sequence using the negotiated symbol duration each time.

[0016] According to one embodiment, an apparatus includes: a transceiver; and a controller configured to: transmit a first synchronization sequence via the transceiver in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence via the transceiver each time using a single channel among the plurality of channels according to a first frequency hopping sequence; after transmitting the first data, transmit a second synchronization sequence via the transceiver in a single second synchronization channel among the plurality of channels; and after transmitting the second synchronization sequence, transmit second data associated with the second synchronization sequence via the transceiver each time using a single channel among the plurality of channels according to a second frequency hopping sequence, wherein: the first synchronization channel is different from the second synchronization channel, or the first synchronization sequence is different from the second synchronization sequence, or the second frequency hopping sequence is different from the first frequency hopping sequence.

[0017] According to one embodiment, an apparatus includes: a transceiver; and a controller configured to: transmit a first synchronization sequence via the transceiver in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence via the transceiver each time using a single channel among the plurality of channels according to a first frequency hopping sequence; and after transmitting the first data, monitor a single second synchronization channel for detecting a second synchronization sequence, wherein the first synchronization channel is different from the second synchronization channel.

[0018] According to one embodiment, an apparatus includes: a transceiver; and a controller configured to: generate a plurality of chip spread spectrums corresponding to a plurality of bits of a first group; generate a plurality of binary phase shift keying (BPSK) symbols based on the plurality of chip spread spectrums; repeat a portion of the corresponding BPSK symbol before each of the plurality of BPSK symbols; apply a windowed filter during a first portion of the repeated portion of each BPSK symbol to generate a second plurality of BPSK symbols; and transmit the second plurality of BPSK symbols in symbol pairs in corresponding channels of a plurality of channels according to a frequency hopping sequence via the transceiver, wherein only a single channel of the plurality of channels is used each time to transmit the second plurality of BPSK symbols.

[0019] According to one embodiment, an apparatus includes: a transceiver; and a controller configured to: transmit a first synchronization sequence via the transceiver in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence via the transceiver each time using a single channel among the plurality of channels according to a first frequency hopping sequence; and after transmitting the first data: use the transceiver to monitor a single second synchronization channel for detecting a second synchronization sequence associated with a second device, and use the transceiver to monitor a single second synchronization channel for detecting a third synchronization sequence associated with a third device.

[0020] According to one embodiment, an apparatus includes: a transceiver; and a controller configured to: generate a first plurality of chip spread spectrum corresponding to a plurality of bits of a first packet; generate a first plurality of binary phase shift keying (BPSK) symbol pairs based on the first plurality of chip spread spectrum; transmit the first plurality of BPSK symbol pairs in corresponding channels of a plurality of channels via the transceiver according to a first frequency hopping sequence; generate a second plurality of chip spread spectrum corresponding to a plurality of bits of a second packet; generate a second plurality of BPSK symbol pairs based on the second plurality of chip spread spectrum; and transmit the second plurality of BPSK symbol pairs in corresponding channels of a plurality of channels via the transceiver according to a second frequency hopping sequence, wherein the second frequency hopping sequence is different from the first frequency hopping sequence, and wherein only a single channel of the plurality of channels is used for transmission at a time.

[0021] According to one embodiment, an apparatus includes: a transceiver; and a controller configured to: negotiate a first symbol duration with a second apparatus via the transceiver; transmit a first synchronization sequence via the transceiver in a single synchronization channel among a plurality of channels using the negotiated first symbol duration; and after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence via the transceiver using the negotiated symbol duration each time in a single channel among the plurality of channels according to a frequency hopping sequence. Attached Figure Description

[0022] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 Various exemplary channel arrangements for wireless communication are shown;

[0024] Figure 2 A communication system according to an embodiment of the present disclosure is shown;

[0025] Figure 3 A schematic diagram illustrating an RF core according to an embodiment of the present disclosure;

[0026] Figure 4 A block diagram illustrating a processing pipeline for generating modulated signals for wireless transmission according to embodiments of the present disclosure;

[0027] Figure 5 and 6 A block diagram illustrating a processing pipeline for processing a received modulated signal according to an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram illustrating a scrambler according to an embodiment of the present disclosure;

[0029] Figure 8 A schematic diagram illustrating a descrambler according to an embodiment of the present disclosure;

[0030] Figure 9 A block diagram illustrating a forward error correction (FEC) encoder according to an embodiment of the present disclosure;

[0031] Figure 10 A schematic diagram illustrating a convolutional encoder according to an embodiment of the present disclosure;

[0032] Figure 11 A block diagram illustrating the operation of an interleaver according to an embodiment of the present disclosure is shown;

[0033] Figure 12 A block diagram illustrating the operation of a deinterleaver according to an embodiment of the present disclosure is shown;

[0034] Figure 13 A block diagram of a direct sequence spread spectrum (DSSS) modulator according to an embodiment of the present disclosure is shown;

[0035] Figure 14 and 15 Chip sequences for different DSSS values ​​and polarities are shown according to embodiments of the present disclosure;

[0036] Figure 16 A block diagram illustrating a DSSS demodulator according to an embodiment of the present disclosure;

[0037] Figure 17A block diagram showing a BPSK encoder according to an embodiment of the present disclosure;

[0038] Figure 18 A block diagram illustrating a BPSK decoder according to an embodiment of the present disclosure;

[0039] Figure 19 A block diagram illustrating a single subcarrier mapper according to an embodiment of the present disclosure;

[0040] Figure 20 A block diagram illustrating an Inverse Fast Fourier Transform (IFFT) block 2000 according to an embodiment of the present disclosure;

[0041] Figure 21 A block diagram illustrating a Fast Fourier Transform (FFT) block according to an embodiment of the present disclosure;

[0042] Figure 22 The operation of a loop prefix with a windowing function according to an embodiment of the present disclosure is illustrated;

[0043] Figures 23A to 23D This demonstrates various possible settings for data rates for the RF core according to embodiments of the present disclosure;

[0044] Figure 24 A flowchart illustrating an embodiment method for selecting communication parameters according to an embodiment of the present disclosure;

[0045] Figure 25 The packet structure of a physical layer (PHY) protocol data unit (PPDU) according to an embodiment of the present invention is shown;

[0046] Figure 26 Demonstrates a short training field (STF) bit sequence according to an embodiment of this disclosure;

[0047] Figure 27 A long training field (LTF) bit sequence is shown according to an embodiment of the present disclosure;

[0048] Figure 28 The transmission of packets coded across multiple subcarrier frequencies is illustrated according to an embodiment of the present disclosure;

[0049] Figure 29A and 29B The possible sets of two coefficients of a linear congruent generator (LCG) for determining a frequency hopping sequence according to embodiments of the present disclosure are shown respectively.

[0050] Figures 30 to 33 Demonstrates the transmission of multiple packets according to embodiments of this disclosure;

[0051] Figure 34 A block diagram illustrating a modulator according to an embodiment of the present disclosure;

[0052] Figure 35 and 36 A block diagram of a demodulator according to an embodiment of the present disclosure is shown;

[0053] Figure 37 A flowchart illustrating an embodiment method for receiving packets according to an embodiment of the present disclosure;

[0054] Figure 38 A flowchart illustrating an embodiment method for generating a frequency hopping sequence according to an embodiment of the present disclosure;

[0055] Figure 39 and 40 A flowchart illustrating an embodiment method for packet switching according to embodiments of the present disclosure;

[0056] Figure 41 A communication system according to an embodiment of the present disclosure is shown;

[0057] Figure 42 and 43 A flowchart illustrating an embodiment method for packet switching according to embodiments of the present disclosure;

[0058] Figure 44 Symbol transmission of a communication system according to an embodiment of the present disclosure is illustrated; and

[0059] Figure 45 and 46 A communication system according to an embodiment of the present disclosure is shown.

[0060] Unless otherwise stated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the preferred embodiments, and the figures are not necessarily drawn to scale. Detailed Implementation

[0061] The formation and use of the disclosed embodiments are discussed in detail below. However, it should be understood that this disclosure provides many applicable inventive concepts that may be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of particular ways of forming and using this disclosure and do not limit the scope of this disclosure.

[0062] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments based on the description. Embodiments may be obtained without one or more specific details or with other methods, components, materials, etc. In some cases, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiment" in this description indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear in different places in this specification do not necessarily refer exactly to the same embodiment. Furthermore, specific forms, structures, or features may be combined in any suitable manner in one or more embodiments.

[0063] The following description uses examples for illustration to describe several aspects of this disclosure. It should be understood that many specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the order of actions or events shown, as some actions may occur in a different order and / or simultaneously with other actions or events.

[0064] Embodiments of this disclosure are described in a specific context, such as wireless communication systems and methods based on long-range OFDM, for example, applicable to Internet of Things (IoT) devices. In some embodiments, long-range OFDM modulation provides a good trade-off between long distance (e.g., link budget > 150 dB), network capacity (e.g., multi-code access), and being a standardized solution that eliminates the need for expensive central nodes and operator subscriptions of other protocols. Long-range OFDM also allows for good utilization of the time / frequency grid. Some embodiments can be used in short-range wireless communication systems. Some embodiments may not be OFDM-based and may rely on other schemes, such as non-orthogonal FDM.

[0065] Some embodiments may operate in one or more frequency bands below 1 GHz (e.g., between 470 MHz and 925 MHz). As an alternative to or supplement to one or more frequency bands below 1 GHz, some embodiments may operate in frequency bands above 1 GHz, such as 2.4 GHz, 5 GHz, 6 GHz, 7 GHz or higher, such as 60 GHz or higher.

[0066] Some embodiments can be implemented in or for IoT devices, such as in or for sensor devices that collect and transmit the sensed data, and / or for devices used for (e.g., remotely) controlling another device. In some embodiments, such IoT devices are battery-powered (and may not be powered by mains power). In some embodiments, such IoT devices may be battery-free (e.g., implemented using a small battery) or battery-independent (implemented without a battery), and may use energy harvesting methods (e.g., backscattering) to harvest energy.

[0067] Some embodiments may be implemented in or for devices that may not be considered IoT devices.

[0068] Some embodiments may be implemented in or for devices powered by mains electricity.

[0069] Some embodiments can be used in applications such as asset management, or applications for monitoring / tracking assets. For example, in some embodiments, a device (e.g., an IoT device) can be attached to an asset (e.g., a tool, package, truck, etc.) and transmit location and / or other information / data to a receiver.

[0070] Some embodiments can be used for applications such as agriculture, for example, for monitoring / tracking cattle, soil conditions, etc. For instance, in some embodiments, the device may be attached to a cattle and transmit its location and / or other information / data (e.g., health status, etc.) to a receiver. As another example, in some embodiments, the device may sense soil conditions (e.g., moisture, etc.) and transmit this sensed data to a receiver.

[0071] Some embodiments can be used for applications such as smart cities. For example, in some embodiments, the device can monitor / track the status of parking spaces and transmit this information / data to a receiver (e.g., to allow drivers to find an available parking space). As another example, in some embodiments, the device can be used to receive control signals and control streetlights based on the received signals.

[0072] Some embodiments can be used in metering applications. For example, in some embodiments, the device can monitor / track one or more parameters associated with electricity, water, and / or gas usage. The device can then transmit the sensed data to a receiver.

[0073] In embodiments of this disclosure, a seed value is selected based on a synchronization sequence associated with the packet (e.g., a short training field), which is used to select a frequency hopping sequence for wireless data transmission (e.g., transmission of the long training field, header field, and / or payload field of the packet).

[0074] In some embodiments, the seed value is selected based on which sub-channel the synchronization sequence is transmitted. In some embodiments, the seed value is selected based on one or more bits of the synchronization sequence.

[0075] In some embodiments, the frequency hopping sequence is determined based on a seed value and one or more coefficients. In some such embodiments, the seed value and / or one or more coefficients are changed for each group.

[0076] In some embodiments, using different frequency hopping sequences can advantageously reduce the probability of collisions between different transmitters, which can advantageously allow multiple independent networks to coexist and use the same available subchannel in the same geographical area, for example, for long-distance transmission. Using different frequency hopping sequences can also advantageously allow a transmitter to serve multiple receivers (e.g., independently) (e.g., using different synchronization sequences, synchronization channels, and / or frequency hopping sequences for each receiver).

[0077] Generally, frequency division multiplexing (FDM) transmitters encode information across multiple frequency bands and combine signals from these bands for transmission. FDM systems offer high throughput compared to some other communication systems. However, FDM transmitters can consume significant power under peak conditions, resulting in a high peak-to-average power ratio (PAPR). For example, the SUN OFDMPHY implementation described in Chapter 20 of IEEE Std 802.15.4-2020 and incorporated herein by reference exhibits an OFDM modulation scheme with a PAPR of approximately 8 to 9 dB.

[0078] In one embodiment, a transmitter using an OFDM-based channel arrangement (e.g., with frequency-overlapping sub-channels) can encode information / data in only one sub-channel at a time, which can result in a reduced PAPR (e.g., a PAPR closer to one) compared to conventional OFDM systems. A reduced PAPR can advantageously lead to higher data throughput (e.g., more bits per second) compared to systems with a higher PAPR. In some embodiments, a reduced PAPR can be advantageous for long-distance transmission.

[0079] Interference or noise experienced by a transmitter, receiver, or transceiver can be classified as vertical interference and horizontal interference. In instances of vertical interference, the transmitter, receiver, or transceiver experiences short bursts of interference that affect all frequencies used by the transmitter, receiver, or transceiver. In instances of horizontal interference, the transmitter, receiver, or transceiver experiences narrowband interference that affects some, but not all, frequency bands in which the transmitter, receiver, or transceiver operates.

[0080] In some embodiments, the transmitter may use techniques such as direct sequence spread spectrum (DSSS) to spread information / data across time. By spreading information / data across time, some embodiments may advantageously be more robust and resilient to vertical interference (e.g., brief energy bursts that may briefly interfere with or otherwise render one or more (or all) communication channels available to the transmitter unavailable). Additionally, in some embodiments, DSSS spreading may advantageously provide redundancy for low sensitivity. Therefore, in some embodiments, transmitting information / data spread across time may advantageously facilitate long-distance transmission.

[0081] Instead of DSSS or other than DSSS, some embodiments may use other spread spectrum techniques, such as frequency hopping spread spectrum (FHSS), time hopping spread spectrum (THSS), linear frequency modulation spread spectrum (CSS), and / or a combination of two or more of DSSS, FHSS, THSS and CSS.

[0082] In some embodiments, the transmitter may use techniques such as single-carrier frequency division multiple access (SC-FDMA) to spread information across multiple frequency bands. By spreading information / data across frequencies, some embodiments may advantageously be more robust and resilient to horizontal interference (e.g., temporary or permanent unavailability of one or more communication channels available to the transmitter (e.g., due to interference, noise, or other factors that may render the communication channels unavailable)). In some embodiments, single-carrier OFDM has no backoff and its PAPR is zero dB, creating an orthogonal time / frequency grid, and / or using a set of pseudo-random codes that provide code diversity between nodes and the network. Therefore, in some embodiments, transmitting information / data spread across frequencies can advantageously facilitate long-distance transmission.

[0083] In some embodiments, the transmitter may use error correction techniques, such as forward error correction (FEC), which advantageously allows the receiver to recover corrupted data. By enabling error detection and correction, in some embodiments, the receiver can reconstruct the received data even when the received data is partially incomplete (e.g., due to packet loss, for example, due to the temporary unavailability of one or more (or all) channels, and / or due to the permanent unavailability of one or more channels). Therefore, in some embodiments, transmitting information / data with error correction capabilities can advantageously facilitate long-distance transmission.

[0084] In some embodiments, the transmitter may use a cyclic prefix to repeat all (or a portion) of each symbol (e.g., before or after transmitting each symbol), which can advantageously introduce additional transmission redundancy. Therefore, in some embodiments, transmitting information / data with a cyclic prefix can advantageously facilitate long-distance transmission.

[0085] In some embodiments, the transmitter may add guard intervals between symbols, which can advantageously reduce inter-symbol interference between adjacent symbols. Therefore, in some embodiments, transmitting symbols with guard intervals between symbols can advantageously facilitate long-distance transmission.

[0086] In some embodiments, the transmitter may transmit symbols in pairs, with each pair of symbols transmitted in a single sub-channel, and each symbol in each pair being differentially encoded (e.g., using binary phase shift keying (BPSK)). By transmitting a pair of differentially encoded symbols (e.g., using BPSK) in a single sub-channel, in some embodiments, the pair of symbols shares a common phase reference, which advantageously allows for successful decoding without the need for precise channel equalization. Furthermore, in some embodiments, BPSK can provide a good demodulation signal-to-noise ratio.

[0087] Instead of BPSK or other digital modulation techniques, some embodiments may use other digital modulation techniques, such as frequency shift keying (FSK), Gaussian FSK (GFSK), amplitude shift keying (ASK), quadrature amplitude modulation (QAM), amplitude shift phase shift keying (APSK), continuous phase modulation (CPS), minimum frequency shift keying (MSK), on / off keying (OOK), and / or combinations of two or more of PSK, GFSK, BPSK, FSK, ASK, QAM, APSK, CPS, MSK, and OOK.

[0088] In some embodiments, each pair of symbols is transmitted in a corresponding subchannel selected according to the frequency hopping sequence. In some embodiments, using different frequency hopping sequences can reduce the probability of collisions between different transmitters operating according to different frequency hopping sequences, which can advantageously allow multiple independent networks to coexist and use the same available subchannel in the same geographical area, for example, for long-distance transmission.

[0089] In some embodiments, a synchronization sequence is used to transmit a seed indicating the frequency hopping sequence from the transmitter to the receiver. Therefore, in some embodiments, a transmitter can independently serve multiple receivers. In some embodiments, multiple transmitters can independently serve multiple receivers, each using a different frequency hopping sequence, for example, for long-distance transmission.

[0090] In some embodiments, the synchronization sequence is transmitted (e.g., globally) in a single (e.g., predetermined) sub-channel. Therefore, in some embodiments, a (e.g., low-power) receiver (such as an IoT device) may periodically switch from a low-power mode to a high-power mode to listen to the predetermined sub-channel. Upon detecting the synchronization sequence, the receiver may initiate frequency hopping according to a frequency hopping sequence based on the synchronization sequence for transmitting and / or receiving data. Thus, in some embodiments, using a single predetermined sub-channel to transmit the synchronization sequence advantageously allows the receiver to have low power consumption (e.g., because the receiver monitors a single sub-channel within a predetermined time window, rather than scanning multiple sub-channels).

[0091] In some embodiments, multiple independent networks can advantageously coexist and use the same available sub-channel in the same geographical area by transmitting corresponding synchronization sequences in the respective (different) sub-channels.

[0092] Figure 2 A communication system 200 according to an embodiment of the present disclosure is shown. The communication system 200 includes wireless devices 202 and 252 that communicate via a network 210.

[0093] In some embodiments, communication between device 202 and device 252 may be symmetrical. Therefore, in some embodiments, the method for transmitting data from device 202 to device 252 and receiving data from device 202 by device 252 may be similar to or the same as the method for transmitting data from device 252 to device 202 and receiving data from device 252 by device 202. Although some features of some embodiments may be described with respect to a particular device (e.g., 202 / 252), such features may equally apply to other devices (e.g., 252 / 202).

[0094] In some embodiments, device 202 may be an access point (AP) that connects to another network (e.g., an intranet, the Internet, etc.) via a wired or wireless protocol, while device 252 may be an IoT device, such as an IoT sensor. In some embodiments, devices 202 and 252 may each be an IoT device, such as an IoT sensor. In some embodiments, devices 202 and 252 may each be an AP device that connects to another network (e.g., an intranet, the Internet, etc.) via a wired or wireless protocol.

[0095] For clarity, many embodiments are described as assuming that device 202 is an AP device and device 252 is an IoT sensor device. However, it should be understood that the illustrated features and inventive concepts are equally applicable to embodiments in which device 202 is not an AP (e.g., is an IoT device, or a non-IoT device that is not an AP) and / or device 202 is not an IoT sensor device (e.g., is a non-sensor IoT device, an AP device, or another device that is not considered an AP device or an IoT device).

[0096] In some embodiments, device 252 may enter a low-power mode between (e.g., periodic) data transmissions and may operate in a high-power mode during data transmissions. In some embodiments, device 252 may not enter a low-power mode between data transmissions.

[0097] In some embodiments, device 252 may use a pure ALOHA media access scheme or a similar scheme, while device 202 is in a continuous listening mode (e.g., not entering a low-power mode). In some such embodiments, device 252 may transmit packets to device 202 and then immediately switch to receiver mode to receive acknowledgments (ACKs) from device 202. Therefore, in some embodiments, device 252 may be in idle / low-power mode most of the time and consume power only when device 252 needs to transmit data and then receive the corresponding ACK. This mechanism can be understood as half-duplex.

[0098] In some embodiments, device 202 may enter a low-power mode between (e.g., periodic) data transmissions and may operate in a high-power mode during data transmissions. In some embodiments, device 202 may not enter a low-power mode between transmissions.

[0099] In some embodiments, device 252 may send one or more packets (e.g., containing sensor data and / or commands) to device 202 at any time (e.g., synchronously or asynchronously); device 202 may receive one or more such packets. In response, device 202 may transmit one or more packets (e.g., containing ACKs, commands, and / or data) to device 252, which may listen for one or more such packets. In some such embodiments, device 252 may enter a low-power mode between transmissions, while device 202 may not enter a low-power mode between transmissions. In other such embodiments, one of devices 202 and 252 may enter a low-power mode between transmissions, while the other of devices 202 and 252 may not enter a low-power mode between transmissions. In still other such embodiments, neither device 202 nor 252 enters a low-power mode between transmissions.

[0100] In some embodiments, device 202 may transmit one or more packets (e.g., synchronously or asynchronously) to device 252 without responding to packets received from device 252. In some such embodiments, device 252 may periodically wake up from a low-power mode to listen for, for example, communications from device 202. In other such embodiments, device 252 may not enter a low-power mode between transmissions and may continuously listen for one or more such packets.

[0101] During normal operation, device 202 wirelessly transmits first data to device 252 via RF core 204 and antenna 208. Device 252 receives the first data and then decodes and processes it. Device 252 may then wirelessly transmit second data to device 202 (or wirelessly transmit to...) via RF core 254 and antenna 258. Figure 2 (Another device not shown in the image).

[0102] In some embodiments, devices 202 and 252 may be separated by a relatively large distance, such as 1 km, 2 km, 10 km, 15 km or more. In some embodiments, devices 202 and 252 may be separated by a distance shorter than 1 km, such as 500 m, 100 m, 30 m, 10 m, 5 m, 1 m or less.

[0103] In some embodiments, device 202 and / or device 252 may be mobile devices and may move during data transmission (such that the distance between devices 202 and 252 may change dynamically). In some embodiments, device 202 and / or device 252 may be in a fixed position during data transmission.

[0104] In some embodiments, device 252 may include sensors, such as temperature sensors, humidity sensors, position sensors, vibration sensors, etc. In some such embodiments, device 252 may wirelessly transmit data to device 202 based on sensed data detected by the sensors.

[0105] In some embodiments, device 202 may operate another device in response to data received from device 202. Figure 2(Not shown) or based on received data, causing action in another device. In some embodiments, the other device includes a motor, speaker, microphone, solenoid, (e.g., LED) light, solar cell, battery, radar, memory, and / or one or more other electronic circuits, such as processor, power management circuitry, etc. In some embodiments, device 252 may, in response to data received from device 202, cause to start, stop, or change the mode of energy harvesting; activate, deactivate, or change the operation of a motor, solenoid, or light; store data to / erase / modify data from memory; play or stop playing sound; start or stop recording data using sensors (e.g., microphone, humidity sensor, temperature sensor, etc.); activate, deactivate, or change the operation of radar; change the operation of electronic circuitry of another device coupled to device 252, etc.

[0106] like Figure 2 As shown, device 202 includes RF core 204 and controller 206; and device 252 includes RF core 254 and controller 256.

[0107] In some embodiments, RF core 204 implements at least part (or all) of the physical (PHY) layer and data link layer (e.g., MAC layer) of wireless protocol 212 for communication via network 210, while controller 206 implements higher layers (e.g., network layer, transport layer, session layer, presentation layer, and / or application layer). In some embodiments, controller 206 may implement all data link layers of wireless protocol 212. In some embodiments, controller 206 may implement at least part of the PHY layer of wireless protocol 212. Other embodiments are also possible.

[0108] In some embodiments, RF core 204 is configured to assemble bits in a given grouping structure for transmission using antenna 208.

[0109] In some embodiments, the RF core 204 supports multiple modulation formats, including (e.g., multi-order) GFSK and MSK, OOK, BPSK and CSS, etc.

[0110] In some embodiments, RF core 204 has dedicated processing accelerators, for example, for forward error correction, data whitening, and / or automatic cyclic redundancy check (CRC). In some embodiments, RF core 204 includes additional accelerators. In some embodiments, RF core 204 does not include any hardware accelerators.

[0111] In some embodiments, RF core 204 includes a wireless transceiver having a transmission path and a reception path coupled to antenna 208. In some embodiments, the transmission path includes a power amplifier having an output coupled to antenna 208. In some embodiments, the reception path includes a low-noise amplifier having an input coupled to antenna 208. In some embodiments, RF core 204 includes one or more analog-to-digital converters (ADCs), one or more digital-to-analog converters (DACs), one or more mixers, combiner circuitry (e.g., parallel-to-serial circuitry) and / or splitter circuitry (e.g., serial-to-parallel circuitry), (e.g., digital) phase-locked loops (PLLs), modems, read-only memory (ROM), random access memory (RAM) (e.g., SRAM), one or more filters, and / or one or more amplifiers to facilitate wireless transmission and reception of data using antenna 208.

[0112] In example Figure 2 In some embodiments shown, a single antenna 208 is used for data transmission and reception. In some embodiments, more than one antenna may be used for data transmission and reception (e.g., one or more antennas may be used for transmission, while one or more other antennas may be used for reception).

[0113] In some embodiments, the controller 206 may generate or cause the generation of data to be wirelessly transmitted by the RF core 204 via the antenna 208, and / or may process data received by the RF core 204 via the antenna 208.

[0114] In some embodiments, controller 206 may be implemented as, for example, a general-purpose or custom controller, processor, or processing core coupled to and configured to execute instructions in that memory. In some embodiments, controller 206 may be implemented using a field-programmable gate array (FPGA). In some embodiments, controller 206 includes a state machine. Other embodiments are also possible.

[0115] In some embodiments (e.g.) Figure 2 As shown in the figure, the controller 206 may be external to the RF core 204. In some embodiments, the controller 206 may be implemented partially or entirely inside the RF core 204.

[0116] In some embodiments, the RF core 204 and controller 206 may be implemented in a single monolithic semiconductor substrate. In some embodiments, the RF core 204 and controller 206 may be implemented in different dies within a single package. In some embodiments, the RF core 204 and controller 206 may be discrete integrated circuits implemented on a printed circuit board (PCB). Other embodiments are also possible.

[0117] like Figure 2As shown, the RF core 204 can be coupled to the antenna 208. In some embodiments, the antenna 208 is external to the package containing the RF core 204. In some embodiments, the antenna 208 is implemented in the same package as the RF core 204.

[0118] In some embodiments, RF core 254 may be implemented in a similar or identical manner to RF core 204. In some embodiments, controller 256 may be implemented in a similar or identical manner to controller 206. In some embodiments, device 252 may be implemented in a similar or identical manner to device 202.

[0119] In some embodiments, devices 202 and 252 may be examples of the same design. Therefore, in some embodiments, devices 202 and 252 may operate using similar or identical configurations. In some embodiments, although devices 202 and 252 may be similar or identical in design, they may operate with different configurations (e.g., they may be programmed into such devices in response to communications via network 210, by the manufacturer of devices 202 and / or 252, and / or by the user of devices 202 and / or 252 (e.g., not via network 210)).

[0120] Figure 3 A schematic diagram of an RF core 300 according to an embodiment of the present disclosure is shown. RF cores 204 and / or 254 may be implemented as RF core 300.

[0121] The RF core 300 includes a PLL 306, a transmitter path 310, and a receiver path 320. The transmitter path 310 includes a DAC 311, a preamplifier 312, a mixer 314, an analog filter 316, and a power amplifier 318. The receiver path 320 includes a low-noise amplifier (LNA) 322, a mixer 324, an intermediate frequency (IF) amplifier 326, an analog filter 328, and an ADC 330.

[0122] In some embodiments, during normal operation, when the RF core 300 is in transmit mode, the transmitter path 310 receives a TX modulated signal from the modulator 302 for wireless transmission via the antenna 308. In some embodiments, when the RF core 300 is in receive mode, the receiver path 320 generates an RX modulated signal based on the signal received from the antenna 308 and provides the RX modulated signal to the demodulator 304 for further processing.

[0123] In some embodiments, antenna 308 is coupled to amplifiers 318 and 322 via a duplexer (not shown).

[0124] In some embodiments, the RF core 300 further includes a modulator 302 and / or a demodulator 304. In some embodiments, the modulator 302 and / or demodulator 304 includes, for example, a general-purpose or custom controller, processor, or processing core coupled to and configured to execute instructions in that memory, or may be implemented using said general-purpose or custom controller, processor, or processing core. In some embodiments, the modulator 302 and / or demodulator 304 includes a field-programmable gate array (FPGA) or may be implemented using a field-programmable gate array (FPGA). In some embodiments, the modulator 302 and / or demodulator 304 includes a state machine. In some embodiments, the modulator 302 and / or demodulator 304 includes or may be implemented as one or more hardware accelerators. Other embodiments are also possible.

[0125] In some embodiments, modulator 302 and / or demodulator 304 are external to RF core 300 (e.g., they are part of a controller (e.g., 206, 256) external to RF core 300).

[0126] In some embodiments, analog filters 276 and / or 288 comprise low-pass or band-pass filters and may have programmable gain. Elements 306, 312, 314, 316, 318, 322, 324, 326, 328, and 330 may be implemented in any manner known in the art.

[0127] In some embodiments, modulator 302 generates a digital signal (TX modulated signal) to be transmitted via transmitter path 310 through antenna 308. In some embodiments, modulator 302 includes a DAC for converting this digital signal into a corresponding modulated analog signal provided to the input of preamplifier 312. In some embodiments, this DAC is external to modulator 302 and may be part of transmitter path 310 (e.g., Figure 3 (As shown in the image).

[0128] In some embodiments, demodulator 304 processes the digital signal (RX modulated signal) received by ADC 330 from receiver path 320.

[0129] Figure 4 A block diagram of a processing pipeline 400 for generating a TX modulated signal for wireless transmission, according to an embodiment of the present disclosure, is shown. The processing pipeline 400 may be implemented by a modulator 302 (e.g., using dedicated circuitry, such as a hardware accelerator, in part or in whole; and / or by executing instructions stored in memory in part or in whole).

[0130] Processing pipeline 400 includes a scrambler block 402, an FEC block 404, an interleaver block 406, a DSSS block 408, a bit-to-symbol block 410, a single subcarrier mapper block 412, an inverse transform 414, a cyclic prefix block 416, and a digital filter block 418. In some embodiments, one or more blocks of processing pipeline 400 may be omitted, or additional blocks (not shown) may be executed. In some embodiments, different portions of a packet are processed by different blocks (e.g., some portions of a packet may be scrambled, while others may not). Other embodiments are also possible.

[0131] During normal operation, packets 401 to be wirelessly transmitted via antenna 308 (e.g., using wireless protocol 212) may be received by processing pipeline 400. For example, in some embodiments, a payload is received (e.g., from the data link layer) and (e.g., by the PHY layer) packets 401 are created, for example, by adding headers and / or other fields to the payload.

[0132] In some embodiments, the processing pipeline 400 receives (e.g., sequentially) a plurality of packets 401 to be transmitted. The processing pipeline 401 may process each of the plurality of packets 401 sequentially, in parallel, and / or in a pipelined manner.

[0133] In some embodiments, scrambler 402 scrambles the bits of packet 401 to produce a scrambled bit stream. By scrambling the bits of the packet, some embodiments can advantageously improve signal quality (e.g., by preventing long sequences of 0s or 1s) and increase transmission security.

[0134] In some embodiments, the FEC encoder 404 modifies the scrambled bitstream to produce an FEC bitstream that allows for error detection and correction. The use of FEC can advantageously allow for the recovery of data affected by horizontal or vertical interference.

[0135] In some embodiments, interleaver block 406 interleaves the bits of the FEC bit stream over time to produce an interleaved bit stream. By interleaving the bits to be transmitted, some embodiments advantageously improve the robustness of data transmission against vertical interference by spreading the data over time.

[0136] In some embodiments, DSSS block 408 encodes, for example, each bit of an interleaved bit stream into multiple bits (also referred to as chips). By adding redundancy through DSSS, some embodiments advantageously increase resistance to horizontal and vertical interference and jamming, and improve signal reliability. For example, in some embodiments, RF core 300 (e.g., demodulator 304, e.g., processing pipeline 500 or 600) or associated controller (e.g., 206, 256) may be able to identify bits in a received signal (e.g., an RX modulated signal) even if a chip associated with that bit is corrupted by interference. For example, a short burst of interference may corrupt a chip, but the receiver can evaluate adjacent chips to identify the true value of the corrupted bit.

[0137] In some embodiments, in addition to or as an alternative to DSSS, DSSS block 408 may implement other spread spectrum techniques. Further details of examples of DSSS in communication systems can be found in jointly assigned U.S. Patent Application Publication No. 2022 / 0255580, filed December 17, 2021, entitled “Frequency-Division Multiplexing”; U.S. Patent No. 9,935,681, filed April 3, 2018, entitled “Preamble Sequence Detection of Direct Sequence Spread Spectrum (DSSS) Signals”; and U.S. Patent No. 9,831,909, filed November 28, 2017, entitled “DSSS Inverted Spreading for Smart Utility Networks,” each of which is incorporated herein by reference in its entirety.

[0138] In some embodiments, bit-to-symbol block 410 converts each chip of the TX chip stream into a symbol (e.g., OFDM) to produce a symbol stream. In some embodiments, each symbol may be represented as a complex number having real and imaginary values.

[0139] In some embodiments, bit-to-symbol block 410 may use modulation processes such as quadrature amplitude modulation (QAM) (16-QAM) or phase shift keying (PSK) (e.g., binary PSK or quadrature PSK). In some embodiments, the ratio of chip to symbol representing each bit may be 1:1, 1:2, 2:1, 4:1, or any other ratio. For example, in some embodiments using BPSK, bit-to-symbol block 410 may convert each chip from DSSS block 408 into a corresponding symbol. Additional instance details of PSK and QAM can be found in commonly assigned U.S. Patent No. 9,001,948, entitled “Pulse Shaping in a Communication System,” published April 7, 2015, which is incorporated herein by reference.

[0140] In some embodiments, the single subcarrier mapping block 412 produces a mapped stream, wherein each symbol of the symbol stream is mapped to a single subcarrier signal (using only a single subchannel from the available subchannels). For example, in some embodiments, the mapped stream maps each symbol to a single input of the inverse transform block 414, thereby setting all other inputs of the inverse transform block 414 to zero. Using a single subcarrier signal each time can advantageously result in a lower PAPR and produce an RF signal that is easier for the receiver to demodulate.

[0141] Although a single subcarrier can be used each time, some embodiments change the subcarrier periodically according to a frequency hopping sequence, which can advantageously spread the signal in frequency, thereby advantageously improving robustness against horizontal interference.

[0142] In some embodiments, the inverse transform block 414 computes the inverse fast Fourier transform (IFFT) on the symbols of the mapped stream to produce an inverse transform stream containing time-domain samples of the mapped symbols.

[0143] In some embodiments, a cyclic prefix block 416 is appended to or prepended to all or a portion of each symbol in the mapped stream to produce a prefixed symbol stream. This cyclic prefix addition can advantageously serve as a guard interval, which can help reduce inter-symbol interference, a potentially important consideration in multipath environments.

[0144] In some embodiments, digital filter block 418 filters samples of a prefixed symbol stream to generate a TX modulated signal, which can be provided to transmission path 310 for wireless transmission via antenna 308.

[0145] In some embodiments, digital filter block 418 is not implemented, and the samples generated by cyclic prefix block 416 constitute the TX modulated signal to be transmitted by antenna 308. In some embodiments, blocks 416 and 418 are not implemented, and the output of inverse transform block 414 constitutes the TX modulated signal to be transmitted by antenna 308. In some embodiments, cyclic prefix block 416 is not implemented, but digital filter block 418 is implemented.

[0146] In some embodiments, one or more (or all) of blocks 402, 404, 406, 408, 410, 412, 414, 416, and 418 are configurable. For example, in some embodiments, one or more (or all) of blocks 402, 404, 406, 408, 410, 412, 414, 416, and 418 may be configured based on data received during previous communication between devices 202 and 252.

[0147] In some embodiments, the TX modulated signal is wirelessly transmitted by the transmitter path 310 of the device 202 and received as the RX modulated signal by the receiver path 320 of the device 252.

[0148] Figure 5 A block diagram of a processing pipeline 500 for processing RX modulated signals according to an embodiment of the present disclosure is shown. The processing pipeline 500 may be implemented by a demodulator 304 (e.g., using dedicated circuitry, such as a hardware accelerator; and / or by executing instructions stored in memory, in part or in part).

[0149] The processing pipeline 500 includes a digital filtering block 502, a Fourier transform block 504, a carrier extraction block 506, an inverse DSSS block 508, a deinterleaving block 510, a symbol bit-to-bit metric block 512, an FEC decoder 514, and a descrambling block 516. In some embodiments, one or more blocks of the processing pipeline 500 may be omitted, or additional blocks (not shown) may be implemented. In some embodiments, different portions of the RX modulated signal are processed by different blocks (e.g., some portions of the signal may be processed by the inverse DSSS block 508, while other portions may not be processed by the inverse DSSS block 508). Other embodiments are also possible.

[0150] During normal operation, the RX modulated signal, which can be wirelessly received via antenna 308, can be received by processing pipeline 500. In some embodiments, digital filter block 502 filters the RX modulated signal (e.g., using a low-pass filter) to produce a filtered signal.

[0151] In some embodiments, Fourier transform block 504 performs a Fourier transform (e.g., DFT, or FFT) in the opposite manner to that of inverse transform block 414, for example, after cyclic prefix removal, in order to recover the symbols generated by the single subcarrier mapping block 412.

[0152] In some embodiments, the carrier extraction block 506 processes the Fourier transform stream generated by the Fourier transform block 504 to determine a single carrier frequency containing symbols, and generates an RX chip symbol stream, for example, based on a frequency hopping sequence associated with an RX modulated signal, the RX chip symbol stream having symbols based on, for example, phase, frequency and / or modulation detected on the carrier signal.

[0153] In some embodiments, the inverse DSSS block 508 uses the redundancy introduced by the DSSS block 408 to generate a symbol metric stream, wherein each symbol metric in the symbol metric stream indicates the likelihood of a symbol corresponding to a plurality of associated chips.

[0154] In some embodiments, deinterleaver block 510 deinterleaves the symbolic metric stream (e.g., in the opposite manner to interleaver block 406) to produce a deinterleaved symbolic metric stream.

[0155] In some embodiments, the symbol-to-bit metric block 512 converts the deinterleaved symbol metric stream into a bit metric stream (e.g., in the opposite manner to the bit-to-symbol block 410), wherein each bit of the metric stream indicates the likelihood of the received bit.

[0156] In some embodiments, the FEC decoder block 514 performs error correction on the bit metric stream to identify and correct any correctable errors in order to produce an error-corrected bit stream.

[0157] In some embodiments, descrambler block 516 descrambles the error-corrected bitstream (e.g., in the opposite manner to scrambler block 402) to produce reconstructed packets 501.

[0158] In some embodiments, when reconstruction is successful, reconstructed group 501 may be identical to group 401. In some embodiments, reconstructed group 501 may include some, but not all, of the fields of group 401. For example, in some embodiments, synchronization fields (e.g., short training fields) that may be part of group 401 may not be part of reconstructed group 501. In some embodiments, reconstructed group 501 may include only the payload (e.g., the same payload as group 401), while omitting all other fields.

[0159] In some embodiments, the processing pipeline 500 processes the RX modulated signal (e.g., continuously, for example, within a predetermined time period) such that when X packets 401 are transmitted (e.g., by device 202), the processing pipeline 500 (e.g., by device 252) generates X reconstructed packets.

[0160] In some embodiments, one or more (or all) of blocks 502, 504, 506, 508, 510, 512, 514, and 516 are configurable. For example, in some embodiments, one or more (or all) of blocks 502, 504, 506, 508, 510, 512, 514, and 516 may be configured based on data received during previous communication between devices 202 and 252.

[0161] For example Figure 5 Some embodiments shown in the diagram can perform inverse DSSS and deinterleaving steps on a metric basis, which can advantageously allow for improved error rates, possibly due to noise and other artifacts exhibited by the RX chip symbol stream (e.g., a symbol may have crossed the boundaries of other symbols). Other implementations are also possible. For example, Figure 6 A block diagram of a processing pipeline 600 for processing RX modulated signals according to an embodiment of the present disclosure is shown. The processing pipeline 600 may be implemented by a demodulator 304 (e.g., using dedicated circuitry, such as a hardware accelerator, in part or in whole; and / or by executing instructions stored in memory in part or in whole).

[0162] Processing pipeline 600 operates in a similar manner to processing pipeline 500 and can produce reconstructed packets 501 that are identical to those produced by processing pipeline 500. However, processing pipeline 600 performs symbol bit-shifting (block 602) before performing the inverse DSSS (block 604) and deinterleaving steps (block 606). Other implementations are also possible.

[0163] Figure 7 A schematic diagram of a scrambler 700 according to an embodiment of the present disclosure is shown. Scrambler block 402 may be implemented as scrambler 700. Scrambler 700 includes a pseudo noise (PN) generator 720 and an XOR gate 730. PN generator 720 includes a plurality of flip-flops (FFs) 722 and an XOR gate 724. In some embodiments, PN generator 720 is loaded / initialized using a seed (e.g., all one—111111111) and timed using the seed as a starting point, and is enabled after a first clock cycle.

[0164] During normal operation, XOR gate 730 receives an input bit stream (e.g., bits from block 401) and an output PN from PN generator 720. outTo generate a scrambled potential flow.

[0165] like Figure 7 As can be seen, in some embodiments, the scrambled bits are obtained by XORing each of the input bits with the output (PNout) of the PN generator, for example, as follows:

[0166] (1)

[0167] Figure 8 A schematic diagram of a descrambler 800 according to an embodiment of the present disclosure is shown. Descrambler block 516 may be implemented as descrambler 800.

[0168] In some embodiments, the descrambler 800 may be implemented in the opposite manner to the scrambler 700. For example, such as Figure 8 As shown, in some embodiments, the descrambler 800 includes the same PN generator 720 as the scrambler 700 (initialized in the same manner), and provides the PNout of this generator 720 to the XOR gate 802, wherein another input of the XOR gate receives the scrambled bit stream, and the output of the XOR gate 802 produces the descrambled bit stream.

[0169] Figure 9 A block diagram of an FEC encoder 900 according to an embodiment of the present disclosure is shown. An FEC encoder block 404 may be implemented as an FEC encoder 900. The FEC encoder 900 includes an encoder 902.

[0170] During normal operation, encoder 902 performs forward error correction by performing convolutional coding, channel coding, and / or polarization coding on the input bit stream (e.g., from XOR gate 730) to produce an FEC bit stream. In some embodiments, encoder 902 uses a concatenated code that includes Reed-Solomon block code and inner half-rate convolutional code.

[0171] In some embodiments, the FEC encoder 900 receives an input bit stream as a sequence of M bits, where M is a multiple of 8. In some embodiments, M may have different values, such as higher than 8, for example 16, 32 or higher, or lower than 8, for example 4 or lower.

[0172] Figure 10 A block diagram of a convolutional encoder 1000 according to an embodiment of the present disclosure is shown. Encoder 902 may be implemented as convolutional encoder 1000.

[0173] like Figure 10As shown, the convolutional encoder 1000 may include two outputs (output data A and output data B). In some embodiments, the two outputs are then serialized to form a single FEC bitstream, which may be provided to a subsequent processing block (e.g., interleaver 406).

[0174] In some embodiments (e.g., such as) Figure 10 In the example shown, the input bits received by the convolutional encoder 1000 are written using a convolutional encoder with a write rate of R = ½. In some embodiments, the convolutional encoder uses a generator polynomial expressed in octal as g0 = 1338 and g1 = 1718. Other embodiments are also possible. For example, in some embodiments, the write rate R may be different from 1 / 2, such as 3 / 4 or different, and / or different polynomials may be used.

[0175] In some embodiments, the convolutional encoder 1000 is initialized to an all-zero state before encoding the input bits, and then reset to an all-zero state.

[0176] In some embodiments, the FEC decoder 514 may be implemented in any manner known in the art to perform error correction on a bitstream generated using the FEC encoder 900 (e.g., implementing encoder 1000).

[0177] Figure 11 A block diagram illustrating the operation of an interleaver 1100 according to an embodiment of the present disclosure is shown. Interleaver block 406 may be implemented as interleaver 1100.

[0178] like Figure 11 As can be seen, in some embodiments, the interleaver 1100 receives the input bit stream and generates an interleaved bit stream. Figure 11 In this example, the input bitstream and the interleaved bitstream each contain 16 bits (b0 to b1). 15 The interleaver 1100 rearranges the bits (e.g., b0 to b0). 15 This allows the interleaved bit stream to contain the same bits as the input bit stream, but in a different order.

[0179] In some embodiments, the interleaver 1100 operates on symbols rather than bits in a similar manner. Thus, in some embodiments, the interleaver 1100 receives an input symbol stream and produces an interleaved symbol stream, for example, in a manner similar to that described with respect to bits.

[0180] In some embodiments, the interleaver 1100 takes a sequence of Q written code bits (e.g., written by the FEC encoder 900) as input and produces a second sequence of Q interleaved bits, where Q is a positive integer, such as a positive integer multiple of M. In some embodiments (e.g.) Figure 11In the example shown, Q equals 16. In some such embodiments, M equals 8.

[0181] In some embodiments, the complete sequence of write-through code bits of length N generated by the interleaver 1100 is defined as , In some embodiments, when M equals 8, N is a multiple of 16.

[0182] In some embodiments, a set of N consecutive subsequences generated by the FEC encoder 900 can be processed by the interleaver 1100 on a first-come, first-served basis. In some embodiments, the set of consecutive subsequences can be processed in a different order.

[0183] In some embodiments, the interleaver 1100 performs the interleaving process by performing one permutation. For example, in some embodiments, such as Figure 11 As shown in the figure, the index of the written code points after the first permutation can be given by the following formula:

[0184] (2)

[0185] Where k represents the written code bits before the first permutation, F represents the factor, mod represents the modulus operation, and floor() represents the floor function. In some embodiments, F is less than M. In some embodiments, (e.g.) Figure 11 (as shown in the figure), F equals 4. In some embodiments, the interleaving process can be performed in different ways, such as by performing more than one permutation, or according to a different formula.

[0186] In some embodiments, the interleaver 1100 processes the output of the previous block (FEC encoder 404) in groups of Q bits (e.g., sequentially), such as when a group of Q bits is generated.

[0187] Figure 12 A block diagram illustrating the operation of an interleaver 1200 according to an embodiment of the present disclosure is shown. A deinterleaver block 510 or 606 may be implemented as a deinterleaver 1200.

[0188] like Figure 12 As shown, in some embodiments, the deinterleaver 1200 operates in the opposite manner to the interleaver 1100 in order to remove the interleaving effect (deinterleaving) introduced by the interleaver 1100.

[0189] Figure 13 A block diagram of a DSSS modulator 1300 according to an embodiment of the present disclosure is shown. DSSS block 408 is implemented as DSSS modulator 1300.

[0190] In some embodiments, the DSSS modulator 1300 receives an input bit stream and generates a bit sequence based on each bit of the input bit stream. Each bit in the generated bit sequence may be referred to as a chip.

[0191] The number of chips generated for each input bit can be controlled by the DSSS value. For example, a DSSS value of 2 will generate 2 chips per input bit. Similarly, a DSSS value of 4 will generate 4 chips per input bit.

[0192] In some embodiments, the DSSS value may be a power of 2 (e.g., 2, 4, 8, 16, 32, 64, etc.). In some embodiments, the DSSS value may not be a power of 2 (e.g., 6, 10, 24, etc.). In some embodiments, the DSSS value may be an even number.

[0193] In some embodiments, the DSSS value of the DSSS modulator 1300 is programmable and can be dynamically changed, for example, based on the portion of a packet (e.g., 401) being processed.

[0194] In some embodiments, the DSSS value may be selected from a set of DSSS values ​​that are powers of 2 (e.g., 2, 4, 8, 16). In some embodiments, the DSSS value may be selected from a set of DSSS values ​​that may include values ​​that are powers of 2 and values ​​that are not powers of 2 (e.g., 2, 4, 6, 8, 12; 2, 4, and 6; or, for example, 2, 4, 8, 12). In some embodiments, the DSSS value may be selected from a set of DSSS values ​​that includes only values ​​that are not powers of 2 (e.g., 6, 12).

[0195] In some embodiments, the DSSS value of the DSSS modulator 1300 is fixed. For example, in some embodiments, the DSSS value may be a predetermined value built into the communication device (e.g., 202 or 252). In some embodiments, a user may be able to set the DSSS value such that the communication device selects (e.g., a fixed) DSSS value based on user input.

[0196] The generated chip sequence for each bit can be associated with a specific polarity. For example, when the DSSS modulator 1300 operates with a DSSS value of 2 and a dipole polarity, input bit 1 can be represented by the chip sequence [0 0], and input bit 0 can be represented by the chip sequence

[01] . When the DSSS modulator 1300 operates with a DSSS value of 2 and an odd polarity, input bit 1 can be represented by the chip sequence [1 1], and input bit 0 can be represented by the chip sequence [1 0].

[0197] In some embodiments, the polarity of the chip sequence is programmable and can be dynamically changed, for example, based on the portion of a packet (e.g., 401) being processed, switching every predetermined number of input bits being processed (e.g., each input bit, every two input bits, etc.) and / or every packet (e.g., the first packet starts with an even polarity and the subsequence packets start with the other polarity) or every predetermined number of packets. For example, the DSSS modulator 1300 can alternate between even and odd spread spectrum, for example, based on which portion of packet 401 is being processed, and can use only even spread spectrum or only odd spread spectrum.

[0198] In some embodiments, the DSSS modulator 1300 may switch between even and odd spreading, for example, to avoid multiple repetitions of the same sequence. For instance, the DSSS modulator 1300 may switch between even and odd spreading after each input bit or after a specific number of input bits. For example, in some embodiments, the DSSS modulator 1300 may generate a first even chip spreading representing a first input bit, and then generate a second odd chip spreading representing the next input bit. Thus, in some embodiments using a DSSS value equal to 2, if three consecutive input bits have a logic value of 1, the transmitter may generate an even spreading 00 representing the first input bit, an odd spreading 11 representing the second input bit, and an even spreading 00 representing the third input bit. Therefore, even if three consecutive input bits may have the same logic value, the chip logic value representing the first input bit may be the opposite of the chip logic value representing the second input bit. The chip logic value representing the first input bit is the same as the chip logic value representing the third input bit, but different from the chip logic value representing the second input bit.

[0199] In some embodiments, the polarity of the chip sequence is fixed. For example, in some embodiments, the polarity may be a predetermined value built into the communication device (e.g., 202 or 252). In some embodiments, a user may be able to set the polarity such that the communication device selects (e.g., a fixed) polarity based on user input.

[0200] In some embodiments, transmitting multiple chips or symbols for each bit can advantageously improve robustness and redundancy, for example, by spreading each bit across time and possibly across frequencies (e.g., in embodiments using frequency hopping). For instance, if a chip is corrupted, a receiver with low sensitivity may still be able to extract the value of the bit by evaluating the remaining chips in the sequence representing the bit.

[0201] Figure 14 Chip sequences for different DSSS values ​​and polarities are shown according to embodiments of the present disclosure. The DSSS modulator 1300 can be configured according to... Figure 14One or more tables shown convert input bits into chips. In some embodiments, the DSSS modulator 1300 can... Figure 14 The two or more tables shown are implemented as selectable sets (e.g., based on selected DSSS values ​​and / or polarities).

[0202] Figure 14 This demonstrates one possible way to spread the input bits into a chip sequence. Other implementations are also possible. For example, Figure 15 Chip sequences for different DSSS values ​​and polarities are shown according to embodiments of the present disclosure. The DSSS modulator 1300 can be configured according to... Figure 15 One or more tables shown convert input bits into chips. In some embodiments, the DSSS modulator 1300 can... Figure 15 The two or more tables shown are implemented as selectable sets (e.g., based on selected DSSS values ​​and / or polarities).

[0203] As in Figure 14 and 15 As can be seen, specific DSSS values ​​and polarities may correspond to different chip sequences, for example, depending on the specific implementation. For instance, in some embodiments, for an input bit equal to 1, each corresponding pair of chips has the same chip value, and for an input bit equal to 0, each corresponding pair of chips has a different chip value (although the order of the chip values ​​may be implemented differently, e.g., ...). Figure 14 and 15 (As shown in the diagram). Other implementation schemes are also possible.

[0204] like Figure 14 and 15 As shown, in some embodiments, each input bit can be converted into a chip sequence. In some embodiments, multiple input bits can be converted into chip sequences, wherein the input sequences have a length r (r > 1) and the corresponding chip sequences have a length s (s > r). For example, some embodiments implement 2-to-8 DSSS, which converts two bits into an eight-chip sequence. In some such embodiments, each pair of two input bits may have four possible values, each of which is associated with at least one unique eight-chip sequence. As other examples, some embodiments may implement 2-to-6-bit DSSS and / or 4-to-6-bit DSSS for communication devices implementing DSSS. Other implementations are also possible.

[0205] In some embodiments, the N-bit input sequence input to the DSSS modulator 1300 is converted into an N×(DSSS value) binary chip sequence.

[0206] Figure 16A block diagram of a DSSS demodulator 1600 according to an embodiment of the present disclosure is shown. Inverse DSSS blocks 508 and 604 may be implemented as the DSSS demodulator 1600.

[0207] like Figure 16 As shown, the DSSS demodulator 1600 can operate using symbols (e.g., as in inverse DSSS block 508) or bits (e.g., as in inverse DSSS block 604).

[0208] In some embodiments, the DSSS demodulator 1600 operates in the opposite manner to the DSSS modulator used to modulate packet 401 (e.g., utilizing the same DSSS value, polarity, and one or more chip conversion tables) to recover the original input bit sequence. For example, in an embodiment using a DSSS of 2 and a dipole, the input sequence 0 1 1 0 can be converted by the DSSS modulator 1300 into the chip sequence 0 0 0 1 0 1 0 0. The DSSS block 508 implementing the DSSS demodulator 1600 (which receives this bit sequence and is configured with a DSSS of 2 and a dipole) produces the despread bit sequence 0 1 1 0 (e.g., by comparing each pair of bits to determine if the bits are corrupted). As another example, the DSSS block 604 implementing the DSSS demodulator 1600 (which receives the symbol sequence S0S0S0S1S0S1S0S0 and is similarly configured) generates the despread symbol sequence S0S1S1S0, where S0 and S1 represent (e.g., OFDM) modulation symbols corresponding to bits 0 and 1, respectively.

[0209] Figure 17 A block diagram of a BPSK encoder 1700 according to an embodiment of the present disclosure is shown. A bit-to-symbol block 410 may be implemented as a BPSK encoder 1700.

[0210] In some embodiments, the BPSK encoder 1700 uses BPSK to map each input bit (e.g., each chip of the input chip stream) to a symbol, for example, according to the following BPSK encoding:

[0211]

[0212] Other implementation schemes are also possible.

[0213] In some embodiments, the symbol duration SymDur for each symbol generated by the BPSK encoder 1700 is fixed. In some embodiments, the symbol duration may be selected from a set including 120 μs, 60 μs, 30 μs, and 15 μs. Other symbol durations are also possible.

[0214] Figure 18A block diagram of a BPSK decoder 1800 according to an embodiment of the present disclosure is shown. The symbol-to-bit metric block 512 and the symbol-to-bit block 602 may be implemented as the BPSK decoder 1800.

[0215] The BPSK decoder 1800 may be implemented in a manner opposite to that of the BPSK decoder 1700 to recover the bits used by the BPSK encoder 1700 to generate symbols.

[0216] Figure 19 A block diagram of a single subcarrier mapper 1900 according to an embodiment of the present disclosure is shown. The single subcarrier mapping block 412 may be implemented as the single subcarrier mapper 1900.

[0217] In some embodiments, the single subcarrier mapper 1900 maps each symbol of an input symbol stream to a single subcarrier channel in a set of available (e.g., OFDM) channels. For example, when the subchannel selection signal CH sel indicates subchannel 0, the next symbol of the input symbol stream is mapped to subchannel 0. More generally, if a set of available channels has L, then when the channel selection signal CH sel indicates subchannel i (0 < i < L), the next symbol of the input symbol stream is mapped to subchannel i.

[0218] In some embodiments, for each time slot, the single subcarrier mapper 1900 maps a single symbol to a single subcarrier by modulating a sine wave or a cosine wave or switching between a sine wave and a cosine wave. In some embodiments, the total communication bandwidth of the RF core 300 may be divided into multiple (e.g., P) frequency bands / channels (also referred to as active subcarriers), and the RF core 300 transmits via the antenna 308 on one of the frequency bands each time. In some embodiments, the single subcarrier mapper 1900 may select the same subchannel for each pair of symbols such that differentially encoded symbols (e.g., DBPSK) share the same subcarrier. In some embodiments, P may be greater than L. In some embodiments, P may be equal to L.

[0219] In some embodiments, the spacing CH spc between channels is fixed. In some embodiments, the spacing CH spc between channels may be selected from a set including 200 kHz, 400 kHz, 800 kHz, and / or 1200 kHz. In some embodiments, different subchannel spacings may be used.

[0220] In some embodiments, P may be configurable and may depend on a specific setting of the RF core 300. For example, in some embodiments, P may be selected from a set including 12 channels, 26 channels, 52 channels, and / or 104 channels.

[0221] In some embodiments, the frequency band used for transmitting one or more symbols is predetermined (and may be fixed, for example, CH). sel This can be fixed, for example, for an entire packet or a group of packets. In some embodiments, a single subcarrier mapper 1900 selects which frequency band to transmit one or more symbols based on a predetermined set of frequency bands, for example, according to a frequency hopping sequence (e.g., a predetermined sequence). In some embodiments, a single subcarrier mapping block 310 selects which frequency band to transmit symbols based on which part of the PPDU 400 is being transmitted.

[0222] Figure 20 A block diagram of an IFFT block 2000 according to an embodiment of the present disclosure is shown. The inverse transform block 414 may be implemented as IFFT block 2000.

[0223] In some embodiments, the IFFT block 2000 computes an IFFT on the symbols of the input symbol stream to produce a sequence of samples (e.g., in the time domain) corresponding to the input symbols. In some embodiments, the number of samples per symbol is the DFT. SZ It is fixed. In some embodiments, the number of samples per symbol (DFTSZ) may be selected from a set containing 16, 32, 64, and / or 128 samples per symbol. Other numbers of samples per symbol (e.g., powers of 2) may also be used.

[0224] Figure 21 A block diagram of an FFT block 2100 according to an embodiment of the present disclosure is shown. A Fourier transform block 504 may be implemented as an FFT block 2100.

[0225] In some embodiments, FFT block 2100 operates in the opposite manner to IFFT block 2000 (e.g., utilizing the same DFT). SZ (Set) Perform a Fourier transform on the input sample stream in order to reconstruct the transmitted symbols used by the IFFT block 2000 to generate the time-domain signal using the resulting sample sequence.

[0226] Figure 22 The operation of a loop prefix with a windowing function according to an embodiment of the present disclosure is illustrated. The loop prefix block 416 can implement a loop prefix with a windowing function, such as... Figure 22 As shown in the image.

[0227] In some embodiments, the cyclic prefix block 416 repeats all or part of a symbol before and / or after it. For example, in some embodiments, each symbol is preceded and / or appended with a cyclic prefix (CP), such as... Figure 22 As shown in the image.

[0228] In some embodiments, the duration of CP may be ¼ of the duration of the basic symbol, but other durations may also be used, such as ½ or different.

[0229] In some embodiments, the sum of the duration of the CP and the duration of the basic symbol produces the total symbol duration. For example, in some embodiments where the duration of the CP is 1 / 4 of the duration of the basic symbol, the total number of samples per symbol can be given by the following formula:

[0230] (3)

[0231] DFT sz This represents the number of samples of the basic symbols (e.g., generated by IFFT 2000). The total symbol duration can be given by multiplying SZ by the basic symbol duration. According to an embodiment of this disclosure, this is illustrated in Table 1, for example.

[0232]

[0233] Table 1 - Duration of Cyclic Prefix

[0234] In some embodiments, to minimize the sidelobes of each subcarrier, a windowed filter can be applied during the first half of the cyclic prefix duration. For example, in some embodiments where the symbol duration is 1 / 4 of the basic symbol, a windowing function can be applied to the first half of the CP. One sample.

[0235] In some embodiments, a windowing filter is not applied during the cyclic prefix duration.

[0236] In some embodiments, for each current symbol k, a linear windowing function can combine samples of OFDM symbol k-1 with samples of the CP of symbol k. For example, in some embodiments where the symbol duration is 1 / 4 of the basic symbol, the preceding OFDM symbol k-1... The first sample and the cyclic prefix of symbol k The samples are combined. In some embodiments, this combination can be linear, such that the sample from OFDM symbol k-1 is multiplied by a factor that starts with 1 at sample 0 and ... A linear function terminated at 0, and the sample from the cyclic prefix multiplied by a function that starts at 0 at sample 0 and is present at sample 0. A linear function terminated by 1. The results of two multiplications can be added together to generate a new cyclic prefix sample. Part of this process is... Figure 22 As shown in the image.

[0237] In some embodiments, the basic symbol duration is predetermined. In some embodiments, the basic symbol duration may be dynamically changed, for example, based on received data (e.g., via previous transmissions between devices 202 and 252). For example, in some embodiments, the basic symbol duration may be dynamically selected from a set of basic symbol durations such as those shown in Table 1.

[0238] In some embodiments, the RF core 300 supports multiple options for the spreading rate and multiple symbol rates. In some embodiments, the selected option determines the total signal bandwidth (BW). In some embodiments, the bandwidth of each of the subcarriers is based on the selected symbol duration. In some embodiments, the spreading rate (e.g., the DSSS value) provides additional write-code mechanisms to increase redundancy and improve the link budget.

[0239] Figures 23A to 23D This demonstrates various possible settings for the data rate of the RF core 300 according to embodiments of the present disclosure.

[0240] In some embodiments, data may be encoded for transmission (e.g., in...). Figures 23A to 23D The total bandwidth of all frequency bands (under any of the settings shown) is 500 kHz (or greater), which advantageously enables the use of asynchronous protocols in the FCC area. In some embodiments, the total bandwidth may be less than 500 kHz.

[0241] like Figures 23A to 23D As shown, in some embodiments, the RF core 300 may have multiple configurable parameters. For example, in RF core 300 supporting... Figures 23A to 23D In all the parameter options shown in the embodiments, the symbol duration SymDur can be selected from a set including 120 μs, 60 μs, 30 μs, and 15 μs. In some such embodiments, when a symbol duration of 120 μs SymDur is selected, the RF core 300 can be configured as option 1, option 2, option 3, or option 4, for example, as... Figure 23A As shown in the diagram. In some such embodiments, if option 1 is selected, the nominal bandwidth for communication is 1.1 MHz with a channel spacing of 1.2 MHz (e.g., total channel spacing, for example, referring to the set of all subcarriers, where the sub-channel spacing can be (5 / 4)). SymDur (given) has a DFT size of 128 samples. SZ It has 104 subcarrier channels (also known as active subcarriers) and DSSS values ​​that can be selected between 2, 4 and 6, the selection of which affects the data rate (where a higher DSSS value results in a lower data rate).

[0242] As in Figures 23A to 23D As can be seen, for some symbol durations (SymDur), some options may be unavailable. For example, such as... Figure 23D As shown in the document, options 2, 3, and 4 may be unavailable for SymDur with a symbol duration of 15 μs.

[0243] In some embodiments, the general relationship between the data rate, which varies with the symbol duration SymDur and DSSS values, and these two values ​​can be given by the following formula:

[0244] (4)

[0245] In some embodiments, the selection options and symbol duration may be negotiated (e.g., pre-negotiated) by the upper protocol layer of the device (e.g., above the PHY layer, such as by the MAC layer, or above the MAC layer). In some embodiments, the spread spectrum rate (DSSS value) may be dynamically represented per packet (e.g., including a specific portion within the packet), such as in the packet header.

[0246] In some embodiments, the RF core may not use any pilot subcarriers (e.g., no channel may be used to transmit pilot signals, such as for synchronization).

[0247] In some embodiments, RF core 300 may support Figures 23A to 23D All settings shown herein. In some embodiments, the RF core 300 may support other settings ( Figures 23A to 23D (Not shown in the text). In some embodiments, the RF core 300 may be... Figures 23A to 23D Some, but more than one, of the settings shown are included. In some embodiments, the RF core 300 may support only... Figures 23A to 23D The settings shown are individual settings (e.g., any one of the settings).

[0248] As an example, in some embodiments, the RF core 300 may support Figures 23A to 23C All option 2 settings listed (e.g., having DSSS values ​​selectable between 2, 4, and 6; having symbol duration selectable between 120 μs, 60 μs, and 30 μs; and having a DFT size selectable based on a set that depends on the symbol duration SymDur) SZ For example, such as Figures 23A to 23C (As shown in the image).

[0249] In some embodiments, communication between devices 202 and 252 uses a frequency band below 1 GHz, such as the band between 470 MHz and 925 MHz. For example, some embodiments use one of the following frequency bands to transmit and / or receive packets:

[0250] 470 to 510 MHz;

[0251] 779 to 787 MHz;

[0252] 863 to 870 MHz;

[0253] 865 to 867 MHz;

[0254] 866 to 869 MHz;

[0255] 870 to 876 MHz;

[0256] 902 to 928 MHz;

[0257] 902 to 928 (alternating) MHz;

[0258] 902 to 907.5 MHz and 915 to 928 MHz;

[0259] 915 to 928 MHz;

[0260] 915 to 921 MHz;

[0261] 915 to 918 MHz;

[0262] 917 to 923.5 MHz;

[0263] 919 to 923 MHz;

[0264] 920 to 928 MHz;

[0265] 920.5 to 924.5 MHz; and

[0266] 920 to 925 MHz.

[0267] Figure 24 A flowchart illustrating an embodiment method 2400 for selecting communication parameters according to embodiments of the present disclosure is shown. In some embodiments, RF core 300 or an associated controller (e.g., 206, 256) may implement method 2400.

[0268] During step 2402, the first device (e.g., 202) negotiates with the second device (e.g., 252) to select the symbol duration to be used during the communication phase between the first and second devices. In some embodiments, the first device uses a default setting (e.g., according to...) Figure 23B SymDur = 60 μs; Option 2) Communicate with the second device to negotiate with the second device.

[0269] In some embodiments, both the first and second devices support various symbol durations (e.g., such as...). Figures 23A to 23D (As shown in the illustration). In some such embodiments, a symbol duration may be selected during step 2404 from a set of generally supported symbol durations, for example, based on the nature of the device, environmental conditions, the nature of the particular application, etc. In some embodiments, if the set of generally supported symbol durations has only one symbol duration, that symbol duration is selected during step 2404.

[0270] During step 2406, the first and second devices negotiate to select an option associated with the selected symbol duration, wherein the selection of the option may mean adjusting the DFT size DFT. SZ The selection of factors such as the number of active subcarriers, for example... Figures 23A to 23D As shown in the illustration. In some embodiments, both the first and second devices support various options (e.g., such as...). Figures 23A to 23C (As shown in the illustration). In some such embodiments, the option may be selected during step 2408 from a set of generally supported options, for example, based on the nature of the device, environmental conditions, the nature of the particular application, etc. In some embodiments, if the set of generally supported options has only one symbolic duration (e.g., as shown in the illustration), the option may be selected from a set of generally supported options. Figure 23D As shown in the image, or if the device only supports Figure 23B If option 2 is selected, then this option is selected during step 2408.

[0271] During step 2410, the first device and the second device communicate using the parameters selected during steps 2404 and 2408.

[0272] Figure 25 The grouping structure of a PPDU 2500 according to an embodiment of the present invention is shown. Grouping 401 can be implemented as PPDU 2500.

[0273] PPDU 2500 includes a Short Training Field (STF) 2502, a Long Training Field (LTF) 2504, a Physical Header (PHR) field 2506, and a PHY Payload field 2508. The PHR field 2506 includes a Rate field 2520, a Frame Length field 2522, a Header Check Sequence (HCS) field 2526, and a Tail field 2526. The PHY Payload field 2508 includes a PHY Service Data Unit (PSDU) field 2540, a PPDU Tail field 2542, and a Padding field 2544.

[0274] In some embodiments, the STF field 2502 may be used by the RF core 300 (e.g., demodulator 304, such as processing pipeline 500 or 600) or an associated controller (e.g., 206, 256) for packet detection and / or for (e.g., coarse) frequency offset determination. In some embodiments, a portion of the STF field 2502 may be configurable. For example, in some embodiments, the last bit of the STF field 2502 may be configurable. In some such embodiments, the portion of the STF field 2502 used for packet detection and / or frequency offset determination may be a fixed (non-configurable) portion of the STF field 2502, while the configurable portion of the STF field 2502 may not be used for packet detection and / or frequency offset determination.

[0275] In some embodiments, STF field 2502 contains 160 symbols. In some embodiments, STF field 2502 may contain fewer than 160 symbols (e.g., 120, 64 or less) or more than 160 symbols (e.g., 200, 320 or more).

[0276] In some embodiments, the symbols of STF field 2502 are transmitted uninterruptedly in a single subcarrier via antenna 308.

[0277] In some embodiments, the content of STF field 2502 is processed by some, but not all, blocks of processing pipeline 400. For example, in some embodiments, blocks 402, 404, and 406 do not process the content of STF field 2502. In some such embodiments, the content of STF field 2502 is processed by DSSS block 408 (e.g., using a predetermined DSSS value, such as 2), bit-to-symbol block 410 (e.g., using BPSK), and single subcarrier mapping block 412 (e.g., using a fixed CH). sel The STF field 2502 is processed by the inverse transform block 414. In some such embodiments, the cyclic prefix block 416 and the filter block 418 also process the contents of the STF field 2502.

[0278] In some embodiments, the content of STF field 2502 is fixed. For example, Figure 26 An STF bit sequence 2600 according to an embodiment of this disclosure is shown. Other STF bit sequences may also be used.

[0279] like Figure 26 As shown, in some embodiments, the STF bit sequence may have 80 bits. This STF bit sequence can be spread by DSSS (e.g., the STF sequence can be doubled when using a DSSS value of 2), so that the sequence transmitted by antenna 308 can contain a multiple of the number of bits of the original STF sequence (e.g., 160 chips when using a DSSS equal to 2).

[0280] In some embodiments, the STF field 2502 includes one or more configurable bits.

[0281] In some embodiments, some or all (e.g., BPSK) symbols of STF field 2502 can be used to generate a series of vectors. , Where k is between 0 and, for example, the total number of symbols in STF field 2502-1 (e.g., from 0 to 159 when STF field 2502 has 160 symbols), where DFT SZ It is defined based on the selected option (e.g., using method 2400), and where and Wherein the STF subcarrier is (e.g., a single) CH used by a single subcarrier mapper 1900 when processing the STF field 2502 (e.g., all of its contents). sel .

[0282] In some embodiments, the LTF field 2504 may be used by the RF core 300 (e.g., demodulator 304, such as processing pipeline 500 or 600) or an associated controller (e.g., 206, 256) for finer frequency offset detection, for time synchronization, and / or for channel equalization.

[0283] In some embodiments, LTF field 2504 contains fewer symbols than STF field 2502. In some embodiments, LTF field 2504 contains 26 symbols. Some embodiments may contain more than 26 symbols (e.g., 32, 40 or more) or fewer than 26 symbols (e.g., 20, 16 or fewer).

[0284] In some embodiments, the symbols of the LTF field 2504 are transmitted sequentially via antenna 308 in multiple subcarriers (using only a single subcarrier at a time) according to a frequency hopping sequence.

[0285] In some embodiments, the content of LTF field 2504 is processed by some, but not all, blocks of processing pipeline 400. For example, in some embodiments, blocks 402, 404, and 406 do not process the content of LTF field 2504. In some such embodiments, the content of LTF field 2504 is processed by DSSS block 408 (e.g., using a predetermined DSSS value, such as 2), bit-to-symbol block 410 (e.g., using BPSK), and single subcarrier mapping block 412 (e.g., using a fixed or frequency-hopping sequence-varying CH). sel The LTF field 2504 is processed by the inverse transform block 414. In some such embodiments, the cyclic prefix block 416 and the filter block 418 also process the contents of the LTF field 2504.

[0286] In some embodiments, the content of LTF field 2504 is fixed. For example, Figure 27 An LTF bit sequence 2700 according to an embodiment of this disclosure is shown. Other LTF bit sequences may also be used.

[0287] In some embodiments, the LTF field 2504 includes one or more configurable bits.

[0288] In some embodiments, the PHR field 2506 may be used by the RF core 300 (e.g., demodulator 304, such as processing pipeline 500 or 600) or an associated controller (e.g., 206, 256) to determine the format, modulation, and / or content of the PHY payload field 2508.

[0289] In some embodiments, the symbols of the PHR field 2506 are transmitted sequentially via antenna 308 in multiple subcarriers (using only a single subcarrier at a time) according to a frequency hopping sequence.

[0290] In some embodiments, the content of the PHR field 2506 is processed by some, but not all, blocks of the processing pipeline 400. For example, in some embodiments, block 402 does not process the content of the LTF field 2504. In some such embodiments, the content of the PHR field 2506 is processed by the FEC encoder block 404, the interleaver block 406, the DSSS block 408 (e.g., using a predetermined DSSS value, such as 6), the bit-to-symbol block 410 (e.g., using BPSK), and the single subcarrier mapping block 412 (e.g., using a fixed or frequency-hopping sequence-varying CH). sel The PHR field 2506 is processed by the inverse transform block 414. In some such embodiments, the cyclic prefix block 416 and the filter block 418 also process the contents of the PHR field 2506.

[0291] In some embodiments, the input to scrambler block 402 includes data octets (e.g., some or all of them) of PHR field 2506.

[0292] In some embodiments, the PHR field 2506 contains 24 bits. In some embodiments, the PHR field contains a different number of bits, such as more than 24 bits or less than 24 bits.

[0293] In some embodiments, some bits of the PHR field 2506 are fixed, and some are configurable. In some embodiments, all bits of the PHR field 2506 are configurable.

[0294] In some embodiments, interleaver block 406 performs interleaving on PHR field 2506 (e.g., some or all of its bits).

[0295] In some embodiments, the PHY payload field 2508 includes data bits.

[0296] In some embodiments, the PHY payload field 2508 has a variable length (e.g., as indicated by the frame length field 2522), so that each packet may have a PHY payload field of different lengths. In some embodiments, the PHY payload field 2508 has a fixed (e.g., predetermined) length.

[0297] In some embodiments, some or all bits of the PHY payload field 2508 are transmitted at a data rate specified by the PHR 2506. In some embodiments, the data rate for transmitting the PHY payload field 2508 is the same as the data rate for transmitting the PHR field 206. In some embodiments, the data rate for transmitting the PHY payload field 2508 is different from the data rate for transmitting the PHR field 2506.

[0298] In some embodiments, the convolutional encoder 1000 is initialized to an all-zero state before encoding the bits associated with the PHR field 2506, and then reset to an all-zero state before encoding the bits of the PHY payload field 2508.

[0299] In some embodiments, the rate field 2520 indicates the DSSS value used to encode the PHY payload field 2508 (and may therefore affect the data rate at which bits of the PHY payload field 2508 are transmitted). In some embodiments, the DSSS value indicated by the rate field 2520 is a DSSS value from a predetermined set of DSSS values. In some embodiments, the predetermined set of DSSS values ​​includes DSSS values ​​of 2, 4, and / or 6. In some embodiments, the predetermined set of DSSS values ​​may include other DSSS values ​​(e.g., 0 (no DSSS), 8, 10, 12, etc.).

[0300] In some embodiments, the rate field 2520 is a 2-bit field. In some embodiments, the rate field may contain more than 2 bits (e.g., 3, 4 or more), or 1 bit. In some embodiments, the content of the rate field 2520 may be fixed. In some embodiments, some or all bits of the frame length field 2520 are configurable. In some embodiments, the rate field 2520 is not implemented (omitted). In some such embodiments, the DSSS value for the PHY payload 2508 may be fixed.

[0301] In some embodiments, the frame length field 2522 indicates the total length of the PPDU 2500, and / or a portion of the PPDU 400, such as the length of the PHY payload field 2508 and / or the length of a portion of the PHY payload field 2508 (e.g., the PSDU field 2540, the PPDU tail field 2542, and / or the padding field 2544).

[0302] In some embodiments, the content of the frame length field 2522 is an unsigned integer that indicates the (e.g., total) number of octets (bytes) contained in the PSDU field 2540 (e.g., before being encoded by the FEC encoder block 404).

[0303] In some embodiments, the frame length field 2522 is an 8-bit field. In some embodiments, the length field 2522 may be a field with more than 8 bits (e.g., 9, 10, 20 or more) or less than 8 bits (e.g., 6, 4, 3, 2 or 1). In some embodiments, the content of the frame length field 2522 may be fixed. In some embodiments, some or all of the bits of the frame length field 2522 are configurable. In some embodiments, the frame length field 2522 is not implemented (omitted). In some such embodiments, the length of the PHY payload field 2508 (and the possible length of the PPDU 2500) may be fixed.

[0304] In some embodiments, the frame length field 2522 is transmitted first with the most significant bit (MSB). In some embodiments, the frame length field 2522 is transmitted first with the least significant bit (LSB).

[0305] In some embodiments, the HCS field 2524 is a Cyclic Redundancy Check (CRC) field. In some embodiments, this CRC is used to verify the transmission of the PHR field 2506 (e.g., to detect / correct errors in the PHR field 406). In some embodiments, this CRC is calculated based on the contents of the rate field 2520 and the frame length field 2522. In some embodiments, the first 10 bits of the PHR field 2506 are used to calculate the HCS field 2524.

[0306] In some embodiments, the RF core 300 (e.g., demodulator 304, such as processing pipeline 500 or 600) or an associated controller (e.g., 206, 256) may compare the value received in the HCS field 2524 with a CRC value calculated based on the contents of the rate field 2520 and the frame length field 2522 to determine whether the PHR field 2506 is corrupted.

[0307] In some embodiments, the following polynomial can be used to calculate HCS field 2524:

[0308] (5).

[0309] In some embodiments, the HCS field 2524 is the one's complement of the modulo-2 sum of the two remainders in a) and b):

[0310] a) by The remainder obtained by dividing by (modulo 2) G8(x), where the value k is the number of bits in the calculated field;

[0311] b) Multiply the content of the calculated field, which is treated as a polynomial, by x. 8 Then divide by (modulo 2) G8(x) to get the remainder.

[0312] In some embodiments, HCS field 2524 is an 8- or 10-bit field. In some embodiments, HCS field 2524 may be a field with more than 8 bits (e.g., 9, 12, 16 or more) or less than 8 bits (e.g., 7, 6 or less). In some embodiments, HCS field 2524 is not implemented (omitted).

[0313] In some embodiments, the tail field 2526 is designed to facilitate decoding, for example, by the FEC decoder 514, to reduce the error probability of, for example, a convolutional encoder (e.g., 1000). For instance, in some embodiments, the tail field 2526 contains all zeros to facilitate Viterbi decoded flushing.

[0314] In some embodiments, the tail field 2526 is a 6-bit field. In some embodiments, the tail field 2526 may contain more than 6 bits (e.g., 7, 9, 10 or more) or less than 6 bits (e.g., 5, 4 or less). In some embodiments, the tail field 2526 may be omitted.

[0315] In some embodiments, the PHR field 2506 includes a scrambler field (not shown) to specify a scrambler seed for scrambling the contents of the PHY payload field 2508 (e.g., by blocks 402, 516). In some embodiments, the scrambler field 2506 may be omitted. In some such embodiments, the scrambling of the contents of the PHY payload field 2508 may be based on a predetermined scrambling seed (e.g., all one) or may be omitted.

[0316] In some embodiments, PSDU field 2540 includes data bits. In some embodiments, such data bits of PSDU field 2540 are data bits received from the MAC layer of an apparatus (e.g., 202, 252) that performs the transmission (e.g., using processing pipeline 400).

[0317] In some embodiments, the input to scrambler block 402 includes data octets (e.g., some or all of them) of PSDU field 2540.

[0318] In some embodiments, the PSDU field 2540 has a variable length (e.g., as indicated by the frame length field 2522). In some embodiments, the length of the PSDU field 2540 is based on the number of data bits received from the MAC layer.

[0319] In some embodiments, the content of PSDU field 2540 is transmitted at a data rate (e.g., data rate 2520) specified by PHR 2506. In some embodiments, the data rate for transmitting PSDU field 2540 is the same as the data rate for transmitting the remainder of PHR payload field 2508 and / or PHR field 2506. In some embodiments, the data rate for transmitting PSDU field 2540 is different from the data rate for transmitting the remainder of PHR payload field 2508 and / or PHR field 2506.

[0320] In some embodiments, the PPDU tail field 2542 is designed to facilitate decoding, for example, by the FEC decoder 514, to reduce the error probability of, for example, a convolutional encoder (e.g., 1000). For instance, in some embodiments, the PPDU tail field 2542 contains all zeros to facilitate Viterbi decoding clearing.

[0321] In some embodiments, the PPDU tail field 2542 is a 6-bit field. In some embodiments, the tail field 2542 may contain more than 6 bits (e.g., 7, 8, 10 or more) or less than 6 bits (e.g., 5, 4 or less). In some embodiments, the PPDU tail field 2542 may be omitted.

[0322] In some embodiments, the processing pipeline (e.g., 500 or 600) of the demodulator (e.g., 304) places (e.g., some or all) fields (e.g., fields 2502, 2504, 2506 and / or 2508) of the reconstructed group 401 in a receiver (RX) first-in-first-out (FIFO) buffer for further processing / use (e.g., by the demodulator 304 and / or associated controllers (e.g., 206, 256)).

[0323] Figure 28 The transmission of packet 2800, coded across multiple subcarrier frequencies, is illustrated according to an embodiment of the present disclosure. In some embodiments, packet 401 may be transmitted as packet 2800, for example, by RF core 300, after processing by processing pipeline 300.

[0324] exist Figure 28In this embodiment, 16 subcarrier frequencies are used. Some embodiments may use fewer than 16 subcarrier frequencies (e.g., 12) or more than 16 subcarrier frequencies (e.g., 26, 52, or 104) for packet transmission. In some embodiments, the number of subcarrier frequencies used is determined by the options for communication, for example, as determined by method 2400.

[0325] In some embodiments, the group 2800 has a grouping structure of the PPDU 2500.

[0326] like Figure 28 As shown, packet 2800 can be transmitted in the following manner: first, a synchronization sequence 2802 (e.g., corresponding to STF field 2502) is transmitted, followed by the transmission of the remaining fields of packet 2800 (e.g., fields 2504, 2506, 2508) according to a frequency hopping sequence 2804.

[0327] like Figure 28 As shown in the diagram, the transmission of packet 2800 may take t packet Time, which includes t sync Time (used for transmitting synchronization sequence 2802) and t hop Time (the time used to transmit data according to frequency hopping sequence 2804).

[0328] exist Figure 28 In the diagram, symbols 2810 to 2850 are shown as two horizontally adjacent boxes. Figure 28 The horizontal axis in the diagram represents the time slots used for data transmission. Figure 28 The vertical axis in the diagram represents the sixteen frequency bands through which data can be encoded for transmission. Although Figure 3 E illustrates a transmission using 16 frequency bands, but some embodiments may use more than 16 frequency bands (e.g., 20, 26, 32, 37, 40, 52, 104 or more, or fewer than 16 frequency bands, e.g., 14, 12, 9, 8, 4 or fewer). In some embodiments, a set of frequency bands available for transmission may be dynamically selected.

[0329] In some embodiments, the frequency band used by the frequency hopping sequence 2804 is all the frequency bands available for communication (e.g., the number of active subcarriers, for example, according to...). Figures 23A to 23D The selected communication option may be a subset of frequency bands (e.g., having fewer frequency bands). For example, in some embodiments, a total of 16 frequency bands (e.g., 16 active subcarriers) may exist for communication, but the frequency hopping sequence uses only 10 of the 16 frequency bands. Other implementations are also possible.

[0330] like Figure 28As shown, some embodiments use a single subcarrier signal for each time slot. This technique can advantageously result in a lower PAPR and produce an RF signal that is easier for a demodulator (e.g., 304) to demodulate.

[0331] like Figure 28 As shown, some embodiments choose to maintain the same subcarrier frequency for the entire synchronization sequence 2802, and select a new subcarrier frequency after every two time slots (every two symbols – every pair of symbols) such that the symbols in each pair share the same frequency band (this may be advantageous for differential modulation (e.g., differential BPSK (DBPSK))). Some embodiments may use FDM to divide the total bandwidth into channels that can be selected for each pair of time slots. Alternatively, some embodiments may implement other forms of division multiplexing for modulating RF signals, such as time division multiplexing or code division multiplexing.

[0332] exist Figure 28 In one embodiment, symbol pair 2810 is assigned to the ninth frequency band, symbol pair 2812 is assigned to the sixth frequency band, and so on. Each pair of symbols is assigned to one frequency band (e.g., fixed or according to a frequency hopping sequence).

[0333] In some embodiments (such as) Figure 28 In the example shown, the first frequency channel of the frequency hopping sequence 2804 is the same as the STF subcarrier (the frequency channel used for the transmission of the synchronization sequence 2802). In some embodiments, the first frequency channel of the frequency hopping sequence 2804 may be different from the STF subcarrier.

[0334] In some embodiments, more than one pair of symbols (e.g., 2, 3, 4 or more) may be transmitted before frequency hopping to the next channel, compared with... Figure 28 Compared to other embodiments, this can advantageously reduce the frequency of channel switching. In some embodiments, the frequency hopping sequence 2804 is random, pseudo-random, quasi-random, or deterministic.

[0335] In some embodiments, the frequency hopping sequence 2804 may switch frequencies for each frequency modulation (e.g., after each pair of symbols). However, in some embodiments, the frequency hopping sequence 2804 may occasionally select the same frequency band for two consecutive transmissions (e.g., as shown by symbol pairs 2820 and 2822). For example, in some embodiments using random, pseudo-random, or quasi-random frequency hopping sequences, the same sub-channel may be selected for consecutive transmissions. In some embodiments, the frequency hopping sequence 2804 is designed to prevent consecutive transmissions using the same frequency band. In some embodiments, the frequency hopping sequence 2804 is designed to traverse all channels before modifying a particular sub-channel (and this sequence may be repeated until all symbols of packet 2800 are transmitted).

[0336] In some embodiments, the demodulator (e.g., 304) determines the bit represented by each pair of symbols by comparing the two symbol values ​​in each pair (e.g., inverse DSSS blocks 508, 604). For example, in some embodiments using the DSSS value 2, the logic value one is represented by two identical symbol values, and the logic value zero is represented by two different symbol values. Therefore, in some embodiments, the demodulator (e.g., inverse DSSS blocks 508, 604) may compare the second symbol value in the pair with the previous symbol value to determine the value of the bit represented by the symbol pair. In some such embodiments, the demodulator may advantageously use local information to demodulate the RF signal without any additional information, which may advantageously reduce interference caused by frequency drift over time and multipath environments.

[0337] In some embodiments (e.g., embodiments using BPSK), reusing the same frequency band for each symbol in a pair advantageously allows differential coding (e.g., DBPSK), which can advantageously allow the phase of a symbol to be determined without precise synchronization, since the phase is relative and the frequency band is the same for both symbols in a pair.

[0338] In some embodiments, each symbol of the transmitted packet 2800 corresponds to a chip. Therefore, in some embodiments, each pair of symbols corresponds to a pair of chips. Thus, in some embodiments (e.g., using DSSS = 2), each pair of symbols (e.g., 602, 604, etc.) corresponds to a bit of PPDU 2500.

[0339] In some embodiments using DSSS values ​​higher than 2 (e.g., 4 or higher), it indicates that each bit of the chip is transmitted on multiple frequencies (e.g., according to frequency hopping sequence 2804). Therefore, some of these embodiments may advantageously be more robust and resilient to horizontal and vertical interference because the bits of the PPDU 2800 are spread over time (e.g., multiple pairs of chips) and multiple frequency bands (e.g., due to frequency hopping sequence 2804). For example, suppose... Figure 28In an embodiment implementing a DSSS value of 4, symbol pairs 2810 and 2812 represent (e.g., PPDU 2800) a single data bit. This data bit is transmitted over 4 time slots (4 symbols) and multiple frequency bands (channels 9 and 6).

[0340] In some embodiments, a higher DSSS value indicates more robust communication. In other embodiments, a lower DSSS value indicates higher data throughput.

[0341] In some embodiments, the frequency hopping sequence 2804 may be selected based on the synchronization sequence 2802. For example, in some embodiments, the seed used to determine the frequency hopping sequence 2804 may be based on which sub-channel is used to transmit the synchronization sequence 2802 (STF subcarrier) and / or one or more bits of the synchronization sequence 2802 (e.g., the last two bits of the STF field 2502).

[0342] In some embodiments, synchronization sequence 2802 is used for packet detection (e.g., detecting PPDU 2800, such as detecting the start of LTF field 2504 to confirm the start of frequency hopping sequence 2804), frequency offset determination, and / or timing synchronization. In some embodiments, synchronization sequence 2802 is the only synchronization sequence transmitted for packets. In some embodiments, a subsequent synchronization sequence (e.g., LTF field 2504) is transmitted after synchronization sequence 2802 to allow for finer synchronization, timing synchronization, and / or channel equalization. For example, in some embodiments, this subsequent synchronization sequence may be transmitted after the frequency hopping sequence (e.g., packets 2810, 2812, etc. may be part of LTF field 2504), wherein the actual header (e.g., 2506) and payload (e.g., 2508) are transmitted after this subsequent synchronization sequence.

[0343] In some embodiments, the synchronization sequence 2802 may include a preamble field and a synchronization sequence field.

[0344] like Figure 28 As shown, in some embodiments, a synchronization sequence 2802 is transmitted in a single frequency band. In some embodiments that include a subsequent synchronization sequence, the subsequent synchronization sequence is transmitted according to a frequency hopping sequence 2804. For example, in some embodiments, the frequency hopping sequence 2804 includes a subsequent synchronization sequence (LTF field 2504). In some such embodiments, the synchronization sequence 2802 (STF field 2502) can be used for packet detection and coarse frequency offset determination, while the subsequent synchronization sequence (LTF field 2504) can be used for finer offset determination, timing synchronization, and channel equalization.

[0345] In some embodiments, the synchronization sequence 2502 includes a plurality of symbols, such as 10, 20, 32, 64, 80, 96, 160 or more.

[0346] In some embodiments, the synchronization sequence 2802 has a duration t longer than the maximum sleep duration of the receiver device (e.g., 252) (the time spent in a low-power mode (e.g., where paths 310 and / or 320 are disabled)). sync In some embodiments, the duration of the synchronization sequence can be dynamically changed, for example, by changing the duration of each symbol, and / or by changing the number of symbols transmitted as part of the synchronization sequence 2802.

[0347] In some embodiments, the receiver and / or transmitter devices (e.g., 252, 202) periodically enter a sleep mode, which can advantageously achieve lower power consumption. In some such embodiments, packet transmission / reception (e.g., 401) can occur when the device is in an active node, for example, where paths 310 and 320 are enabled.

[0348] In some embodiments, the symbol duration of the synchronization sequence 2802 (and / or frequency hopping sequence 2804) is fixed. In some embodiments, the symbol duration of the synchronization sequence 2802 (and / or frequency hopping sequence 2804) may be changed, for example periodically and / or in response to a trigger (e.g., input from an upper layer (e.g., the link layer, MAC layer, and / or transport layer)).

[0349] In some embodiments, the subcarrier channel STF subcarrier selected by a single subcarrier mapping block 412 for the synchronization sequence 2802 may be selected by the link layer / MAC layer / network layer and may be fixed for multiple (or all) packets. In some embodiments, the subcarrier channel STF subcarrier may change after each packet or after multiple packets (e.g., in response to a trigger, such as a trigger from the link layer / MAC layer / network layer, or after a predetermined number of packets have been sent).

[0350] In some embodiments (e.g.) Figure 28 As shown in the diagram, data transmission according to the frequency hopping sequence 2804 begins immediately after the synchronization sequence 2802. In some embodiments, there may be a delay (e.g., a duration of 1 or 2 symbols or more) between the synchronization sequence 2802 and the first transmission (e.g., 2610) of the frequency hopping sequence 2804.

[0351] In some embodiments, the demodulator (e.g., 304) may detect only a portion of the synchronization sequence 2802 (e.g., the last portion) and may still be able to detect packets (2800), perform synchronization, and receive data (e.g., fields 2504, 2506, and 2508) during the frequency hopping sequence 2804.

[0352] In some embodiments, the frequency hopping sequence 2804 is selected based on which sub-channel transmits the synchronization sequence 2802. For example, in Figure 28 In this embodiment, the seed used to select the frequency hopping sequence can be based on sub-channel 9, which is the sub-channel for transmitting the synchronization sequence 2802. Therefore, in Figure 28 In one embodiment, the demodulator (e.g., 304) can derive the frequency hopping sequence for data transmission by using subchannel 9 as a seed for selecting the frequency hopping sequence, either alone or in combination with other parameters.

[0353] In some embodiments, the frequency hopping sequence 2804 is selected based on one or more (e.g., the last) symbols of the synchronization sequence 2802. For example, in some embodiments, the synchronization sequence 2802 may include one or more symbols whose state indicates a value used to determine a seed value for determining the frequency hopping sequence 2804. Therefore, in some embodiments, a demodulator (e.g., 304) can derive the frequency hopping sequence for data transmission by (e.g., alone or in combination with other parameters) using the state of one or more symbols of the synchronization sequence 2802.

[0354] In some embodiments, the frequency hopping sequence 2804 may be determined based on the state of one or more symbols of the synchronization sequence 2802 in conjunction with the sub-channels used to transmit the synchronization sequence 2802.

[0355] In some embodiments, the frequency hopping sequence 2804 is not based on the content of the synchronization sequence 2802 or the sub-channels of the transmission synchronization sequence 2802. For example, in some embodiments, the frequency hopping sequence 2804 is based on an out-of-band transmission seed, a predefined seed, the current time, etc.

[0356] In some embodiments, the seed value used to determine the frequency hopping sequence 2804 is partially determined by the frequency band of the transmission synchronization sequence 2802. In some embodiments, the seed value is entirely determined by the frequency band of the transmission synchronization sequence 2802. In some embodiments, the seed value is not determined by the frequency band of the transmission synchronization sequence 2802.

[0357] In some embodiments, the frequency hopping sequence 2804 is selected based on a seed value in combination with one or more coefficients. In some embodiments, the seed value, together with one or more coefficients, completely determines the frequency hopping sequence 2804.

[0358] In some embodiments, the seed value and one or more coefficients are predetermined, known for both devices (e.g., 202 and 256), and fixed. In some embodiments, the seed value and / or one or more (or all) of the one or more coefficients may be dynamically changed (e.g., periodically, in response to input received by the RF core 300 and / or associated controller, after a predetermined number of transmissions / packets, and / or other factors).

[0359] In some embodiments, the seed value and one or more (or all) of one or more coefficients are received by the PHY layer (e.g., implemented by RF core 300) from an upper layer (e.g., the link layer, the media access control (MAC) layer, and / or the network layer), which may be implemented, for example, by another controller of an associated controller (e.g., 206) or device (e.g., 202).

[0360] In some embodiments, a linear congruent generator (LCG) subcarrier mapping is used to determine one or more coefficients for determining the frequency hopping sequence.

[0361] In some embodiments, subcarrier mapping block 412 (e.g., a single subcarrier mapper 1900) receives one or more coefficients as input from the link layer / MAC layer / network layer. In some embodiments, one or more coefficients are fixed and do not change. In some embodiments, one or more (or all) of the one or more coefficients change after each packet, after transmitting a predetermined number of packets, and / or in response to a trigger (e.g., received from the link layer / MAC layer / network layer).

[0362] Some embodiments include a seed value for determining the frequency hopping sequence 2804 based on the STF subcarrier and two coefficients (i.e., LCGa and LCGc). For example, suppose... , ,in The second vector is a vector containing all seed values ​​for the corresponding frequency hopping sequence. , ,in Na is the number of active subcarriers (e.g., channels used for transmission), the second vector contains the channel indices to be used in the specific symbol, and the starting seed for generating the frequency hopping sequence (e.g., 2804) is... That is, the initial seed of the algorithm, where .

[0363] In some embodiments, for all k values ​​greater than or equal to 2, a temporary (e.g., 8-bit) value Initialized from the previous iteration The seed value is then used. Next, a linear congruent random generator can be used to update the temporary seed value using the following formula:

[0364] (6).

[0365] You can continue to extract P LSBs, where P can be given by the following formula:

[0366] (7)

[0367] DFT sz The number of samples for the symbol is used to create a second temporary seed value using the following formula:

[0368] (8)

[0369] Next, a comparison is made between the three conditions: Greater than or equal to ; Less than or equal to ;as well as Not equal to , where N a This represents the number of data subcarriers in the symbol. In some embodiments, when all three conditions are met, then... and Otherwise, execute a new iteration until all three conditions are met.

[0370] In some embodiments, for each odd value of k and .

[0371] In some embodiments, for each (e.g., BPSK) symbol transmitted as part of frequency hopping sequence 2804 (e.g., fields 2504, 2506, and 2508), , Create vectors , ,in and .

[0372] As an example, for 26 subcarriers (e.g., when SymDur = 120 μs), Figure 23A Option 3 is correct; when SymDur = 60 μs ( Figure 23B Option 2 is correct; or SymDur = 30 μs. Figure 23C Option 1), when When LCGa = 17 and LCGc = 83, and DFTsz is 32 (e.g., since 32 is the minimum number of powers of 2 as the number of adapting subcarriers (26)), the sequence generation outlined above provides the following Qa values:

[0373] 18 5 20 29 19 22 9 24 4 23 26 13 3 6 28 8 27 17 7 10 12 21 11 14 25 15.

[0374] As illustrated by the numerical value Qa, in some embodiments, the frequency hopping sequence generated using the sequence generation outlined above results in no value being repeated. As more symbols are transmitted, the sequence Qa can be repeated (e.g., after 26 pairs of symbols have been transmitted, the next pair of symbols can be reused using subchannel 18).

[0375] As shown by the value Qa, in some embodiments, the first value corresponds to STFsubcarrier=2 +DFTsz / 2.

[0376] As another example, for 26 subcarriers, when When LCGa = 17 and LCGc = 83, and DFTsz = 32, the sequence generation described above provides the following Qb values:

[0377] 19 22 9 24 4 23 26 13 3 6 28 8 27 17 7 10 12 21 11 14 25 15 18 5 20 29.

[0378] As can be seen by comparing sequences Qa and Qb, sequence Qb is a rotated version of sequence Qa, where the last 4 values ​​of sequence Qb are the first 4 values ​​of sequence Qa.

[0379] In some embodiments, the values ​​of LCGa and LCGc are derived from a corresponding predetermined set of possible values. For example, Figure 29A and 29B The possible sets of values ​​for LCGa and LCGc according to embodiments of this disclosure are shown respectively.

[0380] In some embodiments, a synchronization sequence 2802 is transmitted periodically.

[0381] In some embodiments, each packet 2800 transmits a synchronization sequence 2802. For example, in some embodiments, the first field to be transmitted for each packet 2800 is an STF field 2502.

[0382] In some embodiments, the modulation scheme used to transmit the symbols of the synchronization sequence 2802 is the same as the modulation scheme used to transmit the symbol frequency hopping sequence 2804. For example, BPSK (e.g., DBPSK) can be used to transmit all symbols of both the synchronization sequence 2802 and the frequency hopping sequence 2804. In some embodiments, the modulation scheme used to transmit the symbols of the synchronization sequence 2802 may be different from the modulation scheme used to transmit the symbols of the frequency hopping sequence 2804. For example, in some embodiments, the symbols of the frequency hopping sequence 2804 may be transmitted using BPSK (e.g., DBPSK), while the symbols of the synchronization sequence 2802 may be transmitted using PSK, GFSK, BPSK, FSK, ASK, CSS, QAM, APSK, CPS, MSK, or OOK.

[0383] In some embodiments, regardless of the modulation scheme used for symbol transmission, only a single subchannel from the available subchannels is used to transmit symbols at a time, such as... Figure 28 As shown in the figure.

[0384] Figure 30 The transmission 3000 of a plurality of packets 401 according to an embodiment of the present disclosure is illustrated. The processing pipeline 300 can process each of the plurality of packets 401 in the transmission 3000.

[0385] like Figure 30 As shown, in some embodiments, each of the transmitted packets 401 has the same (e.g., fixed) synchronization sequence 2802a (e.g., the STF sequence shown in FIG. 2600) transmitted in the same subchannel (e.g., subchannel 9). Also as Figure 30 As shown, in some embodiments, the frequency hopping sequence 2804 is the same for each of the 401 packets (although the data transmitted may be different).

[0386] Figure 31 The transmission 3100 of a plurality of packets 401 according to an embodiment of the present disclosure is illustrated. The processing pipeline 300 can process each of the plurality of packets 401 in the transmission 3100.

[0387] like Figure 31 As shown, in some embodiments, each of the transmitted packets 401 has the same (e.g., fixed) synchronization sequence 2802a (e.g., the STF sequence shown in FIG. 2600) transmitted for each packet in different sub-channels. Also as Figure 31As shown, in some embodiments, the frequency hopping sequence 2804 of each of the 401 groups may be different. In some embodiments, each of the frequency hopping sequences 2804b, 2804c, and 2804d is a rotated version of the frequency hopping sequence 2804a. In some embodiments, each of the frequency hopping sequences 2804a, 2804b, 2804c, and 2804d is different and not a rotated version of each other.

[0388] Figure 32 The transmission 3200 of a plurality of packets 401 according to embodiments of the present disclosure is illustrated. The processing pipeline 300 can process each of the plurality of packets 401 in the transmission 3200.

[0389] like Figure 32 As shown, in some embodiments, each of the transmitted packets 401 has a different (e.g., fixed or configurable) synchronization sequence 2802 for each packet transmitted on the same subchannel. Also as Figure 32 As shown, in some embodiments, the frequency hopping sequence 2804 of each of the 401 groups changes depending on the content of the synchronization sequence 2802.

[0390] In some embodiments, each of the synchronization sequences 2802a, 2802b, 2802c, and 2802d comprises one or more bits, thereby allowing the selection of different coefficients (e.g., LCGa and LCGc, for example, according to...). Figure 29A and 29B This results in different frequency hopping sequences 2804 being used for associated packets 401.

[0391] Figure 33 The transmission 3300 of a plurality of packets 401 according to an embodiment of the present disclosure is illustrated. The processing pipeline 300 can process each of the plurality of packets 401 in the transmission 3300.

[0392] like Figure 33 As shown, in some embodiments, each of the transmitted packets 401 has a different (e.g., fixed or configurable) synchronization sequence 2802 for transmission on different sub-channels for each packet. Also as... Figure 33 As shown, in some embodiments, the frequency hopping sequence 2804 for each of the 401 packets may be different and may be determined based on the contents of the STF subcarrier and / or synchronization sequence 2802.

[0393] In some embodiments, device 202 may use a first (e.g., fixed or configurable) STF subcarrier (e.g., such as...). Figures 30 to 33 (As shown in the diagram) Data is transmitted to device 252, and can be transferred in a second (e.g., fixed or configurable, such as...) Figures 30 to 33 (As shown in the diagram) it listens for the synchronization sequence from device 252. In some embodiments, the first STF subcarriers and the second STF subcarriers may be the same.

[0394] Figure 34 A block diagram of a modulator 3400 according to an embodiment of the present disclosure is shown. Modulator 302 may be implemented as modulator 3400. Modulator 3400 illustrates a possible implementation of processing pipeline 400.

[0395] like Figure 34 As shown, modulator 3400 includes scrambler block 402, FEC encoder blocks 404a and 404b, interleaver blocks 406a and 406b, DSSS blocks 408a, 408b, 408c and 408d, bit-to-symbol blocks 410a and 410b, single subcarrier mapping blocks 412a and 412b, inverse transform block 414, cyclic prefix block 416 and filter block 418.

[0396] like Figure 34 As shown, in some embodiments, some of the processing blocks can be implemented with multiple instances (e.g., DSSS block 408 may have four instances, which can advantageously allow parallel processing). In some embodiments, a single block instance (e.g., a single DSSS block 408) may be implemented, which may process data sequentially, for example by multiplexing between different inputs, and may switch the block configuration, for example, based on the data being processed (e.g., using DSSS value 2 to process LTF field 2504, using DSSS value 6 to process PHR field 2506, and using a DSSS value selected based on the content of PHR field 2506 to process PHY payload field 2508).

[0397] like Figure 34 As shown, modulator 3400 can process different parts of packet 401 (e.g., in the form of PPDU 2500) in different ways.

[0398] For example, in some embodiments (such as...) Figure 34As shown in the diagram, DSSS blocks 408d and 408c are used to process all contents of STF field 2502 and LTF field 2504 (e.g., without scrambling, FEC encoding, or interleaving) to produce the corresponding chip streams. FEC encoder block 404b, followed by interleaver block 406b, and then DSSS block 408b are used to process all contents of PHR field 2506 (e.g., without scrambling) to produce the corresponding chip stream. PHY payload field 2508 is processed by scrambler block 402, followed by FEC encoder block 404a, interleaver block 406a, and DSSS block 408a to produce the corresponding chip stream.

[0399] The outputs of DSSS blocks 408a, 408b, and 408c are concatenated by concatenated block 3402, and the concatenated chip stream is processed by bit-to-symbol block 410a to produce a symbol stream, which is then mapped to a single carrier (e.g., according to frequency hopping sequence 2804). The chip stream generated by DSSS 408d is processed by bit-to-symbol block 410b to produce a symbol stream, which is then mapped to a single carrier (e.g., mapped to a fixed sub-channel STFsubcarrier).

[0400] The outputs of individual subcarrier mapping blocks 412a and 412b are cascaded by cascade block 3404 to produce a cascaded symbol sequence, which is then processed by inverse transform 414, cyclic prefix block 416 and filter block 418 to produce a TX modulated signal.

[0401] In some embodiments, the modulator 2400 may implement an additional block (not shown), which may be omitted. Figure 34 One or more blocks shown in the image, and / or with Figure 34 The diagram illustrates different ways of processing different parts of the PPDU 2500. For example, in some embodiments, one or more of blocks 402, 404a, 404b, 406a, 406b, 416, 418, 3402, and 3404 may be omitted from the modulator 3400. As another example, some embodiments may include a scrambler block (not shown) to process the PHR field 2506 before the FEC encoder block 404b. Other implementations are also possible.

[0402] In some embodiments, FEC encoder blocks 404a and 404b have the same configuration (e.g., the same write code rate and polynomial, such as convolution encoder 1000). In some embodiments, FEC encoder blocks 404a and 404b each have different configurations (e.g., different write code rates and / or polynomials may be used).

[0403] In some embodiments, interleaver blocks 406a and 406b have the same configuration (e.g., interleaving according to the same algorithm, such as interleaver 1100 implemented according to Equation 2). In some embodiments, interleaver blocks 406a and 406b each have different configurations (e.g., interleaving according to different equations).

[0404] In some embodiments, DSSS blocks 408a, 408b, 408c, and 408d have the same configuration (e.g., the same DSSS value and polarity). In some embodiments, one or more of DSSS blocks 408a, 408b, 408c, and 408d may have a different configuration than another of DSSS blocks 408a, 408b, 408c, and 408d (e.g., different DSSS values ​​and / or polarities may be used). For example, in some embodiments, DSSS blocks 408d and 408c may use a fixed DSSS value 2, DSSS block 408b may use a fixed DSSS value 6, and DSSS block 408a may use a DSSS value selected from a set depending on the content of PHR field 2506 (e.g., which contains DSSS values ​​2, 4, and 6). In some of these embodiments, the polarity used by each of the DSSS blocks 408a, 408b, 408c, and 408d may be equal to each other, may be different, or may be changed based on one or more factors (e.g., in a deterministic manner).

[0405] In some embodiments, bit-to-symbol blocks 410a and 410b have the same configuration (e.g., using the same modulation scheme (e.g., BPSK) and the same symbol duration SymDur). In some embodiments, bit-to-symbol blocks 410a and 410b each have different configurations (e.g., bit-to-symbol block 410a may use BPSK as the modulation scheme, while bit-to-symbol block 410b may use a different modulation scheme than BPSK, such as PSK, GFSK, FSK, ASK, CSS, QAM, APSK, CPS, MSK, or OOK, and / or may use a different symbol duration SymDur).

[0406] In some embodiments, individual subcarrier mapping blocks 412a and 412b may have different configurations. For example, in some embodiments, individual subcarrier mapping block 412a may have a CH that changes according to a frequency hopping sequence (e.g., based on STFsubcarrier, LCGa, and LCGc). sel A single subcarrier mapping block 412a may have a fixed CH for the entire PPDU 2500. sel .

[0407] In some embodiments, the modulator 3400 may receive, for example, some or all of the PHY payload field 2508 from an upper layer (e.g., a MAC layer). For instance, in some embodiments, the modulator 3400 may receive all of the PSDU field 2540 from the MAC layer and may generate all of the PPDU tail field 2542 and padding field 2544. In some embodiments, the modulator 3400 may generate all of the PHY payload field 2508. For instance, in some embodiments, the modulator 3400 may generate all of the PHY payload field 2508 during a test mode. Other implementations are also possible.

[0408] In some embodiments, the modulator 3400 may receive, for example, some or all of the PHR field 2506 from an upper layer (e.g., the MAC layer). For instance, in some embodiments, the modulator 3400 may receive, for example, all of the data rate field 2520 and the frame length field 2522 from the MAC layer, and may generate all of the HCS field 2524 and the tail field 2526. In some embodiments, the modulator 3400 may generate all of the PHR field 2506. Other embodiments are also possible.

[0409] In some embodiments, the modulator 3400 may receive, for example, some or all of the STF field 2502 and / or LTF field 2504 from an upper layer (e.g., a MAC layer). For instance, in some embodiments, the modulator 3400 may receive one or more (e.g., the last) bits of the STF field 2502 from the MAC layer, for example, to select the frequency hopping sequence 2804, and the content of the LTF field 2504 may be determined based on such bits. In some embodiments, the modulator 3400 may generate all of the STF field 2502 and / or LTF field 2504. Other embodiments are also possible.

[0410] Figure 35 A block diagram of a demodulator 3500 according to an embodiment of the present disclosure is shown. A demodulator 304 may be implemented as a demodulator 3500. The demodulator 3500 illustrates a possible implementation of a processing pipeline 500.

[0411] In some embodiments, demodulator 3500 is configured to demodulate the modulated signal generated by modulator 3400, for example, by processing different portions of the modulated signal in different ways, for example, to recover the PPDU (e.g., 2500), such as... Figure 35 As shown in the image.

[0412] like Figure 35As shown, the demodulator 3500 includes a filter block 502, an STF synchronization block 3502, a Fourier transform block 504, carrier extraction blocks 506a and 506b, inverse DSSS blocks 508a and 508b, deinterleaving blocks 510a and 510b, symbol-to-metric blocks 512a and 512b, FEC decoder blocks 514a and 514b, a descrambler block 516, and splitters 3504 and 3506.

[0413] like Figure 35 As shown, in some embodiments, some of the processing blocks can be implemented with multiple instances (e.g., inverse DSSS block 508 may have two instances, which can advantageously allow parallel processing). In some embodiments, a single block instance (e.g., a single inverse DSSS block 508) can be implemented, which can process data sequentially, for example by multiplexing between different inputs, and it is possible to switch the block configuration, for example, based on the data being processed (e.g., using DSSS value 2 to process LTF field 2504, using DSSS value 6 to process PHR field 2506, and using a DSSS value selected based on the content of PHR field 2506 to process PHY payload field 2508).

[0414] like Figure 35 As shown, modulator 3500 can process different parts of packet 401 (e.g., in the form of PPDU 2500) in different ways.

[0415] In some embodiments, the STF synchronization block 3502 receives a signal from the antenna 308 (e.g., after filtering (e.g., 502) or directly from the ADC (e.g., 330)). The STF synchronization block 3502 monitors the received signal (e.g., after filtering by the filtering block 502) to detect the STF field (e.g., 2502) of the PPDU (e.g., 2500) in a particular subcarrier channel STF subcarrier (e.g., which may be fixed or dynamically variable (e.g., for each packet, or, for example, according to a frequency hopping sequence)).

[0416] Once synchronization block 3502 determines that the received sequence matches the predetermined STF value (e.g., according to...), Figure 26 Once an STF match is achieved, the Fourier transform block 504 can begin processing the received packets. For example, in some embodiments, the STF synchronization block 3502 can signal the time / sample position at which the Fourier transform block 504 begins performing an FFT on the received samples (e.g., the output of the filter block 502) upon STF matching.

[0417] like Figure 35As shown, demodulator 3500 can process different portions of PPDU 2500 in different ways (e.g., in the opposite / inverse manner to modulator 3400). For example, splitter 3502 can direct symbols associated with STF field 2502 to be processed by carrier extraction block 506b (e.g., using the same STF subcarrier CH as used by single subcarrier mapping block 412b). sel The remaining symbols are then processed by the inverse DSSS block 508b (e.g., using the same DSSS values ​​and polarities used by the DSSS block 408d), while the remaining symbols are guided to be processed by the carrier extraction block 506a (e.g., using CH based on the same frequency hopping sequence as the single subcarrier mapping block 412a). sel ), and then processed by the inverse DSSS block 508a (e.g., using the same DSSS values ​​and polarities used by DSSS blocks 408a, 408b and 408c, depending on which of fields 2504, 2506 and 208 is being processed).

[0418] Splitter 3506 can direct symbols associated with PHY payload field 2508 to be processed by deinterleaver block 510a, followed by symbol bit metric block 512a, followed by FEC decoder block 514a, followed by descrambler block 516; and simultaneously direct symbols associated with PHR field 2506 to be processed by deinterleaver block 510b, followed by symbol bit metric block 512b, followed by FEC decoder block 514b.

[0419] In some embodiments, demodulator 3500 places the demodulated data (e.g., STF field 2502 from the output of inverse DSSS block 508b, LTF field 2504 from the output of splitter 3506, PHR field 2506 from the output of FEC decoder 514b, and / or PHY payload field 2508 from the output of descrambler block 516) in a receiver (RX) first-in-first-out (FIFO) buffer for further processing / use (e.g., by the same controller / demodulator that performed the demodulation, or by another controller). In some embodiments, some fields (e.g., STF field 2502 and / or LTF field 2506) may not be placed in the FIFO for further processing.

[0420] In some embodiments, such as where the STF field 2502 is a fixed (e.g., predetermined) sequence (e.g., without any configurable bits), blocks 3504, 506b, and 508b may be omitted, and the data associated with the STF field 2502 may not be directly recoverable. Alternatively, in some such embodiments, the STF synchronization block 3502 may implement a function to generate a match and an indication of the starting position for processing the Fourier transform block 504, which may be sufficient to indirectly determine the value of the STF field 2502.

[0421] In some embodiments, the entire contents of STF field 2502 (including the subcarriers used to transmit STF field 2502) are predetermined and known for STF synchronization block 2502 to enable matching (performed packet detection) and / or frequency offset determination. In some embodiments, STF field 2502 may include additional bits (not used for packet detection and / or frequency offset determination) that can be used for other purposes, such as selecting a frequency hopping sequence (e.g., to be followed to receive the remainder of packet 401).

[0422] In some embodiments, blocks 506b and 508b may process only some bits of the STF field 2502 (e.g., the last two bits) (e.g., ignoring the remaining bits of the STF field 2502).

[0423] Figure 36 A block diagram of a demodulator 3600 according to an embodiment of the present disclosure is shown. Demodulator 304 may be implemented as demodulator 3600.

[0424] Demodulator 3600 operates in a similar manner to demodulator 3400. Demodulator 3600 illustrates a possible implementation of processing pipeline 600.

[0425] Figure 37 A flowchart illustrating an embodiment method 3700 for receiving packets (e.g., 401) according to an embodiment of the present disclosure is shown. Method 3700 may be performed, for example, by demodulator 304, such as demodulator 3500 or 3600.

[0426] During step 3702, the demodulator (e.g., 304, 3500, 3600) monitors a predetermined sub-channel for detecting, for example, a predetermined and fixed STF sequence (e.g., using STF synchronization block 3502).

[0427] During step 3704, in response to the detection of a match in the STF sequence, the start of a packet is detected (e.g., using STF synchronization block 3502).

[0428] During step 3706, the transition from the STF sequence to the LTF sequence is detected or determined (e.g., using STF synchronization block 3502).

[0429] During step 3708, coarse and fine frequency offsets are determined based on the STF and LTF sequences (e.g., using STF synchronization block 3502).

[0430] During step 3710, the packets (e.g., the symbols of the packets) are de-rotated based on the estimated frequency offset (e.g., using STF synchronization block 3502). For example, in some embodiments, the symbols of the packets are mixed in frequency to eliminate the estimated frequency offset performed during STF. The resulting symbols may not have a significant frequency offset (e.g., they may actually be baseband symbols).

[0431] During step 3712, triggering is used to select CH. sel A channel indexing selection scheme (e.g., based on frequency hopping sequence 2804) is used to select sub-channels for symbol extraction. For example, in some embodiments, the indexing selection scheme uses LCGa and LCGc, along with an STF subcarrier, to determine the frequency hopping sequence.

[0432] During step 3714, symbol pairs are extracted from the channels selected during step 3712 (e.g., by using the selected CHs for blocks 506a and 506b). sel ), and then process it further (e.g., as Figure 35 and 36 (As shown in the image).

[0433] Figure 38 A flowchart illustrating an embodiment method 3800 for generating a frequency hopping sequence (e.g., 2804) according to an embodiment of the present disclosure is shown. Method 3800 may be performed, for example, by a modulator 304 (e.g., by a single subcarrier mapping block 412), or by a demodulator 3500 or 3600.

[0434] During step 3802, the demodulator (e.g., 304, 3400, e.g., via block 412) configures the subcarrier channel (e.g., STF subcarrier) and one or more coefficients (e.g., LCGa and LCGc) for transmitting the synchronization sequence (e.g., 3802). In some embodiments, the STF subcarrier and / or one or more coefficients are known a priori, for example, through out-of-band reception, or by user programming by the semiconductor manufacturer or device (e.g., 202, 252), etc.

[0435] During step 3804, a starting seed for determining the frequency hopping sequence (e.g., 2804) is selected based on the STF subcarrier received during step 3802. For example, suppose... , ,in The second vector is a vector containing all seed values ​​for the corresponding frequency hopping sequence. , ,in Na is the number of active subcarriers (e.g., subchannels used for transmission), the second vector contains the subchannel indices to be used in the specific symbol, and the starting seed for generating the frequency hopping sequence (e.g., 2804) is... That is, the initial seed of the algorithm, where .

[0436] During step 3806, variable S is initialized. tmp In some embodiments, S tmp Initialized from the previous iteration The seed value.

[0437] During step 3808, variable S is updated using linear congruent random generation based on one or more coefficients received during step 3802. tmp For example, in some embodiments, variable S is updated according to Equation 6. tmp .

[0438] During step 3810, extract from variable S tmp P LSBs and store them in variable r tmp In some embodiments, P may be given by Equation 7. In some embodiments, the extraction of P LSBs may be performed according to Equation 8.

[0439] During step 3812, r tmp Comparison based on three conditions:

[0440] 1. ;

[0441] 2. ;as well as

[0442] 3. ,

[0443] Where N a This represents the number of data subcarriers in the symbol. In some embodiments, when all three conditions are met, then... and The settings are made during step 3814. Otherwise, a new iteration is performed until all three conditions are met.

[0444] In some embodiments, vector J contains a sequence of sub-channels (e.g., j(k) represents the next channel), and vector S is a seed vector.

[0445] Seeds are selected using linear congruent random generation, for example, as in method 3800. Some embodiments advantageously generate frequency-hopping sequences that do not access any channels before repetition. In some embodiments, the sequence is repeated once it has traversed all channels in the set.

[0446] By using an STF subcarrier as a seed for generating frequency-hopping sequences, some embodiments advantageously generate different sequences when using different channels to transmit synchronization sequences, such that the different sequences can advantageously be orthogonal to each other or substantially do not interfere with each other. By generating such different frequency-hopping sequences, some embodiments can advantageously allow the geographical coexistence of multiple networks without substantially affecting the transmission error rate. In some embodiments, such different frequency-hopping sequences are rotated versions of each other.

[0447] In some embodiments (e.g., such as) Figure 2 As shown in the diagram, data can be transferred between two devices (e.g., between devices 202 and 252). For example, Figure 39 A flowchart illustrating an embodiment method 3900 for packet switching according to an embodiment of the present disclosure is shown.

[0448] During step 3902, device 202a uses a predetermined subchannel x for transmitting STF field 2502. ch And use a predetermined frequency hopping sequence (e.g., based on a predetermined x) LCGa x LCGc and x ch For example, 3800 is used to transmit (e.g., broadcast) packets (e.g., 401, e.g., 2500). In some embodiments, the PHY payload 2508 of the broadcast packet may contain a command / request for data.

[0449] During step 3920, device 252a monitors the predetermined sub-channel x ch Packet detection is performed (e.g., using the corresponding STF synchronization block 3502). Upon detecting a broadcast packet (e.g., in response to a command / request for data), device 252a performs carrier sensing (e.g., listen-before-speak) to transmit packets (e.g., 401, e.g., 2500), which may be acknowledgment (ACK) packets or data packets and may contain data (e.g., sensed data).

[0450] Once device 252a detects subchannel x chIf the device is idle, then device 252a begins using the same subchannel x during step 3924 as during step 4002. ch The same frequency hopping sequence is used to transmit (e.g., unicast) packets.

[0451] During step 3904, demonstration 202a listens for packets from device 252a (e.g., monitors subchannel x). ch (For STF detection).

[0452] This process can be repeated periodically, such as... Figure 39 As shown in the image.

[0453] In some embodiments, method 3900 may be synchronous. In some embodiments, method 3900 may be asynchronous. For example, in some embodiments, steps 3902 and 3920 may be omitted, and device 252a may transmit packets asynchronously (e.g., when data becomes available) while device 202a (e.g., continuously) listens during step 3904.

[0454] exist Figure 39 In some embodiments, devices 202a and 252 each use the same STF subcarrier and the same frequency hopping sequence. In some embodiments, devices 202a and 252 may use different STF subcarriers and / or frequency hopping sequences for transmission. For example, Figure 40 A flowchart illustrating an embodiment method 4000 for packet switching according to an embodiment of the present disclosure is shown. Method 4000 is similar to method 3900. However, in method 4000, device 252a uses an expression equal to y during step 4024. ch The device 252a may also use a different frequency hopping sequence (e.g., y) to transmit packets using an STF subcarrier, which is different from the STF subcarrier used by device 202a during step 3902. LCGa and y LCGc Different from x LCGa and x LCGc Therefore, during step 4004, device 202a listens to packets and monitors subchannel y. ch And use the frequency hopping sequence corresponding to step 4024.

[0455] Some embodiments can transmit data from one device to multiple devices, from multiple devices to one device, or from multiple devices to multiple devices, for example, within the same geographical area. For example, Figure 41 A communication system 4100 according to an embodiment of the present disclosure is shown. For example... Figure 41As shown, the communication system 4100 includes multiple devices 252 (in Figure 41 Only two are shown in the image) and a single device 202 is part of network 4110.

[0456] exist Figure 41 In this embodiment, all devices 252 communicate with device 202, but may not communicate with each other.

[0457] In some embodiments, all packet exchanges (e.g., 401) between device 202 and devices 252a and 252b use the same fixed sub-channel (e.g., STF subcarrier) to transmit the synchronization sequence (e.g., 2802). Therefore, in some embodiments, device 202a may use a predetermined STF subcarrier (e.g., sub-channel 9) to transmit (e.g., broadcast) the synchronization sequence (e.g., 2802) to, for example, all devices 252, for example, periodically (e.g., as STF field 2502 for each packet); and each of devices 252 (e.g., 252a and 252b) may use the same fixed sub-channel (e.g., sub-channel 9) for transmitting the synchronization sequence 2802 (e.g., for transmitting STF field 2502) to transmit data (e.g., unicast) to device 202a synchronously or asynchronously, sequentially, or simultaneously. In some of these embodiments, the frequency hopping sequence 2804 transmitted by each of the devices (e.g., 202a, 252a, and 252b) may be the same for packet (e.g., 401, 2800) transmissions. In some of these embodiments, carrier sensing or other listen-before-speak mechanisms (e.g., to avoid collisions) may be performed before attempting to transmit packets.

[0458] Figure 42 A flowchart illustrating an embodiment method 4200 for packet switching according to an embodiment of the present disclosure is shown. Method 4200 is similar to method 3900. However, method 4200 includes a plurality of means 252a (e.g., as in network 4110).

[0459] Steps 3902, 3920, 3922, and 3924 can be related to... Figure 39 Performed in a similar or identical manner as described. However, in method 4200, device 252b also monitors the predetermined sub-channel x during step 4240. ch Packet detection is performed (e.g., using the corresponding STF synchronization block 3502). Upon detection of a broadcast packet (e.g., and in response to a command / request for data), each of devices 252a and 252b performs carrier sensing (e.g., listen-before-speak) during steps 3922 and 4242, respectively, to transmit the corresponding packet (e.g., 401, e.g., 2500).

[0460] exist Figure 42 In one example, device 252a begins using the same subchannel x during step 3924 as device 252b during step 3902. ch The same frequency hopping sequence is used to transmit unicast packets. Due to the subchannel (x ch Because device 252b is busy transmitting STF data, it will wait until the transmission during step 3924 is complete, and then begin using the same subchannel x as during step 3902 during step 4244. ch They use the same frequency hopping sequence to transmit packets.

[0461] During step 4204, device 202a listens for packets from devices 252a and 252b. In some embodiments, device 202a may identify the origin / source of each packet based on the id field of each packet (e.g., in the corresponding PHY payload field 2508).

[0462] In some embodiments, method 4200 may be synchronous. In some embodiments, method 4200 may be asynchronous. For example, in some embodiments, steps 3902, 3920, and 4240 may be omitted, and devices 252a and 252b may transmit packets asynchronously (e.g., when data becomes available) while device 202a (e.g., continuously) listens during step 4204.

[0463] In some embodiments, the frequency hopping sequence 2804 used by each of devices 252a and 252b may be different, for example, when the same fixed subchannel is used for synchronization sequence 2802 (e.g., based on unique LCGa and / or LCGc values) or when different channels are used for synchronization sequence 2802 (e.g., based on a unique STF subcarrier with the same or different coefficients LCGa and / or LCGc). For example, Figure 43 A flowchart illustrating an embodiment method 4300 for packet switching according to an embodiment of the present disclosure is shown. Method 4300 is similar to method 4200. However, method 4300 includes multiple means 252 (e.g., 252a and 252b) that perform transmissions simultaneously.

[0464] Steps 3902, 3920, 4240, 3922, and 4242 can be related to... Figure 42 Performed in a similar or identical manner as described. However, in method 4200, device 252b begins transmitting packets during step 4344, which at least partially overlaps with the packet transmission of device 252a during step 4324.

[0465] During step 4324, device 252a will subchannel xch The detection indicates that the channel is idle, and it is in sub-channel x. ch The synchronization sequence is transmitted (e.g., 2802, e.g., STF field 2502). During step 4342, device 252b transmits the sub-channel x... ch The detection indicates the channel is busy, and subchannel x will continue to be monitored. ch until sub-channel x ch The subchannel xch becomes idle (e.g., once device 252a has completed the transmission of its synchronization sequence). Once the subchannel xch becomes idle, device 252b begins using a different frequency hopping sequence during step 4344 than device 252a did during step 4324 (e.g., (y...). LCGa y LCGc ) can be different from (z) LCGa z LCGc )) to transmit packets.

[0466] By using different frequency hopping sequences, some embodiments advantageously allow for a reduction in the waiting time before the device begins transmission (e.g., carrier sensing step 4342 may be shorter than carrier sensing step 4242).

[0467] In some embodiments, such as when different sub-channels are used to transmit the corresponding synchronization sequences, step 4344 can be performed simultaneously with step 4324.

[0468] In some embodiments, step 4344 may use the same frequency hopping sequence as step 4324, for example, by delaying the start of transmission after a period of time during the transmission in step 4324, which may result in a rotated frequency hopping sequence (e.g., due to a start time offset).

[0469] Figure 44 The symbol transmission of a communication system 3900 according to an embodiment of the present disclosure is illustrated. Specifically, Figure 44 The data symbols transmitted from device 252a, the data symbols transmitted from device 252b, broadband burst interference 4402, and narrowband interference 4404 are shown.

[0470] In some embodiments, device 202a may advantageously recover data bits from data symbols received from device 252a, despite the presence of broadband burst interference 4402, narrowband interference 4404, and interference source symbols (e.g., symbols from device 252b and possibly from other devices 252 (not shown)).

[0471] Similarly, in some embodiments (e.g., as in method 4300), in addition to recovering data bits from data symbols received from device 252b, device 202a may advantageously recover (e.g., in parallel) data bits from data symbols received from device 252b.

[0472] As in Figure 44 As can be seen, narrowband interference 4404 can correspond to the transmission of synchronization sequence 2804 (e.g., during step 4344), thus demonstrating the coexistence of transmissions from multiple devices without (e.g., significantly) degrading the performance of data transmission.

[0473] like Figure 44 As shown, using different frequency hopping sequences (e.g., due to rotation or otherwise) can advantageously help avoid conflicts between simultaneous or temporally overlapping transmissions (e.g., from multiple devices 252 to device 202).

[0474] Figure 45 A communication system 4500 according to an embodiment of the present disclosure is shown. The communication system 4500 operates in a manner similar to communication 200. However, the communication system 4500 includes multiple networks (4510, 4512) that overlap in the same geographical location. Although in Figure 45 Only two devices are shown for each network, but each network may contain more than two devices. In some embodiments, a device (e.g., 202 or 252) may belong to more than one network. Other embodiments are also possible.

[0475] like Figure 45 As shown, each device 252 can communicate with its corresponding device 202 within a corresponding network. In some such embodiments, the devices may not communicate across networks (e.g., device 202a does not communicate with device 252b, and device 202b does not communicate with device 202b).

[0476] Packet switching in each of networks 4510 and 4512 can be performed, for example, in a manner similar to that in methods 3900, 4000, 4200, or 4300.

[0477] like Figure 44 As can be seen, when networks overlap in the same geographical location (e.g. Figure 45 As shown in the diagram, the devices (e.g., 202, 252) can still successfully transmit and receive packets, for example, in the presence of other transmissions and / or interference. For instance, in some embodiments, communication between devices 202a and 252a (and similarly between devices 202b and 252b) enjoys the same capability, i.e., the ability to recover data bits from received symbols (e.g., to match) despite burst interference, narrowband interference, and interference source symbols. Figure 44 (Similar to the example shown).

[0478] In some embodiments, each communication between device 202 and the corresponding device 252 in each of the networks (e.g., 4510, 4512) may use a different subchannel for the synchronization sequence 2802. Using a single subchannel to transmit the synchronization sequence 2802 advantageously allows multiple networks to coexist in the same geographical location with low risk of collision.

[0479] Figure 46 A communication system 4600 according to an embodiment of the present disclosure is shown. The communication system 4600 operates in a manner similar to that of communication 4500. However, the communication system 4600 includes means (e.g., 252a) in multiple networks (e.g., 4610, 4612).

[0480] In some embodiments, each network can be configured in different ways (using the same or different STF subcarriers, the same or different LCGa and LCGc coefficients, the same or different STF sequences, etc.).

[0481] In some embodiments, the actual synchronization sequence 2802 for each network (4610 and 4612) may be different (e.g., to identify each network). In some such embodiments, the frequency hopping sequence 2804 may be different for each network (e.g., 4610 and 4612), even when the same fixed subchannel is used for the synchronization sequence 2802 (e.g., based on unique LCGa and LCGc values).

[0482] Packet switching in each of networks 4610 and 4612 can be performed, for example, in a manner similar to that in methods 3900, 4000, 4200, or 4300.

[0483] In some embodiments, communication between device 252a and device 202a (and similarly between devices 252a and 202b) enjoys the same capability, i.e., the ability to recover data bits from received symbols (e.g., to match) despite the presence of burst interference, narrowband interference, and interference source symbols. Figure 44 (Similar to the example shown).

[0484] In some embodiments, the device may operate, for example, at different times depending on different instances. For instance, in an embodiment, the device (e.g., 252a) may operate using method 3900 or 4000 when in network 200, and may also operate according to method 4200 or 4300. In some embodiments, the device (e.g., 252a) may simultaneously be part of different networks (e.g., 4110, 4610, 4612) and operate in the same geographic area of ​​another network (e.g., 4510). Other implementations are possible.

[0485] In some embodiments, method 2400 may be used, for example, to negotiate the settings of any network of communication systems 200, 3900, 4100, 4500 and 4600.

[0486] Examples of embodiments of this disclosure are outlined herein. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0487] Example 1. A method comprising: transmitting a first synchronization sequence by a first means in a single synchronization channel among a plurality of channels; and, after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence by the first means each time using a single channel among the plurality of channels according to a frequency hopping sequence.

[0488] Example 2. According to the method of Example 1, wherein the frequency hopping sequence includes an initial channel for transmitting the first data, wherein the initial channel of the frequency hopping sequence is equal to the synchronization channel.

[0489] Example 3. The method according to one of Examples 1 or 2, wherein the plurality of channels comprises N channels, where N is a positive integer, and wherein the frequency hopping sequence traverses the N channels in the first N frequency hoppings of the frequency hopping sequence.

[0490] Example 4. The method according to one of Examples 1 to 3, wherein the frequency hopping sequence does not contain consecutive equal channels.

[0491] Example 5. The method according to one of Examples 1 to 4, wherein the frequency hopping sequence comprises consecutive equal channels.

[0492] Example 6. The method according to any one of Examples 1 to 5, wherein transmitting the first synchronization sequence and the first data comprises transmitting the first synchronization sequence and the first data sequentially in an uninterrupted manner.

[0493] Example 7. The method according to one of Examples 1 to 6, wherein transmitting the first synchronization sequence includes transmitting the short training field (STF) of the first packet, and wherein transmitting the first data includes transmitting the header field and payload field of the first packet.

[0494] Example 8. A method according to one of Examples 1 to 7, wherein transmitting the STF includes transmitting the STF using direct sequence spread spectrum (DSSS) having a first DSSS value, and wherein transmitting the header field includes transmitting the header field using a DSSS having a second DSSS value different from the first DSSS value.

[0495] Example 9. A method according to one of Examples 1 to 8, wherein transmitting the payload field includes transmitting the payload field using a DSSS with a third DSSS value based on the content of the header field.

[0496] Example 10. The method according to one of Examples 1 to 9, wherein the second DSSS value is equal to 6 and the first DSSS value is equal to 2.

[0497] Example 11. The method according to one of Examples 1 to 10, wherein transmitting the first data includes transmitting the long training field (LTF) of the first packet before transmitting the header field and the payload field.

[0498] Example 12. A method according to one of Examples 1 to 11, wherein transmitting the STF includes transmitting the STF using direct sequence spread spectrum (DSSS) with a first DSSS value, and wherein transmitting the LTF includes transmitting the LTF using a DSSS with the first DSSS value.

[0499] Example 13. The method according to one of Examples 1 to 12, wherein the LTF contains 26 bits.

[0500] Example 14. The method according to any one of Examples 1 to 13, further comprising: receiving second data from a MAC layer; and scrambling the second data to generate scrambled data, wherein transmitting the payload field includes transmitting the payload field based on the scrambled data.

[0501] Example 15. A method according to any one of Examples 1 to 14, further comprising: generating a first mapped symbol sequence containing symbols of the STF; generating a second mapped symbol sequence containing symbols of the header field and the payload field; concatenating the first mapped symbol sequence and the second mapped symbol sequence to generate a concatenated sequence; performing an inverse transform on the concatenated sequence to generate a sample stream; and applying a cyclic prefix to the sample stream, wherein transmitting the first synchronization sequence and the first data includes transmitting the first synchronization sequence and the first data based on the sample stream.

[0502] Example 16. A method according to one of Examples 1 to 15, wherein the synchronization sequence comprises a plurality of symbols of a first type, and wherein the first data comprises a plurality of symbols of the first type.

[0503] Example 17. The method according to one of Examples 1 to 16, wherein the symbol of the first type is an orthogonal frequency division multiplexing (OFDM) symbol encoded using differential binary phase shift keying (DBPSK).

[0504] Example 18. A method according to one of Examples 1 to 17, wherein the synchronization sequence comprises a plurality of symbols of a first type, and wherein the first data comprises a plurality of symbols of a second type, the second type being different from the first type.

[0505] Example 19. The method according to one of Examples 1 to 18, wherein the symbol of the second type is an orthogonal frequency division multiplexing (OFDM) symbol encoded using binary phase shift keying (BPSK).

[0506] Example 20. The method according to one of Examples 1 to 19, wherein the synchronization sequence is transmitted in symbol pairs using direct sequence spread spectrum (DSSS).

[0507] Example 21. A method according to one of Examples 1 to 20, wherein each symbol of the synchronization sequence is a binary phase shift keying (BPSK) symbol.

[0508] Example 22. The method according to one of Examples 1 to 21, wherein the plurality of channels are a plurality of orthogonal frequency division multiplexing (OFDM) channels.

[0509] Example 23. The method according to one of Examples 1 to 22, further comprising generating the frequency hopping sequence based on the synchronization channel.

[0510] Example 24. The method according to one of Examples 1 to 23, further comprising generating the frequency hopping sequence based on a first coefficient and a second coefficient.

[0511] Example 25. The method according to one of Examples 1 to 24, wherein: the first coefficient is selected from a set containing 17, 29, 37, 41, 53, 61, 73 or 89; and the second coefficient is selected from a set containing 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113 or 127.

[0512] Example 26. The method according to one of Examples 1 to 25, wherein generating the frequency hopping sequence further comprises generating the frequency hopping sequence based on the synchronization channel.

[0513] Example 27. The method according to one of Examples 1 to 26, further comprising using a linear congruent random generator to generate the frequency hopping sequence.

[0514] Example 28. The method according to any one of Examples 1 to 27, further comprising, after transmitting the first data, having the first device monitor the synchronization channel for detecting a second synchronization sequence.

[0515] Example 29. The method according to one of Examples 1 to 28, wherein the second synchronization sequence is equal to the first synchronization sequence.

[0516] Example 30. The method according to one of Examples 1 to 29, further comprising, in response to detecting the second synchronization sequence, processing by the first means a second packet containing the second synchronization sequence.

[0517] Example 31. The method according to one of Examples 1 to 30, wherein processing the second packet includes processing the header field and payload field of the second packet according to the frequency hopping sequence.

[0518] Example 32. The method according to any one of Examples 1 to 31, further comprising, after processing the second packet, the first device transmitting a third synchronization sequence in the synchronization channel.

[0519] Example 33. The method according to one of Examples 1 to 32 further comprises: receiving the second synchronization sequence; and using the received second synchronization sequence to determine the frequency offset.

[0520] Example 34. The method according to one of Examples 1 to 33, wherein the plurality of channels consists of 12, 26, 54 or 104 channels.

[0521] Example 35. The method according to one of Examples 1 to 34, wherein none of the plurality of channels is a pilot channel for transmitting pilot waveforms.

[0522] Example 36. The method according to one of Examples 1 to 35, wherein the first synchronization sequence comprises 160 chips.

[0523] Example 37. The method according to any one of Examples 1 to 36, further comprising: waking the first device from a sleep mode, wherein transmitting the first synchronization sequence includes transmitting the first synchronization channel after waking from the sleep mode; and after transmitting the first synchronization sequence, switching the first device back to the sleep mode.

[0524] Example 38. The method according to one of Examples 1 to 37, wherein the first data includes the location data of the first device.

[0525] Example 39. The method according to one of Examples 1 to 38, further comprising tracking the first device based on the location data.

[0526] Example 40. The method according to one of Examples 1 to 39, further comprising collecting health data of an animal by the first device, wherein the first data includes the health data.

[0527] Example 41. Soil data is collected by the first device according to one of Examples 1 to 40, wherein the first data includes soil data.

[0528] Example 42. The method according to one of Examples 1 to 41, wherein the first data includes data indicating whether the parking space is being used.

[0529] Example 43. The method according to one of Examples 1 to 42, further comprising tracking the status of the parking space based on the first data.

[0530] Example 44. The method according to one of Examples 1 to 43, wherein the first data includes metering data associated with the use of electricity, water, or gas.

[0531] Example 45. A method comprising: monitoring a single synchronization channel among a plurality of channels by a first means for detecting a first synchronization sequence; and in response to detecting the first synchronization sequence, extracting a first data symbol associated with the first synchronization sequence each time using a single channel among the plurality of channels according to a frequency hopping sequence.

[0532] Example 46. The method according to Example 45, wherein the frequency hopping sequence includes an initial channel for receiving an initial symbol in the first data symbol, wherein the initial channel of the frequency hopping sequence is equal to the synchronization channel.

[0533] Example 47. The method according to one of Examples 45 or 46, wherein the plurality of channels comprises N channels, where N is a positive integer, and wherein the frequency hopping sequence traverses the N channels in the first N frequency hoppings of the frequency hopping sequence.

[0534] Example 48. The method according to one of Examples 45 to 47, wherein the frequency hopping sequence does not contain consecutive equal channels.

[0535] Example 49. The method according to one of Examples 45 to 48, wherein the frequency hopping sequence comprises consecutive equal channels.

[0536] Example 50. The method according to one of Examples 45 to 49, wherein receiving the first synchronization sequence and the first data symbol comprises receiving the first synchronization sequence and the first data symbol sequentially in an uninterrupted manner.

[0537] Example 51. A method according to one of Examples 45 to 50, wherein receiving the first synchronization sequence includes receiving a short training field (STF) of the first packet, and wherein receiving the first data symbol includes receiving a header field and a payload field of the first packet.

[0538] Example 52. A method according to one of Examples 45 to 51, wherein receiving the STF includes receiving the STF using a direct sequence spread spectrum (DSSS) having a first DSSS value, and wherein receiving the header field includes receiving the header field using a DSSS having a second DSSS value different from the first DSSS value, the method further comprising: determining bits of the STF based on the first DSSS value; and determining bits of the header field based on the second DSSS value.

[0539] Example 53. A method according to one of Examples 45 to 52, wherein receiving the payload field includes receiving the payload field using a DSSS with a third DSSS value based on the content of the header field.

[0540] Example 54. A method according to one of Examples 45 to 53, wherein the second DSSS value is equal to 6 and the first DSSS value is equal to 2.

[0541] Example 55. The method according to one of Examples 45 to 54, wherein receiving the first data symbol includes receiving the long training field (LTF) of the first packet before receiving the header field and the payload field.

[0542] Example 56. The method according to one of Examples 45 to 55, wherein the LTF contains 26 symbols.

[0543] Example 57. A method according to one of Examples 45 to 56, wherein receiving the STF includes receiving the STF using a direct sequence spread spectrum (DSSS) having a first DSSS value, and wherein receiving the LTF includes receiving the LTF using a DSSS having the first DSSS value, the method further comprising: determining bits of the STF based on the first DSSS value; and determining bits of the LTF based on the first DSSS value.

[0544] Example 58. A method according to one of Examples 45 to 57, further comprising: performing a descrambling operation based on the symbol of the payload field; determining bits of the payload field based on the descrambling operation; and determining bits of the header field without performing a descrambling operation.

[0545] Example 59. A method according to one of Examples 45 to 58, wherein the synchronization sequence comprises a plurality of symbols of a first type, and wherein the first data symbol comprises a plurality of symbols of the first type.

[0546] Example 60. The method according to one of Examples 45 to 59, wherein the symbol of the first type is an orthogonal frequency division multiplexing (OFDM) symbol encoded using differential binary phase shift keying (DBPSK).

[0547] Example 61. A method according to one of Examples 45 to 60, wherein the synchronization sequence comprises a plurality of symbols of a first type, and wherein the first data symbols comprise a plurality of symbols of a second type, the second type being different from the first type.

[0548] Example 62. The method according to one of Examples 45 to 61, wherein the symbol of the second type is an orthogonal frequency division multiplexing (OFDM) symbol encoded using binary phase shift keying (BPSK).

[0549] Example 63. The method according to one of Examples 45 to 62, wherein the first synchronization sequence comprises 160 symbols.

[0550] Example 64. A method according to one of Examples 45 to 63, wherein the synchronization sequence uses direct sequence spread spectrum (DSSS) in a symbol pair.

[0551] Example 65. The method according to one of Examples 45 to 64, wherein each symbol of the synchronization sequence is a binary phase shift keying (BPSK) symbol.

[0552] Example 66. The method according to one of Examples 45 to 65, wherein the plurality of channels are a plurality of orthogonal frequency division multiplexing (OFDM) channels.

[0553] Example 67. The method according to one of Examples 45 to 66, further comprising generating the frequency hopping sequence based on the synchronization channel.

[0554] Example 68. The method according to one of Examples 45 to 67, further comprising generating the frequency hopping sequence based on a first coefficient and a second coefficient.

[0555] Example 69. The method according to one of Examples 45 to 68, wherein: the first coefficient is selected from a set containing 17, 29, 37, 41, 53, 61, 73 or 89; and the second coefficient is selected from a set containing 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113 or 127.

[0556] Example 70. A method according to one of Examples 45 to 69, wherein generating the frequency hopping sequence further comprises generating the frequency hopping sequence based on the synchronization channel.

[0557] Example 71. A method according to one of Examples 45 to 70, further comprising using a linear congruent random generator to generate the frequency hopping sequence.

[0558] Example 72. The method according to one of Examples 45 to 71, further comprising, after receiving the first data symbol, the first device transmitting a second synchronization sequence in the synchronization channel.

[0559] Example 73. The method according to one of Examples 45 to 72, wherein the second synchronization sequence is equal to the first synchronization sequence.

[0560] Example 74. The method according to one of Examples 45 to 73, further comprising performing carrier sensing on the synchronization channel, wherein transmitting the second synchronization sequence comprises transmitting the second synchronization sequence in response to determining that the synchronization channel is idle.

[0561] Example 75. The method according to one of Examples 45 to 74, further comprising, after transmitting the second synchronization sequence, having the first means monitor the synchronization channel for detecting a third synchronization sequence.

[0562] Example 76. The method according to one of Examples 45 to 75, wherein the plurality of channels consists of 12, 26, 54 or 104 channels.

[0563] Example 77. The method according to one of Examples 45 to 76, wherein none of the plurality of channels is a pilot channel for transmitting pilot waveforms.

[0564] Example 78. A method according to one of Examples 45 to 77, further comprising: detecting a start position of a first packet based on detecting the first synchronization sequence, the first packet comprising the first synchronization sequence and the first data symbol; and performing a Fourier transform on the first packet based on the start position.

[0565] Example 79. A method according to one of Examples 45 to 78, wherein the first synchronization sequence comprises a short training field (STF), the method further comprising: detecting a transition from the STF to a long training field (LTF) of the first packet; estimating coarse and fine frequency offsets based on the STF and the LTF; de-rotating the first packet based on the estimated frequency offset; triggering channel selection on the LTF based on the frequency hopping sequence; and extracting symbol pairs of the LTF in response to triggering the channel selection.

[0566] Example 80. A method according to one of Examples 45 to 79, further comprising the first device alternating between an active mode that enables the receive path of the transceiver of the first device and a sleep mode that disables the receive path, wherein the single synchronization channel is monitored to detect that the first synchronization sequence is included when the first device is in the active mode.

[0567] Example 81. A method according to one of Examples 45 to 80, further comprising periodically monitoring the single synchronization channel.

[0568] Example 82. The method according to one of Examples 45 to 81, further comprising controlling the light based on the first data.

[0569] Example 83. A method comprising: generating a first plurality of chip spreads corresponding to a synchronization sequence of a packet by a first means; generating a second plurality of chip spreads corresponding to a header field of the packet by the first means; generating a first plurality of binary phase shift keying (BPSK) symbol pairs by the first means based on the first plurality of chip spreads; generating a second plurality of BPSK symbol pairs by the first means based on the second plurality of chip spreads; transmitting the first plurality of BPSK symbol pairs by the first means in a single synchronization channel of a plurality of channels; and after transmitting the first plurality of BPSK symbol pairs, transmitting the second plurality of BPSK symbol pairs by the first means in corresponding channels of the plurality of channels according to a frequency hopping sequence, wherein only a single channel of the plurality of channels is used for transmission at a time.

[0570] Example 84. The method according to Example 83, wherein the frequency hopping sequence does not repeat a channel in the plurality of channels before all channels in the plurality of channels have been used.

[0571] Example 85. The method according to one of Examples 83 or 84, wherein the frequency hopping sequence is based on a channel used for transmitting the synchronization sequence.

[0572] Example 86. An apparatus comprising: a transceiver; and a controller configured to: transmit a first synchronization sequence via the transceiver in a single synchronization channel among a plurality of channels; and, after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence each time using a single channel among the plurality of channels according to a frequency hopping sequence.

[0573] Example 87. The apparatus according to Example 86 further includes an antenna coupled to the transceiver, wherein transmitting the first synchronization sequence includes transmitting the first synchronization sequence via the antenna.

[0574] Example 88. An apparatus comprising: a transceiver; and a controller configured to: use the transceiver to monitor a single synchronization channel among a plurality of channels for detecting a first synchronization sequence; and in response to detecting the first synchronization sequence, each time using the single channel among the plurality of channels to extract a first data symbol associated with the first synchronization sequence according to a frequency hopping sequence.

[0575] Example 89. An apparatus comprising: a transceiver; and a controller configured to: generate a first plurality of chip spreads corresponding to a plurality of bits of a synchronization sequence of a packet; generate a second plurality of chip spreads corresponding to a plurality of bits of a header field of the packet; generate a first plurality of binary phase shift keying (BPSK) symbol pairs based on the first plurality of chip spreads; generate a second plurality of BPSK symbol pairs based on the second plurality of chip spreads; transmit the first plurality of BPSK symbol pairs via the transceiver in a single synchronization channel among a plurality of channels; and after transmitting the first plurality of BPSK symbol pairs, transmit the second plurality of BPSK symbol pairs via the transceiver in corresponding channels among the plurality of channels according to a frequency hopping sequence, wherein only a single channel among the plurality of channels is used for transmission at a time.

[0576] Example 90. A method comprising: transmitting a first synchronization sequence by a first means in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence by the first means each time using a single channel among the plurality of channels according to a first frequency hopping sequence; after transmitting the first data, transmitting a second synchronization sequence by the first means in a single second synchronization channel among the plurality of channels; and after transmitting the second synchronization sequence, transmitting second data associated with the second synchronization sequence by the first means each time using a single channel among the plurality of channels according to a second frequency hopping sequence, wherein: the first synchronization channel is different from the second synchronization channel, or the first synchronization sequence is different from the second synchronization sequence, or the second frequency hopping sequence is different from the first frequency hopping sequence.

[0577] Example 91. The method according to Example 90, wherein the first synchronization channel is different from the second synchronization channel.

[0578] Example 92. The method according to one of Examples 90 or 91, further comprising: generating the first frequency hopping sequence based on a first synchronization channel; and generating the second frequency hopping sequence based on a second synchronization channel.

[0579] Example 93. The method according to one of Examples 90 to 92, wherein the first synchronization sequence is different from the second synchronization sequence.

[0580] Example 94. A method according to one of Examples 90 to 93, wherein the first synchronization sequence is equal to the second synchronization sequence.

[0581] Example 95. The method according to one of Examples 90 to 94, wherein the second frequency hopping sequence is different from the first frequency hopping sequence.

[0582] Example 96. The method according to one of Examples 90 to 95, wherein the first synchronization sequence is different from the second synchronization sequence.

[0583] Example 97. A method according to one of Examples 90 to 96, further comprising: generating the first frequency hopping sequence based on a first coefficient, wherein the first coefficient is based on the content of the first synchronization sequence; and generating the second frequency hopping sequence based on a second coefficient, wherein the second coefficient is based on the content of the second synchronization sequence.

[0584] Example 98. A method according to one of Examples 90 to 97, wherein the first synchronization channel is equal to the second synchronization channel.

[0585] Example 99. The method according to one of Examples 90 to 98, wherein the second frequency hopping sequence is different from the first frequency hopping sequence.

[0586] Example 100. The method according to one of Examples 90 to 99, wherein the first data is directed to a second device and wherein the second data is directed to a third device.

[0587] Example 101. A method according to one of Examples 90 to 100, wherein transmitting the first synchronization sequence and the first data comprises broadcasting a first packet containing the first synchronization sequence and the first data.

[0588] Example 102. A method according to one of Examples 90 to 101, wherein the first frequency hopping sequence includes an initial channel for transmitting initial symbols of the first data, wherein the initial channel of the first frequency hopping sequence is equal to the first synchronization channel.

[0589] Example 103. A method according to one of Examples 90 or 102, wherein the plurality of channels comprises N channels, where N is a positive integer, wherein the first frequency hopping sequence traverses the N channels in the first N frequency hopping of the first frequency hopping sequence.

[0590] Example 104. A method according to one of Examples 90 to 103, wherein the first frequency hopping sequence does not contain consecutive equal channels.

[0591] Example 105. A method according to one of Examples 90 to 104, wherein the first frequency hopping sequence comprises consecutive equal channels.

[0592] Example 106. The method according to one of Examples 90 to 105, wherein transmitting the first synchronization sequence includes transmitting a short training field (STF) of the first packet, and wherein transmitting the first data includes transmitting a header field and a payload field of the first packet.

[0593] Example 107. A method according to one of Examples 90 to 106, further comprising: generating a first mapped symbol sequence containing symbols of the STF; generating a second mapped symbol sequence containing symbols of the header field and the payload field; concatenating the first mapped symbol sequence and the second mapped symbol sequence to generate a concatenated sequence; performing an inverse transform on the concatenated sequence to generate a sample stream; and applying a cyclic prefix to the sample stream using windowing, wherein transmitting the first synchronization sequence and the first data includes transmitting the first synchronization sequence and the first data based on the sample stream.

[0594] Example 108. A method according to one of Examples 90 to 107, wherein the synchronization sequence comprises a plurality of symbols of a first type, and wherein the first data comprises a plurality of symbols of a second type, the second type being different from the first type.

[0595] Example 109. A method according to one of Examples 90 to 108, wherein the symbol of the second type is an orthogonal frequency division multiplexing (OFDM) symbol encoded using binary phase shift keying (BPSK).

[0596] Example 110. A method comprising: transmitting a first synchronization sequence by a first means in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence by the first means each time using a single channel among the plurality of channels according to a first frequency hopping sequence; and after transmitting the first data, monitoring a single second synchronization channel by the first means for detecting a second synchronization sequence, wherein the first synchronization channel is different from the second synchronization channel.

[0597] Example 111. The method according to Example 110, wherein transmitting the first synchronization sequence and the first data includes broadcasting a first packet containing the first synchronization sequence and the first data.

[0598] Example 112. The method according to one of Examples 110 or 111, further comprising: after transmitting the first data, the first device monitoring a single third synchronization channel for detecting a third synchronization sequence, wherein the third synchronization channel is different from the first synchronization channel and the second synchronization channel, wherein the second synchronization channel is associated with the second device, and wherein the third synchronization channel is associated with the third device.

[0599] Example 113. A method comprising: generating a plurality of chip spread spectrums corresponding to a plurality of bits of a first group; generating a plurality of binary phase shift keying (BPSK) symbols based on the plurality of chip spread spectrums; repeating a portion of a corresponding BPSK symbol before each of the plurality of BPSK symbols; applying a windowed filter during a first portion of the repeated portion of each BPSK symbol to generate a second plurality of BPSK symbols; and transmitting the second plurality of BPSK symbols in symbol pairs in corresponding channels of a plurality of channels according to a frequency hopping sequence, wherein only a single channel of the plurality of channels is used each time to transmit the second plurality of BPSK symbols.

[0600] Example 114. The method according to Example 113, wherein the frequency hopping sequence does not repeat a channel in the plurality of channels before all channels in the plurality of channels have been used.

[0601] Example 115. The method according to one of Examples 113 or 114, further comprising transmitting a synchronization sequence in one of the plurality of channels before transmitting the second plurality of BPSK symbols according to the frequency hopping sequence.

[0602] Example 116. The method according to one of Examples 113 to 115, wherein the frequency hopping sequence is based on the channel used for transmitting the synchronization sequence.

[0603] Example 117. A method according to one of Examples 113 to 116, wherein the first portion of the repeating portion is half of a portion of the repeating portion.

[0604] Example 118. A method according to one of Examples 113 to 117, wherein the windowed filter performs a linear windowing function that combines samples of the previous symbol with samples of the repeating portion of the symbol.

[0605] Example 119. A method comprising: transmitting a first synchronization sequence by a first means in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence by the first means each time using a single channel among the plurality of channels according to a first frequency hopping sequence; and after transmitting the first data: monitoring a single second synchronization channel by the first means for detecting a second synchronization sequence associated with a second means, and monitoring the single second synchronization channel by the first means for detecting a third synchronization sequence associated with a third means.

[0606] Example 120. The method according to Example 119, wherein the second synchronization sequence is different from the third synchronization sequence.

[0607] Example 121. The method according to one of Examples 119 or 120, wherein the second synchronization sequence is equal to the third synchronization sequence.

[0608] Example 122. The method according to one of Examples 119 to 121, wherein the first synchronization channel is different from the second synchronization channel.

[0609] Example 123. The method according to one of Examples 119 to 122, wherein the first synchronization channel is equal to the second synchronization channel.

[0610] Example 124. A method according to one of Examples 119 to 123, further comprising: receiving a second synchronization sequence by the first device in a second synchronization channel, and subsequently receiving second data according to a second frequency hopping sequence; and receiving the third synchronization sequence by the first device in the third synchronization channel, and subsequently receiving third data according to a third frequency hopping sequence.

[0611] Example 125. The method according to one of Examples 119 to 124, wherein receiving the second data according to the second frequency hopping sequence and receiving the third data according to the third frequency hopping sequence partially overlap in time.

[0612] Example 126. A method comprising: generating a first plurality of chip spread spectrums corresponding to a plurality of bits of a first group; generating a first plurality of binary phase shift keying (BPSK) symbol pairs based on the first plurality of chip spread spectrums; transmitting the first plurality of BPSK symbol pairs in corresponding channels of a plurality of channels according to a first frequency hopping sequence; generating a second plurality of chip spread spectrums corresponding to a plurality of bits of a second group; generating a second plurality of BPSK symbol pairs based on the second plurality of chip spread spectrums; and transmitting the second plurality of BPSK symbol pairs in corresponding channels of the plurality of channels according to a second frequency hopping sequence, wherein the second frequency hopping sequence is different from the first frequency hopping sequence, and wherein only a single channel of the plurality of channels is used for transmission at a time.

[0613] Example 127. The method according to Example 126, wherein the frequency hopping sequence does not repeat a channel in the plurality of channels before all channels in the plurality of channels have been used.

[0614] Example 128. The method according to one of Examples 126 or 127, further comprising transmitting the first plurality of BPSK symbol pairs according to the first frequency hopping sequence prior to transmitting the first synchronization sequence in one of the plurality of channels.

[0615] Example 129. The method according to one of Examples 126 to 128, wherein the first frequency hopping sequence is based on the channel used for transmitting the first synchronization sequence.

[0616] Example 130. A method comprising: negotiating a first symbol duration with a second device; transmitting a first synchronization sequence in a single synchronization channel among a plurality of channels using the negotiated first symbol duration; and after transmitting the first synchronization sequence, transmitting first data associated with the first synchronization sequence in a single channel among the plurality of channels according to a frequency hopping sequence using the negotiated symbol duration each time.

[0617] Example 131. The method according to Example 130, wherein negotiating the symbol duration includes transmitting packets by the first device using a second symbol duration different from the first symbol duration.

[0618] Example 132. An apparatus comprising: a transceiver; and a controller configured to: transmit a first synchronization sequence via the transceiver in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence via the transceiver, each time using a single channel among the plurality of channels according to a first frequency hopping sequence; after transmitting the first data, transmit a second synchronization sequence via the transceiver in a single second synchronization channel among the plurality of channels; and after transmitting the second synchronization sequence, transmit second data associated with the second synchronization sequence via the transceiver, each time using a single channel among the plurality of channels according to a second frequency hopping sequence, wherein: the first synchronization channel is different from the second synchronization channel, or the first synchronization sequence is different from the second synchronization sequence, or the second frequency hopping sequence is different from the first frequency hopping sequence.

[0619] Example 133. An apparatus comprising: a transceiver; and a controller configured to: transmit a first synchronization sequence via the transceiver in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence via the transceiver each time using a single channel among the plurality of channels according to a first frequency hopping sequence; and after transmitting the first data, monitor a single second synchronization channel for detecting a second synchronization sequence, wherein the first synchronization channel is different from the second synchronization channel.

[0620] Example 134. An apparatus comprising: a transceiver; and a controller configured to: generate a plurality of chip spread spectrums corresponding to a plurality of bits of a first packet; generate a plurality of binary phase shift keying (BPSK) symbols based on the plurality of chip spread spectrums; repeat a portion of a corresponding BPSK symbol before each of the plurality of BPSK symbols; apply a windowing filter during a first portion of the repeated portion of each BPSK symbol to generate a second plurality of BPSK symbols; and transmit the second plurality of BPSK symbols in symbol pairs in corresponding channels of a plurality of channels according to a frequency hopping sequence via the transceiver, wherein only a single channel of the plurality of channels is used each time to transmit the second plurality of BPSK symbols.

[0621] Example 135. An apparatus comprising: a transceiver; and a controller configured to: transmit a first synchronization sequence via the transceiver in a single first synchronization channel among a plurality of channels; after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence via the transceiver each time using a single channel among the plurality of channels according to a first frequency hopping sequence; and after transmitting the first data: use the transceiver to monitor a single second synchronization channel for detecting a second synchronization sequence associated with a second device, and use the transceiver to monitor the single second synchronization channel for detecting a third synchronization sequence associated with a third device.

[0622] Example 136. An apparatus comprising: a transceiver; and a controller configured to: generate a first plurality of chip spread spectrum corresponding to a plurality of bits of a first packet; generate a first plurality of binary phase shift keying (BPSK) symbol pairs based on the first plurality of chip spread spectrum; transmit the first plurality of BPSK symbol pairs in corresponding channels of a plurality of channels via the transceiver according to a first frequency hopping sequence; generate a second plurality of chip spread spectrum corresponding to a plurality of bits of a second packet; generate a second plurality of BPSK symbol pairs based on the second plurality of chip spread spectrum; and transmit the second plurality of BPSK symbol pairs in corresponding channels of the plurality of channels via the transceiver according to a second frequency hopping sequence, wherein the second frequency hopping sequence is different from the first frequency hopping sequence, and wherein only a single channel of the plurality of channels is used for transmission at a time.

[0623] Example 137. An apparatus comprising: a transceiver; and a controller configured to: negotiate a first symbol duration with a second apparatus via the transceiver; transmit a first synchronization sequence via the transceiver in a single synchronization channel among a plurality of channels using the negotiated first symbol duration; and after transmitting the first synchronization sequence, transmit first data associated with the first synchronization sequence via the transceiver using the negotiated symbol duration, each time using a single channel among the plurality of channels according to a frequency hopping sequence.

[0624] Although this disclosure has been described with reference to illustrative embodiments, this specification is not restrictive. Those skilled in the art will understand, upon referring to this specification, various modifications and combinations of the illustrative embodiments and other embodiments.

Claims

1. A method comprising: The first device transmits a first synchronization sequence in a single first synchronization channel among multiple channels; After transmitting the first synchronization sequence, the first device uses a single channel from the plurality of channels each time to transmit first data associated with the first synchronization sequence according to the first frequency hopping sequence; After transmitting the first data, the first device transmits the second synchronization sequence in a single second synchronization channel among the plurality of channels; and After transmitting the second synchronization sequence, the first device transmits second data associated with the second synchronization sequence using a single channel from the plurality of channels according to the second frequency hopping sequence, wherein: The first synchronization channel is different from the second synchronization channel, or The first synchronization sequence is different from the second synchronization sequence, or The second frequency hopping sequence is different from the first frequency hopping sequence.

2. The method according to claim 1, wherein the first synchronization channel is different from the second synchronization channel.

3. The method according to claim 2, further comprising: The first frequency hopping sequence is generated based on the first synchronization channel; and The second frequency hopping sequence is generated based on the second synchronization channel.

4. The method according to claim 2, wherein the first synchronization sequence is different from the second synchronization sequence.

5. The method according to claim 2, wherein the first synchronization sequence is equal to the second synchronization sequence.

6. The method of claim 5, wherein the second frequency hopping sequence is different from the first frequency hopping sequence.

7. The method according to claim 1, wherein the first synchronization sequence is different from the second synchronization sequence.

8. The method of claim 7, further comprising: The first frequency hopping sequence is generated based on a first coefficient, wherein the first coefficient is based on the content of the first synchronization sequence; and The second frequency hopping sequence is generated based on a second coefficient, wherein the second coefficient is based on the content of the second synchronization sequence.

9. The method of claim 7, wherein the first synchronization channel is equal to the second synchronization channel.

10. The method of claim 2, wherein the second frequency hopping sequence is different from the first frequency hopping sequence.

11. The method of claim 1, wherein the first data is directed to the second device, and wherein the second data is directed to the third device.

12. The method of claim 1, wherein transmitting the first synchronization sequence and the first data comprises broadcasting a first packet containing the first synchronization sequence and the first data.

13. The method of claim 1, wherein the first frequency hopping sequence includes an initial channel for transmitting initial symbols of the first data, wherein the initial channel of the first frequency hopping sequence is equal to the first synchronization channel.

14. The method of claim 1, wherein the plurality of channels comprises N channels, where N is a positive integer, and wherein the first frequency hopping sequence traverses the N channels in the first N frequency hopping sequences.

15. The method of claim 1, wherein the first frequency hopping sequence does not contain consecutive equal channels.

16. The method of claim 1, wherein the first frequency hopping sequence comprises consecutive equal channels.

17. The method of claim 1, wherein transmitting the first synchronization sequence includes transmitting the short training field (STF) of the first packet, and wherein transmitting the first data includes transmitting the header field and payload field of the first packet.

18. The method of claim 17, further comprising: Generate a first mapped symbol sequence containing the symbols of the STF; Generate a second mapping symbol sequence containing symbols for the header field and the payload field; The first mapping symbol sequence and the second mapping symbol sequence are concatenated to generate a concatenated sequence; Perform an inverse transform on the cascaded sequence to generate a sample stream; and Applying a windowing prefix to the sample stream, wherein transmitting the first synchronization sequence and the first data includes transmitting the first synchronization sequence and the first data based on the sample stream.

19. The method of claim 1, wherein the synchronization sequence comprises a plurality of symbols of a first type, and wherein the first data comprises a plurality of symbols of a second type, the second type being different from the first type.

20. The method of claim 19, wherein the symbol of the second type is an orthogonal frequency division multiplexing (OFDM) symbol encoded using binary phase shift keying (BPSK).

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