Monitoring FEC information in a multi-chip environment

Abstract

A first integrated circuit (IC) chip of a communication device includes: a first communication interface to receive a first portion of an input data signal; a first forward error correction (FEC) decoder circuit to generate first error information regarding first code symbols in the first portion of the input data signal; a second communication interface; and a first statistics generator circuit to generate error statistics information using a) the first error information and b) second error information received via the second communication interface. A second IC chip includes: a third communication interface to receive a second portion of the input data signal; a second FEC decoder circuit to generate second error information regarding second code symbols in the second portion of the input data signal; and iii) a fourth communication interface to send the second error information to the second communication interface.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 548,540, filed November 14, 2023, entitled “Chip to Chip FEC Monitor,” the disclosure of which is expressly and entirely incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to forward error correction (FEC) for high-speed communication links, and more particularly to monitoring FEC statistics in multi-chip devices. Background Technology

[0003] The methods described in this background section are possible methods, but not necessarily previously conceived or adopted methods. Therefore, unless otherwise indicated, no method described in this section should be assumed to be prior art solely because it is included in this section.

[0004] During this period of rapid growth in internet technology and usage, the demand for high-speed data transmission has increased dramatically. Technologies supporting this sustained level of usage will continue to proliferate and evolve. For example, the Institute of Electrical and Electronics Engineers (IEEE) recently released a standard for 800 gigabits per second (800 Gbps) Ethernet, and IEEE is currently developing a standard for 1.6 megabits per second (1.6Tbps) Ethernet.

[0005] Optical transmission of data can support large amounts of data per channel, which is generally limited more by the rate at which electronics can encode signals onto the optical channel than by the bandwidth of the channel itself. In some implementations, particularly over short distances, high-speed communication via electrical media is used instead of optical communication or in combination with it. For example, network devices typically communicate with optical modules or intermediate communication devices (such as retimers, rate adapters, etc.) via high-speed electrical connections. As another example, intermediate communication devices (such as retimers, rate adapters, etc. between network devices and optical modules) typically communicate with optical modules via high-speed electrical connections.

[0006] In communication systems that utilize short-distance intermediate communication links (e.g., between network devices and optical modules) and long-distance communication links (e.g., on optical cables), it is sometimes useful to monitor errors occurring in the short-distance communication links. This helps to troubleshoot link performance issues by identifying where the errors occur (i.e., across short-distance intermediate links and across long-distance links). Summary of the Invention

[0007] In an embodiment, a communication device includes: a first integrated circuit (IC) chip, comprising: i) a first communication interface configured to receive a first portion of an input data signal; ii) a first forward error correction (FEC) decoder circuit configured to generate first error information relating to a first code character in the first portion of the input data signal; iii) a second communication interface; and iv) a first statistics generator circuit configured to generate error statistics using a) the first error information and b) second error information received via the second communication interface; and a second IC chip, comprising: i) a third communication interface configured to receive a second portion of the input data signal; ii) a second FEC decoder circuit configured to generate second error information relating to a second code character in the second portion of the input data signal; and iii) a fourth communication interface communicatively coupled to the second communication interface of the first IC chip, the fourth communication interface being configured to transmit the second error information to the second communication interface.

[0008] In another embodiment, a method for generating error statistics in a communication system includes: generating first error information regarding a first code character in a first portion of an input data signal received at the first IC chip at a first FEC decoder circuit of a first IC chip; generating second error information regarding a second code character in a second portion of an input data signal received at the second IC chip at a second FEC decoder circuit of a second IC chip; transferring the second error information from the second IC chip to the first IC chip; and generating error statistics using a) the first error information and b) the second error information received from the second IC chip at a first statistics generator circuit of the first IC chip.

[0009] In another embodiment, an optical module for optical communication includes: an optical transmitter configured to receive an electrically transmitted signal and generate one or more optical transmitted signals based on the electrically transmitted signal; and a first IC chip coupled to the optical transmitter, the first IC chip being configured to generate a first subset of the electrically transmitted signals, the first IC chip including: i) a first communication interface configured to receive a first portion of an input data signal, ii) a first FEC decoder circuit configured to generate first error information regarding a first code character in the first portion of the input data signal, iii) a second communication interface, and iv) a first statistical generator circuit configured to use a) the first error information b) generating error statistics from second error information received via a second communication interface; and a second IC chip coupled to an optical transmitter, the second IC chip being configured to generate a second subset of an electrical emission signal, the second IC chip comprising: i) a third communication interface configured to receive a second portion of an input data signal, ii) a second FEC decoder circuit configured to generate second error information relating to a second code character in the second portion of the input data signal, and iii) a fourth communication interface communicatively coupled to the second communication interface of the first IC chip, the fourth communication interface being configured to send the second error information to the second communication interface. Attached Figure Description

[0010] Figure 1 This is a simplified block diagram of an example communication system according to an embodiment, in which multiple integrated circuit (IC) chips process communication signals according to error correction codes and generate error statistics.

[0011] Figure 2 According to the embodiments, it is used for Figure 1 A simplified block diagram of an example IC chip in a communication system.

[0012] Figure 3 It is according to the embodiment for use in Figure 1 A simplified diagram illustrating an example format for grouping error information between IC chips.

[0013] Figures 4A to 4B The illustration shows an IC chip (such as...) according to various embodiments. Figure 1 An example of timing diagrams showing the timing of error information transfer between IC chips.

[0014] Figure 5 The illustration shows an IC chip (such as...) according to an embodiment. Figure 1 The timing diagram shows the timing of the example error statistics generation operation performed by the IC chip.

[0015] Figure 6 The illustration shows an IC chip (such as...) according to another embodiment. Figure 1Another example of timing the timing of the error statistics generation operation performed by the IC chip.

[0016] Figure 7 The illustration shows multiple IC chips (such as...) according to embodiments. Figure 1 The timing diagram of the IC chip relative to the generation of error statistics for the implementation of alignment mark (AM) locking.

[0017] Figure 8 It is according to the embodiments for use in such as Figure 1 The flowchart shows an example method for generating error statistics in communication systems such as communication systems. Detailed Implementation

[0018] As data rates continue to increase, it is sometimes desirable to use multiple integrated circuit (IC) chips operating in parallel to process data signals, for example, due to cost or other reasons.

[0019] In some implementations, the data signals processed by multiple IC chips comprise multiple streams of forward error correction (FEC) codewords (CWs) interleaved across multiple channels, resulting in more than one IC chip processing CWs from a single stream. Therefore, compiling error information (e.g., statistics) for a single CW stream is complex because errors in a single CW stream are detected across multiple IC chips. Thus, one option is to forgo compiling such error statistics. However, as mentioned above, such error statistics can often be helpful in troubleshooting link performance issues.

[0020] In the following embodiment, multiple IC chips operating in parallel (including at least a first IC chip and a second IC chip) process a data signal comprising FEC CWs of multiple data streams interleaved across multiple channels. Each of the first and second IC chips includes a corresponding FEC decoding circuitry system configured to generate corresponding error information regarding the corresponding CW data processed by the corresponding FEC decoding circuitry system. The first FEC decoding circuitry system of the first IC chip is configured to send the error information regarding the CW data processed by the first FEC decoding circuitry system to the second FEC decoding circuitry system of the second IC chip, so that the second FEC decoding circuitry system generates error statistics for the data streams processed by the multiple IC chips.

[0021] Figure 1 This is a simplified block diagram of an example communication system 100 for transmitting optical communication signals according to an embodiment. The communication system 100 includes a network switch 104 communicatively coupled to an optical module 108 via a communication link 112.

[0022] Network switch 104 includes multiple network interfaces 116 (only one is shown). Network switch 104 also includes: a packet processor 120 configured to analyze at least packet header data of packets received via network interface 116 to determine the network interface 116 through which the packets will be forwarded; and a memory 124 configured to store packet data while packet processor 120 processes packet header data.

[0023] Figure 1 The illustration shows a network interface 116 that is communicatively coupled to optical module 108. According to various embodiments, other network interfaces 116 (not shown) are communicatively coupled to other optical modules (not shown) having the same or similar structure as optical module 108, other conventional optical modules (not shown) having a suitable structure different from optical module 108, and / or electrical ports (not shown), etc.

[0024] Communication link 112 is an electrical communication link that operates at a suitable data rate (such as 800 gigabits per second (800 G), 1.6 terabits per second (1.6 T), 3.2 T, etc.) or another suitable data rate. In an embodiment, communication link 112 operates according to an 800 G communication protocol. In other embodiments, communication link 112 operates according to another suitable protocol.

[0025] In some embodiments, communication link 112 includes multiple channels. For example, in an embodiment where communication link 112 operates according to an 800 G communication protocol, communication link 112 includes 16 channels.

[0026] Network interface 116 is configured to transmit FEC-encoded codewords (CW) via communication link 112. In some embodiments where communication link 112 includes multiple channels, network interface 116 is configured to interleave multiple CW streams across multiple channels.

[0027] In some embodiments where the communication link 112 includes multiple channels, the network interface 116 periodically inserts one or more alignment marks (AMs) between the CWs on the communication link 112, and the optical module 108 uses AMs to correct skew between the channels.

[0028] The optical module 108 includes multiple receivers 140 and multiple transmitters 144. Each receiver 140 is communicatively coupled to a corresponding transmitter 144.

[0029] In an embodiment where communication link 112 includes multiple channels, each receiver 140 is communicatively coupled to a corresponding subset of the channels. In another embodiment, optical module 108 includes distribution circuitry (not shown) configured to distribute data received via communication link 112 to the multiple receivers 140.

[0030] exist Figure 1 In one example, optical module 108 includes two receivers 140 and two transmitters 144. In other embodiments, optical module 108 includes i) more than two receivers 140 and / or ii) a) one transmitter 144 or b) more than two transmitters 144. Each receiver 140 is configured to process CW data received via communication link 112 and output the CW data to the corresponding transmitter 144. In an embodiment, each receiver 140 includes communication interface circuitry (not shown) configured to output a transmit signal corresponding to the CW data to the corresponding transmitter 144. In an embodiment, each receiver 140 is also configured to compile error statistics regarding errors detected in the CW received via communication link 112.

[0031] Each transmitter 144 is configured to i) receive an electrical transmission signal from a corresponding receiver 140, ii) convert the electrical transmission signal into one or more optical transmission signals, and iii) output one or more optical transmission signals to a suitable corresponding optical medium, such as an optical fiber cable.

[0032] In other embodiments, receiver 140 outputs an electrical transmission signal to a single transmitter 144, which is configured to i) receive the electrical transmission signal from receiver 140; ii) convert the electrical transmission signal into one or more optical transmission signals; and iii) output one or more optical transmission signals to a suitable optical medium, such as an optical fiber cable.

[0033] Receiver 140-1 is implemented on the first IC chip 160-1, and receiver 140-2 is implemented on a second IC chip 160-2, which is different from the first IC chip 160-1. In another embodiment, at least a portion of transmitter 144-1 is also implemented on the first IC chip 160-1, and at least a portion of transmitter 144-2 is also implemented on the second IC chip 160-2.

[0034] In one embodiment, each IC chip 160 is included within a suitable corresponding chip package with appropriate external interconnect structures for inputting and outputting signals to and from the IC chip 160, such as a ball grid array (BGA), pin grid array (PGA), etc., and the IC chip 160 is communicatively coupled via such external interconnect structures. In other embodiments, the IC chip 160 is included within a multi-chip module, system-in-package (SiP), etc., and the IC chip 160 is communicatively coupled via appropriate interconnect structures (such as wires, solder bumps, through-silicon vias (TSVs), Cu-to-Cu connections, etc.).

[0035] Each receiver 140 includes a corresponding FEC decoder circuit 168 configured to process CW data received by the corresponding IC chip 160 via the communication interface 112 and generate error information regarding the CW data received by the corresponding IC chip 160. Additionally, the FEC decoder circuit 168-2 is configured to send at least a portion of the error information generated by the FEC decoder circuit 168-2 to the first IC chip 160-1; and the FEC decoder circuit 168-1 is configured to use i) the error information generated by the FEC decoder circuit 168-1 and ii) the error information generated by the FEC decoder circuit 168-2 to generate error statistics regarding the data received via the communication interface 112. In an embodiment, the FEC decoder circuit 168-1 is further configured to send at least a portion of the error information generated by the FEC decoder circuit 168-1 to the second IC chip 160-2; and the FEC decoder circuit 168-2 is configured to use i) the error information generated by the FEC decoder circuit 168-2 and ii) the error information generated by the FEC decoder circuit 168-1 to generate error statistics about the data received via the communication interface 112.

[0036] In one embodiment, the FEC decoder circuit 168 does not decode the CW received via communication interface 112, but only detects errors in at least some of the CWs and generates statistics about the detected errors in the CWs. In at least some embodiments, such statistics help troubleshoot link performance problems by helping to pinpoint where the errors occurred (i.e., across communication link 112 and some other segment of the communication path, such as across one or two optical media). In other embodiments, the FEC decoder circuit 168 is configured to decode at least some of the CWs received via communication interface 112 and / or use the error statistics for other purposes.

[0037] In embodiments, IC chip 160 is configured to communicate via one or more synchronization signals to synchronize the collection of error information and / or the generation of error statistics. For example, according to an embodiment, IC chip 160 exchanges one or more lock signals indicating when all IC chips 160 have achieved lock on AM received via communication interface 112, and the IC chip uses the error information generated after all IC chips 160 have achieved lock on AM to generate error statistics. As another example, when IC chip 160 is to generate error statistics for a specific time period and / or CW group, IC chip 160 exchanges one or more measurement timing signals indicating the specific time period and / or specific CW group. For example, according to various embodiments, IC chip 160 exchanges one or more measurement timing signals indicating when to start measuring error information, when to end measuring error information, and / or how many CWs will be used to generate error statistics for a specific set of error statistics.

[0038] Figure 2 This is a simplified block diagram of an example IC chip 200 for processing signals using multiple IC chips in a communication system according to an embodiment. In the embodiment, IC chip 200 is used as... Figure 1 The IC chip 160-1, and for ease of explanation, refer to... Figure 1 describe Figure 2 In other embodiments, the IC chip 200 is used with... Figure 1 The communication system 100 is different from other communication systems. In other embodiments, the communication system 100 uses a suitable IC chip different from the IC chip 200.

[0039] IC chip 200 is coupled to a subset of channels of communication interface 112, and IC chip 200 receives CW data corresponding to four CW streams (i.e., CW-A, CW-B, CW-C, and CW-D) via the subset of channels. Another IC chip (not shown; e.g., IC chip 160-2) is coupled to another subset of channels of communication interface 112, and another IC chip (e.g., IC chip 160-2) receives additional CW data corresponding to the four streams CW-A, CW-B, CW-C, and CW-D via the subset of channels. In an embodiment, the other IC chip (not shown) has a structure similar to that of IC chip 200.

[0040] The symbols of the CW received by the IC chip 200 via a channel subset are interleaved across the channels of the communication interface 112 according to a predetermined interleaving pattern, which is synchronized with the AM periodically included in the CW data received by the IC chip 200 via the channel subset. The locking / reordering circuit 204 is configured to achieve locking relative to the AM, and after achieving locking relative to the AM, reorder the symbols of the CW to output CW symbol streams corresponding to four streams: CW-A, CW-B, CW-C, and CW-D.

[0041] The CW symbols output by the lock / reordering circuit 204 are provided to the FEC decoder circuit 168-1, which includes corresponding FEC decoder circuit systems 208 configured to: i) generate error information for the streams of CW-A, CW-B, CW-C, and CW-D respectively, according to the FEC decoding algorithm. Each of at least some of the FEC decoder circuit systems 208 is configured to generate error statistics for the corresponding stream of CW symbols processed by the FEC decoder circuit system 108.

[0042] Each FEC decoder circuit system 208 includes a corrector calculation circuit system 212 configured to generate corresponding first error information about the CW symbol processed by the FEC decoder 208. For example, each corrector calculation circuit system 212 is configured to generate first error information about the CW symbol processed by the FEC decoder circuit system 208. In an embodiment, each corrector calculation circuit system 212 is configured to output first partial corrector information about the CW symbol processed by the FEC decoder circuit system 208.

[0043] IC chip 200 also includes a communication interface 216 configured to transmit information to and from another IC chip (e.g., IC chip 160-2). Communication interface 216 is coupled to FEC decoder circuitry 208-3 and FEC decoder circuitry 208-4, and receives first error information (e.g., a first corrector value or other suitable error information) generated by FEC decoders 208-3 and 208-4, and first error information regarding the symbols of the CW-C and CW-D streams processed by FEC decoder circuitry 208-3 and FET decoder circuitry 208-4. Communication interface 216 is configured to transmit the first error information corresponding to the CW-C and CW-D streams to another IC chip, such as IC chip 160-2. Communication interface 216 also receives second error information generated by the other IC chip, corresponding to the symbols of the CW-A and CW-B streams processed by the other IC chip.

[0044] At least some of the FEC decoder circuit systems 208 also include monitor circuits 220, for example, at least FEC decoders 208-1 and 208-2 include corresponding monitor circuits 220. Monitor circuit 220-1 receives i) first error information from the corrector calculation circuit 212-1 regarding the CW-A symbols processed by FEC decoder 208-1, and ii) second error information from IC chip 160-2 regarding the CW-A symbols processed by IC chip 160-2. Monitor circuit 220-1 uses the first error information from the corrector calculation circuit system 212-1 and the second error information from IC chip 160-2 to generate error statistics regarding the CW-A symbols processed by both IC chip 200 and IC chip 160-2.

[0045] In an embodiment where the first error information includes a first corrector value for the CW and the second error information includes a second corrector value for the CW, the monitor circuit 220-1 is configured to generate a corrector for the CW using the first and second corrector values, wherein the corrector indicates the number of errors detected in the CW. In another embodiment, the monitor circuit 220-1 is configured to use the generated corrector to calculate error statistics.

[0046] The monitor circuit 220-2 receives i) first error information about the CW-B symbols processed by the FEC decoder 208-2 from the collimator calculation circuit 212-2, and ii) second error information about the CW-B symbols processed by the IC chip 160-2 from the IC chip 160-2. The monitor circuit 220-2 uses the first error information from the collimator calculation circuit system 212-2 and the second error information from the IC chip 160-2 to generate error statistics about the CW-B symbols processed by both the IC chip 200 and the IC chip 160-2.

[0047] In an embodiment where the first error information includes a first corrector value for the CW and the second error information includes a second corrector value for the CW, the monitor circuit 220-2 is configured to generate a corrector for the CW using the first and second corrector values, wherein the corrector indicates the number of errors detected in the CW. In another embodiment, the monitor circuit 220-2 is configured to use the generated corrector to calculate error statistics.

[0048] In some embodiments where the monitor circuit 220 receives calibration information, each monitor circuit 220 includes a circuit system configured to process the calibration information to extract error information and use the extracted error information to generate error statistics. In some embodiments where the monitor circuit 220 receives calibration information, each monitor circuit 220 includes a circuit system configured to process the calibration information to extract error information, and the monitor circuit 220 is configured to use the error information generated by the monitor circuit to generate error statistics. In some embodiments where the IC chip 200 receives calibration information from another IC chip (e.g., IC chip 160-2), the IC chip 200 directs the calibration information to one or more FEC decoder circuit systems 208, which process the calibration information to extract error information.

[0049] In one embodiment, communication interface 216 is configured to communicate at a data rate much slower (i.e., at least 1000 times slower) than the data rate at which IC chip 200 receives data via communication interface 112. In some such embodiments, communication interface 216 is implemented using conventional techniques. More generally, communication interface 216 is implemented to provide error information between IC chip 200 and another IC chip (e.g., IC chip 160-2) at a suitable data rate that allows monitor circuitry 220 to generate error statistics.

[0050] In one embodiment, communication interface 216 includes a serial interface. In another embodiment, communication interface 216 includes a Universal Asynchronous Receiver / Transmitter (UART) interface. In yet another embodiment, communication interface 216 includes a parallel interface.

[0051] In some embodiments, the IC chip 200 is configured to generate error statistics corresponding to specific time intervals, such that the generated error statistics correspond to the sampling statistics, i.e., the error statistics provide relevant information about performance during the specific time interval. In other embodiments, the IC chip 200 is configured to continuously generate error statistics, i.e., the error statistics continuously provide information about performance over consecutive time periods.

[0052] IC chip 200 includes a controller 224 configured to communicate with another IC chip (e.g., IC chip 160-2) via one or more synchronization signals to synchronize the collection of error information and / or the generation of error statistics. For example, controller 224 is coupled to lock / reordering circuitry 204 and configured to determine when lock / reordering circuitry 204 has locked AM received via communication interface 112. Additionally, controller 224 is configured to determine when another IC chip (e.g., IC chip 160-2) has similarly locked AM based on one or more locking signals coupled to IC chip 160-2. Additionally, according to an embodiment, controller 224 is configured to signal to another IC chip (e.g., IC chip 160-2) that IC chip 200 has locked AM using one or more locking signals.

[0053] In an embodiment, IC chip 200 includes a first open-drain IC chip output circuit coupled to a single lock signal, and IC chip 160-2 similarly includes a second open-drain IC chip output circuit coupled to a single lock signal; additionally, the single lock signal is coupled to a pull-up (or pull-down) resistor, which is also coupled to a first logic voltage level. When IC chip 200 does not lock to AM, controller 224 controls the first open-drain IC chip output circuit to pull the single lock signal to a second logic voltage value. On the other hand, when IC chip 200 has locked to AM, controller 224 controls the first open-drain IC chip output circuit to float the single lock signal. Similarly, when IC chip 160-2 does not lock to AM, the second open-drain IC chip output circuit of IC chip 160-2 pulls the single lock signal to a second logic voltage value; and when IC chip 160-2 has locked to AM, the second open-drain IC chip output circuit of IC chip 160-2 floats the single lock signal.

[0054] Therefore, when either IC chip 200 or IC chip 160-2 is not locked, a single lock signal is set to the second logic value; on the other hand, when both IC chip 200 and IC chip 160-2 are locked, the single lock signal is pulled up (or pulled down) to the first logic value by a pull-up (or pull-down) resistor.

[0055] As another example, according to the embodiment, when IC chip 200 / 160 is to generate error statistics for a specific time period and / or CW group, controller 224 is configured to exchange one or more measurement timing signals with another IC chip (e.g., IC chip 160-2), one or more measurement timing signals indicating when to start measuring error information and / or when to end measuring error information.

[0056] In one embodiment, IC chip 200 includes a third open-drain IC chip output circuit coupled to a single measurement timing signal, and IC chip 160-2 similarly includes a fourth open-drain IC chip output circuit coupled to a single measurement timing signal; additionally, the single measurement timing signal is coupled to a pull-up (or pull-down) resistor, which is also coupled to a first logic voltage level. When IC chip 200 operates in a leader role and IC chip 160-2 operates in a follower role, the fourth open-drain IC chip output circuit of IC chip 160-2 floats the single measurement timing signal. Additionally, when an error information measurement for generating error statistics is to occur, controller 224 controls the third open-drain IC chip output circuit to pull the single measurement timing signal to a second logic voltage value, and when no error signal measurement for generating error statistics is to occur, controls the first open-drain IC chip output circuit to float a single lock signal.

[0057] Therefore, when an error information measurement for generating error statistics is to occur, the individual measurement timing signal is set to the second logic value; on the other hand, when no error information measurement for generating error statistics is to occur, the pull-up (or pull-down) resistor pulls the individual measurement timing signal to the first logic value.

[0058] According to an embodiment, the controller 224 is configured to control when the monitor circuit 220 generates control statistics and / or which error information the monitor circuit 200 uses to generate control statistics based on one or more synchronization signals.

[0059] In some embodiments, decoder circuit system 208-3 and / or decoder circuit system 208-4 have the same or similar structure as FEC decoder circuit system 208-1. In embodiments, the monitor circuit system 220 is omitted from decoder circuit system 208-3 and / or decoder circuit system 208-4.

[0060] Figure 3 According to the embodiment, it is used in IC chip 160 ( Figure 1 Between and / or to / from IC chip 200 ( Figure 2 A simplified diagram of an example format for group 300 that transmits error information. For ease of explanation, refer to... Figure 1 and 2 describe Figure 3 In some embodiments, IC chip 160 ( Figure 1 ) and / or IC chip 200 ( Figure 2 ) Use and Figure 3 A different suitable grouping format than grouping format 300 is used to transmit error information. In some embodiments, with IC chip 160 ( Figure 1 ) and / or IC chip 200 ( Figure 2Different other suitable IC chips are used Figure 3 The grouping format 300 is used to transmit error information.

[0061] Packet 300 includes a header 304, a data field 308, and a parity field 312. The header 304 includes a preamble 316 having a suitable predetermined signal and / or bit pattern to facilitate detection of the packet 300. In embodiments where the preamble 316 includes all logic 1s, the header 304 includes a start field 320 (set to logic 0) immediately following the preamble 316 and indicating the start of the remainder of the packet 300. In some embodiments, the start field 320 is omitted from the packet 300.

[0062] The header 304 also includes an AM identifier (ID) field 324, which performs connection switching when the IC chip receives a set of one or more AMs via the communication interface. For example, the IC chip sets the AM ID field 324 to logic 0 for all packets 300 of error information for transmitting CWs, which are located between a first set of one or more AMs and a subsequent second set of one or more AMs; next, the IC chip sets the AM ID field to logic 1 for all packets 300 of error information for transmitting CWs, which are located between a second set of one or more AMs and a subsequent third set of one or more AMs; next, the IC chip sets the AM ID field to logic 0 for all packets 300 of error information for transmitting CWs, which are located between a third set of one or more AMs and a subsequent fourth set of one or more AMs; and so on. In some embodiments, the AM ID field 324 can be used to account for skew between CWs received by different IC chips, as described below.

[0063] According to an embodiment, data portion 308 includes multiple fields 328, each containing corresponding error information corresponding to a specific CW. In one embodiment, field 328-1 includes error information for CW-C, and field 328-2 includes error information for CW-D. In another embodiment, each group 300 includes error information for only a single CW.

[0064] In an embodiment where IC chip 160-2 has a structure similar to that of IC chip 200, the monitor circuit of IC chip 160-2 generates i) error statistics on CW-C processed by both IC chip 200 and IC chip 160-2, and ii) error statistics on CW-D processed by both IC chip 200 and IC chip 160-2.

[0065] In another embodiment, IC chip 160-2 also sends error information to IC chip 200 regarding the stream symbols corresponding to CW-C and CW-D, and IC chip 200 includes additional monitor circuitry similar to monitor circuitry 220, which generates i) error statistics regarding CW-C processed by IC chip 200 and IC chip 160-2, and ii) error statistics regarding CW-D processed by both IC chip 200 and IC chip 160-2. In some such embodiments, IC chip 200 does not send error information regarding stream CW-C and CW-D to IC chip 160-2.

[0066] As discussed above, according to some embodiments, a set of one or more AMs is periodically transmitted via communication interface 112. In some embodiments, the collection of error information, the transfer of error information between IC chips 160 / 200, and / or the generation of error statistics for IC chips 160 / 200 are triggered by receiving a set of one or more AMs via communication interface 112. Depending on the data rate of communication interface 112, the rate at which AM sets are transmitted via communication interface 112, the data rate of communication interface 216, and / or the amount of error information collected, for example, the transfer of error information may or may not be completed between consecutive AM sets.

[0067] Figures 4A to 4B These are timing diagrams 400 / 450 illustrating example timing for error information transfer between IC chips according to various embodiments. For ease of explanation, refer to... Figure 1 and 2 describe Figures 4A to 4B .

[0068] IC chip 160 / 200 periodically receives a set of one or more AMs via communication interface 112 according to AM period T.

[0069] exist Figure 4A In the example, the error information collected by IC chip 160 / 200 can be transferred via communication interface 216, and error statistics can be generated over a duration of less than T, and corresponding error statistics can be generated between consecutive AM sets.

[0070] On the other hand, Figure 4B In the example, the error information collected by IC chips 160 / 200 is transferred via communication interface 216, and error statistics are generated over a duration exceeding T. Therefore, no corresponding error statistics are generated between consecutive AM sets. Instead, a corresponding error statistic is generated once for every two AM sets received via communication interface 112.

[0071] More generally, the frequency at which error information collected by IC chip 160 / 200 is transferred via communication interface 216 and / or the frequency at which error statistics are generated varies depending on the specific embodiment. In some embodiments, the frequency at which error information collected by IC chip 160 / 200 is transferred via communication interface 216 and / or the frequency at which error statistics are generated are configurable.

[0072] Refer again Figure 1 In embodiments where the communication interface 112 includes multiple channels, a skew may exist between the first set of channels coupled to the first IC chip 160-1 and the second set of channels coupled to the second IC chip 160-2. At least in some embodiments, the magnitude of the skew may affect the frequency at which the IC chip 160 can generate error statistics.

[0073] Figure 5 This is a timing diagram 500 illustrating the timing of an example error statistics generation operation performed by an IC chip according to an embodiment. For ease of explanation, see reference... Figure 1 and 2 describe Figure 5 .

[0074] exist Figure 5 In the example, there is a skew that causes the IC chip ("transmitter") that sends error information to be ahead of another IC chip ("receiver") that receives error information, and error statistics are generated using the received error information.

[0075] The transmitter sends error information to the receiver (e.g., via communication interface 216) during time period 504, and the receiver generates error statistics during time period 508. During time period 512, the receiver is idle relative to the generation of error statistics.

[0076] More specifically, the error information transmitted by the transmitter during time period 504-1 is used by the receiver to generate error statistics during time period 508-1. Due to the skew between the first set of channels coupled to the transmitter and the second set of channels coupled to the receiver, the transmitter begins transmitting new error information during time period 504-2 before the receiver completes the generation of error statistics during time period 508-1. This may lead to increased complexity in generating error statistics and / or require additional storage at the receiver to store the error information from the transmitter. However, if the transmitter begins transmitting new error information during time period 512-1, when the receiver is idle relative to the generation of error statistics, the receiver can store the new error information in a buffer memory (e.g., a first-in-first-out (FIFO) buffer) for later use during time period 512-2.

[0077] In some embodiments, group 300 ( Figure 3Use the AM ID field 324 to detect Figure 5 The scenario is illustrated in the diagram. For example, packets used to transmit error information during time period 504-1 have an AM ID field 324 set to a first logical value, while packets used to transmit error information during time period 504-2 have an AM ID field 324 set to a second logical value. Therefore, when the receiver receives a packet with the AM ID field 324 set to the second logical value during time period 508 (e.g., when the receiver generates error statistics using error information received in a packet with the AM ID field 324 set to the first logical value), the receiver determines... Figure 5 The scene depicted in the middle illustration is taking place.

[0078] Therefore, in some embodiments, in response to receiver determination Figure 5 The scenario illustrated in the diagram is taking place where the receiver and transmitter communicate to reduce the frequency at which the receiver generates error statistics and, optionally, the frequency at which the transmitter sends error information to the receiver. As an illustrative example only, according to an embodiment, the receiver generates error statistics after every two sets of AMs (multiple AMs), rather than after each set of AMs (multiple AMs).

[0079] Figure 6 This is a timing diagram 600 illustrating another example of the timing of an error statistics generation operation performed by an IC chip according to another embodiment. For ease of explanation, see reference to... Figure 1 and 2 describe Figure 6 .

[0080] exist Figure 6 In the example, there is a skew that causes the IC chip ("transmitter") that sends error information to lag behind another IC chip ("receiver") that receives error information, and error statistics are generated using the received error information.

[0081] The transmitter sends error information to the receiver during time period 604 (e.g., via communication interface 216), and the receiver generates error statistics during time period 608. More specifically, the error information transmitted by the transmitter during time period 604-1 is used by the receiver to generate error statistics during time period 608-1. Due to the skew between the first set of channels coupled to the transmitter and the second set of channels coupled to the receiver, the transmitter does not complete the transmission of new error information during time period 504-2 before the receiver receives the next set of AM(s). This may lead to increased complexity in generating error statistics and / or require additional storage at the receiver to store the error information from the transmitter.

[0082] In some embodiments, in response to receiver determination Figure 6The scenario illustrated in the diagram is taking place where the receiver and transmitter communicate to reduce the frequency at which the receiver generates error statistics and, optionally, the frequency at which the transmitter sends error information to the receiver. As an illustrative example only, according to an embodiment, the receiver generates error statistics after every two sets of AMs (multiple AMs), rather than after each set of AMs (multiple AMs).

[0083] Figure 7 This illustration shows a timing diagram 700 illustrating the locking generation error statistics of multiple IC chips relative to the AM received by the multiple IC chips in the CW according to an embodiment. For ease of explanation, see reference to... Figure 1 and 2 describe Figure 7 In some embodiments, IC chip 160 ( Figure 1 ) and / or IC chip 200 ( Figure 2 ) operation and Figure 7 The diagram in the image differs. In some embodiments, it is different from IC chip 160 ( Figure 1 ) and / or IC chip 200 ( Figure 2 Other suitable IC chips, such as Figure 7 Operate as shown in the diagram.

[0084] exist Figure 7 In the scenario illustrated, the first IC chip (IC chip 1) starts in a state where IC chip 1 is not locked to AM, while the second IC chip (IC chip 2) has been locked to AM. Additionally, in this embodiment, both IC chip 1 and IC chip 2 start without error statistics and / or exchange of error information.

[0085] Ultimately, IC chip 1 has achieved locking to AM, so the lock signal between IC chip 1 and IC chip 2 (as discussed above) transitions from logic low to logic high. In response to the lock signal transitioning from logic low to logic high, the two IC chips activate their respective counters 240, which are included in or coupled to their respective controllers 224.

[0086] According to an embodiment, when each counter 240 reaches a threshold, the corresponding internal readiness line of the corresponding IC chip transitions from a first logic value to a second logic value, where the first logic value corresponds to the IC chip not being ready to generate error statistics and / or not being ready to transmit error information to another IC chip, and the second logic value corresponds to the IC chip being ready to generate error statistics and transmit error information to another IC chip. In this embodiment, the threshold is selected to be longer than the typical maximum skew expected between IC chips. In this embodiment, the threshold used by the IC chip is configurable.

[0087] In response to i) the internal ready line of IC chip 1 being at a second logic value and ii) the detection of a set of AMs (multiple AMs), IC chip 1 transitions to i) IC chip 1 transmitting error information to IC chip 2 (when error information is available), and ii) IC chip 1 generating a state such as the error statistics described above. Similarly, in response to i) the internal ready line of IC chip 2 being at a second logic value and ii) the detection of a set of AMs (multiple AMs), IC chip 2 transitions to i) IC chip 2 transmitting error information to IC chip 1 (when error information is available), and ii) IC chip 2 generating a state such as the error statistics described above.

[0088] Figure 8 This is a flowchart of an example method 800 for generating error statistics in a communication system according to an embodiment. According to the embodiment, method 800 is performed by... Figure 1 IC chip 160 and / or Figure 2 The IC chip 200 is implemented and referenced for illustrative purposes only. Figure 1 and 2 Method 800 is described. In other embodiments, method 800 is derived from different methods. Figure 1 IC chip 160 and Figure 2 Other suitable IC chip implementations of IC chip 200. Additionally, Figure 1 IC chip 160 and / or Figure 2 The IC chip 200 does not implement method 800 and / or implements other suitable methods for generating error statistics that are different from the example method 800.

[0089] In block 804, a first FEC decoder circuit of the first IC chip generates first error information regarding a first code character in a first portion of the input data signal received at the first IC chip. For example, the first IC chip 160-1 generates first error information regarding a first code character in a first portion of the input data signal received at the first IC chip 160-1 via communication interface 112. As another example, IC chip 200 generates first error information regarding a first code character in a first portion of the input data signal received at the IC chip 200 via communication interface 112.

[0090] In block 808, the second FEC decoder circuit of the second IC chip generates second error information regarding the second code character in the second portion of the input data signal received at the second IC chip. For example, the second IC chip 160-2 generates the second error information regarding the second code character in the second portion of the input data signal received at the second IC chip 160-2 via the communication interface 112.

[0091] In block 812, the second error information is transferred from the second IC chip to the first IC chip. For example, the second error information is transferred from the second IC chip 160-2 to the first IC chip 160-1. As another example, the second error information is transferred from the second IC chip 160-2 to the IC chip 200 via communication interface 216.

[0092] In block 816, the first statistics generator circuit of the first IC chip uses a) first error information and b) second error information received from the second IC chip to generate error statistics. For example, FEC circuit 168-1 uses a) the first error information generated by FEC circuit 168-1 and b) the second error information received from the second IC chip 160-2 to generate error statistics. As another example, monitor 220-1 uses a) the first error information generated by FEC circuit 208-1 and b) the second error information received from the second IC chip 160-2 to generate error statistics.

[0093] In another embodiment, the error statistics are first error statistics, and method 800 further includes: generating third error information regarding a third code character in a second portion of the input data signal at a second FEC decoder circuit; generating fourth error information regarding a fourth code character in a first portion of the input data signal at a first FEC decoder circuit; transferring the fourth error information from a first IC chip to a second IC chip; and generating second error statistics using a) the third error information and b) the fourth error information received from the first IC chip at a second statistics generator circuit of the second IC chip.

[0094] In another embodiment, generating error statistics in block 816 includes: generating error statistics in response to determining at the first IC chip i) that the first IC chip has achieved locking of a first alignment mark relative to a first portion of the input data signal received by the first IC chip, and ii) that the second IC chip has achieved locking of a second alignment mark relative to a second portion of the input data signal received by the second IC chip.

[0095] In another embodiment, method 800 further includes: generating an electrical signal at a second IC chip indicating whether the second IC chip has achieved locking relative to a second alignment mark; and using the electrical signal at a first IC chip to determine whether the second IC chip has achieved locking relative to the second alignment mark.

[0096] In another embodiment, generating an electrical signal indicating whether the second IC chip has achieved locking relative to the second alignment mark includes: when the second IC chip has not achieved locking relative to the second alignment mark, the second IC chip pulls the electrical signal to a first logic voltage level; when the second IC chip has achieved locking relative to the second alignment mark, the second IC chip floats the voltage of the electrical signal; when the first IC chip has not achieved locking relative to the first alignment mark, the first IC chip pulls the electrical signal to a first logic voltage level; when the first IC chip has achieved locking relative to the first alignment mark, the first IC chip floats the voltage of the electrical signal; and when the first IC chip and the second IC chip float the voltage of the electrical signal, a resistor coupled between the electrical signal and the second logic voltage level pulls the electrical signal to the second logic voltage level.

[0097] In another embodiment, method 800 further includes: generating an electrical signal at a first IC chip that instructs a second IC chip on a time interval for a second FEC decoder circuit to provide second error information.

[0098] In another embodiment, method 800 further includes: generating an electrical signal at a first IC chip that instructs a second IC chip to provide a subset of second codewords for a second FEC decoder circuit to provide second error information.

[0099] In another embodiment, method 800 further includes: generating an electrical signal at a first IC chip that indicates to a second IC chip the amount of a second codeword for which a second FEC decoder circuit will provide second error information.

[0100] Refer again Figure 1 and 2In some embodiments, IC chips 160 / 200 may be configured to operate in a system with interleaved CW symbols on communication interface 112, such that IC chip 160-1 receives only the CW symbols corresponding to streams CW-A and CW-B, and IC chip 160-2 receives only the CW symbols corresponding to streams CW-C and CW-D. In embodiments, in such a system, FEC circuitry system 168-1 (e.g., monitor circuitry system 220) is configured to generate error statistics for streams CW-A and CW-B without using error information from chip 160-2, and FEC circuitry system 168-2 is configured to generate error statistics for streams CW-C and CW-D without using error information from chip 160-1. In some such embodiments, IC chips 160 / 200 are configurable such that error information is not exchanged between IC chips 160 / 200. In some such embodiments, FEC circuit system 168-1 (e.g., monitor circuit system 220) may be configured to generate error statistics for all CWs received by IC chip 160-1 between AMs in streams CW-A and CW-B, and FEC circuit system 168-2 may be configured to generate error statistics for all CWs received by IC chip 160-2 between AMs in streams CW-C and CW-D.

[0101] At least some of the aforementioned frameworks, operations, and techniques are appropriately implemented using dedicated hardware, such as discrete components, integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), processors executing firmware instructions, processors executing software instructions, or any combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions can be stored in any suitable computer-readable storage medium, such as read-only memory (ROM), random access memory (RAM), etc. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause one or more processors to perform various actions.

[0102] Although the invention has been described with reference to specific examples which are intended to be illustrative and not limiting, changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention.

Claims

1. A communication device, comprising: A first integrated circuit (IC) chip includes: i) a first communication interface configured to receive a first portion of an input data signal; ii) a first forward error correction (FEC) decoder circuit configured to generate first error information relating to a first code character in the first portion of the input data signal; iii) a second communication interface; and iv) a first statistics generator circuit configured to generate error statistics using a) the first error information and b) second error information received via the second communication interface; and The second IC chip includes: i) a third communication interface configured to receive a second portion of the input data signal; ii) a second FEC decoder circuit configured to generate the second error information, the second error information relating to a second code character in the second portion of the input data signal; and iii) a fourth communication interface communicatively coupled to the second communication interface of the first IC chip, the fourth communication interface being configured to send the second error information to the second communication interface.

2. The communication device according to claim 1, wherein the error statistics are first error statistics, and wherein: The first FEC decoder circuit is also configured to generate third error information, the third error information relating to the third code character in the first portion of the input data signal; The second communication interface is configured to send the third error information to the fourth communication interface of the second IC chip; The second FEC decoder circuit is further configured to generate fourth error information relating to the fourth code character in the second portion of the input data signal; and The second IC chip further includes a second statistical generator circuit, which is configured to generate second error statistics using a) the third error information received via the fourth communication interface and b) the fourth error information.

3. The communication device according to claim 1, wherein the first statistical generator of the first IC chip is further configured to: In response to determining i) that the first IC chip has achieved locking of a first alignment mark relative to the first portion of the input data signal received by the first IC chip, and ii) that the second IC chip has achieved locking of a second alignment mark relative to the second portion of the input data signal received by the second IC chip, the error statistics are generated.

4. The communication device of claim 3, wherein the second IC chip includes circuitry configured to generate an electrical signal indicating whether the second IC chip has achieved locking relative to the second alignment mark; and The first IC chip is configured to use the electrical signal to determine whether the second IC chip has achieved locking relative to the second alignment mark.

5. The communication device of claim 4, wherein the circuit of the second IC chip configured to generate the electrical signal indicating whether the second IC chip has achieved locking relative to the second alignment mark comprises: A first circuit is configured to i) pull the electrical signal to a first logic voltage level when the second IC chip fails to lock relative to the second alignment mark; and ii) when the second IC chip has achieved locking relative to the second alignment mark, the voltage of the electrical signal is floated; The first IC chip includes a first circuit configured to: i) pull the electrical signal to the first logic voltage level when the first IC chip fails to lock relative to the first alignment mark; and ii) when the first IC chip has achieved locking relative to the first alignment mark, the voltage of the electrical signal is floated; and The communication device further includes a resistor coupled between the electrical signal and the second logic voltage level, the resistor being configured to pull the electrical signal to the second logic voltage level when the first circuit and the second circuit cause the voltage of the electrical signal to float.

6. The communication device of claim 1, wherein the first IC chip includes a circuit system configured to generate an electrical signal that indicates to the second IC chip a time interval for the second FEC decoder circuit to provide the second error information.

7. The communication device of claim 1, wherein the first IC chip includes a circuit system configured to generate an electrical signal that indicates to the second IC chip that the second FEC decoder circuit is to provide a subset of the second codewords containing the second error information.

8. The communication device of claim 1, wherein the first IC chip includes a circuit system configured to generate an electrical signal that indicates to the second IC chip the amount of the second codeword for which the second FEC decoder circuit will provide the second error information.

9. The communication device according to claim 1, wherein the first IC chip is separate from the second IC chip.

10. A method for generating error statistics in a communication system, the method comprising: At the first forward error correction (FEC) decoder circuit of the first integrated circuit (IC) chip, first error information is generated, the first error information relating to a first code character in a first portion of the input data signal received at the first IC chip; At the second FEC decoder circuit of the second IC chip, second error information is generated, the second error information relating to the second code character in the second part of the input data signal received at the second IC chip; The second error information is transferred from the second IC chip to the first IC chip; as well as Error statistics are generated at the first statistics generator circuit of the first IC chip using a) the first error information and b) the second error information received from the second IC chip.

11. The method for generating error statistics according to claim 10, wherein the error statistics are first error statistics, and wherein the method further comprises: At the second FEC decoder circuit, third error information is generated, the third error information relating to the third code character in the second part of the input data signal; At the first FEC decoder circuit, fourth error information is generated, the fourth error information relating to the fourth code character in the first portion of the input data signal; The fourth error information is transferred from the first IC chip to the second IC chip; as well as At the second statistical generator circuit of the second IC chip, second error statistics are generated using the third error information (a) and the fourth error information (b) received from the first IC chip.

12. The method for generating error statistics according to claim 10, wherein generating the error statistics comprises: In response to determining at the first IC chip i) that the first IC chip has achieved locking of a first alignment mark relative to the first portion of the input data signal received by the first IC chip, and ii) that the second IC chip has achieved locking of a second alignment mark relative to the second portion of the input data signal received by the second IC chip, the error statistics are generated.

13. The method for generating error statistics according to claim 12, further comprising: At the second IC chip, an electrical signal is generated that indicates whether the second IC chip has achieved locking relative to the second alignment mark; as well as At the first IC chip, the electrical signal is used to determine whether the second IC chip has achieved locking relative to the second alignment mark.

14. The method for generating error statistics according to claim 13, wherein generating the electrical signal indicating whether the second IC chip has achieved locking relative to the second alignment mark comprises: When the second IC chip fails to lock relative to the second alignment mark, the second IC chip pulls the electrical signal to the first logic voltage level; When the second IC chip has achieved locking relative to the second alignment mark, the voltage of the electrical signal is floated by the second IC chip; When the first IC chip fails to lock relative to the first alignment mark, the first IC chip pulls the electrical signal to the first logic voltage level; When the first IC chip has achieved locking relative to the first alignment mark, the voltage of the electrical signal is floated by the first IC chip; as well as When the first IC chip and the second IC chip float the voltage of the electrical signal, the electrical signal is pulled to the second logic voltage level by a resistor coupled between the electrical signal and the second logic voltage level.

15. The method for generating error statistics according to claim 10, further comprising: At the first IC chip, an electrical signal is generated, which instructs the second IC chip that the second FEC decoder circuit should provide the time interval for the second error information.

16. The method for generating error statistics according to claim 10, further comprising: At the first IC chip, an electrical signal is generated that instructs the second IC chip that the second FEC decoder circuit should provide a subset of the second codewords containing the second error information.

17. The method for generating error statistics according to claim 10, further comprising: At the first IC chip, an electrical signal is generated, which instructs the second IC chip that the second FEC decoder circuit should provide the amount of the second codeword for the second error information.

18. The method for generating error statistics according to claim 10, wherein transferring the second error information comprises: The second error information is transferred from the second IC chip to the first IC chip via a communication link that couples the first IC chip and the second IC chip, thereby separating the second IC chip from the first IC chip.

19. An optical module for optical communication, the optical module comprising: An optical transmitter is configured to receive an electrical emission signal and generate one or more optical emission signals based on the electrical emission signal; A first integrated circuit (IC) chip, coupled to the optical transmitter, is configured to generate a first subset of the electrically transmitted signal. The first IC chip includes: i) a first communication interface configured to receive a first portion of an input data signal; ii) a first forward error correction (FEC) decoder circuit configured to generate first error information relating to a first code character in the first portion of the input data signal; iii) a second communication interface; and iv) a first statistics generator circuit configured to generate error statistics using a) the first error information and b) second error information received via the second communication interface; and A second IC chip, coupled to the optical transmitter, is configured to generate a second subset of the electrical emission signal. The second IC chip includes: i) a third communication interface configured to receive a second portion of the input data signal; ii) a second FEC decoder circuit configured to generate second error information relating to a second code character in the second portion of the input data signal; and iii) a fourth communication interface communicatively coupled to the second communication interface of the first IC chip, the fourth communication interface being configured to send the second error information to the second communication interface.

20. The optical module of claim 19, wherein the error statistics are first error statistics, and wherein: The first FEC decoder circuit is also configured to generate third error information, the third error information relating to the third code character in the first portion of the input data signal; The second communication interface is configured to send the third error information to the fourth communication interface of the second IC chip; The second FEC decoder circuit is further configured to generate fourth error information relating to the fourth code character in the second portion of the input data signal; and The second IC chip further includes a second statistics generator circuit, which is configured to generate second error statistics using a) the third error information received via the fourth communication interface and b) the fourth error information.

21. The optical module according to claim 19, wherein the first statistical generator of the first IC chip is further configured to: In response to determining i) that the first IC chip has achieved locking of a first alignment mark relative to the first portion of the input data signal received by the first IC chip, and ii) that the second IC chip has achieved locking of a second alignment mark relative to the second portion of the input data signal received by the second IC chip, the error statistics are generated.

22. The optical module of claim 19, wherein the first IC chip includes a circuit system configured to generate an electrical signal that indicates to the second IC chip a time interval for the second FEC decoder circuit to provide the second error information.

23. The optical module according to claim 19, wherein the first IC chip is separate from the second IC chip.

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