Printed line ultra-thin capacitor for high breakdown voltage

Abstract

Provided herein is a printed wiring ultra-thin capacitor for high breakdown voltage, comprising: a multi-layer structure comprising a plurality of capacitor layers, the plurality of capacitor layers comprising: first and second conductive layers having a thickness of no more than about 3 um; and a dielectric layer having a thickness of about 8 um to about 15 um positioned therebetween; and a bonding resin applied between each of the plurality of capacitor layers having substantially equal electric potential, the bonding resin configured to fill gaps in the conductive pattern having substantially equal electric potential, such that a dependence of the breakdown voltage on the properties of the bonding resin is avoided; wherein a total thickness of the printed wiring board and the capacitor is about 1 mm or less; and wherein the capacitor is capable of operating at an applied voltage of up to 2,500 V.

Description

Technical Field

[0001] According to some embodiments of this disclosure, this disclosure generally relates to capacitors, and more specifically, to printed circuit ultrathin capacitors and methods of manufacturing the same. Background Technology

[0002] Capacitors are devices that accumulate charge and store electrical energy. They are widely used in various types of electrical and electronic devices. The basic capacitor structure consists of two parallel conductive plates separated by a dielectric material. Increasing the area of ​​the conductive plates results in an increase in capacitance. Furthermore, connecting several capacitors in parallel increases the total capacitance and the energy stored therein, because the equivalent capacitance of a capacitor connected in parallel is the sum of the capacitances of each of its individual plates. However, the large area required can increase the likelihood of defects (e.g., defects in the dielectric material), thereby increasing leakage current and potentially causing premature breakdown of the capacitor. Increased leakage current leads to a shorter hold time. In other words, increased leakage current causes energy dissipation from the capacitor, resulting in a reduction in the charge / energy stored in the capacitor. Therefore, to compensate for the reduced capacitance, capacitors are often connected in parallel or stacked; however, in such cases, the total area of ​​the capacitors increases. Alternative methods to increase capacitance may include using high-k materials.

[0003] Therefore, there is a need in this field for thin capacitors with high breakdown voltage. Summary of the Invention

[0004] According to some embodiments of this disclosure, aspects of this disclosure relate to electrical devices or discrete devices, and more specifically, to printed circuit ultrathin capacitors and methods of manufacturing the same.

[0005] According to some embodiments, a printed circuit ultrathin capacitor for high breakdown voltage is provided, the capacitor comprising: a multilayer structure including a plurality of capacitor layers, each of the plurality of capacitor layers including: first and second conductive layers comprising copper, each of the first and second conductive layers having a thickness of no more than about 3 μm; and a dielectric layer located between the first and second conductive layers, the dielectric layer having a thickness of about 8 μm to about 15 μm; wherein each of the first and second conductive layers includes a conductive pattern; wherein the multilayer structure includes an adhesive resin applied between each of the plurality of capacitor layers having substantially equal potential, the adhesive resin being configured to fill gaps in the conductive pattern having a substantially uniform potential, thereby avoiding dependence of the breakdown voltage on the properties of the adhesive resin; wherein the thickness of the adhesive resin is at least about the sum of the thicknesses of the first and second conductive layers; wherein the total thickness of the printed circuit board and the capacitor is about 1 mm or less; and wherein the capacitor is capable of operating at an applied voltage of up to about 2,500 V.

[0006] According to some embodiments, the adhesive resin can be configured to fill the gaps between each of the plurality of capacitor layers having positive and negative potentials in the conductive pattern, thereby increasing its capacitance.

[0007] According to some implementation schemes, the capacitance per unit area and per capacitor layer is approximately 0.5 nF / cm². 2 Approximately 1 nF / cm 2 .

[0008] According to some implementations, the first and second conductive layers are made of copper or include copper.

[0009] According to some implementations, the thickness of each of the first and second conductive layers can be in the range of about 0.5 μm to about 1.5 μm.

[0010] According to some implementation schemes, the thickness of the bonding resin can be in the range of about 12 μm to about 50 μm.

[0011] According to some implementation schemes, the adhesive resin may be made of or include acrylic resin, epoxy resin or polyimide.

[0012] According to some implementation schemes, the dielectric layer may be made of or include acrylic resin, epoxy resin or polyimide.

[0013] According to some implementation schemes, the dielectric layer may include one or more of the following high-permeability additives: Al2O3, TiO2, BaTiO3, or a combination thereof.

[0014] According to some implementation schemes, multiple capacitor layers may include at least about 5 capacitor layers.

[0015] According to some implementations, the multiple capacitor layers may include about 20 capacitor layers, and the total thickness of the printed circuit board and capacitors may be about 0.8 mm.

[0016] According to some implementation schemes, the capacitance of the printed circuit ultrathin capacitor can be approximately 40 nF, and the total area of ​​the multiple capacitor layers can be approximately 5 cm². 2 .

[0017] According to some implementation schemes, capacitors can be flexible.

[0018] According to some implementation schemes, each of the multiple capacitor layers may be able to be bent to a radius of about 10 cm to about 20 cm.

[0019] According to some implementation schemes, the top and bottom of the first part of the multilayer structure may be coated with an insulating protective layer, which may be configured to provide electrical insulation to prevent surface breakdown of the capacitor.

[0020] According to some implementation schemes, contact pads can be formed on the top and bottom of the second part of the multilayer structure, wherein the contact pads comprise copper, and wherein the contact pads can be coated with a finish layer comprising one or more of the following: nickel, gold, silver, and tin.

[0021] According to some implementations, the thickness of the finishing layer can be between about 0.1 μm and about 20 μm.

[0022] According to some embodiments, a method for manufacturing an ultrathin printed circuit capacitor is provided, the method comprising: obtaining a plurality of capacitor layers, each of the plurality of capacitor layers comprising first and second conductive copper layers, and a dielectric layer positioned between the first and second conductive copper layers; performing a first surface treatment comprising a pre-patterning surface treatment of the first and second conductive copper layers and a first micro-etching, the first micro-etching being configured to adjust the surface roughness of the first and second conductive copper layers; forming a pattern on each of the first and second conductive copper layers; performing a second surface treatment comprising a post-patterning surface treatment and a second micro-etching; stacking the plurality of capacitor layers one above the other, the stacking comprising applying and laminating an adhesive resin configured to attach the plurality of capacitor layers to each other to form a multilayer structure; drilling to form vias, the vias being configured to electrically connect the first and second conductive copper layers having positive and negative potentials; electroplating the vias; forming an external pattern to obtain pads; applying an isolation coating layer on at least a portion of the multilayer structure; performing a fourth surface treatment comprising surface cleaning and a fourth micro-etching, the fourth surface cleaning being configured to remove copper oxide from the pads; and performing a surface finishing of the multilayer structure.

[0023] According to some implementations, the first micro-etching and / or the second micro-etching and / or the third micro-etching and / or the fourth micro-etching may include a wet etching process.

[0024] According to some implementation schemes, the first micro-etch and / or the second micro-etch and / or the third micro-etch and / or the fourth micro-etch can be configured to remove about 0.5 μm or less.

[0025] According to some implementation schemes, the first micro-etching, second micro-etching, third micro-etching, and / or fourth micro-etching removes no more than about 2 μm.

[0026] According to some implementation schemes, the thickness of the bonding resin can be the sum of the approximate thickness of the first and second conductive copper layers and the approximate depth of the gaps in the copper pattern.

[0027] According to some embodiments, patterning may include performing resist lamination; laser direct imaging to expose the resist, wherein the resist is solid; developing the resist; and removing material from the first and second conductive copper layers.

[0028] Some embodiments of this disclosure may include some, all, or none of the advantages described above. One or more other technical advantages will become apparent to those skilled in the art from the accompanying drawings, description, and claims. Furthermore, while specific advantages have been listed above, various embodiments may include some, all, or none of the listed advantages.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In case of conflict, the patent specification including the definitions shall prevail. As used herein, the indefinite articles a (“a” and “an”) mean “at least one” or “one or more” unless the context clearly indicates otherwise. Attached Figure Description

[0030] This document describes some embodiments of the present disclosure with reference to the accompanying drawings. This description is consistent with the accompanying drawings. Figure 1 This makes it clear to those skilled in the art how some implementation schemes can be practiced. The accompanying drawings are for illustrative purposes and do not attempt to show the structural details of the embodiments in more detail than necessary for a basic understanding of this disclosure. For clarity, some objects depicted in the drawings are not drawn to scale. Furthermore, two different objects in the same drawing may be drawn at different scales. In particular, in the same drawing, the scale of some objects may be greatly magnified compared to other objects.

[0031] In block diagrams and flowcharts, optional elements / components and optional stages can be included within dashed boxes.

[0032] In the attached diagram:

[0033] Figure 1 A schematic diagram of a cross-sectional side view of a printed circuit capacitor with high breakdown voltage according to some embodiments is shown;

[0034] Figure 2A-2B A schematic cross-sectional side view of a printed circuit capacitor with a high breakdown voltage having first and second configurations according to some embodiments is shown.

[0035] Figure 3A schematic diagram of a flowchart illustrating a method for manufacturing a printed circuit capacitor with high breakdown voltage according to some embodiments is shown; and

[0036] Figures 4A-4E The following are examples of manufacturing methods according to some embodiments. Figure 3 High breakdown voltage printed circuit capacitors Figure 3 A schematic diagram of a cross-sectional side view of some steps of the method.

[0037] Detailed Implementation Plan

[0038] Referring to the accompanying instructions and figures will provide a better understanding of the principles, uses, and implementation methods of the teachings herein. After carefully reading the descriptions and figures herein, those skilled in the art will be able to implement the teachings without excessive effort or experimentation.

[0039] In the following description, various aspects of the invention will be described. Specific details are set forth for purposes of explanation in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without the specific details set forth herein. Furthermore, well-known features may be omitted or simplified so as not to obscure the invention.

[0040] As used herein, the term "about" can be used to specify a quantity or parameter (e.g., the length of an element) within a continuous range of values ​​near (and including) a given value. According to some embodiments, "about" can specify a parameter value between 80% and 120% of a given value. For example, stating "the length of the element is about 1 m" is equivalent to stating "the length of the element is between 0.8 m and 1.2 m." According to some embodiments, "about" can specify a parameter value between 90% and 110% of a given value. According to some embodiments, "about" can specify a parameter value between 95% and 105% of a given value.

[0041] As used herein, the terms “basic” and “about” may be interchangeable depending on some implementation schemes.

[0042] As used herein, the terms “isolation” and “insulation” may be used interchangeably depending on some implementation schemes.

[0043] As used herein, according to some embodiments, the term "ultra-thin" may refer to the thickness of a printed circuit capacitor. According to some embodiments, the term "ultra-thin" may refer to the thickness of a printed circuit board and its printed circuit capacitors. According to some embodiments, the term "ultra-thin" may refer to a thickness of about 2 mm or less. According to some embodiments, the term "ultra-thin" may refer to a thickness of about 1 mm or less, about 0.8 mm or less, about 0.5 mm or less, about 0.4 mm or less, or about 0.3 mm or less. Each possibility is a separate embodiment.

[0044] According to some embodiments, the term "ultra-thin" can refer to a thickness of about 0.5 mm to about 1.5 mm for a printed circuit board having printed circuit capacitors. According to some embodiments, the term "ultra-thin" can refer to a thickness of about 0.3 mm to about 1 mm. According to some embodiments, the term "ultra-thin" can refer to a thickness of about 0.5 mm to about 1 mm. Each possibility is a separate embodiment.

[0045] Those skilled in the art will understand that the ultrathin thickness of a printed circuit board with printed circuit capacitors can depend in particular on the number of layers and its manufacturing technique. According to some embodiments, the term "ultrathin" can refer to the thickness of a printed circuit board made of multiple capacitor layers (i.e., multiple capacitor cells). According to some embodiments, the term "ultrathin" can refer to a printed circuit board having a thickness of about 0.5 mm, wherein the printed circuit board includes 10 or more capacitor layers. According to some embodiments, the term "ultrathin" can refer to a printed circuit board having a thickness ranging from about 0.3 mm to about 1.5 mm, wherein the printed circuit board includes 10 or more layers. According to some embodiments, the term "ultrathin" can refer to a printed circuit board having a thickness ranging from about 0.3 mm to about 1 mm, wherein the printed circuit board includes at least 10 or more layers.

[0046] As used herein, according to some embodiments, the term "ultra-thin" may refer to, for example, the thickness of a capacitor layer (i.e., a capacitor cell) in a printed circuit board. According to some embodiments, the capacitor may have a thickness of about 2 mm or less, about 1 mm or less, about 0.8 mm or less, about 0.5 mm or less, about 0.4 mm or less, and about 0.3 mm or less. Each possibility is a separate embodiment. According to some embodiments, the capacitor may have a thickness in the range of about 0.1 mm to about 1 mm, about 0.1 mm to about 0.5 mm, about 0.3 mm to about 0.5 mm, and about 0.1 mm to about 0.8 mm. Each possibility is a separate embodiment.

[0047] As used herein, according to some embodiments, the term "high breakdown voltage" may refer to the breakdown voltage of a printed circuit capacitor as disclosed herein, wherein the high breakdown voltage is about 500V or higher, about 700V or higher, about 800V or higher, about 1000V or higher, about 1200V or higher, about 1500V or higher, about 1700V or higher, about 1800V or higher, about 2000V or higher, about 2200V or higher, about 2500V or higher, etc. Each possibility is a separate embodiment.

[0048] According to some implementations, the term "high breakdown voltage" can refer to any breakdown voltage within the range of approximately 500V-1000V, approximately 500V-1500V, approximately 500V-2000V, approximately 500V-2500V, approximately 500V-3000V, approximately 800V-3000V, approximately 1000V-1500V, approximately 1000V-2000V, approximately 1000V-2500V, approximately 1500V to approximately 2500V, approximately 1000V-3000V, approximately 2000V-2500V, approximately 2000V-3000V, etc., or any combination thereof. Each possibility is a separate implementation.

[0049] According to some implementations, the term "high breakdown voltage" can refer to a breakdown voltage of approximately 2500V, approximately 2700V, or approximately 3000V. Each possibility is a separate implementation.

[0050] According to some embodiments, this document provides a printed circuit capacitor with a multilayer structure comprising a plurality of capacitor layers, the plurality of capacitor layers comprising: first and second conductive layers, each of the first and second conductive layers having a thickness of no more than about 3 μm, and a dielectric layer located between the first and second conductive layers, the dielectric layer having a thickness of about 2 μm to about 25 μm; wherein each of the first and second conductive layers comprises a conductive pattern; wherein the multilayer structure comprises an adhesive resin applied between each of the plurality of capacitor layers having a substantially equal potential, the adhesive resin being configured to fill gaps in the conductive pattern having a substantially uniform potential, thereby avoiding dependence of breakdown voltage on the properties of the adhesive resin; wherein the thickness of the adhesive resin is at least about the sum of the thicknesses of the first and second conductive layers; wherein the total thickness of the printed circuit board and the capacitor is about 1 mm or less; and wherein the capacitor is capable of operating at an applied voltage of up to about 3000 V.

[0051] Advantageously, according to some embodiments, the printed circuit capacitor disclosed herein has a capacitance of approximately 0.5 nF / cm². 2 Approximately 1 nF / cm 2The capacitance per unit area of ​​each individual capacitor layer within the range, while the total thickness of the printed circuit board and capacitors is approximately 1 mm or less.

[0052] Advantageously, according to some implementations, printed circuit capacitors are capable of operating at high operating voltages (e.g., about 500V or greater, about 1000V or greater, up to about 2500V, up to about 3000V, etc.) while having a total thickness of about 1mm or less for the printed circuit board and the capacitor.

[0053] Advantageously, according to some implementations, printed circuit capacitors can minimize the size of the device while achieving high capacitance per unit area, and are therefore suitable for a variety of applications, such as, but not limited to, energy storage devices, fast discharge applications, medical devices, electrical devices, discrete devices, etc., or any combination thereof.

[0054] According to some embodiments, a method for manufacturing printed circuit capacitors is disclosed. Advantageously, in some embodiments, the disclosed method is a simple and cost-effective method. Advantageously, in some embodiments, the disclosed method can be implemented as a mass production method, as described in more detail elsewhere herein. Advantageously, the disclosed method facilitates the manufacture of lightweight and / or ultra-thin devices, such as, but not limited to, electrical and discrete devices.

[0055] refer to Figure 1 It shows a schematic diagram of a cross-sectional side view of a capacitor 100 according to some embodiments.

[0056] According to some embodiments, capacitor 100 is a printed circuit board capacitor. According to some embodiments, capacitor 100 can be an ultra-thin capacitor. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can be about 2 mm or less. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can be about 1 mm or less. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can be about 0.8 mm or less. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can be about 0.5 mm or less. Each possibility is a separate embodiment. As a non-limiting example, the thickness of the printed circuit board including capacitor 100 can be less than the thickness of about a standard credit card (i.e., a standard credit card has a thickness of about 0.5 mm to about 0.7 mm).

[0057] According to some embodiments, the thickness of the printed circuit board including capacitor 100 can be in the range of about 0.4 mm to about 0.8 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can be in the range of about 0.4 mm to about 0.7 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can be in the range of about 0.4 mm to about 0.8 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can be in the range of about 0.4 mm to about 1 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can be in the range of about 0.4 mm to about 2 mm. Each possibility is a separate embodiment.

[0058] According to some embodiments, the thickness of the printed circuit board including capacitor 100 can range from about 0.1 mm to about 2 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can range from about 0.2 mm to about 2 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can range from about 0.1 mm to about 1 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can range from about 0.1 mm to about 0.8 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 can range from about 0.1 mm to about 0.5 mm. Each possibility is a separate embodiment. Those skilled in the art will understand that the thickness of the printed circuit board including capacitor 100 can depend particularly on its manufacturing techniques and the number of capacitor layers (e.g., capacitor cells) therein.

[0059] According to some embodiments, capacitor 100 may be a flexible capacitor. According to some embodiments, capacitor 100 may be bendable. According to some embodiments, one capacitor layer of capacitor 100 (e.g., as...) Figure 1 The capacitor layer 110a depicted can be bent to a radius of about 20 cm without damaging it (i.e., without causing plastic deformation). According to some embodiments, a capacitor layer can be bent to a radius of about 15 cm to about 20 cm without damaging it (i.e., without causing plastic deformation). According to some embodiments, a capacitor layer can be bent to a radius of about 5 cm to about 20 cm without damaging it (i.e., without causing plastic deformation). According to some embodiments, a capacitor layer can be bent to a radius of about 2 cm to about 10 cm without damaging it (i.e., without causing plastic deformation). Each possibility is a separate embodiment. Alternatively, in some embodiments, the capacitor 100 may be a substantially rigid capacitor, i.e., substantially without bending capability.

[0060] According to some implementation schemes, capacitor 100 may have a parallel-plate capacitor configuration, such as Figure 1 The image is schematically depicted. Those skilled in the art will understand that the configuration of capacitor 100 is not limited thereto. In some embodiments, the configuration of capacitor 100 may include a radial configuration (not shown), etc.

[0061] According to some embodiments, capacitor 100 may have a multilayer structure 101. According to some embodiments, the multilayer structure 101 may include one or more capacitor layers / sheets 110a-c (also referred to as "multiple capacitor layers / sheets 110"). According to some embodiments, and as... Figure 1 As shown, the multiple capacitor layers / sheets 110 of the multilayer structure 101 may include three capacitor layers / sheets 110a-c.

[0062] According to some embodiments, each of the plurality of capacitor layers / sheets 110 includes a first conductive layer / sheet, a second conductive layer / sheet, and a dielectric layer therebetween. In other words, in some embodiments, each of the plurality of capacitor layers / sheets 110 includes a capacitor unit. According to some embodiments, and as... Figure 1 As depicted, the first capacitor layer / sheet 110a includes a first conductive layer / sheet 112a, a second conductive layer 116a, and a dielectric layer 114a therebetween. Similarly, the second capacitor layer 110b includes a first conductive layer / sheet 112b, a second conductive layer / sheet 116b, and a dielectric layer 114b therebetween; and the third capacitor layer 110c includes a first conductive layer / sheet 112c, a second conductive layer / sheet 116c, and a dielectric layer 114c therebetween.

[0063] According to some embodiments, the plurality of capacitor layers / sheets 110 may include 2, 3, 4, 5, 6, 7, 8, 9, 10 or more capacitor layers / sheets. According to some embodiments, the plurality of capacitor layers / sheets 110 may include at least about 10 capacitor layers or more. According to some embodiments, the plurality of capacitor layers / sheets 110 may include about 20 capacitor layers or more. According to some embodiments, the plurality of capacitor layers / sheets 110 may include from about 5 capacitor layers to about 40 capacitor layers. According to some embodiments, the plurality of capacitor layers / sheets 110 may include from about 20 to about 40 capacitor layers 110. As another non-limiting example, the plurality of capacitor layers / sheets 110 may include about 11 capacitor layers 110.

[0064] According to some embodiments, the plurality of capacitor layers / sheets 110 may include about 20 capacitor layers, such that their thickness is about 0.8 mm. According to some embodiments, the plurality of capacitor layers / sheets 110 may include about 30 capacitor layers, such that their thickness is about 1.2 mm. According to some embodiments, the plurality of capacitor layers / sheets 110 may include about 40 capacitor layers, such that their thickness is about 1.6 mm. Each possibility is a separate embodiment.

[0065] According to some implementations, capacitor 100 may include a single capacitor layer / sheet (e.g., capacitor layer 110a).

[0066] According to some implementation schemes, the total number of capacitor layers / sheets 110 may include an odd or even number, such as in... Figure 2A-2B It is explained in more detail in the text.

[0067] According to some embodiments, each of the first and second conductive layers / sheets 112a-c and 116a-c can be in the form of a conductive sheet, coating, layer, foil, surface, etc. Each possibility is a separate embodiment.

[0068] According to some embodiments, the first conductive layer 112a-c and the second conductive layer 116a-c may be the same or similar in thickness and / or composition. According to some embodiments, the first conductive layer 112a-c and the second conductive layer 116a-c may be made of or comprise one or more metals, such as, but not limited to, metal alloys, compounds, and mixtures.

[0069] According to some embodiments, the first conductive layer 112a-c and the second conductive layer 116a-c may be made of copper or comprise copper. According to some embodiments, each of the first conductive layer 112a-c and the second conductive layer 116a-c may comprise a copper sheet. According to some embodiments, each of the first conductive layer 112a-c and the second conductive layer 116a-c may comprise a copper foil. According to some embodiments, each of the first conductive layer 112a-c and the second conductive layer 116a-c may comprise a copper coating. According to some embodiments, each of the first conductive layer 112a-c and the second conductive layer 116a-c may comprise a copper layer.

[0070] According to some embodiments, the thickness of each of the first conductive layers 112a-c and each of the second conductive layers 116a-c of the capacitor 100 can be about 3 μm or less. According to some embodiments, the thickness of each of the first conductive layers 112a-c and each of the second conductive layers 116a-c of the capacitor 100 can be in the following ranges: about 0.5 μm to about 3 μm, about 0.5 μm to about 1.5 μm, about 1 μm to about 2.5 μm, about 1.5 μm to about 3 μm, etc. Each possibility is a separate embodiment.

[0071] According to some embodiments, the thickness of each of the first conductive layers 112a-c and each of the second conductive layers 116a-c of the capacitor 100 can be in the range of about 0.4 μm to about 1.5 μm, about 0.5 μm to about 1 μm, about 1 μm to about 1.5 μm, about 1 μm to about 1.2 μm, about 1.2 μm to about 1.5 μm, about 0.7 μm to about 1.5 μm, etc. Each possibility is a separate embodiment. According to some embodiments, the thickness of each of the first conductive layers 112a-c and each of the second conductive layers 116a-c of the capacitor 100 can be about 0.4 mm, about 0.5 μm, about 0.8 μm, about 1 μm, or about 1.2 μm. Each possibility is a separate embodiment.

[0072] Alternatively, in some embodiments, the thickness of each of the first conductive layers 112a-c and each of the second conductive layers 116a-c of the capacitor 100 may be about 3 μm or higher.

[0073] According to some embodiments, each of the dielectric layers 114a-c may be made of or comprise one or more insulating materials. According to some embodiments, the one or more insulating materials may comprise one or more polymers. According to some embodiments, each of the dielectric layers 114a-c may be made of or comprise polyimide, epoxy resin, acrylic resin, or combinations thereof. According to some embodiments, the acrylic resin may comprise a high-capacitance additive. According to some embodiments, the high-capacitance additive may comprise Al2O3, TiO2, perovskite materials, or any combination thereof. As a non-limiting example, the perovskite material may include barium titanate, etc.

[0074] According to some embodiments, the thickness of each of dielectric layers 114a-c can be in the range of about 2 μm to about 25 μm. According to some embodiments, the thickness of each of dielectric layers 114a-c can be in the range of about 8 μm to about 15 μm. According to some embodiments, the thickness of each of dielectric layers 114a-c can be in the range of about 10 μm to about 15 μm, about 2 μm to about 15 μm, about 2 μm to about 10 μm, about 10 μm to about 15 μm, about 10 μm to about 12 μm, etc. Each possibility is a separate embodiment.

[0075] According to some embodiments, each of the first layers 112a-c and each of the third layers 116a-c may include a pattern or be in the form of a pattern. According to some embodiments, in particular, each of the first layers 112a-c and each of the third layers 114a-c may be etched to form a pattern. As a non-limiting example, the pattern of each of the first layers 112a-c and each of the third layers 116a-c may include multiple conductive islands / regions. According to some embodiments, each of the first layers 112a-c and each of the third layers 114a-c may have different patterns. According to some embodiments, each of the first layers 112a-c and each of the third layers 116a-c may have partially similar and partially different patterns. According to some embodiments, each of the first layers 112a-c and each of the third layers 116a-c may have substantially the same or similar patterns. Each possibility is a separate embodiment.

[0076] According to some implementation schemes, holes can be drilled to electrically connect each of the first layers 112a-c to each of the third layers 116a-c with a positive potential, and each of the first layers 112a-c to each of the third layers 116a-c with a negative potential.

[0077] According to some implementation schemes, and such Figure 1 As schematically depicted, a portion of the pattern may include a first pad 120a formed on a first surface / side 102 (also referred to as "top surface / side 102") of the capacitor 100 and a second pad 120c formed on a second surface / side 104 (also referred to as "bottom surface / side 104"). According to some embodiments, the first and second pads 120a / 120c may be configured to connect the capacitor 100 to external devices, circuits, etc. (not shown). According to some embodiments, the first and second pads 120a / 120c may be made of or comprise copper or any other suitable conductive material.

[0078] According to some embodiments, each of the first layers 112a-c and each of the third layers 116a-c are made of or comprise copper, and an environmentally stable oxide layer / coating 118a-c may be present at least partially thereon, as described in more detail elsewhere herein. According to some embodiments, the stabilizing oxide may comprise environmentally stable copper oxide. According to some embodiments, the oxide layer / coating 118a-c may be made of or comprise CuO, CuO2, or a combination thereof. According to some embodiments, the oxide layer / coating 118a-c may be configured to increase the surface roughness of the first and second conductive layers 112a-c and 116a-c. According to some embodiments, the oxide layer / coating 118a-c may be configured to promote adhesion between the second conductive layers 112a-c and 116a-c and the adhesive resin 122 during lamination.

[0079] According to some embodiments, pads 120a / 120c are substantially free of oxide coatings 118a-c. According to some embodiments, pads 120a / 120c may be coated with a surface finish layer (not shown). According to some embodiments, the finish layer may be configured to protect pads 120a / 120c from oxidation and optionally and / or additionally, for example, to facilitate connection of capacitor 100 to other devices by promoting wire bonding, promoting solderability of pads 120a / 120c, etc. According to some embodiments, the finish layer may comprise one or more metals. According to some embodiments, the one or more metals of the finish layer may include nickel, gold, silver, tin, etc., or any combination thereof. According to some embodiments, the finish layer may be applied by an electroless nickel immersion gold process or any variation thereof.

[0080] According to some implementation schemes, and such Figure 1 As schematically depicted, each of a plurality of capacitor layers / sheets 110 can be attached / stacked layer by layer by an adhesive polymer resin 122 applied therebetween. According to some embodiments, the adhesive polymer resin 122 is configured to attach and fill gaps in the pattern of each of the first conductive layers 112a-c and each of the second conductive layers 116a-c. According to some embodiments, the adhesive polymer resin 122 is configured to electrically isolate each of the first conductive layers 112a-c and each of the second conductive layers 116a-c. As a non-limiting example, such as Figure 1 As shown, the adhesive polymer resin 122 is configured to electrically insulate the second conductive layer 116a of the first capacitor layer 110a from the first conductive layer 112b of the adjacent second capacitor layer 110b, thereby preventing short circuits between them.

[0081] According to some embodiments, the adhesive polymer resin 122 may be made of or comprise a dielectric paste. According to some embodiments, the adhesive polymer resin 122 may be made of or comprise an acrylic resin, epoxy resin, polyimide, or any combination thereof. Each possibility is a separate embodiment.

[0082] According to some embodiments, the thickness of the adhesive polymer resin 122 applied between the first conductive layers 112a-c and the second conductive layers 116a-c can be at least about twice its thickness. In other words, as a non-limiting example, the thickness of the adhesive polymer resin 122 applied between the first conductive layers 112b of the second capacitor layer 110b and between the second conductive layers 116a of the first capacitor layer 110a can be at least about the sum of the thicknesses of the first conductive layers 112b and the second conductive layers 116a.

[0083] According to some implementation schemes, and such Figure 1 As schematically depicted, the thickness of the adhesive polymer resin 122 can vary due to the pattern (pattern gaps) of the first conductive layer 112a-c and the second conductive layer 116a-c.

[0084] According to some embodiments, the thickness of the bonding polymer resin 122 can be in the range of about 12 μm to about 50 μm, about 25 μm to about 50 μm, about 12 μm to about 30 μm, etc. Each possibility is a separate embodiment.

[0085] According to some implementation schemes, and such Figure 1 As schematically depicted, the top surface 102 of capacitor 100 is partially coated with an insulating coating layer 106. Similarly, the bottom (opposite) surface 104 of capacitor 100 is partially coated with an insulating coating layer 108. In some embodiments, coating layer 106 may be the same as or similar to coating layer 108 in terms of its composition and / or thickness. According to some embodiments, coating layers 106 / 108 may be made of or include a protective polymer coating, layer, etc. According to some embodiments, coating layers 106 / 108 may include a solder resist layer / cover. According to some embodiments, coating layers 106 / 108 may be made of or include a cover layer comprising polyimide and an adhesive such as acrylic resin.

[0086] According to some embodiments, coating layer 106 / 108 may be made of or comprise one or more polymers configured to protect the conductive patterns of the first conductive layer 112a and the second conductive layer 116c from environmental influences. According to some embodiments, coating layer 106 / 108 may be configured to provide sufficient insulation to prevent surface breakdown.

[0087] According to some implementation schemes, the capacitance per unit area of ​​each individual capacitor layer of capacitor 100 can be approximately 0.5 nF / cm². 2 Approximately 1 nF / cm 2 Approximately 0.8 nF / cm 2 Approximately 1 nF / cm 2 Within the range of, etc.

[0088] According to some implementation schemes, it has approximately 5 cm 2 The capacitance of the multilayer capacitor 100 can be approximately 40 nF, wherein the capacitor 100 is made of 10 laminated capacitor units. In other words, in some embodiments, the capacitance of the capacitor 100 can be approximately 7 nF / cm². 2 Or larger. As a non-limiting example, the capacitance of the multilayer capacitor 100 could be approximately 7 nF / cm. 2 Or larger, wherein each capacitor cell may include first and second conductive layers having a thickness of about 3 μm, and a dielectric layer having a thickness of about 8 μm therebetween, and wherein an adhesive polymer resin having a thickness of about 25 μm is applied thereon for laminating each capacitor cell.

[0089] refer to Figure 2A -B, which shows a schematic cross-sectional side view of a printed circuit capacitor having a first and second configuration with high breakdown voltage according to some embodiments.

[0090] According to some implementation plans, in Figure 2A The following components 206, 208, 210a-d, 212a-d, 214a-d, 216a-d, 220, and 222 depicted in the text correspond to respectively Figure 1 The aforementioned components 106, 108, 110a-c, 112a-c, 114a-c, 116a-c, 120, and 122 may have substantially the same or similar structure and configuration as them. Similarly, according to some embodiments, in Figure 2B The following components 206', 208', 210a-d', 212a-d', 214a-d', 216a-d', 220' and 222' depicted in the diagram correspond to respectively Figure 1 The aforementioned components 106, 108, 110a-c, 112a-c, 114a-c, 116a-c, 120 and 122 may have substantially the same or similar structure and configuration as them.

[0091] According to some implementation schemes, and such Figure 2AAs shown, a capacitor 200 having a multilayer structure 201 may have a first configuration. According to some embodiments, the first configuration includes an adhesive resin 222 applied between conductive layers having alternating potentials. In other words, adhesive resin 222 is applied between each of the plurality of capacitor layers 210a-d, wherein the first and second conductive layers / sheets 212a-d and 216a-d have alternating positive and negative potentials. According to some embodiments, such as Figure 2A As shown, an adhesive resin 222 is applied to laminate a second conductive layer / sheet 216a having a first potential (e.g., a positive potential) onto a first conductive layer / sheet 216b having a second opposite potential (e.g., a negative potential). Therefore, in some embodiments, a capacitor is formed therebetween, such that the adhesive resin 222 can be configured as its dielectric layer, which in turn can increase the capacitance of the capacitor 200.

[0092] According to some implementation plans, such as Figure 2A As shown, the capacitor 200 may also include a plurality of vias 230 / 232 configured to electrically connect each of the first conductive layers 212a-d and the second conductive layers 214a-d.

[0093] According to some implementation schemes, and such Figure 2B As shown, a capacitor 200' having a multilayer structure 201' can have a second configuration. According to some embodiments, the second configuration includes an adhesive resin 222' applied between conductive layers having substantially the same potential / polarity. In other words, the adhesive resin 222' is applied between each of the plurality of capacitor layers 210a-d', wherein the first and second conductive layers / sheets 212a-d' and 216a-d' have substantially uniform / equal potentials. According to some embodiments, such as Figure 2B As shown, an adhesive resin 222' is applied to laminate a second conductive layer / sheet 216a' having a first potential (e.g., a positive potential) onto a first conductive layer / sheet 216b' having the same polarity (e.g., a positive potential). Therefore, in some embodiments, there may be no potential drop across the adhesive resin 222'. In other words, in some embodiments, in the second configuration, the breakdown voltage of the capacitor 200' may be substantially unaffected by the properties of the adhesive resin 222'.

[0094] refer to Figure 3 It illustrates, according to some embodiments, methods for forming / manufacturing printed circuit capacitors (e.g., but not limited to...). Figure 1 The flowchart 300 of the method for the capacitor 100), and reference Figure 4A -E, which schematically and partially illustrates its steps.

[0095] According to some implementation plans, in Figure 4AThe following components described in -E, 401, 402, 404, 406, 408, 410a, 410b, 410c, 412a, 412b, 412c, 414a, 414b, 414c, 416a, 416b, 416c, 418a, 418b, 418c, 420, and 422, respectively correspond to Figure 1 The aforementioned components 101, 102, 104, 106, 108, 110a, 110b, 110c, 112a, 112b, 112c, 114a, 114b, 114c, 116a, 116b, 116c, 118a, 118b, 118c, 120, and 122 may have substantially the same or similar structure and configuration as them.

[0096] According to some embodiments, in step 302, the method may include obtaining a plurality of capacitor layers / sheets 410a-c. According to some embodiments, and as shown in a cross-sectional side view of the plurality of capacitor layers / sheets 410a-c... Figure 4A The schematic depiction includes multiple capacitor layers / sheets comprising three capacitor layers / sheets. According to some embodiments, the number of capacitor layers / sheets 410a-c may include about 5 or more, about 10 or more, about 15 or more, about 20 or more, about 30 or more, about 40 or more, or any other number of capacitor layers / sheets. Each possibility is a separate embodiment.

[0097] According to some implementation plans, such as Figure 3 As shown in Figure A, each capacitor layer 410a-c includes a first conductive layer 412a-c, a second conductive layer 416a-c, and a dielectric layer 314a-c. According to some embodiments, each dielectric layer 414a-c is located between each first conductive layer 412a-c and each second conductive layer 316a-c. According to some embodiments, the first conductive layer 412a-c may be made of copper or comprise copper. According to some embodiments, the second conductive layer 316a-c may be made of copper or comprise copper. According to some embodiments, the first conductive layer 412a-c may be similar to or identical to the second conductive layer 316a-c in terms of thickness and / or composition.

[0098] According to some embodiments, each of the plurality of capacitor layers / sheets 410a-c can be in the form of a stack, i.e., first and second conductive layers are attached to a dielectric layer located therebetween. According to some embodiments, obtaining the plurality of capacitor layers / sheets 410a-c may optionally include obtaining a plurality of stacks, such as, but not limited to, Oak-Mitsui's FaradFlex. TM .

[0099] According to some embodiments, obtaining multiple stacks may optionally include stripping their first and second conductive layers and forming first and second conductive layers having a desired thickness and / or composition, such that the first and second conductive layers having desired properties are attached to the dielectric layer of each of the multiple stacks.

[0100] According to some embodiments, dielectric layer 414a-c may be made of or comprise one or more polymers. According to some embodiments, dielectric layer 414a-c may be made of or comprise a polymer resin and a material / particles having a high dielectric constant (i.e., a high-permeability additive). According to some embodiments, the polymer resin of dielectric layer 414a-c may be made of or comprise epoxy resin and / or polyimide. According to some embodiments, dielectric layer 414a-c may be a high-permeability additive, such as, but not limited to, Al2O3, TiO2, BaTiO3, etc., or any combination thereof. As a non-limiting example, dielectric layer 414a-c may be in the form of a layered structure, comprising first and second polymers and a high-permeability layer therebetween. According to some embodiments, the initial thickness (i.e., the thickness in step 302) of each of the first conductive layer 412a-c and the second conductive layer 416a-c may be in the range of about 1.5 μm to about 5 μm. According to some embodiments, the initial thickness (i.e., the thickness in step 302) of each of the first conductive layers 412a-c and the second conductive layers 416a-c can be in the range of about 3 μm to about 5 μm. According to some embodiments, the thickness of each of the first and second conductive layers 412a-c and 316a-c can be about 3 μm or less, about 4 μm or less, about 4.5 μm or less, or about 5 μm or less. Each possibility is a separate embodiment.

[0101] According to some embodiments, the initial thickness of each of the first conductive layers 412a-c and the second conductive layers 416a-c (i.e., in some embodiments, the initial thickness of the copper layer / sheet) advantageously allows for the realization of ultra-thin printed circuit capacitors, as described in more detail elsewhere herein. Those skilled in the art will understand that reducing the initial thickness of the first conductive layers 412a-c and the second conductive layers 316a-c (i.e., in some embodiments, reducing the thickness of the copper layer / sheet) results in a reduction in the final thickness of the printed circuit capacitor. According to some embodiments, the thickness of the first and second conductive layers can affect the thickness of the resin applied between each capacitor layer / sheet to attach the capacitor layers to each other, as described in more detail elsewhere herein.

[0102] According to some embodiments, in step 304, the method may include performing a first surface treatment on each of the plurality of capacitor layers 410a-c. According to some embodiments, the first surface treatment may include cleaning the plurality of capacitor layers 410a-c.

[0103] According to some embodiments, the first surface treatment may include performing a first micro-etching on each of the first conductive layers 412a-c and the second conductive layers 416a-c, such as Figure 4A The image is schematically depicted. In some embodiments, as described in detail elsewhere herein, the first micro-etching is configured to enhance photoresist adhesion by smoothing the surface roughness of the first conductive layers 412a-c and the second conductive layers 416a-c. According to some embodiments, the first micro-etching is advantageously configured to etch / remove from the surface of each of the first conductive layers 412a-c and the second conductive layers 416a-c by about 0.5 μm or less, about 0.4 μm or less, about 0.3 μm or less, or about 0.2 μm or less. Each possibility is a separate embodiment. As a non-limiting example, the first micro-etching is configured to etch / remove from about 0.2 μm to about 0.5 μm of copper from each of the first conductive layers 412a-c and the second conductive layers 416a-c.

[0104] Advantageously, in some embodiments, removing about 0.5 μm or less can reduce the thickness variation of the remaining portions of the first conductive layers 412a-c and the second conductive layers 416a-c (e.g., the remaining portions of the copper sheet / layer), which in turn facilitates substantially uniform etching. Therefore, in some embodiments, image / pattern formation is facilitated. In some embodiments, achieving substantially uniform thicknesses of the first conductive layers 412a-c and the second conductive layers 416a-c (e.g., copper layers) while minimizing their thickness variations can result in maintaining integrity and minimizing the probability of defects forming in the first conductive layers 412a-c and the second conductive layers 416a-c.

[0105] According to some implementation schemes, the first micro-etching may include wet etching processes, etc.

[0106] According to some embodiments, in step 306, the method may include forming a pattern on each of the first conductive layers 412a-c and the second conductive layers 416a-c of each of the plurality of capacitor layers / sheets 410a-c. According to some embodiments, the patterns formed on each of the first conductive layers 412a-c and the second conductive layers 416a-c may be similar or identical, as schematically depicted in FIG4. According to some embodiments, the patterns formed on each of the first conductive layers 412a-c and the second conductive layers 416a-c may be different. According to some embodiments, a first portion of the pattern formed on the first conductive layers 412a-c and / or the second conductive layers 416a-c may be similar or identical, while a second portion (i.e., the remaining portion) of the pattern may be different. Each possibility is a separate embodiment.

[0107] According to some implementation schemes, the pattern can be formed by any suitable process, such as, but not limited to, etching (e.g., wet / chemical etching), photolithography, etc.

[0108] According to some embodiments, patterning may include applying a photoresist layer to the surfaces of the first conductive layers 412a-c and the second conductive layers 416a-c. According to some embodiments, the photoresist may be applied by spin coating, dip coating, or dry film lamination.

[0109] According to some embodiments, patterning may include, for example, exposing the photoresist by applying sufficient wavelength and dose to it. According to some embodiments, photoresist exposure can be performed using a blocking mask. According to some embodiments, photoresist exposure can be performed by implementing maskless processes, such as direct imaging, laser imaging, etc. According to some embodiments, photoresist exposure can be configured to alter the chemical properties of the exposed areas, thereby allowing selective removal of the resist in a subsequent resist development stage.

[0110] According to some implementation schemes, pattern formation may include the development of a resist.

[0111] According to some embodiments, patterning may include removing material from the first conductive layers 412a-c and the second conductive layers 416a-c. According to some embodiments, material removal may include removing the resist by any suitable process after patterning, such as etching, stripping, laser ablation, or any combination thereof.

[0112] According to some embodiments, in step 308, the method may include performing a second surface treatment on each of the plurality of capacitor layers 410a-c. According to some embodiments, the second surface treatment may include performing a post-patterning surface treatment. According to some embodiments, the post-patterning surface treatment may include cleaning the plurality of capacitor layers 410a-c by any suitable cleaning procedure.

[0113] According to some embodiments, the post-patterning surface treatment may include a second micro-etching of each of the first conductive layers 412a-c and the second conductive layers 416a-c. According to some embodiments, the second micro-etching may include etching a portion of copper from the first conductive layers 412a-c and the second conductive layers 416a-c to form an environmentally stable copper oxide compound, as described in detail elsewhere herein.

[0114] According to some embodiments, the second micro-etching can be configured to trim / adjust the surface roughness of the first conductive layers 412a-c and the second conductive layers 416a-c, and provide environmental protection for the stacking steps / processes. According to some embodiments, the second micro-etching can advantageously be configured to etch / remove from the surface of each of the first conductive layers 412a-c and the second conductive layers 416a-c by about 0.5 μm or less, about 0.4 μm or less, about 0.3 μm or less, or about 0.2 μm or less. Each possibility is a separate embodiment. As a non-limiting example, the second micro-etching can be configured to etch / remove from about 0.2 μm to about 0.5 μm of copper from each of the first conductive (copper) layers 412a-c and the second conductive (copper) layers 416a-c. Advantageously, in some embodiments, removing about 0.5 μm or less can reduce the thickness variation of the remaining portions of the first conductive layers 412a-c and the second conductive layers 416a-c (e.g., the remaining portions of the copper sheet / layer), which in turn reduces the final thickness of the printed circuit capacitor while maintaining and / or ensuring process reliability.

[0115] According to some implementation plans, such as Figure 4C As shown, the second surface preparation may include forming a substantially stable surface oxide 418a-c on each of the first conductive layers 412a-c and the second conductive layers 416a-c. According to some embodiments, the surface oxide may be formed thereon simultaneously. According to some embodiments, wherein each of the first conductive layers 412a-c and the second conductive layers 416a-c is made of copper, the surface oxide may be made of an environmentally stable copper oxide or include environmentally stable copper oxides such as CuO (also known as "black oxide"), and mixtures of CuO and Cu2O oxides (also known as "brown oxide").

[0116] According to some implementations, in step 310, the method may include stacking multiple capacitor layers / sheets 410a-c layer by layer to create a multilayer structure (e.g., but not limited to...). Figure 1 (The capacitor 100 in the multilayer structure 101). According to some embodiments, stacking capacitor layers / sheets 410a-c may include pre-stacking each of the capacitor layers / sheets 410a-c layer by layer.

[0117] According to some implementation plans, such as Figure 4D As shown, stacking multiple capacitor layers / sheets 410a-c layer by layer may include applying an adhesive polymer resin 422 between each of the multiple capacitor layers / sheets 410a-c. According to some embodiments, the adhesive polymer resin 422 is configured to attach the multiple capacitor layers 410a-c to each other and provide electrical isolation therebetween.

[0118] According to some embodiments, the adhesive polymer resin 422 may be made of or comprise a dielectric paste. According to some embodiments, the adhesive polymer resin 422 may be made of or comprise an acrylic resin, epoxy resin, polyimide, or any combination thereof. Each possibility is a separate embodiment.

[0119] According to some implementation schemes, the thickness of the polymer resin 322 may be at least approximately the sum of the thicknesses of the first conductive layer 412b and the second conductive layer 416a.

[0120] According to some embodiments, in step 312, the method may include drilling through through-holes in the first conductive layers 412a-c and the second conductive layers 416a-c. According to some embodiments, the drilling may be performed to electrically connect each of the first layers 412a-c to each of the third layers 416a-c having a positive potential, and each of the first layers 412a-c to each of the third layers 416a-c having a negative potential.

[0121] According to some embodiments, in step 314, the method may include performing a third surface treatment. According to some embodiments, the third surface treatment may include surface cleaning by any suitable process. According to some embodiments, the third surface treatment may include a third micro-etching. According to some embodiments, the third surface treatment may include electroless copper plating.

[0122] According to some embodiments, in step 316, the method may include electroplating, such as copper electroplating. According to some embodiments, the electroplating may be configured to form a conductive coating on the borehole wall in step 314.

[0123] According to some embodiments, in step 318, the method may include forming an outer layer pattern on the top surface / surface 402 and the bottom surface / side surface 404 to form conductive pads. According to some embodiments, forming the outer layer pattern may include performing a second pre-patterning surface treatment. According to some embodiments, the second pre-patterning surface treatment may include cleaning and micro-etching of the first conductive layer 412a or a portion thereof and the second conductive layer 416c or a portion thereof. According to some embodiments, the second pre-patterning surface treatment in step 318 may be similar to or the same as the pre-patterning surface treatment in step 304.

[0124] According to some implementations, conductive pads may include conductive areas of any type, shape, or configuration, such as, but not limited to, pads, wires, etc., or combinations thereof.

[0125] According to some embodiments, in step 320, the method may include a portion of the top surface / surface 402 and a portion of the bottom surface / side surface 404 of the multilayer structure 401 (e.g., as shown in the figure). Figure 4E An isolation coating is applied to layers 406 and 408 shown. According to some embodiments, the isolation coating 406 / 408 may be made of or include one or more polymers. According to some embodiments, the isolation coating 406 / 408 may include a solder mask or any other type of protective coating, layer, etc. According to some embodiments, the protective polymer layer 406 / 408 may be made of or include epoxy resin. According to some embodiments, the isolation coating 406 / 408 may be made of or include Kapton®.

[0126] According to some embodiments, the thickness of the insulating coating 406 / 408 can be in the range of about 25um to about 50um, about 20um to about 40um, about 25um to about 35um, etc. Each possibility is a separate embodiment.

[0127] According to some embodiments, in step 322, the method may include performing a fourth surface treatment. According to some embodiments, the fourth surface treatment may include surface cleaning and a fourth micro-etching. Specifically, in some embodiments, step 322 may include performing micro-etching on a second portion (i.e., the top surface / side 402) of the first surface / side 402 and a second portion (i.e., the bottom surface / side 404) of the second surface / side 404 of the multilayer structure 401. According to some embodiments, the fourth micro-etching is configured to remove oxides 418a-c (e.g., CuO and / or CuO2) from the surface of the pads.

[0128] According to some implementation schemes, the micro-etching of the fourth surface treatment can be carried out by wet etching techniques, etc.

[0129] According to some embodiments, each of the first micro-etch and / or the second micro-etch and / or the third micro-etch and / or the fourth micro-etch can be configured to remove an area of ​​about 0.5 μm or less, about 0.4 μm or less, or about 0.3 μm or less. Each possibility is a separate embodiment. According to some embodiments, each of the first micro-etch and / or the second micro-etch and / or the third micro-etch and / or the fourth micro-etch can be configured to remove an area of ​​about 0.2 μm to about 0.5 μm.

[0130] According to some implementation schemes, the total removal thickness through the first micro-etching, the second micro-etching, the third micro-etching and the fourth micro-etching may not exceed about 2 μm.

[0131] According to some implementations, the total thickness removed from each of the first copper layer and the second copper layer by the first micro-etch, the second micro-etch, and the third micro-etch may not exceed about 2 μm.

[0132] According to some embodiments, in step 324, the method may include performing a surface finishing of the capacitor 400. According to some embodiments, the surface finishing may include applying a surface finishing layer, etc., to pads (not shown). According to some embodiments, the finishing layer is configured to protect the conductive pads 420a / 420b from oxidation and, optionally, to promote their solderability.

[0133] According to some embodiments, surface finishing may include applying one or more metals to the conductive pad. In other words, the finishing layer may include one or more metals, such as, but not limited to, nickel, gold, silver, tin, etc., or any combination thereof. According to some embodiments, surface finishing may include electroless nickel plating, immersion gold, immersion silver, tin coating, etc., or any other variations thereof.

[0134] According to some embodiments, the thickness of the finishing layer can be about 5 μm or less, about 4 μm or less, about 3 μm or less, or about 2 μm or less. Each possibility is a separate embodiment. According to some embodiments, the thickness of the finishing layer can range from about 0.1 μm to about 30 μm, about 0.1 μm to about 2 μm, about 1 μm to about 10 μm, etc. As a non-limiting example, the surface finishing may include electroplated gold and / or dip-plated silver with a thickness of about 0.1 μm or less. As another non-limiting example, the surface finishing includes tin coating, and the thickness of the finishing layer can range from about 10 μm to about 20 μm.

[0135] In the specification and claims of this application, the words “comprising” and “having” and their forms are not limited to members of the list that may be associated with these words.

[0136] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In case of conflict, the patent specification including the definitions shall prevail. As used herein, the indefinite articles a (“a” and “an”) mean “at least one” or “one or more” unless the context clearly indicates otherwise.

[0137] It should be understood that, for clarity, certain features of this disclosure described in the context of individual embodiments may also be provided in combination in a single embodiment. Conversely, for brevity, various features of this disclosure described in the context of individual embodiments may also be provided individually or in any suitable sub-combination or as suitably as in any other described embodiments of this disclosure. Features described in the context of an embodiment should not be considered essential features of that embodiment unless expressly specified otherwise.

[0138] Although the stages of a method according to some embodiments may be described in a specific order, the method of this disclosure may include some or all of the described stages performed in a different order. The method of this disclosure may include several or all of the described stages. No particular stage is considered essential to the method unless expressly stated otherwise.

[0139] Although this disclosure has been described in conjunction with specific embodiments thereof, it will be apparent to those skilled in the art that many alternatives, modifications, and variations may be made. Therefore, this disclosure encompasses all such alternatives, modifications, and variations that fall within the scope of the appended claims. It should be understood that the scope of this disclosure is not necessarily limited in its application to the details of the construction and arrangement of the components and / or methods set forth herein. Other embodiments may be practiced and may be implemented in various ways.

[0140] The wording and terminology used herein are for descriptive purposes and should not be construed as limiting. Any references or designations used in this application should not be interpreted as an admission that such references are prior art. Section headings are used herein to facilitate understanding and should not be construed as necessarily limiting.

Claims

1. A high breakdown voltage printed circuit ultrathin capacitor, the capacitor comprising: A multilayer structure comprising multiple capacitor layers, each of the multiple capacitor layers comprising: First and second conductive layers comprising copper, each of the first and second conductive layers having a thickness not exceeding about 3 μm; and A dielectric layer located between the first and second conductive layers, the dielectric layer having a thickness of about 8 μm to about 15 μm; Each of the first and second conductive layers includes a conductive pattern; The multilayer structure includes an adhesive resin applied between each of the plurality of capacitor layers having a substantially equipotential, the adhesive resin being configured to fill gaps in a conductive pattern having a substantially equipotential, thereby avoiding dependence of breakdown voltage on the properties of the adhesive resin. The thickness of the adhesive resin is at least approximately the sum of the thicknesses of the first and second conductive layers; The total thickness of the printed circuit board and capacitors is approximately 1 mm or less; and The capacitor is capable of operating at an applied voltage of up to about 2,500V.

2. The printed circuit ultrathin capacitor of claim 1, wherein the bonding resin is configured to fill the gaps between each of a plurality of capacitor layers having positive and negative potentials in the conductive pattern, thereby increasing its capacitance.

3. The printed circuit ultrathin capacitor according to claim 1 or 2, wherein its capacitance per unit area and per capacitor layer is approximately 0.5 nF / cm². 2 Approximately 1 nF / cm 2 .

4. The printed circuit ultrathin capacitor according to any one of claims 1-3, wherein the thickness of each of the first and second conductive layers is in the range of about 0.5 μm to about 1.5 μm.

5. The printed circuit ultrathin capacitor according to any one of claims 1-4, wherein the thickness of the bonding resin is in the range of about 12 μm to about 50 μm.

6. The printed circuit ultrathin capacitor according to any one of claims 1-5, wherein the bonding resin is made of or includes acrylic resin, epoxy resin or polyimide.

7. The printed circuit ultrathin capacitor according to any one of claims 1-6, wherein the dielectric layer is made of acrylic resin, epoxy resin or polyimide or includes acrylic resin, epoxy resin or polyimide.

8. The printed circuit ultrathin capacitor according to claim 7, wherein the dielectric layer comprises one or more high-capacitance additives: Al2O3, TiO2, BaTiO3, or a combination thereof.

9. The printed circuit ultrathin capacitor according to any one of claims 1-8, wherein the plurality of capacitor layers comprises at least about 5 capacitor layers.

10. The printed circuit ultrathin capacitor according to any one of claims 1-9, wherein the plurality of capacitor layers comprises about 20 capacitor layers, and wherein the total thickness of the printed circuit board and the capacitor is about 0.8 mm.

11. The printed circuit ultrathin capacitor according to any one of claims 1-10, wherein the capacitance of the printed circuit ultrathin capacitor is about 40 nF, and wherein the total area of ​​the plurality of capacitor layers is about 5 cm². 2 .

12. The printed circuit ultrathin capacitor according to any one of claims 1-11, wherein the capacitor is flexible.

13. The printed circuit ultrathin capacitor of claim 12, wherein each of the plurality of capacitor layers is capable of bending to a radius of about 10 cm to about 20 cm.

14. The printed circuit ultrathin capacitor according to any one of claims 1-13, wherein the top and bottom of the first portion of the multilayer structure are coated with an insulating protective layer, the insulating protective layer being configured to provide electrical insulation to prevent surface breakdown of the capacitor.

15. The printed circuit ultrathin capacitor according to any one of claims 1-14, wherein pads are formed on the top and bottom of the second portion of the multilayer structure, wherein the pads comprise copper, and wherein the pads are coated with a finishing layer comprising one or more of the following: nickel, gold, silver, and tin.

16. The printed circuit ultrathin capacitor of claim 15, wherein the thickness of the finishing layer is between about 0.1 μm and about 20 μm.

17. A method for manufacturing a printed circuit ultrathin capacitor, the method comprising: A plurality of capacitor layers are obtained, each of the plurality of capacitor layers comprising first and second conductive copper layers and a dielectric layer located between the first and second conductive copper layers; A first surface treatment is performed, the first surface treatment including a pre-patterning surface treatment of first and second conductive copper layers and a first micro-etching, the first micro-etching being configured to adjust the surface roughness of the first and second conductive copper layers; A pattern is formed on each of the first and second conductive copper layers; A second surface treatment is performed, which includes post-patterning surface treatment and second micro-etching. The plurality of capacitor layers are stacked one by one, the stacking comprising applying an adhesive resin configured to attach the plurality of capacitor layers to each other and laminating them to form a multilayer structure; Drilling is performed to form through holes, which are configured to electrically connect each of the first and second conductive copper layers having positive and negative potentials; Electroplating of the through holes; Form an external pattern to obtain pads; An insulating coating is applied to at least a portion of the multilayer structure; A fourth surface treatment is performed, the fourth surface treatment including surface cleaning and a fourth micro-etching, the fourth surface cleaning being configured to remove copper oxide from the pads; as well as Surface finishing is performed on multi-layer structures.

18. The method of claim 17, wherein the first micro-etching and / or the second micro-etching and / or the third micro-etching and / or the fourth micro-etching comprises a wet etching process.

19. The method of claim 17 or 18, wherein the first micro-etch and / or the second micro-etch and / or the third micro-etch and / or the fourth micro-etch is configured to remove about 0.5 μm or less.

20. The method according to any one of claims 17-19, wherein the first micro-etching, the second micro-etching, the third micro-etching, and / or the fourth micro-etching removes no more than about 2 μm.

21. The method according to any one of claims 17-20, wherein the thickness of the bonding resin is at least approximately the sum of the approximate thickness of the first and second conductive copper layers and the approximate depth of the gap in the copper pattern.

22. The method according to any one of claims 17-21, wherein forming the pattern comprises performing resist lamination; laser direct imaging to expose the resist, wherein the resist is a solid; developing the resist; and removing material from the first and second conductive copper layers.

23. The method according to any one of claims 17 to 22, wherein obtaining the plurality of capacitor layers comprises obtaining first and second conductive copper layers having a thickness of about 3 μm or less.

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