Semiconductor layer for voltaic devices

Abstract

A semiconductor layer on a substrate, the semiconductor layer being a solid particulate composite of semiconductor particles and cohesive particles, wherein the cohesive particles comprise from 10% to 45% by volume of the solid particulate composite. Also provided is a method of forming the semiconductor layer on a substrate, the method comprising mixing semiconductor particles, cohesive particles and a non-solvent liquefying agent to form a solid suspension, coating the solid suspension on a substrate and removing the liquefying agent from the coated solid suspension to form the semiconductor layer.

Description

Cross-references to related applications

[0001] This application claims priority to Australian Provisional Patent Application 2023904192, filed on 22 December 2023, the contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to an improved semiconductor layer and a method for forming such an improved semiconductor layer, which is suitable for use in photovoltaic devices such as photovoltaic devices. While common uses of such devices include solar cells for generating solar energy, this application is not limited to these uses. Background Technology

[0003] Photovoltaic devices rely on the conversion of light into electrical energy using semiconductor materials that exhibit the photovoltaic effect. Semiconductor layers are crucial for such devices; these layers absorb incident radiation (such as sunlight) and generate electron-hole pairs to produce electricity. These semiconductor layers are typically formed through recrystallization processes, such as spin-coating semiconductor chemicals dissolved in a solvent, where the effective area of ​​a single cell is typically only a few millimeters. 2 Within the range.

[0004] Such methods can also be limited in thickness and prone to short-circuiting, often due to poor wettability of the underlying substrate and the difficulty in subsequently forming the semiconductor layer, leading to pinholes. Furthermore, the need for high-temperature annealing to crystallize the semiconductor to form the desired atomic structure again limits the form of the underlying substrate and / or other layers in the voltaic device.

[0005] The present invention aims to provide an efficient semiconductor layer that can be scaled to a larger surface area and can be formed relatively easily on substrates that do not need to be complex or special. In this regard, although the following description may sometimes emphasize that the semiconductor layer of the present invention is intended for use in photovoltaic devices, the invention is not limited thereto. Specifically, the present invention relates to semiconductor layers for use in all photovoltaic devices. Summary of the Invention

[0006] The present invention provides a semiconductor layer on a substrate, the semiconductor layer being a solid particle composite of semiconductor particles and cohesive particles, wherein the cohesive particles comprise 10% to 45% (volume percentage) of the solid particle composite.

[0007] The present invention also provides a method for forming a semiconductor layer on a substrate, the method comprising mixing semiconductor particles, cohesive particles and a non-solvent liquefying agent to form a solid suspension, coating the solid suspension on the substrate, and removing the liquefying agent from the coated solid suspension to form a semiconductor layer, wherein the semiconductor layer is a solid particle composite comprising semiconductor particles and cohesive particles, wherein the cohesive particles comprise 10% to 45% (volume percentage) of the solid particle composite.

[0008] Alternatively, cohesive particles may constitute 20% to 40% (volume percentage) of the solid particulate composite. Furthermore, cohesive particles may constitute 25% to 35% (volume percentage) of the solid particulate composite. Additionally, cohesive particles may constitute approximately 30% (volume percentage) of the solid particulate composite.

[0009] The semiconductor layer of this invention is substrate-independent, thus allowing the use of simple substrates such as glass, foil, or polymers. Therefore, it has been found that voltaic devices incorporating the semiconductor layer of this invention can have conventional structures (substrate, electron transport layer, semiconductor, hole transport layer, top contact structure) or inverted structures (substrate, hole transport layer, semiconductor, electron transport layer, top contact structure), and can have or not have a transport layer. This is useful, one reason being that it allows for the existence of depletion regions within the device, which are the target areas where the energy source strikes and generates electron / hole pairs that produce a current output in the device. Depending on the application of the device, the ideal location of such depletion regions within the device varies, as the device can be exposed to the energy source from opposite sides.

[0010] Furthermore, the present invention allows for customization of the composition of the semiconductor layer, for example by changing the stoichiometry of the semiconductor layer, by doping the semiconductor layer with particles of different compositions, or by employing a semiconductor layer thickness suitable for the requirements of the final voltaic device.

[0011] In fact, it should be understood that in some forms of the present invention, post-processing steps can be used to further modify the semiconductor layer so that the properties and / or functions of the obtained semiconductor are enhanced, which can change the volume ratio of semiconductor particles to cohesive particles in the semiconductor layer.

[0012] Furthermore, it should be understood that in some forms of the invention, it may be desirable to coat the substrate with multiple semiconductor layers of the invention, such that the method of the invention includes multiple solid suspension coating steps, each time removing a non-solvent liquefying agent to form a new semiconductor layer.

[0013] Furthermore, regarding the phrase "semiconductor layer on substrate" as used herein, those skilled in the art will understand that it may be desirable to include other types of layers between the substrate and the semiconductor layer. Therefore, the wording "on substrate" must be understood in this regard.

[0014] Therefore, the present invention provides versatility in terms of the substrate used, device configuration, semiconductor composition, thickness and roughness, as well as device size and shape.

[0015] Regarding preferred general features of the semiconductor layer of the present invention, the layer preferably has the thickness required for a given radiation energy. In this respect, the higher the radiation energy, the thicker the layer is required. For low-energy photovoltaic devices, such as those with incident photon energies in the range of 0.5 eV to 3.0 eV, the semiconductor layer will be thinner, and ideally will have a thickness in the range of 100 nm to 400 micrometers (final dried thickness). In other forms, the thickness of the semiconductor layer may be in the range of 200 nm to 350 micrometers, or in the range of 200 nm to 200 micrometers, or in the range of 200 nm to 100 micrometers, or in the range of 200 nm to 50 micrometers, or in the range of 200 nm to 5 micrometers.

[0016] Nevertheless, it should be understood that the thickness of the semiconductor layer is also related to the rheological properties (i.e., viscosity as a function of shear rate) of the solid suspension formed in this method. In this regard, viscosity increases with increasing solid concentration in the suspension (and vice versa), wherein the method of the present invention preferably uses a higher viscosity to facilitate coating the solid suspension onto the substrate. In the method of the present invention, the solid fraction in the solid suspension is preferably in the range of 15% to 30% (volume percentage), or in the range of 18% to 25% (volume percentage), 20% to 23% (volume percentage), or more preferably about 21% (volume percentage).

[0017] In one formulation, regarding the preferred viscosity of the solid suspension, it has been found advantageous to shear-thin the solid suspension, meaning that the solid suspension flows when subjected to shear forces, thereby facilitating coating the solid suspension onto the substrate. In this respect, when the shear force ceases, the solid suspension will have an effectively high viscosity to maintain its shape and form on the substrate, thus helping to prevent further flow of the solid suspension.

[0018] Viscosity is also inversely proportional to particle size; for a given solids fraction, smaller particles provide higher viscosity. Therefore, it has been recognized that a balance needs to be struck when determining the ideal particle sizes for semiconductor and cohesive particles. In a preferred embodiment, the diameters of the semiconductor and cohesive particles are in the range of 200 nm to 5000 nm, and they are provided in the form of a dry powder for use in this method.

[0019] In another preferred embodiment, the method may include compacting the semiconductor layer after or during the removal of the liquefying agent. This compaction helps to densify the solid particle composite and / or improve the mechanical strength of the semiconductor layer. Compaction can be provided by known compaction equipment, such as a uniaxial hydraulic press, a roller press, or a calender, which may or may not provide some degree of heating during the compaction process.

[0020] In this regard, it should be understood that the preferred objective is to maintain the voltaic properties of the semiconductor particles after they have been formed in the semiconductor layer. To this end, it has been found advantageous to include larger particles, in which intraparticle properties are maximized relative to interparticle properties. This helps to minimize the amount of particle-to-particle contact (interparticle) and maximize the amount of internal particle mechanisms (intraparticle).

[0021] Therefore, ideally, the compaction step in the method of the present invention can be used to densify the solid particulate composite, thereby maximizing the physical contact between adjacent particles. Furthermore, maximizing the contact between particles also facilitates the cohesive effect exerted by the cohesive particles.

[0022] Therefore, it should be understood that the semiconductor layer of the present invention formed from the particulate composite ideally has a non-zero porosity. For explanation, a zero-porosity semiconductor layer would be the extreme limit, where only intraparticle mechanisms exist and no interparticle mechanisms are present, which would mean a single-crystal semiconductor with zero porosity. However, this is undesirable for the present invention because it would require the use of the problematic, difficult, and challenging coating process mentioned above.

[0023] Therefore, it should be understood that the other extreme would be the use of very small particles, where interparticle mechanisms are maximized while intraparticle mechanisms are minimized. However, this often results in semiconductor layers with high porosity and poor performance.

[0024] In this invention, generally speaking, the semiconductor layer is a solid particle composite of semiconductor particles and cohesive particles, which should be understood as ideally having a non-zero porosity. In this invention, interparticle mechanisms are preferably minimized, preferably achieved by using relatively large particles. However, the particles are ideally connected into a network structure, which is relatively dense and minimizes porosity.

[0025] Therefore, the final semiconductor layer preferably possesses the desired voltaic function, i.e., the layer absorbs incident radiation and generates electron-hole pairs, which are then transported to electrodes under the influence of an internal electric field to be extracted from the device to generate electricity. The semiconductor layer also preferably possesses the desired mechanical strength to allow for strong adhesion to any substrate and strong cohesion so that the layer does not crumble or disintegrate. In this respect, the ideal mechanical strength is: sufficiently high cohesion in the solid particulate composite so that it can withstand any reasonable external mechanical force without deterioration.

[0026] Regarding the material of the semiconductor particles in the semiconductor layer of the present invention, preferably, the semiconductor particles should be a material with a medium-sized and non-zero electronic band gap and behave as an insulator at absolute zero. With this in mind, it should be understood that at temperatures below the melting point of the semiconductor material, electrons can be thermally excited from the top of the valence band to the bottom of the conduction band (crossing the band gap). In contrast, materials with large band gaps are insulators (no amount of thermal excitation can excite electrons to cross the band gap), while materials with no band gap are conductors.

[0027] Semiconductor materials can be inherently semiconductors (intrinsic semiconductors) or may require some form of doping to acquire semiconductor properties (extrinsic semiconductors). In the latter case, doping typically leads to a reduction in the band gap, allowing thermal excitation to excite electrons across the band gap. Furthermore, more than one semiconductor material can be used, resulting in a semiconductor layer comprising more than one type of semiconductor particle.

[0028] More specifically, the semiconductor material may be one or more materials selected from the group consisting of: i. Silicon, germanium, etc.; ii. Silicon carbide, gallium nitride, aluminum nitride, gallium arsenide, diamond, aluminum arsenide, aluminum gallium arsenide, boron nitride, zinc selenide, etc.; iii. N-doped silicon carbide, N-doped gallium nitride, N-doped silicon, etc.; iv. Zinc oxide, titanium dioxide, nickel oxide, tin oxide, copper oxide, zinc sulfide, tungsten oxide, molybdenum oxide, etc.; v. Perovskite compounds with crystal structures conforming to the general formula ABX3, including cesium lead tribromide, methylammonium lead triiodide, cesium tin trichloride, etc.; and vi. Poly(3,4-ethylenedioxythiophene): polystyrene sulfonate; polyaniline: chloride; polypyrrole: perchlorate; polythiophene: chloride; poly(3-hexylthiophene): chloride; poly(3,4-ethylenedioxythiophene): p-toluene sulfonate, etc.

[0029] Regarding perovskite compounds, these include specific minerals “perovskite” that conform to the general formula ABX3. “A” and “B” are positively charged ions (cations), typically of different sizes, while X is a negatively charged ion (anion) that binds to both cations, and the “A” atom is typically larger than the “B” atom. The ideal cubic structure of the B cation is 6-coordinated, surrounded by an anionic octahedron, and the A cation is 12-coordinated, with 12-fold cuboctahedral coordination. Other perovskite forms may exist where one or both of the A and B sites possess A1 x-1 A2 x and / or B1 y-1 B2 y The configuration of X may deviate from the ideal coordination configuration due to changes in the oxidation state of the ions within sites A and B. Natural compounds with this structure include perovskite, loparite, and silicate perovskite bridgmanite.

[0030] In a preferred form, the semiconductor material will be an inorganic halide perovskite (e.g., CsPbBr3) or a hybrid organic-inorganic halide perovskite (e.g., MAPbI3).

[0031] As described above, the final semiconductor layer preferably possesses the desired voltaic function, i.e., the layer absorbs incident radiation and generates electron-hole pairs, which are then transported to electrodes under the influence of an internal electric field to be extracted from the device to generate electricity. Thus, ideally, the cohesive particles should be materials that do not inhibit this function, are solid at room temperature, and also have an affinity for semiconductor grain boundaries.

[0032] In this regard, the cohesive particles used to form the semiconductor layer are preferably materials capable of providing mechanical cohesion to the semiconductor layer without impairing the voltaic performance of the voltaic device containing the semiconductor layer. A preferred example is polyethylene glycol, which is solid at room temperature. Other suitable cohesive materials are polyamides, epoxy resins, etc.

[0033] Regarding the liquefying agents used in the methods of the present invention, all liquefying agents mentioned throughout this specification are "non-solvent" liquefying agents, in order to narrow down the list of preferred liquefying agents to exclude those that may dissolve semiconductor particles or cohesive particles.

[0034] In a preferred embodiment, the non-solvent liquefying agent used to form the solid suspension should be of the type that allows the solid suspension to flow, thereby allowing the use of simple thin-film coating processes such as doctor blade coating, bar coating, or slot die coating.

[0035] Ideally, the non-solvent liquefying agent should also be of the type that allows the liquefying agent to be easily removed from the coated solid suspension, such as by using a relatively low-temperature drying process, for example, a drying temperature of about 40°C to 100°C.

[0036] Based on the materials of the aforementioned semiconductor particles and cohesive particles, suitable liquefying agents can be envisioned as glycerol, ethylene glycol, ethyl cellulose, isopropanol, n-butanol, or water, etc.

[0037] From the above description of the invention, it should be understood that the improved semiconductor layer can maintain the chemical and voltaic properties of the particulate material without the need for complex solvents or antisolvents, without the need for any heat treatment of the semiconductor to induce the desired properties, or without the need for a specific substrate to accommodate complex semiconductor processing.

[0038] Finally, the present invention also provides a voltaic device, such as a photovoltaic device, comprising a semiconductor layer on a substrate, the semiconductor layer being a solid particle composite of semiconductor particles and cohesive particles, wherein the cohesive particles constitute 10% to 45% (volume percentage) of the solid particle composite. Alternatively, the cohesive particles may constitute 20% to 40% (volume percentage) of the solid particle composite. Furthermore, the cohesive particles may constitute 25% to 35% (volume percentage) of the solid particle composite. Further, the cohesive particles may constitute approximately 30% (volume percentage) of the solid particle composite. Detailed Implementation

[0039] The invention will now be described with reference to preferred embodiments illustrated by various working examples. However, the following description does not limit the generality of the above description.

[0040] In the first embodiment of the present invention (prepared for comparison with the three comparative examples described below), 1.5 g of semiconductor particle perovskite compound CsPbBr3 was mixed with 0.15 g of pre-ground cohesive particles of polyethylene glycol (PEG) in a vial, and then 1 mL of the non-solvent liquefying agent isopropanol was added. The mixture was stirred with a magnetic stirrer for 30 minutes to produce a solid suspension. The particle size of both the semiconductor particles and the cohesive particles was 200 nm to 5 micrometers.

[0041] The solid suspension was then coated onto a glass substrate pre-coated with 500 nm fluorine-doped tin oxide (FTO) and 35 nm zinc oxide (ZnO) as electron transport layers using a blade coating process. The resulting semiconductor layer was then dried at 60°C for 1 hour to remove substantially all of the liquefying agent. The thickness of the semiconductor layer was measured to be 45 micrometers using a mechanical profilometer, with uniform coverage exceeding 20 cm. 2 The area of ​​the layer was measured, and the non-zero porosity of the layer was determined. Then, a 150 nm hole transport layer (NiO) was coated onto this layer. x ) and 150 nm electrodes (Au) to form a voltaic device.

[0042] Before proceeding to the measured electrical properties of this exemplary voltaic device, it should be understood that the semiconductor layer can also be subjected to a rolling process while still warm to compact and densify the layer. In this embodiment, this results in the formation of a more densely compacted solid particle composite, which consists of approximately 70% semiconductor particles and approximately 30% cohesive particles by solid volume. Due to this compaction of the particles, the resulting layer still has a non-zero porosity.

[0043] The electrical performance of the formed voltaic device was characterized by measuring the current flowing through the device as a function of the voltage applied between the two electrodes (FTO and Au) using a source meter unit. Current-voltage curves were measured under both "dark" (no light) and "illuminated" (exposed to a solar simulator) conditions. Short-circuit current, open-circuit voltage, fill factor, and efficiency were determined by the illumination response; note that the open-circuit voltage in the dark condition was 0.10 V. The electrical performance is reported in Table 1.

[0044]

[0045] Table 1 In the first comparative example, a 0.5 M solution of the semiconductor perovskite compound CsPbBr3 was dissolved in dimethyl sulfoxide (DMSO), wherein the molar ratio of liquid polyethylene glycol to CsPbBr3 was 1:0.1. This liquid was spin-coated to a 5 cm thick layer. 2 The substrate was coated with FTO on a glass substrate with a pre-coated 30 nm layer of amorphous ZnO as an electron transport layer. The substrate was preheated to 85°C before spin coating.

[0046] The solution was spin-coated at 500 RPM for 10 seconds, followed by spin-coating at 2000 RPM for 30 seconds. CsPbBr3 was annealed at 120°C to 150°C for 30 minutes to remove DMSO and crystallize the perovskite compound. The resulting semiconductor layer was 300 nm thick. NiO was then coated onto this layer. x (30 nm) and Au (180 nm) to recreate the voltaic device, although it is not the device according to the invention.

[0047] The electrical performance was characterized again by measuring the current flowing through the device as a function of the voltage applied between the two electrodes using the source instrumentation. Current-voltage curves were measured under both "dark" (no light) and "lit" (exposed to a solar simulator) conditions. Short-circuit current, open-circuit voltage, fill factor, and efficiency were determined by the illumination response. The electrical performance is reported in Table 2.

[0048]

[0049] Table 2 In the second comparative example, a two-step recrystallization process was used. First, a 1 M solution of the precursor compound PbBr2 was dissolved in dimethylformamide (DMF), wherein the molar ratio of liquid polyethylene glycol to PbBr2 was 1:0.05, and the solution was stirred at 65°C to 80°C for more than 4 hours. At 80°C, the liquid was spin-coated to a 5 cm thick layer. 2 The substrate was coated with FTO on a glass substrate with a pre-coated 30 nm layer of amorphous ZnO as an electron transport layer. The substrate was preheated to 80°C before spin coating.

[0050] The PbBr2-PEG layer was spin-coated at 80 RPM for 3 seconds, then at 2000 RPM for 30 seconds, and then annealed at 100°C for 1 hour to remove DMF and crystallize the precursor compound.

[0051] Next, a 1.5 M solution of the precursor compound CsBr in water was stirred at 40°C to 80°C for 2 hours, and then spin-coated onto a PbBr2-PEG layer at room temperature at 800 RPM for 3 seconds and then at 2000 RPM for 30 seconds. The resulting multilayer was annealed at 250°C for 10 minutes to allow the precursor to react and form a CsPbBr3-PEG layer. The thickness of the resulting semiconductor layer was 620 nm. NiO was then coated onto this layer. x (150 nm) and Au (150 nm) to recreate the voltaic device, although this is not the device according to the invention.

[0052] The electrical performance was characterized again by measuring the current flowing through the device as a function of the voltage applied between the two electrodes using the source instrumentation. Current-voltage curves were measured under both "dark" (no light) and "lit" (exposed to a solar simulator) conditions. Short-circuit current, open-circuit voltage, fill factor, and efficiency were determined by the illumination response. The electrical performance is reported in Table 3.

[0053]

[0054] Table 3 In the third comparative example, 1.4 g of CsPbBr3 and 0.14 g of PEG were mixed in a mortar and ground until a homogeneous mixture was formed. Then, 750 μL of DMSO as a conventional solvent was added, and grinding continued for several seconds to form a solid suspension. The solid suspension was then coated onto a glass substrate with 500 nm of FTO and 30 nm of ZnO using a doctor blade coating process. The resulting coating was then dried at 60 °C for 1 hour. The resulting coating was visibly non-uniform, with obvious pinholes and defects.

[0055] In this comparative example, even with a relatively small amount of DMSO, CsPbBr3 was completely dissolved and a recrystallized deposition was obtained, unlike the coating that could be obtained when using a non-solvent liquefying agent instead of a solvent.

[0056] The first embodiment of the present invention provides a functional voltaic device that overcomes the challenges and problems associated with processing temperatures above 100°C (first and second comparative examples), relatively complex precursor solutions (second comparative example), poor substrate wetting (third comparative example), limited coating area (first and second comparative examples), and limited layer thickness (first and second comparative examples).

[0057] Several more specific embodiments, referred to as Embodiments A to I, are now provided, with reference to the accompanying drawings. Figures 1 to 12 The accompanying drawings are described below: Figures 1 to 3 This relates to embodiment A, which is: a. Figure 1 - Cross-sectional views of the entire apparatus obtained by the following methods: A) Electron beam induced current (EBIC) (white areas represent the current being generated), B) Scanning electron microscopy (SEM) (brighter areas represent the entire apparatus); b. Figure 2 - Top views of the entire device obtained through: A) EBIC (white areas represent the current being generated), B) SEM (brighter areas represent the entire device); and c. Figure 3- This is the dark state IV curve; Figure 4 This is the dark state IV curve associated with Example B; Figure 5 This is the dark state IV curve associated with Example C; Figure 6 It is the dark state IV curve associated with Example D; Figure 7 This is the dark state IV curve associated with Example E; Figure 8 It is the dark state IV curve associated with Example F; Figure 9 It is the dark state IV curve associated with Example G; Figure 10 This relates to embodiment H, which is the normalized current response obtained under dark conditions and 1 sun conditions; and Figure 11 and Figure 12 This relates to embodiment I, and it is: a. Figure 11 - Dark state IV curve; and b. Figure 12 - Normalized current response obtained in the dark state and under 1x solar conditions.

[0058] Examples A through I will now be described more fully in the following paragraphs.

[0059] Example A Preparation of the solid suspension: Both the cohesive particles and the semiconductor particles were ground using a mortar and pestle. In the mortar, 0.064 g of PEG and 0.651 g of CsPbBr3 were mixed and ground until a homogeneous mixture was formed. Then, 0.5 mL of isopropanol was added to the homogeneous mixture to form a CsPbBr3 solid suspension in slurry form. The solid suspension was then coated onto the substrate mentioned below using a doctor blade coating process. After coating with the solid suspension, the sample was dried under atmospheric conditions, and then the Volta apparatus was completed as follows. The average thickness of the deposited semiconductor layer was 45 μm, and the volume ratio of semiconductor to cohesive particles was 71 / 29.

[0060] The voltaic device structure is provided in a general form of substrate / contact structure / ETL / CsPbBr3 / HTL / contact structure, but in this embodiment, the voltaic device structure is more specifically glass / ITO / ZnO / CsPbBr3 / NiO. x / Au. Except for the CsPbBr3 solid suspension, all layers were deposited via PVD, as described above, the CsPbBr3 solid suspension was deposited via blade coating.

[0061] Figure 1 The electrical performance test of the voltaic device in A shows a cross-sectional EBIC image, where white areas represent current being generated and dark areas represent no current. Figure 1 B is the corresponding SEM image, where the brighter areas correspond to the entire device area.

[0062] Figure 2 The electrical performance test of the voltaic device in A shows a top-down EBIC image, where white areas represent current being generated and dark areas represent no current. Figure 2 B is the corresponding SEM image, where the brighter areas correspond to the entire device area.

[0063] Figure 3 Electrical performance testing of the voltaic device revealed the dark-state IV response of the semiconductor layer. That is, on a logarithmic scale, the current increases nonlinearly with voltage.

[0064] Example B In this embodiment, the voltaic apparatus is manufactured using the same process and structure as in Example A, but the preparation of the solid suspension uses a different grinding process and calendering step.

[0065] The cohesive and semiconductor particles were ground using 2 mL vials containing 1.5 mm diameter hardened zirconia abrasive media. 0.07 g of PEG was weighed and placed in a 2 mL vial along with 0.820 mL of isopropanol. The vial was placed in a BeadBug 6 homogenizer and ground for 10 cycles at 2500 rpm, 90 s / cycle, with a 30 s pause between cycles. For the same purpose, 0.76 g of CsPbBr3 was weighed and placed in the same 2 mL vial. This was then ground for 10 cycles at 2500 rpm, 90 s / cycle, with a 1 s pause between cycles. The average thickness of the rolled semiconductor layer was 20 μm, and the volume ratio of semiconductor to cohesive particles in the layer was 72 / 28.

[0066] Figure 4 Electrical performance testing of the voltaic device revealed the dark-state IV response of the semiconductor layer. That is, on a logarithmic scale, the current increases nonlinearly with voltage.

[0067] Example C The slurry and apparatus were prepared using the same method as in Example B, except that the cohesive particles were nylon 6 instead of PEG.

[0068] Figure 5 Electrical performance testing of the voltaic device revealed the dark-state IV response of the semiconductor layer. That is, on a logarithmic scale, the current increases nonlinearly with voltage.

[0069] Example D The slurry and apparatus were fabricated using the same method as in Example A, except that the semiconductor particles were n-SiC instead of CsPbBr3. To achieve this, the n-SiC particles were prepared by grinding n-SiC wafers (Summit Semiconductors) in a WC ring mill (Rocklabs) equipped with a WC headset. The slurry shown in this example comprises a mixture of two different particle sizes achieved by varying the grinding time: 30 wt% n-SiC was ground for 80 s, and 70 wt% n-SiC was ground for 240 s. The volume ratio of semiconductor to cohesive particles in the layer was 72 / 28.

[0070] Device structure: substrate / LWF contact structure / n-SiC / HWF contact structure. Except for n-SiC, which is deposited via blade coating, all layers are deposited via PVD. (LWF = low work function; HWF = high work function).

[0071] Figure 6 Electrical performance testing of the voltaic device revealed the dark-state IV response of the semiconductor layer. That is, on a logarithmic scale, the current increases nonlinearly with voltage.

[0072] Example E The slurry and apparatus were fabricated using the same method as in Example D, except that the semiconductor slurry was drop-cast. The slurry used in this example was milled for 40 seconds. The volume ratio of semiconductor to cohesive particles in the layer was 72 / 28.

[0073] Device structure: substrate / LWF contact structure / n-SiC / HWF contact structure. Except for n-SiC, which is deposited by drop casting, all layers are deposited by PVD.

[0074] Figure 7 Electrical performance testing of the voltaic device revealed the dark-state IV response of the semiconductor layer. That is, on a logarithmic scale, the current increases nonlinearly with voltage.

[0075] Example F The slurry and apparatus were prepared using the same method as in Example B, except that the mass of the PEG cohesive particles was increased to 50% by volume. Therefore, the volume ratio of semiconductors to cohesive particles in the layer was 50 / 50.

[0076] Figure 8 The electrical performance testing of the voltaic apparatus in the figure does not show the dark-state IV response of the semiconductor layer. That is, it was observed that the current increases linearly with voltage on a logarithmic scale.

[0077] Example G The slurry and apparatus were prepared using the same method as in Example B, except that the mass of the PEG cohesive particles was increased to 10% by volume. Therefore, the volume ratio of semiconductors to cohesive particles in the layer was 90 / 10.

[0078] Figure 9 Electrical performance testing of the voltaic device revealed the dark-state IV response of the semiconductor layer. That is, on a logarithmic scale, the current increases nonlinearly with voltage.

[0079] Example H The apparatus fabricated in Example B can be used to perform electrical performance testing on the photovoltaic response—such as... Figure 10 As shown, when the device was irradiated with simulated sunlight (Newport LSH-7320), a significant increase in current was observed (an increase of 2000 times).

[0080] Example I This embodiment follows the same fabrication method as Embodiment B, except that it is heat-treated at 400°C after semiconductor deposition / rolling but before the addition of the additional layer.

[0081] Figure 11 Electrical performance testing of the voltaic device revealed the dark-state IV response of the semiconductor layer. That is, on a logarithmic scale, the current increases nonlinearly with voltage.

[0082] The electrical performance of the photovoltaic response can be tested—such as Figure 12 As shown, when the device was irradiated with simulated sunlight (Newport JSH-7320), a significant increase in current was observed (more than 2000 times).

[0083] Finally, it should be understood that other variations and modifications to the above content may also fall within the scope of this invention.

Claims

1. A semiconductor layer located on a substrate, said semiconductor layer being a solid particle composite of semiconductor particles and cohesive particles, wherein, The cohesive particles account for 10% to 45% of the volume of the solid particle composite.

2. The semiconductor layer according to claim 1, wherein, The cohesive particles may account for 20% to 40% of the volume percentage of the solid particle composite, or 25% to 35% of the volume percentage of the solid particle composite, or about 30% of the volume percentage of the solid particle composite.

3. The semiconductor layer according to claim 1 or 2, wherein, The semiconductor layer has the required thickness for a given radiation energy, wherein the higher the radiation energy, the thicker the layer is required.

4. The semiconductor layer according to any one of claims 1 to 3, wherein, The semiconductor layer will be incorporated into, or has already been incorporated into, a low-energy photovoltaic device, wherein the energy of the incident photons is in the range of 0.5 eV to 3.0 eV, and the thickness of the semiconductor layer is in the range of 100 nm to 400 micrometers.

5. The semiconductor layer according to any one of claims 1 to 4, wherein, The thickness of the semiconductor layer is in the range of 100 nm to 400 micrometers, or in the range of 200 nm to 350 micrometers, or in the range of 200 nm to 200 micrometers, or in the range of 200 nm to 100 micrometers, or in the range of 200 nm to 50 micrometers, or in the range of 200 nm to 5 micrometers.

6. The semiconductor layer according to any one of claims 1 to 5, wherein, The diameters of the semiconductor particles and the cohesive particles are in the range of 200 nm to 5 micrometers.

7. The semiconductor layer according to any one of claims 1 to 6, wherein, The porosity of the semiconductor layer is non-zero.

8. The semiconductor layer according to any one of claims 1 to 7, wherein, The mechanical strength of the semiconductor layer allows it to adhere strongly to the substrate and has strong cohesion, preventing the semiconductor layer from cracking or disintegrating.

9. The semiconductor layer according to any one of claims 1 to 8, wherein, The semiconductor particles are made of a material with a medium-sized and non-zero electronic band gap, and which behaves as an insulator at absolute zero.

10. The semiconductor layer according to any one of claims 1 to 9, wherein, The semiconductor particles are made of materials that are inherently semiconductor (intrinsic semiconductor) or require doping to give them semiconductor properties (non-intrinsic semiconductor).

11. The semiconductor layer according to any one of claims 1 to 10, wherein, The semiconductor material is one or more materials selected from the group consisting of: i. Silicon, germanium, etc.; ii. Silicon carbide, gallium nitride, aluminum nitride, gallium arsenide, diamond, aluminum arsenide, aluminum gallium arsenide, boron nitride, zinc selenide, etc.; iii. N-doped silicon carbide, N-doped gallium nitride, N-doped silicon, etc.; iv. Zinc oxide, titanium dioxide, nickel oxide, tin oxide, copper oxide, zinc sulfide, tungsten oxide, molybdenum oxide, etc.; v. Perovskite compounds with crystal structures conforming to the general formula ABX3, including cesium lead tribromide, methylammonium lead triiodide, cesium tin trichloride, etc.; and vi. Poly(3,4-ethylenedioxythiophene): polystyrene sulfonate; polyaniline: chloride; polypyrrole: perchlorate; polythiophene: chloride; poly(3-hexylthiophene): chloride; poly(3,4-ethylenedioxythiophene): p-toluene sulfonate, etc.

12. The semiconductor layer according to claim 11, wherein, The semiconductor material is one or more perovskite compounds.

13. The semiconductor layer according to claim 12, wherein, The perovskite compound is an inorganic halide perovskite or a hybrid organic-inorganic halide perovskite.

14. The semiconductor layer according to claim 13, wherein, The perovskite compound is an inorganic halide perovskite CsPbBr3 or a hybrid organic-inorganic halide perovskite MAPbI3.

15. The semiconductor layer according to any one of claims 1 to 14, wherein, The material of the cohesive particles is polyethylene glycol or polyamide.

16. A method for forming a semiconductor layer on a substrate, the method comprising: A semiconductor layer is formed by mixing semiconductor particles, cohesive particles, and a non-solvent liquefying agent to form a solid suspension, coating the solid suspension onto a substrate, and removing the liquefying agent from the coated solid suspension. The semiconductor layer is a solid particle composite of semiconductor particles and cohesive particles, wherein the cohesive particles account for 10% to 45% of the volume percentage of the solid particle composite.

17. The method according to claim 16, wherein, The cohesive particles may account for 20% to 40% of the volume percentage of the solid particle composite, or 25% to 35% of the volume percentage of the solid particle composite, or about 30% of the volume percentage of the solid particle composite.

18. The method according to claim 16 or 17, wherein, The solids fraction of the solid suspension is in the range of 15% to 30% by volume, or in the range of 18% to 25% by volume, or in the range of 20% to 23% by volume, or about 21% by volume.

19. The method according to any one of claims 16 to 18, wherein, The semiconductor layer is coated with a thickness required for a given radiation energy, wherein the higher the radiation energy, the thicker the layer is required.

20. The method according to any one of claims 16 to 19, wherein, The thickness of the semiconductor layer is in the range of 100 nm to 400 micrometers, or in the range of 200 nm to 350 micrometers, or in the range of 200 nm to 200 micrometers, or in the range of 200 nm to 100 micrometers, or in the range of 200 nm to 50 micrometers, or in the range of 200 nm to 5 micrometers.

21. The method according to any one of claims 16 to 20, wherein, The diameters of the semiconductor particles and the cohesive particles are in the range of 200 nm to 5000 nm.

22. The method according to any one of claims 16 to 21, wherein, The mechanical strength of the semiconductor layer allows for strong adhesion to the substrate and strong cohesion, preventing the semiconductor layer from cracking or disintegrating.

23. The method according to any one of claims 16 to 22, wherein, The semiconductor particles are made of a material with a medium-sized and non-zero electronic band gap, and which behaves as an insulator at absolute zero.

24. The method according to any one of claims 16 to 23, wherein, The semiconductor particles are made of materials that are inherently semiconductor (intrinsic semiconductor) or require doping to give them semiconductor properties (non-intrinsic semiconductor).

25. The method according to any one of claims 16 to 24, wherein, The semiconductor material is one or more materials selected from the group consisting of: i. Silicon, germanium, etc.; ii. Silicon carbide, gallium nitride, aluminum nitride, gallium arsenide, diamond, aluminum arsenide, aluminum gallium arsenide, boron nitride, zinc selenide, etc.; iii. N-doped silicon carbide, N-doped gallium nitride, N-doped silicon, etc.; iv. Zinc oxide, titanium dioxide, nickel oxide, tin oxide, copper oxide, zinc sulfide, tungsten oxide, molybdenum oxide, etc.; v. Perovskite compounds with crystal structures conforming to the general formula ABX3, including cesium lead tribromide, methylammonium lead triiodide, cesium tin trichloride, etc.; and vi. Poly(3,4-ethylenedioxythiophene): polystyrene sulfonate; polyaniline: chloride; polypyrrole: perchlorate; polythiophene: chloride; poly(3-hexylthiophene): chloride; poly(3,4-ethylenedioxythiophene): p-toluene sulfonate, etc.

26. The method of claim 25, wherein, The semiconductor material is one or more perovskite compounds.

27. The method according to claim 26, wherein, The perovskite compound is an inorganic halide perovskite or a hybrid organic-inorganic halide perovskite.

28. The method according to claim 27, wherein, The perovskite compound is an inorganic halide perovskite CsPbBr3 or a hybrid organic-inorganic halide perovskite MAPbI3.

29. The method according to any one of claims 16 to 28, wherein, The material of the cohesive particles is polyethylene glycol or polyamide.

30. The method according to any one of claims 16 to 29, wherein, The non-solvent liquefying agent allows the solid suspension to flow, enabling the use of simple thin-film coating processes, including blade coating, bar coating, or slot coating.

31. The method according to any one of claims 16 to 30, wherein, The non-solvent liquefying agent is removed from the coated solid suspension by using a drying temperature in the range of 40°C to 100°C.

32. The method according to any one of claims 16 to 31, wherein, The liquefying agent is glycerol, ethylene glycol, ethyl cellulose, isopropanol, n-butanol, or water, etc.

33. The method according to any one of claims 16 to 32, comprising compacting the solid particulate composite.

34. The method according to claim 33, wherein, The compaction is carried out using a single-axis hydraulic press, a roller press, or a calender.

35. A voltaic device comprising a semiconductor layer on a substrate, said semiconductor layer being a solid particle composite of semiconductor particles and cohesive particles, wherein, The cohesive particles account for 10% to 45% of the volume of the solid particle composite.

36. A voltaic apparatus comprising a semiconductor layer, said semiconductor layer being the semiconductor layer according to any one of claims 1 to 15.

37. A voltaic apparatus comprising a semiconductor layer formed by the method according to any one of claims 16 to 34.

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