Back contact solar cell and method for manufacturing a back contact solar cell

Abstract

The invention relates to a back contact solar cell (10) and a method for manufacturing such a back contact solar cell (10).

Description

Technical Field

[0001] This invention relates to a back-contact solar cell and a method for manufacturing a back-contact solar cell. Background Technology

[0002] In the case of a back-contact solar cell, both polarity electrodes, as well as the electrodes for the emitter and base regions, are arranged on the back side of the solar cell. The back side of the solar cell is the side facing away from the sun during solar cell operation. Therefore, the front side of the solar cell is the side facing the sun.

[0003] Back-contact solar cells typically achieve higher efficiencies than solar cells with electrodes of one polarity on the front and electrodes of the opposite polarity on the back. In the case of back-contact solar cells, the front side is not shaded by electrodes. To minimize resistance and recombination losses in back-contact solar cells, electrodes of both polarities, as well as the emitter and base regions, are arranged alternately on the back side with a small spacing.

[0004] Technically, generating multiple PN junctions with small spacing is much more difficult than, for example, a solar cell typically having only large-area PN junctions in contact on both sides. Alternating emitter and base regions on the back side can be achieved, for example, by laser irradiation. In this process, N-type and P-type dopants are locally driven into the semiconductor substrate by temporally and spatially separated melting of the surface through laser irradiation, thereby creating P-type or N-type doped regions depending on the dopant. Such a laser doping method is disclosed, for example, in DE 102013 219 564 A1. Due to low internal series resistance and high current output, the described back-side structure allows for efficiencies up to 24%.

[0005] Even higher efficiencies are largely limited by recombination mechanisms in the base and on highly doped, contact, and non-contact surfaces. Recombination in the base depends on the quality of the semiconductor substrate and is only limited by further fabrication processes in the solar cell. Recombination mechanisms on doped N-type and P-type surfaces are limited only by Auger recombination in the non-contact regions, where the surface fit is good, and Auger recombination increases with increasing dopant concentration in silicon. In the contact regions where the metal electrode contacts silicon, contact with the metal leads to high interfacial recombination. During fabrication, Auger recombination on non-contact surfaces can be reduced by minimizing doping. On the other hand, high dopant concentrations are advantageous on contact surfaces because contact resistance and interfacial recombination are thus reduced.

[0006] To overcome this difference, so-called passivated contacts or charge-carrier selective contacts are known to be used, see, for example, DE 10 2013 219 564 A1 or WO 2014 / 100004 A1. In this case, the electrode does not directly contact the crystalline silicon wafer used as an absorber, but is separated by a thin dielectric layer (e.g., a silicon oxide layer). On the one hand, the silicon oxide layer passivates the silicon surface. On the other hand, the silicon oxide layer is so thin that charge carriers (especially electrons) can pass through the silicon oxide layer from the semiconductor into the electrode or from the electrode into the semiconductor (depending on polarity). Therefore, the silicon oxide layer can be referred to as a tunneling layer through which charge carriers can pass. Small holes, for example in the nm (nanometer) range, can also be arranged in the tunneling layer, which allows current to flow.

[0007] To induce charge carrier tunneling, an electric field can be present in the tunnel layer. This field can be generated, for example, by highly doped N-type or P-type silicon on the tunnel layer. Doping this highly doped silicon layer above the tunnel layer causes band bending in the silicon base beneath the tunnel layer. Therefore, classical doping of the silicon base to form a PN junction is no longer required. Auger recombination in the base is reduced because the silicon base is no longer doped or is at least only slightly doped. Spatial separation of the metal / silicon interface of the electrode from the silicon base also reduces interfacial recombination. Furthermore, low contact resistance can be achieved because the electrode contacts the highly doped silicon layer. Suitable doped silicon layers are, for example, amorphous, microcrystalline, or polycrystalline silicon layers with a thickness of 20 nm to 400 nm, which can be deposited, for example, by PECVD, LPCVD, APCVD, or PVD processes.

[0008] Back-contact solar cells with charge-carrier selective contacts of opposite polarities have achieved efficiencies as high as 26.7% to date. However, the fabrication of such solar cells is extremely complex because the two passivated contacts with different doping can only be applied through a variety of intricate masking and patterning steps. High precision and fine resolution in masking and patterning are absolutely essential. The distance between the charge-carrier selective contacts of opposite polarities should not exceed the diffusion length of free charge carriers. A large distance also leads to an increase in internal series resistance due to the lateral current flow in the base.

[0009] Differently doped silicon layers in charge carrier selective contacts can also be separated by an undoped silicon layer or by spatial separation (e.g., trenches or interruptions). Without such separation, the junction between the different doped layers will have a highly defective pn junction, which limits the efficiency of the solar cell. Ideally, the separation should be as fine as possible, as large separation regions can be affected by short-circuit currents and open-circuit voltages. Summary of the Invention

[0010] Therefore, one object of the present invention is to provide a back-contact solar cell and a method for manufacturing a back-contact solar cell, wherein the solar cell has the highest possible efficiency and can be manufactured cheaply and efficiently.

[0011] This objective is achieved by a back-contact solar cell comprising a semiconductor substrate, a front side, and a back side. The semiconductor substrate may include or be formed of silicon. A plurality of first regions, a plurality of second regions, and a plurality of third regions are disposed on the back side of the solar cell. Each first region includes a first doped silicon layer. Each second region includes a second doped silicon layer. The doping of the first and second doped silicon layers may have different or opposite polarities. In each case, the first and second doped silicon layers are amorphous, microcrystalline, or polycrystalline. In each case, the third regions do not contain amorphous, microcrystalline, or polycrystalline silicon. The first and second regions are configured as passivated contacts. In each case, a first tunnel layer is disposed between the first doped silicon layer and the semiconductor substrate. In each case, a second tunnel layer is disposed between the second doped silicon layer and the semiconductor substrate.

[0012] The back and / or front surfaces of the solar cell are at least partially covered by a dielectric layer (passivation). The dielectric layer can be in the form of a stacked layer, i.e., composed of several layers. In each case, the dielectric layer has a first interruption in a first region and a second interruption in a second region. Thus, the dielectric layer has multiple first interruptions and multiple second interruptions, particularly on the back side of the solar cell. The solar cell has multiple first electrodes and multiple second electrodes. In each case, the first electrode contacts a first doped silicon layer through a first interruption. Specifically, in each case, the first electrode may contact a second doped silicon layer and / or a second tunnel layer in the first region. In each case, the second electrode contacts a second doped silicon layer through a second interruption.

[0013] The first region is disposed on a plateau-shaped protrusion on a semiconductor substrate. Each plateau-shaped protrusion has a cross-section that widens (or increases) along a first direction. In particular, the cross-sectional shape of the plateau-shaped protrusion may be trapezoidal.

[0014] The third region can be formed in the concave region that widens laterally to the first direction, forming a "shadow" of the first region (relative to the first direction). Therefore, the first and second doped silicon layers, particularly the first and second regions, are separated from each other by the third region in each case. Specifically, the third region forms a step within the "shadow" of the first region. Thus, selectively doped charge carrier contacts can be finely separated and converted at high resolution within a few micrometers without further complex structuring steps. This separation avoids PN junctions in the first and second doped silicon layers, which would particularly limit the fill factor and thus also the efficiency. Therefore, solar cells with the highest possible efficiency can be realized, and they can be manufactured cheaply and efficiently.

[0015] In this context, the first direction refers to the direction away from the back of the solar cell. Specifically, the first direction is perpendicular to both the front and back of the solar cell.

[0016] The first doped silicon layer can be formed as a P-type (positive) or N-type (negative) layer. The second doped silicon layer can be formed as a P-type or N-type layer. The first and second doped layers are amorphous, microcrystalline, or polycrystalline, and therefore quite different from crystalline, especially single-crystal semiconductor substrates (or silicon-based substrates).

[0017] The widened cross-section of the platform-shaped protrusion can be achieved by under-etching (see below). In this way, a third region can be formed, which is transverse to the first direction and ranges from 0.5 μm to 20 μm, preferably from 1 μm to 10 μm, and the third region does not have a layer of amorphous, microcrystalline or polycrystalline silicon disposed thereon.

[0018] According to the improved scheme of solar cells, the third region can be constructed as an under-etched region.

[0019] Therefore, the third region can be implemented using a simple method.

[0020] According to the improved scheme of solar cells, the third region can be undoped.

[0021] In this context, "undoped" does not mean there is no additional (process-dependent) doping. In this case, the undoped layer has the same doping (type and concentration) as the semiconductor substrate. The semiconductor substrate can have a low doping concentration, such as 5 × 10⁻⁶. 16 cm -3 Therefore, an "undoped" layer can have the same low doping concentration. Thus, doping refers to additional doping relative to the semiconductor substrate.

[0022] Therefore, the third region can be implemented using a simple method. In particular, this allows for a clear separation between the first doped silicon layer and / or the second doped silicon layer (undoped).

[0023] According to the improved design, the third region can have a third doped silicon layer. Therefore, the surface of the semiconductor substrate in the third region can be doped.

[0024] Therefore, the efficiency of solar cells can be further improved.

[0025] According to the improved solar cell design, a fourth doped silicon layer can be placed on the front side of the solar cell.

[0026] Therefore, the efficiency of solar cells can be further improved.

[0027] According to the improved solar cell design, the semiconductor substrate, the front side of the first doped silicon layer, the second doped silicon layer, the third doped silicon layer or the third doped silicon layer, and the fourth doped silicon layer can have one of the combinations according to Table 1.

[0028] Table 1:

[0029]

[0030] In this context, specifically in Table 1, “P” indicates additional positive doping relative to the semiconductor substrate, “N” indicates additional negative doping relative to the semiconductor substrate, and “-” indicates no additional doping relative to the semiconductor substrate.

[0031] Therefore, solar cells can be designed and implemented with as much flexibility as possible.

[0032] According to the improved solar cell design, the first doped silicon layer, the second doped silicon layer, the first tunnel layer, and / or the second tunnel layer may all be pore-free. The first tunnel layer and / or the second tunnel layer may each be configured as a closed layer. Specifically, the first tunnel layer and / or the second tunnel layer are not penetrated (or penetrated through) by the first electrode and / or the second electrode, or are only slightly penetrated.

[0033] Therefore, the efficiency of solar cells can be further improved.

[0034] According to the improved solar cell design, the first doped silicon layer, the second doped silicon layer, the first tunnel layer, and / or the second tunnel layer can all be penetrated by an aluminum-silicon eutectic in each case. The aluminum-silicon eutectic can be disposed on the corresponding first electrode and / or the corresponding second electrode.

[0035] Therefore, the efficiency of solar cells can be further improved.

[0036] According to the improved solar cell design, the aluminum-silicon eutectic can be at least partially surrounded by a fifth doped silicon layer. This fifth doped silicon layer can have P-type doping, for example, through aluminum; or N-type doping. If the aluminum-silicon eutectic is disposed on the first and second electrodes, the corresponding fifth doped silicon layer can have the same polarity as the electrode. Specifically, the fifth doped layer of the aluminum-silicon eutectic disposed on the first electrode and the fifth doped layer of the aluminum-silicon eutectic disposed on the second electrode can have opposite polarities.

[0037] Therefore, the efficiency of solar cells can be further improved. Furthermore, manufacturing can be carried out at a lower cost.

[0038] The above objective is achieved by a method for manufacturing a back-contact solar cell according to the above embodiment. The method includes the following steps:

[0039] Provides a semiconductor substrate with a front side and a back side.

[0040] A first tunnel layer is formed on the back side of the semiconductor substrate.

[0041] A first doped silicon layer of the first polarity is formed on the first tunnel layer.

[0042] An etch-stable barrier layer is formed on the first doped silicon layer.

[0043] Remove the etch-stable barrier layer in multiple etched areas.

[0044] Etching is performed in the etched area, particularly on the surfaces of the first doped silicon layer, the first tunnel layer, and the semiconductor substrate. This etching, especially by under-etching, etches a stable barrier layer, creating plateau-shaped protrusions on the semiconductor substrate with a cross-section widened in a first direction. These plateau-shaped protrusions thus extend out of the semiconductor substrate. The etching can be wet chemical etching.

[0045] In particular, the etch-stable barrier layer is completely removed.

[0046] A second tunnel layer is formed, particularly in the region between the plateau-shaped protrusions of the semiconductor substrate.

[0047] A second doped silicon layer with a second polarity opposite to the first polarity is formed, particularly in the region between the plateau-shaped protrusions. In the third region, no second doped silicon layer is formed due to the widening of the cross-section of the plateau-shaped protrusions. Therefore, the third region does not contain amorphous, microcrystalline, or polycrystalline silicon.

[0048] For the advantages that can be obtained through this method, refer to the relevant statements about solar cells. The measures described in conjunction with the solar cell description and / or further explained below can be used in the design of this method.

[0049] According to the improved version of this method, the method may include the following steps:

[0050] A third doped silicon layer is formed in the third region by furnace diffusion and / or a fourth doped silicon layer is formed on the front side.

[0051] According to the improved version of this method, the method may include the following steps:

[0052] Remove the silicate glass layer, such as phosphosilicate glass or borosilicate glass, formed during furnace diffusion, especially by (wet chemical) etching.

[0053] According to the improved version of this method, the method may include the following steps:

[0054] An aluminum-silicon eutectic is formed on a first electrode and / or a second electrode by using a paste or paste stack, particularly wherein the paste or paste stack contains a P-type dopant, especially aluminum and / or an N-type dopant.

[0055] This method specifically includes anisotropic or isotropic wet chemical etching of a first doped silicon layer, a first tunnel layer, and / or a semiconductor substrate. Wet chemical etching can be performed after depositing or growing the first tunnel layer, the first doped silicon layer, depositing an etch barrier layer, and constructing an etch barrier layer, for example, by laser irradiation. For example, wet chemical etching can remove approximately 0.5 μm to 20 μm, particularly 1 μm to 10 μm (etch depth), of silicon along a first direction (i.e., perpendicular to the surface). Regardless of whether the etching is anisotropic or isotropic, under-etching can occur in both the barrier layer and the first doped silicon layer; under-etching can also occur if the first doped silicon layer possesses excellent etch stability due to its chemical properties.

[0056] The etch barrier layer can then be removed.

[0057] After exposing the second tunnel layer on the surface of the passivated semiconductor substrate, a second doped silicon layer can be deposited, for example, by physical vapor deposition (PVD). Unlike conventional chemical vapor deposition processes (PECVD, LPCVD, APCVD), there is little or no particle deposition laterally in the first direction (i.e., on the surface perpendicular to the particle deposition direction). In particular, no particles are deposited in this manner between the under-etched regions. Therefore, a third region can be formed that does not include either the first or second doped silicon layer. Consequently, the PN junction can be located solely within the semiconductor substrate (silicon wafer), resulting in low recombination. Thus, a high fill factor and high efficiency can be achieved.

[0058] In other words, when the first doped silicon layer is removed by post-chemical etching in a region without a barrier layer, isotropic or anisotropic under-etching of the barrier layer occurs. The deposition of the second doped silicon layer can be achieved through physical, oriented, unidirectional vapor deposition. The second doped silicon layer is not deposited on all exposed surfaces on the back of the solar cell, but rather interrupted at least in the under-etched shaded regions. Therefore, no further process steps are required to separate the first doped silicon layer in the first region and the second doped silicon layer in the second region (i.e., two distinct doped silicon layers). Furthermore, this separation (i.e., the region without the first and second doped silicon layers) extends over a width exceeding several micrometers (the sum of the etch depth and the under-etched region). Therefore, ultrafine separation of charge carrier selective contacts can be achieved in the micrometer range. Attached Figure Description

[0059] Other features, details, and advantages of the invention will become apparent from the wording of the claims and from the following description of embodiments based on the accompanying drawings. It is shown that:

[0060] Figure 1 A schematic cross-section of a back-contact solar cell according to a first embodiment is shown;

[0061] Figure 2 A schematic cross-section of a back-contact solar cell according to a second embodiment is shown;

[0062] Figure 3 A schematic cross-section of a back-contact solar cell according to a third embodiment is shown;

[0063] Figure 4 It shows according to Figures 1 to 3 The illustration shows scanned electron images of the first, second, and third regions of a solar cell;

[0064] Figures 5 to 16 A method for manufacturing a back-contact solar cell according to a first embodiment is shown;

[0065] Figures 17 to 28 A method for manufacturing a back-contact solar cell according to a second embodiment is shown.

[0066] In the following description and accompanying drawings, corresponding components and elements have the same reference numerals. For clarity, not all reference numerals are shown in all the drawings. Detailed Implementation

[0067] Figure 1A schematic cross-section of a back-contact solar cell 10 according to a first embodiment is shown. In this example, the solar cell 10 includes a crystalline N-type semiconductor substrate 12. In this case, the semiconductor substrate 12 forms a silicon base 12. In this case, the semiconductor substrate 12 acts as a light-absorbing layer. In another embodiment, the semiconductor substrate 12 may also be a crystalline P-type silicon base 12.

[0068] The solar cell 10 includes a front side 14 and a back side 16. During operation of the solar cell 10, the front side 14 faces the sun. In the illustrated embodiment, the front side 14 is textured. A plurality of first regions 18, a plurality of second regions 22, and a plurality of third regions 26 are arranged on the back side 16 of the solar cell 10. Each first region 18 has a first doped silicon layer 20, and each second region 22 has a second doped silicon layer 24. In this case, the second doped silicon layer 24 is disposed above the first doped silicon layer 20 in the first region 18. However, in each case, the second doped silicon layer 24 disposed in the first region 18 is inactive.

[0069] The first doped silicon layer 20 and the second doped silicon layer 24 are in each case amorphous, microcrystalline, or polycrystalline. Therefore, they differ from the (mono)crystalline silicon base 12 (or semiconductor substrate 12). In each case, the third region 26 does not contain amorphous, microcrystalline, or polycrystalline silicon. In each case, a first tunnel layer 28 is disposed between the first doped silicon layer 20 and the semiconductor substrate 12. In each case, a second tunnel layer 30 is disposed between the second doped silicon layer 24 and the semiconductor substrate 12.

[0070] The first region 18 and the second region 22 are each configured as passivation contacts. In this case, the surfaces of the back side 16 and the front side 14 of the solar cell 10 are at least partially, and particularly completely, covered by the dielectric layer 32 or a dielectric layer stack. In this case, the dielectric layer 32 is formed of two layers. The dielectric layer 32 can passivate the front side 14 and / or the back side 16, reduce reflection at the front side 14, and improve the light absorption efficiency of the solar cell 10. The dielectric layer 32 includes, for example, aluminum oxide (AlOx), silicon oxide (SiOx), or silicon nitride (SiNx). The dielectric layer 32 can be formed as a layer stack (i.e., composed of several layers). The layer stack can consist of two or more layers, including, for example, AlOx, SiOx, and / or SiNx materials. Other materials for reducing reflection and / or improving passivation are also possible. The dielectric layer 32 or dielectric layer stack on the front side 14 and the dielectric layer 32 or dielectric layer stack on the back side 16 can have the same or different structures.

[0071] The dielectric layer 32 has a first interruption 34 in the first region 18 and a second interruption 36 in the second region 22 in each case. The first interruption 34 may continue through the second doped silicon layer 24 in the first region 18 and extend to the first doped silicon layer 20.

[0072] The solar cell 10 includes a plurality of first electrodes 38 and a plurality of second electrodes 40. In each case, the first electrode 38 contacts the first doped silicon layer 20 through a first interruption 34. In each case, the first electrode 38 can penetrate the second doped silicon layer 24. It is also conceivable that the second doped silicon layer 24 can form an (additional) tunnel junction in the region of the first interruption 34. In each case, the second electrode 40 contacts the second doped silicon layer 24 through a second interruption 36. A first region 18 is disposed on a plateau-shaped protrusion 42 of the semiconductor substrate 12. The plateau-shaped protrusion 42 has a cross-section that widens along a first direction 44. In other words, the cross-section of the plateau-shaped protrusion 42 gradually tapers in the opposite direction to the first direction 44.

[0073] The third region 26 can be configured as an under-etched region. The third region 26 can be undoped.

[0074] In the example, a fourth doped silicon layer 48 is disposed on the front side 14. The fourth doped silicon layer 48 can be P-type doped silicon. The fourth doped silicon layer 48 can form a so-called "front floating emitter" (FFE) because the doping type of the fourth doped silicon layer 48 is opposite to that of the silicon base 12 or the semiconductor substrate 12, thus enabling the formation of an emitter with a PN junction.

[0075] The fourth doped silicon layer 48 can be doped with a p-type dopant, such as boron, with a dopant concentration ranging from approximately 5 × 10⁻⁶. 17 cm -3 Up to 1 × 10 20 cm -3 Preferably about 5 × 10 18 cm -3 Up to 5 × 10 19 cm -3 .

[0076] In another embodiment, the fourth doped silicon layer 48 may also be N-type doped, preferably with a dopant concentration comparable to or consistent with that described above. In this case, the doping on the front side is referred to as the "front surface field" (FSF), i.e., the same type of doping as the silicon substrate 12 or the semiconductor substrate 12. The fourth doped silicon layer 48 may be doped with an N-type dopant, such as phosphorus, with a dopant concentration ranging from approximately 5 × 10⁻⁶. 17 cm -3 Up to 1 × 10 20 cm -3 Preferably about 5 × 1018 cm -3 Up to 5 × 10 19 cm -3 .

[0077] The surface of the back side 16 can be textured or chemically polished across its entire surface. The surface of the back side 16 can also include a combination of textured and polished regions. For example, the surface corresponding to the first region 18 can be polished, and the surface corresponding to the second region 22 can be textured (and vice versa). After anisotropic etching of silicon, the silicon surface can be chemically polished using, for example, a hot potassium solution.

[0078] The first doped silicon layer 20 may comprise N-type doped polysilicon. The second doped silicon layer 24 may comprise P-type doped polysilicon. In each case, a second doped silicon layer 24 is disposed above the first doped silicon layer 20 within each first region 18 along the first direction 44. These second doped silicon layers 24 disposed in the first regions 18 are non-functional.

[0079] In this configuration, the first region 18 and the second region 22 are arranged alternately. The distance 'a' between the center M1 of the N-type doped first region 18 and the center M2 of the adjacent N-type doped first region 18 ranges from 300 μm to 3000 μm, preferably between 400 μm and 2000 μm. Correspondingly, the distance between the center of the P-type doped second region 22 and the center of the adjacent P-type doped second region 22 ranges from 300 μm to 3000 μm, preferably between 400 μm and 2000 μm.

[0080] On the back side 16 of the solar cell, the ratio of the total area of ​​the P-type doped region to the total area of ​​the N-type doped region ranges from 1:9 to 9:1, preferably from 2:8 to 8:2, and even more preferably from 3:7 to 7:3.

[0081] The alternating pattern of the first region 18 and the second region 20 can, in principle, extend completely or at least approximately over the entire back surface 16 of the solar cell 10. However, the alternating pattern can also be partially interrupted, for example, by breaking it in the area where the busbars are laid out.

[0082] The thickness of the first doped silicon layer 20 and / or the second doped silicon layer 24 can be, for example, from 20 nm to 400 nm. The first doped silicon layer 20 and the second doped silicon layer 24 can have the same layer thickness. It is also conceivable that the first doped silicon layer 20 and the second doped silicon layer 24 can have different layer thicknesses.

[0083] The first doped silicon layer 20 and / or the second doped silicon layer 24 may be doped with an N-type dopant, such as phosphorus, and the dopant concentration ranges from 1 × 10⁻⁶. 19 cm -3 Up to 1 × 10 21 cm -3 Preferably 5 × 10 19 cm -3 Up to 2 × 10 20 cm -3 .

[0084] The first tunnel layer 28 and / or the second tunnel layer 30 may each be formed as a dielectric layer. The first tunnel layer 28 and / or the second tunnel layer 30 may be a layer containing silicon oxide (SiOx) or a layer containing silicon nitride (SiON).

[0085] The first tunnel layer 28 and / or the second tunnel layer 30 can passivate the surface of the semiconductor substrate 12 (or silicon base 12). The thickness of the first tunnel layer 28 and / or the second tunnel layer 30 can be from 0.5 nm to 4 nm, which allows for the tunneling conduction of charge carriers.

[0086] The first tunnel layer 28 and / or the second tunnel layer 30 are without holes in any case. It is also conceivable that the first tunnel layer 28 and / or the second tunnel layer 30 may have nanometer-level openings, i.e., so-called pinholes. Thus, ohmic contacts can be achieved between the semiconductor substrate 12 (silicon base 12) and the first doped silicon layer 20 and the second doped silicon layer 24.

[0087] In this configuration, the first doped silicon layer 20 in the first region 18 and the second doped silicon layer 24 in the second region 22 are separated from each other by the third region 26. In this configuration, the third region 26 is formed from an under-etched silicon substrate of the semiconductor substrate 12 (silicon base 12). The third region 26 can be formed from the first region 27 and the second region 29. In this configuration, the first region 27 can be laterally (vertically) oriented relative to the first direction 44, and the second region 29 can be tilted or angled relative to the first direction 44. Similarly, it is conceivable that the first region 27 and the second region 29 can be tilted or angled relative to the first direction 44, respectively (see...). Figure 4 ).

[0088] Specifically, there is no (or only a very small) second doped silicon layer 24 located in the third region 26. Therefore, there is no PN junction between the first doped silicon layer 20 corresponding to the first region 18 and the second doped silicon layer 24 corresponding to the second region 22. In the illustrated embodiment, the silicon base 12 (or semiconductor substrate 12) is undoped in the third region 26. Therefore, the dopant concentration of the third region 26 specifically corresponds to the dopant concentration of the silicon base 12. The surface of the third region 26 may be covered or passivated by a dielectric layer, particularly the second tunnel layer 30. Additionally or alternatively, the surface of the third region 26 may be covered by a dielectric layer 32 (or a stack of dielectric layers). For this purpose, the dielectric layer 32 (or the stack of dielectric layers) may be non-oriented and completely cover the third region 26, compared to the second doped silicon layer 24.

[0089] The dielectric layer 32 is primarily used to passivate the surface of the silicon base 12 (or semiconductor substrate 12). On one hand, the dielectric layer 32 serves as a hydrogen source to improve the passivation effect in conjunction with the first tunnel layer 28 and the second tunnel layer 30; on the other hand, the dielectric layer 32 can also saturate the open bonds in the third region 26 and further enhance the passivation performance through the field effect. The dielectric layer 32 can also be used to optimize the optical characteristics of the solar cell 10, especially when the solar cell 10 is used on both sides. The material of the dielectric layer 32 includes one or more of, for example, aluminum oxide (AlOx), silicon oxide (SiOx), and silicon nitride (SiNx). The dielectric layer 32 can be composed of a stack of at least two layers, such as AlOx, SiNx, or SiNx. Furthermore, other materials that reduce reflection and / or improve passivation can also be selected.

[0090] In this example, the dielectric layer 32 covers almost the entire surface of the back side 16 and the front side 14.

[0091] The first interrupt 34 and the second interrupt 36 are disposed in the dielectric layer 32 on the back side 16, and the first interrupt 34 and the second interrupt 36 can be configured as openings. With the aid of the first interrupt 34 and the second interrupt 36, electrical connections can be formed between the corresponding first doped silicon layer 20, the second doped silicon layer 24 and the matching first electrode 38, the second electrode 40. In other words, the first electrode 38 contacts the first doped silicon layer 20 through the first interrupt 34, and the second electrode 40 contacts the second doped silicon layer 24 through the second interrupt 36.

[0092] Therefore, in the first region 18, the second doped silicon layer 24 and the second tunnel layer 30 can also each have interruptions to allow the first electrode 38 to contact the corresponding first doped silicon layer 20 (see [link]). Figure 1 These interrupts can be designed similarly to the first interrupt 34 and / or the second interrupt 36.

[0093] For example, the first interruption 34 and / or the second interruption 36 can be continuous, circular, angular, linear, or segmented. Therefore, contact surfaces of corresponding shapes, such as point, circular, linear, or segmented contact surfaces, can be provided for the first electrode 38 and the second electrode 40, respectively.

[0094] In the example shown, the first electrode 38 contacts the first doped silicon layer 20, which in this example is configured as N-type doped. Therefore, the first electrode 38 can also be referred to as the negative electrode. In the example shown, the second electrode 40 contacts the second doped silicon layer 24, which in this example is configured as P-type doped. Therefore, the second electrode 40 can also be referred to as the positive electrode.

[0095] The first electrode 38 or the second electrode 40 (positive or negative electrode) can be made of one or more metals, such as silver, copper, or aluminum. The first electrode 38 and the second electrode 40 can be designed as, for example, a stack of layers of silver and copper to minimize the silver content in the metallization. In this case, the corresponding first tunnel layer 28 is formed continuously in the first region 18 (as a complete sealing layer). In this case, the corresponding second tunnel layer 30 is formed continuously in the second region 22 (as a complete sealing layer). It is also conceivable that the first tunnel layer 28 and / or the second tunnel layer 30 can be made into an interrupted structure in the regions of the first interruption 34 and / or the second interruption 36.

[0096] Figure 2 A schematic cross-section of a back-contact solar cell 10 according to a second embodiment is shown. The second embodiment is... Figure 1 The difference in the first embodiment shown is that:

[0097] Specifically, the surface of the semiconductor substrate 12 in the third region 26 may be additionally doped, such that the dopant concentration in the third region 26 exceeds the dopant concentration of the semiconductor substrate 12. In this case, the third region 26 has a third doped silicon layer 46. Furthermore, the second tunnel layer 30 is absent in the third region 26 or has been removed. The third doped silicon layer 46 may be, for example, N-type or P-type doped. This additional doping compared to the semiconductor substrate 12 can improve the passivation effect in the third region 26. Depending on the doping type of the third doped silicon layer 46, the third doped silicon layer 46 may form a PN junction with the first doped silicon layer 20 (e.g., P-type) or the second doped silicon layer 24 (e.g., N-type).

[0098] Figure 3 A schematic cross-section of a back-contact solar cell 10 according to a third embodiment is shown. The third embodiment and... Figure 2 The difference in the second embodiment shown is that:

[0099] In this configuration, the second electrode 40 (e.g., designed as a positive electrode) is constructed as an aluminum alloy electrode. An aluminum-silicon eutectic 50 is located in the region of the second interruption 36 in the dielectric layer 32, penetrating or extending through the second doped silicon layer 24 and the second tunnel layer 30. In each case, the aluminum-silicon eutectic 50 is formed on the second electrode 40 (or its underside). In this case, the aluminum-silicon eutectic 50 is at least segmentally surrounded by the fifth doped silicon layer 52. In other words, the silicon surrounding the aluminum-silicon eutectic 50 is doped, and the doping can be aluminum doping. In the example of an N-type semiconductor substrate 12 (silicon base 12), the aluminum doping surrounding the aluminum-silicon eutectic 50 forms the emitter. In another embodiment with a P-type semiconductor substrate 12, an aluminum-doped back surface field (Al-BSF) can be formed at the interruption.

[0100] Similarly, it can be imagined that the first electrode 38 also forms a eutectic with the fifth doped silicon layer 52. The fifth doped silicon layer corresponding to the eutectic of the first electrode 38 and the fifth doped silicon layer corresponding to the eutectic of the second electrode 40 can have opposite polarities. The doping type of the corresponding eutectic can match the polarity of the corresponding first electrode 38 and second electrode 40, or match the polarity of the corresponding first doped silicon layer 20 and second doped silicon layer 24.

[0101] Similarly, it is conceivable that the aforementioned aluminum electrode, based on... Figure 1 The first embodiment of the solar cell is combined with the present.

[0102] According to one of the above three embodiments, the semiconductor substrate 12, the first doped silicon layer 20, the second doped silicon layer 24, the third region 26 or the third doped silicon layer 46, the front side or the fourth doped silicon layer 48 of the solar cell 10 may each have one of the combinations according to Table 1.

[0103] Table 1:

[0104]

[0105] Figure 4 A scanned electronic image of the first region 18, the second region 22, and the third region 26 of the solar cell 10 is shown. This can be a solar cell 10 according to one of the three embodiments described above. In this case, the third region 26 is produced by under-etching.

[0106] In the case of unidirectional deposition, such as physical vapor deposition, particles can only be deposited on the free surface, i.e., outside the third region 26 shown (or outside the under-etched region). Therefore, the third region 26 results in a unidirectionally deposited layer (e.g., the second doped silicon layer 24). Figure 4 (not shown in the image) interruption.

[0107] Figures 5 to 16A method for manufacturing a back-contact solar cell 10 according to a first embodiment is shown. Using the method shown, the above-described embodiments can be implemented, particularly according to… Figure 1 The first embodiment shown is used to manufacture the solar cell 10.

[0108] First, a semiconductor substrate 12 having a front side 54 and a back side 56 is provided. Figure 5 A semiconductor substrate 12 (or silicon wafer) is shown. The front side 54 of the semiconductor substrate 12 corresponds to the front side 14 of the solar cell 10; the back side 56 of the semiconductor substrate 12 corresponds to the back side 16 of the solar cell 10. A first direction 44 is perpendicular to the front side 54 and the back side 56, and is away from the back side 56. When the second doped silicon layer 24 is prepared by physical vapor deposition (PVD), the deposition direction is opposite to the first direction 44. In other words, the deposition direction of the second doped silicon layer 24 is opposite to the first direction 44.

[0109] First, the semiconductor substrate 12 can be textured by isotropic etching, particularly on the front side 54 and the back side 56. Additional etching can be performed prior to texturing to eliminate sawing damage. Other texturing methods are also conceivable.

[0110] Semiconductor substrate 12 can undergo full-surface diffusion, such as furnace diffusion, to complete doping on the front side 54 and back side 56. The dopant can be either P-type or N-type dopant, such as boron or phosphorus. This forms a fourth doped silicon layer 48 on the front side 14 of solar cell 10. Depending on the doping type, the dopant forms a so-called "front floating emitter" or "front surface field." Similarly, on the back side 56 of semiconductor substrate 12, the dopant can diffuse to the back side 56, creating an undesirable doped layer 49 (see [link to documentation]). Figure 6 ).

[0111] During diffusion, such as furnace diffusion, dopant-rich silicate glasses, such as borosilicate glass (BSG) or phosphosilicate glass (PSG), can be grown. Therefore, silicate glass layers 62 are formed, specifically, on the front side 54 and back side 56 of the semiconductor substrate 12 (see...). Figure 6 On the back side 56 of the semiconductor substrate 12, the doped layer 49 and the silicate glass layer 62 are undesirable and need to be completely or at least partially suppressed from formation, or should be further removed. In particular, for the solar cell 10 having a P-type semiconductor substrate 12, this diffusion step can also be skipped, such that the doping concentration on the front side 54 of the semiconductor substrate 12 (or the front side 14 of the solar cell 10) is no higher than the base doping concentration of the semiconductor substrate 12.

[0112] Figure 7A wet chemical etching (on demand) of the back side 56 of the semiconductor substrate 12 is shown. Thus, the doped layer 49 and the silicate glass layer 62 are removed. For example, the silicate glass layer 62 of the back side 56 can be removed first by etching in an acidic single-sided etching solution. Another alkaline etching removes only the exposed silicon on the back side 56 and removes the doped layer 49. The silicate glass layer 62 on the front side 54 of the semiconductor substrate 12 avoids etching of the fourth doped silicon layer 48. Advantageously, the etching is anisotropic, resulting in a flat surface on the back side 56 of the semiconductor substrate 12. Isotropic etching can also be used to further texturize the back side 56 of the semiconductor substrate 12.

[0113] Next, a first tunnel layer 28 is formed on the back surface 56 of the semiconductor substrate 12 (see...). Figure 8 The first tunnel layer 28 can be formed by growth or deposition. The thickness of the first tunnel layer 28 can be between 5 and 40 angstroms. The first tunnel layer 28 can be made of silicon oxide, or other dielectric materials or substances that provide surface passivation and allow charge carriers to pass through. If desired, the first tunnel layer 28 can also be grown or deposited on the front side 54. However, deposition on the front side 54 does not have a decisive impact on further processes and is therefore not considered further.

[0114] Then a first doped silicon layer 20 is formed on the first tunnel layer 28 (see...). Figure 9 This can be achieved through deposition. The thickness of the first doped silicon layer 20 can be between 20 nm and 400 nm. The first doped silicon layer 20 can have a thickness of 1 × 10⁻⁶. 19 cm -3 Up to 1 × 10 21 cm -3 The dopant concentration is within a certain range. The deposition of the first doped silicon layer 20 can be performed, for example, by PVD, LPCVD, PECVD, or APCVD. In this case, the first doped silicon layer 20 can also be deposited on the front side 54 of the semiconductor substrate 12, at least partially at the edge. The first doped silicon layer 20 can be deposited in situ or first intrinsically deposited and then ex-situ doped. In the case of ex-situ doping, it should be noted that the silicate glass layer 62 on the front side 54 must at least partially serve as a diffusion barrier, especially when the doping types of the first doped silicon layer 20 and the fourth doped silicon layer 48 are opposite. If the first doped silicon layer 20 is also deposited on the front side 54, it must optionally be removed and / or processed in a further process step.

[0115] Next, an etch-stabilized barrier layer 58 is formed on the first doped silicon layer 20 (see...). Figure 10This can be achieved through deposition. The material of the barrier layer 58 can be silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride (SiON). The barrier layer 58 can also be disposed as a multilayer stack on the back side 56 of the semiconductor substrate 12. In another process step, the barrier layer 58 serves as an etch barrier layer to prevent alkaline etching. In the case of ectopic doping of the first doped silicon layer 20, for example, silicate glass grown by furnace diffusion can also be used as the barrier layer 58. The barrier layer 58 can also completely or only partially cover the front side 54, for example at the edge. Any barrier layer 58 on the front side 54 is not shown, but can be retained or removed in further process steps if necessary.

[0116] After the barrier layer 58 is formed, the barrier layer 58 is removed in multiple etched regions 60 (see [reference]). Figure 11 This can be achieved, for example, by laser ablation. The ablation width can be between 50 μm and 2000 μm. The distance (center to center) between the two etched regions 60 can be between 200 μm and 3000 μm. Ablation can proceed linearly, forming a so-called "cross" pattern. This pattern can be interrupted in the busbar region of the solar cell 10. When the barrier layer 58 in the etched region 60 is removed, the first doped silicon layer 20 and / or the first tunnel layer 28 can also be partially or completely removed. Furthermore, the semiconductor structure 12 on the back surface 56 can also be partially removed.

[0117] The etched area 60 is then etched, wherein a platform-shaped protrusion 42 of the semiconductor substrate 12 is created by etching (see [reference]). Figure 12 A first region 18 is disposed on a platform-shaped protrusion 42, and a second region 22 is disposed between the platform-shaped protrusions 42. In this case, specifically, the first doped silicon layer 20, the first tunnel layer 28, and a portion of the semiconductor substrate 12 on the back surface 56 in the second region 22 are removed by etching. The etching can be performed with an acidic or alkaline solution, which removes silicon isotropically or anisotropically. In this case, the barrier layer 58 (outside the etched region 60) is not etched or is etched only very slowly, such that the first doped silicon layer 20 is not etched or is only slightly etched parallel to the first direction 44 outside the etched region 60. The barrier layer 58, the first doped silicon layer 20, and the first tunnel layer 28 are under-etched, and a third region 26 is formed that is shielded along the first direction 44 (perpendicular to the back surface).

[0118] The depth of the etched area 60 is determined by the etching process and ranges from 0.5 μm to 20 μm.

[0119] In a single-sided process, etching can only be performed on the back side 56. When using a batch process, where both the front side 54 and back side 56 of the semiconductor substrate 12 (or silicon wafer) are fully immersed in the etching solution, the silicate glass layer 62 can act as an etching barrier and prevent etching of the semiconductor substrate 12 on the front side 54. If the first doped silicon layer 20 was also deposited on the front side 54 in a previous step, the first doped silicon layer 20 can be etched until the underlying silicate glass layer 62 is exposed. If the barrier layer 58 was also deposited on the front side 54 in a previous step, it can be selectively removed by (acidic) etching on the front side 54, as in single-sided etching, for example. This also applies to cases where an etch-stable silicate glass is grown on the first doped silicon layer 20 during ex-situ doping.

[0120] Then the barrier layer 58 and / or the silicate glass layer 62 can be completely removed (see [link]). Figure 13 This can be achieved using an acidic solution. A cleaning step can then be performed.

[0121] In the next step, the second tunnel layer 30 will be formed (see...). Figure 13 The second tunnel layer 30 can be formed by deposition or growth. The second tunnel layer 30 can be formed on the back side 56; alternatively, the second tunnel layer 30 can also be formed on the front side 54. The second tunnel layer 30 can saturate the open bonds on the surface of the semiconductor substrate 12. The second tunnel layer 30 can have a layer thickness of 5 to 40 angstroms.

[0122] Then a second doped silicon layer 24 is formed (see...) Figure 14 The second doped silicon layer 24 can be formed by deposition. The second doped silicon layer 24 can be deposited using a directional process, such as PVD. The second doped silicon layer 24 (e.g., P-type) specifically has a doping type opposite to that of the first doped silicon layer 20 (e.g., N-type). Because the cross-section of the plateau-shaped protrusion 42 widens along the first direction 44, the second doped silicon layer 24 is not formed in the third region 26. Therefore, the third region 26 does not contain amorphous, microcrystalline, or polycrystalline silicon. In particular, due to directional deposition (parallel to and opposite to the first direction 44), particles of the second doped silicon layer 24 are not deposited in the third region 26 because these regions are shielded.

[0123] Within the first region 18, a second doped silicon layer 24 is deposited on the second tunnel layer 30 and the first doped silicon layer 20 below it. The thickness of the second doped silicon layer 24 can be between 20 nm and 400 nm. The second doped silicon layer 24 can have a thickness of 1 × 10⁻⁶ nm. 19 cm -3 Up to 2 × 10 20 cm -3The dopant concentrations are varied. Specifically, due to the directional deposition characteristics, the second doped silicon layer 24 will not be deposited on the front side 54. A subsequent high-temperature process can be added for crystallizing the first doped silicon layer 20 and / or the second doped silicon layer 24, and for activating the dopants in the first doped silicon layer 20 and / or the second doped silicon layer 24.

[0124] Next, a dielectric layer 32 can be deposited to passivate the surfaces of the front side 54 and the back side 56 (see [link]). Figure 15 The dielectric layer 32 may consist of one or more layers, such as aluminum oxide, silicon oxide, and / or silicon nitride. In this case, the dielectric layer 32 consists of two layers. The dielectric layer 32 on the front side 54 and the dielectric layer 32 on the back side 56 may be designed the same or different, particularly having different properties. A wet chemical cleaning step may be performed prior to the deposition process of the dielectric layer 32. Hydrogen contained in the dielectric layer can be used for opening bonds on the surface of the saturated semiconductor substrate 12, particularly in the first region 18 and the second region 22 where the first doped silicon layer 20 and the second doped silicon layer 24 are respectively disposed. The dielectric layer 32 can also be used as an anti-reflective coating, particularly formed on the front side 54, to increase the luminous efficiency of the solar cell.

[0125] Then the first electrode 38 and the second electrode 40 can be formed and / or applied (see...). Figure 16 The first electrode 38 and / or the second electrode 40 are arranged such that the first electrode 38 respectively contacts the first doped silicon layer 20, and the second electrode 40 respectively contacts the second doped silicon layer 24. In this case, the first electrode 38 within the first region 18 can penetrate the second doped silicon layer 24 and the second tunnel layer 30.

[0126] To facilitate contact between the first electrode 38 and the second electrode 40, the dielectric layer 32 may have a first interruption 34 and a second interruption 36 at corresponding locations. The transition between the first interruption 34 and the second interruption 36 can be achieved, for example, by localized ablation, such as laser irradiation. A paste can also be used to form the first electrode 38 and the second electrode 40. The first interruption 34 and / or the second interruption 36 can also be generated during paste burning, as the paste locally dissolves the dielectric layer 32. The burning step can also positively impact the passivation of the non-metallized surface, as hydrogen contained in the dielectric layer 32 is moved during the high-temperature step, diffuses to the surface of the semiconductor substrate 12, and saturates the open bonds there, enhancing the passivation effect.

[0127] The first interruption 34 and / or the second interruption 36 can be made into continuous lines, dots, squares, or segmented lines. The slurry can be made of, for example, silver, copper, or aluminum as the conductive metal. After firing, the particles in the slurry sinter together to form the first electrode 38 and / or the second electrode 40. The first electrode 38 and / or the second electrode 40 can also be made of, for example, a stack of silver and copper layers (slurry stacking). When using aluminum, the composition of the slurry can be selected to achieve a very low degree of aluminum-silicon alloying. This composition is suitable for both positive and negative polarities.

[0128] Alternatively, the composition of the slurry can be chosen such that, during sintering, aluminum alloys with silicon, and the resulting aluminum-silicon eutectic 50 penetrates the first doped silicon layer 20 and / or the second doped silicon layer 24. In this case, aluminum can be further doped with silicon and surround the aluminum-silicon eutectic 50, allowing for the formation of an aluminum-doped emitter or an aluminum-doped back surface field, depending on the polarity of the base electrode. This alloy slurry is particularly suitable for positive electrodes (see...). Figure 3 For the negative electrode, an N-type dopant can be added to the paste so that after the eutectic is formed, the N-type doped silicon surrounds the eutectic, making the paste suitable for forming the negative electrode.

[0129] Figures 17 to 28 A method for manufacturing a back-contact solar cell 10 according to a second embodiment is shown. Using the method shown, the above-described embodiments can be implemented, particularly according to… Figure 2 The first embodiment shown is used to manufacture the solar cell 10.

[0130] In the first step, the semiconductor substrate 12 is anisotropically etched to remove any sawing damage. This results in a flat surface on the front side 54 and back side 56 of the semiconductor substrate 12 (see [link]). Figure 17 ).

[0131] Next (similar to the first embodiment of this method), a first tunnel layer 28 is formed on the back surface 56 of the semiconductor substrate 12, followed by a first doped silicon layer 20, and then a barrier layer 58 (see...). Figure 18 , 19 and 20).

[0132] In this case, the first tunnel layer 28 may have a layer thickness of 5 to 40 angstroms, the first doped silicon layer 20 may have a layer thickness of 20 nm to 400 nm, and the barrier layer 58 may be formed similarly to the first embodiment of the method.

[0133] The first tunnel layer 28 can also be thermally grown. The first tunnel layer 28, the first doped silicon layer 20, and / or the barrier layer 58 can completely cover the back side 56 of the semiconductor substrate 12. The first tunnel layer 28, the first doped silicon layer 20, and / or the barrier layer 58 can each partially or completely cover the front side 54 of the semiconductor substrate 12, or they can only partially cover it at the edges.

[0134] The first doped silicon layer 20 can be deposited using in-situ doping with a dopant concentration of 1 × 10⁻⁶. 19 Up to 2 × 10 20 cm -3 Alternatively, intrinsic deposition followed by ex-situ doping, such as via furnace diffusion, may be used. If the silicate glass is grown on the surface during furnace diffusion, this can optionally serve as the barrier layer 58. According to Table 1, the doping of the first doped silicon layer 20 may include N-type or P-type doping. The barrier layer 23 may include a dielectric layer, the material of which may be, for example, SiOx, SiON, or SiNx, or a stack of multiple such layers.

[0135] Subsequently (similar to the first embodiment of this method), the barrier layer 58 is locally removed to form the etched region 60 (see [reference]). Figure 21 This can be achieved, for example, by laser ablation. In this case, the first doped silicon layer 20 and / or the first tunnel layer 28 can also be partially or completely removed in the etched region 60. Furthermore, it can be at least partially removed in the etched region 60 on the back side 56 of the semiconductor substrate 12.

[0136] Subsequently, a wet chemical etching step is performed to remove (if still present) the first tunnel layer 28, the first doped silicon layer 20, and a portion of the semiconductor substrate 12 (see [link to relevant documentation]). Figure 22 In this case, approximately 0.5 μm to 20 μm of the semiconductor substrate 12 can be removed in the etched area 60. The etching using an alkaline silicon etchant can be performed only on one side of the back side 56, or it can also include the front side 54. In this case, if necessary, layers that may have been deposited on the front side 54 in previous process steps should also be etched, with additional single-sided etching if required.

[0137] Similarly, it is conceivable to clean and / or etch the front side 54 in earlier or later process steps. Etching the front side 54 produces a textured surface. Importantly, during etching on the back side 56, under-etching occurs on the barrier layer 58 and optionally the first doped silicon layer 20, forming an under-etched region (i.e., forming the protrusion 42 and the third region 26). The third region 26 is masked along the first direction 44 (perpendicularly) by the barrier layer 58 and the first doped silicon layer 20. The third region 26 is formed regardless of whether isotropic or anisotropic etching is used. Particularly in the case of isotropic etching, the surface of the third region 26 can be textured and given a slope, such as... Figure 4 As shown.

[0138] After etching, a second tunnel layer 30 is formed by growth or deposition (see [reference]). Figure 23 The second tunnel layer 30 can have a thickness of 5 to 40 angstroms. The second tunnel layer 30 can be grown or deposited non-directionally, so that the second tunnel layer 30 can also be formed in the first region 18, the second region 22 and the third region 26. The second tunnel layer 30 can also be formed on the front face 54.

[0139] Then a second doped silicon layer 24 is formed (see...) Figure 24 This can be achieved through directional deposition, for example, by physical vapor deposition (PVD). In this case, the second doped silicon layer 24 is deposited over the entire unshaded surface of the back side 56 of the semiconductor substrate 12. The second doped silicon layer 24 is not deposited in the under-etched shaded third region 26. Therefore, the second doped silicon layer 24 is isolated by the third region 26. Within the second region 22, the second doped silicon layer 24 is also not in contact with the first doped silicon layer 20.

[0140] The second doped silicon layer 24 can be deposited in situ or intrinsically deposited, and then doped, for example, in a furnace diffusion process (see [link to documentation]). Figure 25 Another layer can be deposited on the second doped silicon layer 24 by PVD. This layer can serve as a diffusion barrier in the subsequent furnace diffusion step, preventing further doping of the second doped silicon layer 24 during furnace diffusion. In each case, a third doped silicon layer 46 with the opposite doping type to the second doped silicon layer 24 can be formed in the third region 26. According to Table 1, the doping of the second doped silicon layer 24 should be opposite to the doping of the first doped silicon layer 20.

[0141] To form charge carrier-selective contacts, a high-temperature step can be added, which crystallizes the amorphous, microcrystalline, or polycrystalline silicon of the first doped silicon layer 20 and / or the second doped silicon layer 24 and activates the dopant. This crystallization can also be carried out, for example, in the furnace diffusion step described above, thus eliminating the need for the high-temperature step.

[0142] Figure 25A diffusion process using dopants such as boron and phosphorus is illustrated for forming a fourth doped silicon layer 48 on the front side 54. The doping polarity of the fourth doped silicon layer 48 is selected according to Table 1. It may prove advantageous if the back side 56 is also fully or at least partially doped in the same process step. In this case, in particular, the same or similar doping as the front side 54 is formed in the third region 26, i.e., a third doped silicon layer 46 is formed. If the second doped silicon layer 24 has already been intrinsically deposited, the second doped silicon layer 24 can be doped in the same way during this diffusion step, or if the second doped silicon layer 24 is not covered by a diffusion barrier, it can be further doped.

[0143] The dopant concentration of the second doped silicon layer 24 may differ from that of the third region 26 and the fourth doped silicon layer 48 because the diffusion rate in amorphous, microcrystalline, or polycrystalline silicon is higher than that in the single-crystal semiconductor substrate 12. Furthermore, if a second tunnel layer 30 is present on the surfaces of the third region 26 and the front side 54, the second tunnel layer 30 can prevent or reduce the diffusion of impurities in the third region 26 and the front side 54.

[0144] During the diffusion step, particularly during furnace diffusion, a silicate glass layer 62, such as borosilicate glass (BSG) or phosphosilicate glass (PSG), can be grown on the front side 54 and the back side 56 (see [link to documentation]). Figure 25 In the case of a P-type semiconductor substrate 12, this step can be omitted. Figure 25 The method steps shown prevent the formation of a highly doped fourth doped silicon layer 48 on the front side 54, and also prevent the formation of a highly doped third doped silicon layer 46 in the third region 26. In this case, the second doped silicon layer 24 can be deposited in an in-situ doped manner.

[0145] In a further step, wet chemical cleaning may be performed to remove the silicate glass layer 62 on the front side 54 and the back side 56 (see [link]). Figure 26 ).

[0146] During the etching step, the second tunnel layer 30 in the third region 26 may also be removed (if present). The second tunnel layer 30 can be removed in the same etching step as the silicate glass layer 62. In other words, the second tunnel layer 30 and the silicate glass layer 62 can be removed together (or by the same etching) (if present).

[0147] Figure 27 and 28 The dielectric layer 32 formed on the front side 54 and the back side 56 (in this example, each consists of two layers) is shown, as well as the formation of the first electrode 38 and the second electrode 40. Figure 27 and 28 The steps shown correspond to Figure 15 and 16The steps of the first embodiment shown are, in particular, the same as these steps.

[0148] The steps of the two embodiments of the above method can be combined and / or supplemented with each other as needed.

Claims

1. A back-contact solar cell (10), characterized in that, The device includes a semiconductor substrate (12), a front side (14), and a back side (16). The back side (16) is provided with a plurality of first regions (18), a plurality of second regions (22), and a plurality of third regions (26). Each first region (18) includes a first doped silicon layer (20), and each second region (22) includes a second doped silicon layer (24). The first doped silicon layer (20) and the second doped silicon layer (24) are each formed as amorphous, microcrystalline, or polycrystalline. The third region (26) does not contain amorphous, microcrystalline, or polycrystalline silicon. A first tunnel layer (28) is disposed between the first doped silicon layer (20) and the semiconductor substrate (12). A second tunnel layer (30) is disposed between the second doped silicon layer (24) and the semiconductor substrate (12). The first region (18) and the second region (22) are each configured as passivated contacts. The back side (16) of the solar cell (10), or the surfaces of the back side (16) and the front side (14), is at least partially covered with a dielectric layer (32) or a stack of dielectric layers, the dielectric layer (32) including a first interruption (34) in the first region (18) and a second interruption (36) in the second region (22); the solar cell (10) includes a plurality of first electrodes (38) and a plurality of second electrodes (40), wherein the first electrodes (38) contact a first doped silicon layer (20) through the first interruption (34); the second electrodes (40) contact a second doped silicon layer (24) through the second interruption (36); the first region (18) is arranged on a platform protrusion (42) of the semiconductor substrate (12), each of the platform protrusions (42) having a cross section widened along a first direction (44).

2. The back-contact solar cell (10) according to claim 1, characterized in that, The third region (26) is configured as an under-etched region.

3. The back-contact solar cell (10) according to claim 1 or 2, characterized in that, The third region (26) is undoped.

4. The back-contact solar cell (10) according to claim 1 or 2, characterized in that, The third region (26) has a third doped silicon layer (46).

5. The back-contact solar cell (10) according to any one of the preceding claims, characterized in that, A fourth doped silicon layer (48) is disposed on the front side (14) of the solar cell (10).

6. The back-contact solar cell (10) according to any one of the preceding claims, characterized in that, The semiconductor substrate (12), the first doped silicon layer (20), the second doped silicon layer (24), the third region (26) or the third doped silicon layer (46), the front side or the fourth doped silicon layer (48) of the solar cell (10) have doping according to one of the combinations in Table 1; Table 1 。 7. The back-contact solar cell (10) according to any one of the preceding claims, characterized in that, The first doped silicon layer (20), the second doped silicon layer (24), the first tunnel layer (28) and / or the second tunnel layer (30) have no pores.

8. The back-contact solar cell (10) according to any one of claims 1 to 5, characterized in that, The first doped silicon layer (20), the second doped silicon layer (24), the first tunnel layer (28) and / or the second tunnel layer (30) are each penetrated by an aluminum-silicon eutectic (50), wherein the aluminum-silicon eutectic (50) is disposed on the first electrode (38) and / or the second electrode (40).

9. The back-contact solar cell (10) according to claim 8, characterized in that, The aluminum-silicon eutectic (50) is at least partially surrounded by a fifth doped silicon layer (52), wherein the fifth doped silicon layer (52) has P-type doping or N-type doping depending on the doping of the first doped silicon layer (20) or the second doped silicon layer (24).

10. A method for manufacturing a back-contact solar cell (10) according to any one of the preceding claims, comprising the following steps: A semiconductor substrate (12) having a front side (54) and a back side (56) is provided. A first tunnel layer (28) is formed on the back side (56) of the semiconductor substrate (12). A first doped silicon layer (20) of the first polarity is formed on the first tunnel layer (28); An etch-stable barrier layer (58) is formed on the first doped silicon layer (20); Remove the etch-stabilized barrier layer (58) in multiple etched regions (60); Etching is performed in the etched area (60) to create a platform-shaped protrusion (42) on the semiconductor substrate (12) having a cross-section that widens along the first direction (44). Completely remove the etch-stabilized barrier layer (58); A second tunnel layer (30) is formed in the region between the platform-shaped protrusions (42) of the semiconductor substrate (12). In the region between the platform-shaped protrusions (42), a second doped silicon layer (24) with a second polarity opposite to the first polarity is formed. Due to the widened cross-section of the platform-shaped protrusions (42), no second doped silicon layer (24) is formed in the third region (26).

11. The method according to claim 10, characterized in that, The method includes the following steps: The third doped silicon layer (46) is formed in the third region (26) by furnace diffusion and / or the fourth doped silicon layer (48) is formed on the front side (54).

12. The method according to claim 11, characterized in that, The method includes the following steps: Remove the silicate glass layer (62) formed during furnace diffusion, particularly by etching.

13. The method according to any one of claims 10 to 12, characterized in that, The method includes the following steps: An aluminum-silicon eutectic (50) is formed by using a paste or paste stack on the first electrode (38) and / or the second electrode (40), in particular, the paste or paste stack contains a P-type dopant, especially aluminum and / or an N-type dopant.

Images