Stress layer modification via photoresist mask using energy beam processing

Abstract

A method can include disposing a stress compensation stack on a major surface of a substrate, where the stress compensation stack includes a patterned resist layer and a stress compensation layer disposed beneath the patterned resist layer. The patterned resist layer can be determined according to a surface map of the major surface of the substrate. The method can also include directing a process species to the stress compensation stack, where the stress compensation layer is selectively varied according to a location on the substrate.

Description

[0001] Related applications

[0002] This application claims priority to U.S. nonprovisional patent application serial number 18 / 399,346, filed on December 28, 2023, entitled “Strress Layer Modification by Energy Beam Processing via Photoresist Mask”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to stress control in a substrate, and more specifically, to stress compensation for managing substrate stress. Background Technology

[0004] Devices such as integrated circuits, memory devices, and logic devices can be fabricated on substrates such as semiconductor wafers through a combination of deposition, etching, ion implantation, annealing, and other processes. Typically, the complete fabrication of a device and its associated circuitry may require hundreds of operations, including dozens of lithography operations. Specifically, lithography operations may require the alignment of a given mask used to fabricate a structure in a given area or layer with a pre-existing structure.

[0005] A problem arising from substrate fabrication is the generation of out-of-plane distortion (OPD) caused by stress within the wafer, a type of distortion often referred to as warping. This OPD can result from stress generated within the wafer during processing. Therefore, OPD management can be critical for achieving proper overlay between structures fabricated at different levels of the device. For example, a common type of OPD encountered is global wafer curvature, which can occur at many processing locations due to stress buildup within the wafer caused by processing operations. A related problem is so-called in-plane distortion, which refers to the distortion of the substrate in the XY plane caused by the XYZ distortion characteristics of the OPD.

[0006] One method for managing wafer (substrate) stress is to provide a stress compensation layer on the back of the substrate. This layer can be used to counteract existing stress within the substrate, thereby reducing OPD. In specific embodiments, ion implantation has been used to implant ions into the stress compensation layer in an attempt to alter the stress state within the stress compensation layer, and thus indirectly change the stress and OPD within the substrate.

[0007] In some methods, blanket ion implantation can be performed to address the global curvature of the substrate by uniformly varying the stress state in the stress compensation layer across the substrate. In other methods, patterned implantation can be performed to address more varied OPD patterns in the substrate, such as so-called potato chip curvature or saddle curvature. In known ion implantation methods, an ion beam can be guided to scan different locations on the substrate to impart varying ion doses based on the substrate location.

[0008] Currently, methods for implanting ion beams into stress-compensation layers of substrates can process the substrate at a rate of approximately one to ten wafers per hour, a rate that may be too slow for commercial wafer manufacturers. Furthermore, patterned ion implantation methods that use ion beam scanning to generate implantation patterns may lack sufficient spatial resolution to address complex OPD patterns on the substrate, such as chip-level variations that may arise from processing operations performed to define circuit systems on each die portion of the wafer.

[0009] Embodiments of this disclosure are provided in consideration of these and other considerations. Summary of the Invention

[0010] In one embodiment, a method is provided. The method may include forming a stress compensation stack on a main surface of a substrate, wherein the stress compensation stack includes a patterned resist layer and a stress compensation layer disposed beneath the patterned resist layer. The patterned resist layer may be determined based on a surface pattern of the main surface of the substrate. The method may further include directing a processing species to the stress compensation stack, wherein the stress compensation layer is selectively modified according to its location on the substrate.

[0011] In another embodiment, an ion implanter may include: an ion source for generating an ion beam; a beamline assembly for varying the scanning of the ion beam; and a controller including: a processor; and a memory unit coupled to the processor and including a scanning implantation routine. The scanning implantation routine operates on the processor to control the ion implanter: receiving a surface map of a substrate; and applying an implantation pattern to a stress-compensating layer on the substrate by performing scanning implantation based on the surface map.

[0012] In another embodiment, a controller for an ion implanter may include: a processor; and a memory unit coupled to the processor and including a scanning implantation routine. The scanning implantation routine may operate on the processor to control the ion implanter: receiving a surface map of a substrate; and applying an implantation pattern to a stress compensation layer on the substrate by performing scanning implantation based on the surface map. Attached Figure Description

[0013] Figure 1A An exemplary ion implantation system according to this disclosure is shown;

[0014] Figure 1B Further details of a controller according to some embodiments of the present disclosure are shown;

[0015] Figure 2A An example of a wafer pattern is shown, which depicts the surface of a substrate exhibiting an OPD pattern;

[0016] Figure 2B Showing the use of Figure 2A An exemplary gray-toned resist pattern for stress management in the substrate shown;

[0017] Figures 3A to 3G Exemplary stages are shown when processing a substrate to reduce OPD according to some embodiments of the present disclosure;

[0018] Figure 3H An embodiment for processing a stress compensation layer is shown;

[0019] Figure 4A and Figure 4B The illustration shows two stages, according to one embodiment, in which a gray-toned resist is treated to produce a variable resist layer thickness;

[0020] Figure 5A Another embodiment of using a digital implantation hood for substrate-level stress management is shown;

[0021] Figure 5B Another embodiment of chip-level stress management using a digital implantation veil is shown;

[0022] Figure 6A It is a curve diagram that presents a three-dimensional surface view of a portion of the substrate at the chip level;

[0023] Figure 6B It is an illustration showing a three-dimensional surface view of the entire substrate, which shows repeating OPD patterns corresponding to 24 different chip regions;

[0024] Figure 6C This demonstrates the use of a grayscale mask to process repeating OPD patterns. Figure 6B Top view of the substrate shown;

[0025] Figure 6D Show Figure 6C Side view of the arrangement shown;

[0026] Figure 6E Shown in Figure 6C Examples follow Figure 6BThe strip bundle treatment of the gray-toned resist pattern developed on the substrate shown.

[0027] Figure 6F An example of a non-uniform scan of the processing beam is shown;

[0028] Figure 6G Shown in Figure 6E After the treatment and after the subsequent removal of the gray resist Figure 6B A three-dimensional surface view of the substrate shown;

[0029] Figure 7 An exemplary manufacturing process is shown;

[0030] Figure 8 An exemplary manufacturing process is shown; and

[0031] Figure 9 An exemplary manufacturing process is shown. Detailed Implementation

[0032] Embodiments of this disclosure will now be described more fully below with reference to the accompanying drawings, in which some embodiments are illustrated. The subject matter of this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and that they will fully convey the scope of the subject matter to those skilled in the art. In the drawings, the same reference numerals consistently refer to the same components.

[0033] The embodiments described herein relate to techniques and apparatus for improved substrate stress management and related management of out-of-plane distortion (OPD). This disclosure proposes a method that employs energy beam processing or energy particle processing in conjunction with a patterned photoresist (“resist”) layer and a stress control layer to control the distribution of damage in the X, Y, and Z directions within the stress control layer, thereby achieving better accuracy and resolution control of OPD on the substrate.

[0034] Now refer to Figure 1AThis illustration shows an exemplary system according to the present disclosure. The ion implantation system (hereinafter referred to as the "system") 10 represents a beamline that houses components such as an ion source 14 for generating an ion beam 18, an ion implanter, and a series of beamline assemblies 16. The ion source 14 may include a chamber for receiving a gas flow 24 and generating ions therein. The ion source 14 may also include a power source and an extraction electrode assembly disposed near the chamber. While not limiting, the ion source 14 may include a power generator, a plasma exciter, a plasma chamber, and the plasma itself. The plasma source may be an inductively coupled plasma (ICP) source, a toroidal coupled plasma (TCP) source, a capacitively coupled plasma (CCP) source, a helical source, an electron cyclotron resonance (ECR) source, an indirectly heated cathode (IHC) source, a glow discharge source, an electron beam-generated ion source, or other plasma sources known to those skilled in the art. As shown, one or more feed sources 28 may be present and can operate together with the chamber of ion source 14. In various embodiments, different species may be used as ions for treating stress in the film. Non-limiting examples of suitable ions include silicon (Si), boron (B), carbon (C), oxygen (O), germanium (Ge), phosphorus (P), arsenic (As), argon (Ar), krypton (Kr), neon (Ne), and so on, to control substrate stress.

[0035] The beamforming assembly 16 may include, for example, a mass analyzer 34, a first acceleration or deceleration stage 36, a collimator 38, a quality resolution slit 40, and other suitable downstream beamforming assemblies (e.g., an energy filter 42) to accelerate, decelerate, shape, scan, etc., the ion beam 18. In specific embodiments, the beamforming assembly 16 may filter, focus, accelerate, decelerate, and otherwise manipulate ions or the ion beam 18 to have desired species, shape, energy, and other qualities. The ion beam 18 passing through the beamforming assembly 16 may be guided toward a substrate mounted on a platen or fixture within the process chamber 46. As understood, the substrate may be movable in one or more dimensions (e.g., translation, rotation, and tilt).

[0036] According to various embodiments of this disclosure, ion source 14 can be embedded in a patterned layer to generate an ion beam 18 for processing a substrate to reduce OPD in the substrate. In various embodiments, the ion beam (in cross-section) may have a targeted shape, such as a dot beam or a strip beam, as known in the art. In the Cartesian coordinate system shown, the propagation direction of the ion beam 18 may be represented as parallel to the Z-axis, while the actual trajectory of the ions within the ion beam 18 may vary. To process the substrate, the ion beam 18 can be accelerated to obtain a target energy by establishing a voltage (potential) difference between the ion source 14 and the wafer (substrate). In a specific embodiment, the ion beam 18 may be a strip beam extending along the x-direction to cover the entire substrate 100 along the x-direction. As further shown in FIG1, system 10 may include controller 50 to control the operation of various components of system 10, including, for example, components for scanning pressure plate 48, components for tilting pressure plate 48, components for scanning ion beam 18, or components for adjusting the energy of ion beam 18. Figure 1B Details of an embodiment of the controller 50, further discussed below, are provided. In this manner, the ion beam 18 and / or the pressure plate 48 can be scanned along the Y direction to expose the entire substrate 100.

[0037] Figure 2A An example of a wafer pattern is shown, which depicts the surface of a substrate 100 exhibiting an OPD pattern. For example... Figure 2A The OPD shown can be a reflection of non-uniform stress within the substrate 100, thus producing a pattern of substrate curvature at least partially caused by non-uniform stress. Figure 2A The OPD shown is characterized by a substrate surface that is shifted downward along the y-axis in the top and bottom regions and upward along the X-axis in the leftmost and rightmost regions, thereby giving the substrate a saddle-shaped shape in three dimensions. The center of substrate 100 can be considered to be located at point 0 along the z-axis. For the 300 mm diameter wafer (substrate 100) shown, the maximum downward OPD relative to θ is approximately 90 micrometers, while the maximum upward OPD (to the left and right) is approximately 263 micrometers.

[0038] Figure 2B Showing the use of Figure 2A An exemplary gray-toned resist pattern for stress management in the substrate shown (for brevity, unless otherwise stated, the term "resist" as used herein refers to photoresist). Resist pattern 101 can be produced to provide a mask for use in conjunction with ion implantation, thereby reducing or eliminating stress such as... Figure 2AThe OPD is shown in the figure. In this example, resist pattern 101 may represent a gray-toned resist pattern formed using a gray-toned resist. For the purpose of simplification, resist pattern 101 is shown as having multiple distinct areas (shown as gray-toned areas 102). However, embodiments of this disclosure cover more complex resist patterns, as detailed below. Resist pattern 101 may include blocking areas 104 and gray-toned areas 102. These areas may be designed to cause more or less ion attenuation of the ion beam to be used for implantation into the stress compensation layer (not visible) located beneath resist pattern 101 on the substrate 100.

[0039] In a non-limiting example, the blocking region 104 may include a resist having a uniform thickness sufficient to block all ion impacts of the stress-compensating layer from the ion beam. The grayscale region 102 may be defined by a resist region and an area where the resist is completely removed, the thickness of which varies depending on its location on the substrate (in the XY plane). In one embodiment, when the resist pattern 101 is exposed to an ion beam, the ion beam will create an implantation pattern within the stress-compensating layer to reduce or eliminate... Figure 2A The OPD pattern shown alters the stress state in the stress compensation layer.

[0040] To further elaborate on substrate stress management using grayscale resist patterning combined with ion implantation Figures 3A to 3G Exemplary stages are shown when processing a substrate to reduce OPD according to some embodiments of this disclosure. Figure 3A The diagram illustrates a substrate 100, which may be a silicon wafer. In some embodiments, substrate 100 may exhibit curvature, including OPD characterized by complex warping patterns. In the illustrated example, the substrate is shown in cross-section, for example, in the XZ plane of the illustrated Cartesian coordinate system, but the relative dimensions in terms of width, substrate thickness, and curvature may not be drawn to scale. For example, according to some non-limiting embodiments, substrate 100 may represent a wafer with a diameter of 200 mm, 300 mm, or other sizes along its main surface. In some embodiments, the thickness of substrate 100 may be on the order of several hundred micrometers. Furthermore, the maximum OPD exhibited by substrate 100 (which can be expressed using deviations from a nominally flat XY plane) may be on the order of several hundred micrometers.

[0041] exist Figure 3BThe diagram illustrates a subsequent example where a stress compensation layer 202 has been formed on the main surface of the substrate 100. The stress compensation layer 202 can be a known stress compensation layer material, such as an oxide layer or nitride layer according to some non-limiting embodiments, including silicon nitride (also referred to below as "SiN"). In this way, the stress compensation layer 202 may substantially alter the overall stress state of the substrate 100 or may not substantially alter the overall stress state of the substrate 100, and therefore, as... Figure 3A The OPD pattern presented in it is sustainable, such as Figure 3B As shown in the image.

[0042] exist Figure 3C Here, a subsequent example is shown in which a blanket-like photoresist layer, referred to as a grayscale photoresist layer 204, has been applied to the stress compensation layer 202. The grayscale photoresist layer 204 may be composed of a known photoresist material (e.g., a suitable grayscale photoresist material). The formation of the grayscale photoresist layer 204, having a low elastic modulus, may cause little or no change to the overall stress state of the substrate 100, and therefore, as... Figure 3A The OPD presented in the document is sustainable.

[0043] exist Figure 3D In the middle, a subsequent example is shown, in which the grayscale resist layer 204 has been processed into a patterned resist layer exhibiting a variation in film thickness (meaning the thickness along the Z-axis varies depending on its position along the XY plane). This variation in resist thickness may or may not create exposed areas in which the upper surface of the underlying layer (stress compensation layer 202) is exposed. Similarly, the patterning of the grayscale resist layer 204 may have little or no effect on the OPD pattern on the substrate 100.

[0044] In the various embodiments further discussed below, patterning of the gray-toned resist layer 204 can be selected to provide an implantation mask for subsequent ion implantation processes to be performed. For example, in... Figure 3C At the stage shown, for example, the exact pattern of the implantation mask (meaning the patterned grayscale resist layer) is selected based on the OPD pattern presented on the substrate 100. In different embodiments, the patterning of the grayscale resist layer 204 can be accomplished by exposing the grayscale resist layer to radiation passing through a grayscale lithography mask, which presents a suitable pattern based on the OPD pattern. In some examples further discussed below, the resist mask process can be a digital process. After exposure to radiation, the grayscale resist layer 204 can be developed to produce... Figure 3DThe structure is shown. A grayscale lithography mask can be specifically selected to vary the degree to which the grayscale resist layer 204 is exposed to radiation according to its position along the XY plane. Therefore, the depth of the irradiated grayscale resist layer 204 will vary along the XY plane, allowing the final thickness of the grayscale resist layer 204 to vary after subsequent development processes. Known grayscale resist masks provide the ability to vary the resist layer thickness according to its position along the XY plane at scales as small as 100 nanometers or smaller. Therefore, the thickness variation of the grayscale resist layer 204 can appear smooth on lateral (XY) scales of micrometers or larger.

[0045] In some embodiments, the grayscale mask used to pattern the grayscale resist layer 204 may be applied directly to the grayscale resist layer 204 to produce, for example, a grayscale mask. Figure 3D The embossed mask of the structure shown.

[0046] Transfer to Figure 3E This illustrates a subsequent example when a substrate 100, including a stress compensation layer 202 and a grayscale resist layer 204, after patterning, is exposed to an ion implantation process (represented by an ion beam 206). The ion beam 206 can be selected to have appropriate ion energy for implantation into the substrate 100 to alter the stress state (specifically within the stress compensation layer 202). Figure 3E In the operation shown, ion beam 206 is represented as multiple ions, the trajectories of which are indicated by vertical arrows. Since ions can cross ion beam 206 with similar energies, the depth to which ions are implanted into stress compensation layer 202 is specifically determined by the local thickness of gray resist layer 204, which varies depending on its position in the XY plane. Therefore, some areas of stress compensation layer 202 will receive a relatively larger dose of ions compared to other areas, such as... Figure 3E The implantation profiles 208 associated with different ion positions are shown. Therefore, in locations where the grayscale resist layer 204 is sufficiently thick, some implantation profiles 208 can be completely contained within the grayscale resist layer 204; in other regions, the implantation distribution can extend into the stress compensation layer in smaller or larger quantities. Therefore, in Figure 3E Following the implantation procedure shown, the amount of implantation damage and thus the stress state within the stress compensation layer 202 will be selectively changed based on the XY position.

[0047] Transfer to Figure 3F , shown in Figure 3EThe example shown is a subsequent step after the implantation process is completed, in which the stress state of the stress compensation layer has been selectively modified in the XY plane. Therefore, through appropriate mask selection and ion beam parameter selection, the stress compensation layer 202 exhibits an implantation damage pattern reflecting the pattern of the gray-toned resist layer 204, thereby enabling… Figure 3A The original OPD shown is reduced or removed, such as Figure 3F As shown in the image.

[0048] exist Figure 3G The diagram illustrates a subsequent processing stage in which the gray-toned resist has been selectively removed, for example, by ashing. Note that the stress compensation layer 202 with a non-uniform implantation pattern is retained. Therefore, this non-uniform implantation pattern and the resulting non-uniform stress pattern continue to apply pressure to the substrate 100 to maintain the substrate with a low OPD.

[0049] In an alternative embodiment, Figure 3E At the processing stage shown, the energy of the ion beam 206 can be customized to produce substantial etching of the stress compensation layer 202 in areas where the grayscale resist has been completely removed or in areas where the grayscale resist is relatively thin so that ions can penetrate into the stress compensation layer 202. Figure 3H An embodiment is shown in which the stress compensation layer 202 is exposed to an energy beam to selectively etch the stress compensation layer 202 in areas where the gray-toned resist layer is absent or relatively thin. Thus, a patterned stress compensation layer with patterned or etched areas is formed. The patterned etched areas can be designed to selectively change the stress state in the stress compensation layer 202 according to their position in the XY plane, and therefore selectively change the stress state in the underlying substrate (i.e., substrate 100). In this way, a stress pattern can be imparted to the substrate 100 to reduce pre-existing OPD.

[0050] In different embodiments, the selective etching of the stress compensation layer 202, as shown in FIG2H, can be carried out by an inert ion beam, a reactive ion beam, a free radical beam generated from plasma (e.g., by immersion in a plasma chamber) or by chemical etching.

[0051] According to various embodiments of this disclosure, a grayscale photomask with a customized pattern can be used to process a grayscale resist layer to create a variable thickness within the grayscale resist layer over a suitable length scale to counteract initial substrate OPD. For example, for curvatures resulting in significant OPD at the wafer level (many centimeters in the XY plane) or chip level (many millimeters in the XY plane), stress control within the substrate may be necessary in a sub-millimeter range along the XY plane to reduce such curvature. Therefore, in various embodiments, a grayscale resist layer with a characteristic thickness can be fabricated, the thickness of which is customized to vary significantly over millimeter, hundred-micrometer, micrometer, or hundred-nanometer length scales. Such a characteristic can be easily fabricated using current grayscale resist technology.

[0052] In one approach, as previously described, a grayscale mask can be used to treat a grayscale resist, the grayscale mask being exposed to appropriate radiation to produce a desired pattern of the grayscale resist. Figure 4A and Figure 4B Two stages are shown in which a grayscale resist is treated to produce a resist layer of variable effective thickness according to one embodiment. In this example, a substrate 250, on which a stress compensation layer 202 and a grayscale resist layer 204 are disposed, is exposed using an illumination source 252. In known methods, a diffuser (not shown separately) may optionally be included between the illumination source 252 and the substrate 250. A grayscale mask 254 is disposed between the grayscale resist layer 204 and the illumination source 252 to partially attenuate radiation from the illumination source 252, thereby creating an exposure pattern in the grayscale resist layer 204. The grayscale mask 254 may include a patterned region 256 composed of sub-features arranged such that radiation passing through the grayscale mask is attenuated in a manner that smoothly varies along the XY plane. For example, the feature size of the patterned features in the patterned region 256 may be designed according to the wavelength of the radiation. For illustrative purposes, the dimensions of the patterned areas shown along the X and Y directions can be any suitable distance, such as equivalent to the wafer diameter, the size of the chip (die) on the wafer being processed, or in sub-millimeter lengths. Figure 4A As shown, the radiation attenuation in the patterned area 256 is greater on the left and smaller on the right. In the case of a positive resist, this will make the areas of the gray-toned resist layer 204 on the right side more easily dissolved by the developer than those areas on the left. Therefore, in Figure 4A After exposure and subsequent development, patterned features 204A are formed in the grayscale resist layer 204, such as... Figure 4BAs shown in the example. In this instance, the patterned feature 204A has a wedge shape in which the thickness changes smoothly along the X direction. However, with proper design of the patterned grayscale mask, any suitable shape (including three-dimensional shapes) can be imparted to the grayscale resist layer 204.

[0053] In other embodiments of this disclosure, a non-grayscale resist layer (e.g., a known resist with a “binary” response) may be patterned to facilitate selective modification of the underlying stress compensation layer. Figure 5A Another embodiment is shown, in which a resist layer is patterned to create a mask that serves as an implantation or etching mask, thereby selectively patterning the underlying stress compensation layer. In this example, a resist layer such as a binary resist is patterned to form a digitally patterned resist layer (shown as resist layer 292) in which resist layer 292 partially covers stress compensation layer 290. In a suitable example of digital resist patterning, a series of lines may be formed in resist layer 292, wherein a fixed pitch is implemented between adjacent lines. To vary the opacity of the digitally patterned resist layer, resist layer 292, and thus the degree to which stress compensation layer 290 is exposed to implanted ions or etch species, the duty cycle (linewidth) of the lines forming pattern 292A may vary depending on their position on substrate 280. In one example, such as Figure 5ASpecifically, the duty cycle applied to the pulse deposition beam can vary with the resist layer 292, thereby increasing towards the center of the substrate 280. Because the linewidth is relatively large towards the center of the substrate 280, the dose of the energy species that may affect the stress compensation layer 290 in the center of the substrate 280 is relatively low compared to the dose towards the edges of the substrate 280, as shown in the graph. In one example, where the substrate is a 300 mm wafer with a thickness on the order of 500 to 800 micrometers, this variation in dose implanted into the stress compensation layer 290 located above the substrate 280 can offset the global curvature of the substrate 280 (meaning wafer-level variations, e.g., the opposite of local variations at the chip level) depending on location. Note that in the pattern of the resist layer 292, the line pitch can be on the order of 1 to 10 micrometers, causing the linewidth to vary within a similar range depending on the duty cycle. Furthermore, the resist layer 292 can be arranged as a series of fields, which have a uniform working cycle (meaning a uniform linewidth) for the resist lines contained therein, wherein the field width of the lines is on the order of 1 mm to 10 mm. Thus, each field of a line can include approximately 1000 lines of uniform width, wherein the ion dose received in the stress compensation layer 290 from the ion beam treating the substrate 300 is uniform. Therefore, the average ion dose received in the substrate 280 can vary across the substrate 280 in steps of 1 mm to 10 mm width. However, such a step variation on a length scale of approximately 1 mm can still produce continuous effect changes on the substrate 280.

[0054] In such Figure 5B In another example shown, the digitally patterned resist layer is illustrated as resist layer 296 and is formed by a series of chip-scale fields, illustrated as field 296A, which have chip dimensions, for example, 1 cm or 2 cm per side. Within field 296A, patterning can be performed by digitally varying the work cycle with a fixed pitch, as described above, to address the curvature of the chip-level OPD or substrate 300.

[0055] In the above embodiments, the grayscale resist process can be used in conjunction with ion implantation to produce an implantation pattern that generates a variable amount of damage depending on its location on the substrate. Note that, in addition to areas where the resist thickness varies, this grayscale resist layer can also include large macroscopic areas (on the order of centimeters or millimeters) where the resist thickness does not change and therefore the implantation damage does not change. As described above, the exact pattern of this grayscale resist layer can be determined, for example, by an OPD pattern measured on the substrate during the formation of a stress compensation layer. When fabricating semiconductors or electronic devices on substrates such as silicon wafers, the wafer can be processed by generating similar or identical arrays of chip regions and subsequently dicing them into individual semiconductor dies. Therefore, during processing, repeatable patterns of means and circuit features can be formed across the substrate, where such repeatable means patterns generate accompanying repeatable stress or OPD patterns within the substrate. In other instances, an array of chip patterns in which the chip patterns vary from one another can be generated on the wafer. In either case, variations in OPD across wafers can be characterized on the length scale of individual chips (e.g., from a few millimeters to a few centimeters).

[0056] To address these issues, embodiments of this disclosure include a method for patterning a grayscale resist layer to mimic an OPD pattern in a wafer that has been processed to define an array of chip regions.

[0057] Figure 6A This is a graph depicting a portion of the substrate's three-dimensional surface at the chip level. In this example, an array of 24 rectangular regions (shown as chip regions 302) is defined on the surface of substrate 100. Figure 6B This is an illustration showing a three-dimensional surface view of the entire substrate 300, which shows the corresponding... Figure 6A The chip region 302 shown contains 24 different repeating OPD patterns. As previously mentioned, Figure 6A Chip region 302 is shown to have a saddle-shaped shape. Substrate 300 may correspond to, for example, a silicon wafer with a diameter of 300 mm. Thus, each of chip regions 302 may have a dimension of, for example, 40 mm in the X or Y direction. Note that in this example, the three-dimensional pattern of the OPD is substantially identical in each of the chip regions 302. In other words, a series of 24 different rectangular regions present a repeating OPD pattern on the surface of substrate 300, the repeating OPD pattern varying on a length scale from millimeters to centimeters. To flatten the substrate and reduce this OPD pattern, a gray-toned mask may be designed with a suitable pattern, the pattern being arranged to facilitate selective patterning. Embedded into substrate 300.

[0058] In known wafer patterning, chip-level processing that produces repeating device chip patterns (e.g., the 24 different chip regions shown) can also cause variations in the degree of localized OPD, for example, depending on the chip location on the wafer. Therefore, chip regions 302 can be further grouped according to their location on the substrate 300. For illustrative purposes, four groups of different chip regions are shown, wherein these groups are symmetrical with respect to the center of the substrate 300. Figure 6B In the diagram, the four different zones are shown as zone 302A, zone 302B, zone 302C, and zone 302D.

[0059] According to embodiments of this disclosure, an implantation pattern can be added to a chip-level resist pattern to control wafer bending within the requirements of subsequent device processing, the bending being on the order of 100 micrometers across the entire width of the substrate 300 and approximately 50 times smaller at the chip level.

[0060] Figure 6C Showing the use of grayscale screens Figure 6B The repeated OPD pattern shown is processed Figure 6B Top view of the substrate shown. Figure 6D Show Figure 6C The side view shows the arrangement. The gray-toned awning 310 can generally be designed based on the principles discussed above, especially for... Figure 4A and Figure 4B In this example, the grayscale mask 310 comprises an array of 24 features (shown as feature 312), the features having feature shapes shown for illustrative purposes only. Feature 312 itself may include resist features or a set of features having varying thicknesses in the XY plane. Note that when the grayscale mask 310 is aligned over the substrate 300, the features of the mask 310 can be resized and spaced to cover the chip region 302 in the substrate 300. Figure 6C In the case of a blanket coating of a gray resist layer 322 and a stress compensation layer 320, radiation 330 can be guided through the mask 310 to expose the substrate 300, such as... Figure 6D As further shown in the figure. Alternatively, grayscale mask features of individual chip regions 302 can be stepped on the substrate 300 to individually expose the chip regions 302.

[0061] like Figure 6CThe diagram further illustrates that, in some embodiments, feature 312 can vary in position on the grayscale mask 310. For example, based on the pattern of chip region 302, feature 312 can be grouped into four different groups according to its position, such as region 312A, region 312B, region 312C, and region 312D. Regarding the exact pattern of feature 312, these four different regions can vary from one another to address local differences in pattern or OPD amount between different regions 302A to 302D on the substrate 300.

[0062] Figure 6E Shown in Figure 6C After the instance Figure 6B The gray-toned resist pattern 332 is developed within the gray-toned resist layer 322 on the substrate 300. Subsequently, an ion implantation process can be performed, in which an ion beam is directed to the substrate 300 to selectively implant the ion beam into the stress compensation layer 320 according to the gray-toned resist pattern 332. Since the gray-toned resist pattern 332 presents a regular array of features overlying the corresponding features 312, the implantation pattern within the stress compensation layer 320 will reflect a similar pattern. Therefore, the implantation damage and stress release pattern in the substrate 300 is customized to mimic the original OPD pattern, and thus the substrate is locally planarized within each feature 312. Note that... Figures 6A to 6E The methods outlined herein facilitate simpler and faster implantation processes, which can effectively reduce complex OPD patterns in the substrate.

[0063] like Figure 6E As further shown, in some embodiments, the grayscale resist pattern 332 can vary depending on its position on the grayscale mask substrate 300. For example, according to the pattern of the chip region 302, the final pattern of the grayscale resist pattern 332 can be divided into four different groups based on position, such as region 332A, region 332B, region 332C, and region 332D. Regarding the exact pattern of the resist features, these four different regions can vary between each other to address local differences in pattern or OPD amount between different regions 302A to 302D on the substrate 300.

[0064] For example, Figure 6EAn embodiment is also shown in which a strip-shaped processing beam having the width of substrate 300 can be scanned along the Y direction to expose the entire substrate 300 to the processing species (e.g., ions). Note that in some embodiments, the processing beam may be an ion beam 340 that remains stationary relative to the Y direction while the substrate 300 is scanned along the Y direction. In some variations, the ion beam 340 may be a scan spot beam that scans rapidly along the X direction at a frequency of about 1 kHz or greater to produce a strip-shaped beam, as shown, while the scanning of the substrate 300 is performed at a relatively slow rate (e.g., a few centimeters per second for a 30 cm wafer). In some instances, the substrate 300 may be scanned back and forth along the Y direction. After the scanning of the substrate and / or after the scanning of the substrate 300 by the ion beam 340, ions from the ion beam 340 are selectively implanted into the substrate according to the pattern of the grayscale resist pattern 332 (including any variations between regions 332A, 332B, 332C, and 332D). This implantation can selectively alter the stress within the stress compensation layer 320 by selectively implanting ions into different regions of the stress compensation layer 320, as defined by the characteristics of the grayscale resistive pattern. Therefore, when exposed to the ion beam 340, these chip regions receiving the ion beam may have reduced OPD. Thus, selective and precise modification of the original OPD pattern of the substrate 300 can be accomplished in a simple ion exposure process. In one example, Figure 6A The OPD on substrate 300 can be removed at both the global and chip levels of substrate 300, resulting in a smooth, featureless OPD pattern after resist removal, such as... Figure 6G As shown in the image.

[0065] In further embodiments of this disclosure, scan-selective ion implantation can be employed in conjunction with the aforementioned grayscale resist mask to control substrate stress and OPD. As an example, instead of imparting a uniform ion dose across the substrate, a non-uniform scanning, such as a strip ion beam plasma beam, can be performed relative to the substrate to additionally vary the effective ion dose imparted to the substrate. As an example, non-uniform scanning may refer to a situation where the scanning speed of the substrate relative to the ion beam varies depending on the beam position on the substrate. This non-uniform scanning of the substrate relative to the ion beam can be combined with a variable thickness pattern of the grayscale resist to impart a more complex implantation damage pattern to the stress compensation layer located beneath the grayscale resist layer. In some instances, where the ion beam can be guided to the substrate along the Z-axis, the substrate can additionally rotate about the Z-axis between scans, can tilt between scans, can tilt and rotate between scans, etc. In embodiments where the ion beam is provided as a scanning spot beam scanning along the X-direction at a frequency on the order of 1 kHz or greater, the scanning speed of the scanning spot beam can be varied according to the position along the X-direction and the substrate scanning along the Y-direction to impart a non-uniform ion dose that varies according to the position in the XY plane. The embodiments are not limited to this context.

[0066] In these later embodiments, the ion implanter for implanting the substrate can receive a set of substrate information (including OPD information of the substrate before processing) to determine an appropriate processing procedure to impart a suitable implantation pattern to reduce or eliminate OPD. In addition to OPD information, the substrate information may also include a grayscale resist pattern to be applied to the substrate. The substrate information can then be used to determine ion beam processing parameters, which are customized to reduce OPD based on the specific OPD pattern and the designed grayscale resist pattern. Such processing parameters may include non-uniform beam scanning conditions, including variations in the scanning speed of the scanning beam, variations in the scanning speed of the scanned substrate, substrate rotation, substrate tilt, etc. An example of a non-uniform implantation pattern that can be used with the scanning ion beam is beam scanning pattern 350, also in… Figure 6F As shown in the figure, the beam dose can increase toward the center of the substrate 300.

[0067] return Figures 6A to 6FIn other embodiments, the grayscale resist pattern 332 can be formed by having regions 332A, 332B, 332C, and 332D all exhibit the same pattern. Conversely, to address localized variations in OPD between regions 302A and 302D, a non-uniform beam scanning operation can be performed, in which the processing beam (e.g., an ion beam) is scanned differently relative to the substrate 300 according to different regions 332A to 332D. Therefore, the beam scanning can direct a smaller ion dose towards region 332D, opposite to region 332A, and so on. Thus, when exposed to the ion beam 340, when scanning non-uniformly over the grayscale resist pattern 332 (when the grayscale resist pattern varies between regions 332A and 332D), these chip regions used to receive the ion beam may have reduced OPD, such as... Figure 6G As shown in the diagram. Therefore, selective and precise modification of the original OPD pattern of the substrate 300 can be completed in a patterned ion exposure process. In one example, it can be removed Figure 6A The OPD of the substrate 300 in the middle, and then after the resist is removed, a smooth, featureless OPD pattern is produced, such as Figure 6G As shown in the image.

[0068] In other embodiments, to reduce OPD both overall and locally across substrate 300, the grayscale resist pattern 332 can be arranged such that the patterning between different regions 332A to 332D is different, and a non-uniform beam scanning process can be performed on the grayscale resist pattern 332. More generally, according to various embodiments of the present disclosure, a non-uniform beam scanning process can be applied to the substrate, which solves the problem of repetitive, non-uniform chip-level photoresist patterning applied over a stress compensation layer.

[0069] To further illustrate the operations related to the non-uniform implantation procedure used to treat the stress compensation layer (SCL) in conjunction with a patterned gray-toned resist layer, Figure 1BFurther details of controller 50 are shown. In this embodiment, controller 50 may include processor 52, such as a microprocessor, dedicated processor chip, general-purpose processor chip, or similar device of known types. Controller 50 may also include memory or memory unit 54 coupled to processor 52, wherein memory unit 54 contains a scan implantation routine 56. As described above, scan implantation routine 56 may operate on processor 52 to manage the implantation process using ion beam 18 and substrate 100, thereby imparting an implantation pattern to the stress compensation layer. Memory unit 54 may include an article of manufacture. In one embodiment, memory unit 54 may include any non-transitory computer-readable or machine-readable medium, such as optical storage, magnetic storage, or semiconductor storage. Storage media may store various types of computer-executable instructions to implement one or more logical flows set forth herein. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. Instances of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and similar code. Examples are not limited to this context.

[0070] In some embodiments, as discussed above, for a given wafer or set of wafers, memory cell 54 may receive and / or store OPD information related to the substrate / stress compensation layer. Examples of OPD information may be wafer surface patterns determined by individual wafers, or characteristics of a batch of wafers. In some embodiments, the memory cell may store information related to a grayscale resist pattern to be applied to a wafer or set of wafers. This information may be expressed using any suitable format (including databases, tables, etc.) and may include pre-stored grayscale resist patterns and pre-stored OPD patterns. This information can then be used by scan implantation routine 56 to calculate the optimal set of parameters to be used in the ion implantation process to manage the OPD in the implanted wafer. This ion implantation process will involve implanting an ion beam pattern, rather than a uniform ion beam, into the substrate, where, for example, a uniform ion beam can impart a uniform ion dose and uniform ion energy across the substrate.

[0071] As an example, this information can be used to calculate the residual dose pattern of ions of a given energy and species for implantation into a stress-compensating layer, where the residual dose pattern effectively eliminates OPD. In this way, the residual dose pattern can be determined by applying an ion beam pattern to the resist pattern of the implanted gray photosensitive resist layer.

[0072] While the foregoing embodiments focus on using a patterned resist layer combined with ion implantation to selectively pattern the stress compensation layer, thereby reducing substrate OPD, in other embodiments, the patterned resist layer can be used as an etching mask to facilitate selective etching of the stress compensation layer, such as... Figure 3H As shown in the figure. Furthermore, selective etching can be performed using inert ion beams, reactive ion beams, radical beams, etc. In some embodiments, such selective etching can be performed at the chip level, for example, on... Figures 6A to 6G As shown in the figure. In some instances, selective etching can be achieved by combining a scanning beam with a patterned stress compensation layer (including adjusting the beam scan according to the position of a given chip region on the substrate).

[0073] Figure 7 An exemplary process flow is illustrated. At block 702, a wafer pattern is received. The wafer pattern may correspond to a surface map used to represent an OPD pattern across a substrate. The wafer pattern may correspond to an OPD on an existing substrate under a particular processing example.

[0074] At block 704, a stress relief pattern is calculated based on the wafer image to apply the stress relief pattern to the substrate. The stress relief pattern can be determined as an equivalent pattern for OPD modification and can be further used to determine an ion implantation pattern, which will be implanted into the stress compensation layer to achieve OPD modification. This ion implantation pattern can take into account ion species, ion energy, ion dose, the composition of the stress compensation layer, and other characteristics. Specifically, the stress relief pattern will generate an ion dose map to be applied to the stress compensation layer, which varies depending on its location on the substrate.

[0075] At block 706, a stress compensation layer is provided on the main surface of the substrate. Note that this operation can be performed after, before, or simultaneously with the operation at block 704.

[0076] At block 708, a resist layer is provided on the stress compensation layer. In some embodiments, the resist layer may be a gray-toned resist layer. In other embodiments, the resist layer may be a binary resist or other known resists.

[0077] At block 710, the resist layer is patterned according to a stress-relief pattern to form a patterned resist layer. This patterning can be performed using a grayscale mask to form a pattern of one or more areas, each area having a varying resist thickness across the surface of the substrate. These areas are designed to selectively deliver more or less ion dose to the stress-compensation layer depending on their location on the main surface of the substrate. In some instances, patterning can be performed according to a digital pattern in which a series of resist lines are characterized by line pitch, wherein variable linewidths are used to create areas with varying overall resist opacity. In other instances, an imprint mask with the desired pattern can be used to pattern the resist layer.

[0078] At block 712, blanket exposure of the substrate's main surface is performed, wherein blanket exposure guides implanted species to the substrate's main surface with the patterned resist layer in place. For example, blanket exposure can be performed by scanning the substrate relative to an inert ion beam or a reactive ion beam (e.g., a ribbon ion beam). In some embodiments, blanket exposure may allow the implantation of species such as energetic ions, which are selectively implanted into regions of the stress-compensating layer where the resist layer is thin or has zero thickness.

[0079] At block 714, the resist layer is removed from the substrate after blanket implantation.

[0080] Figure 8 Another exemplary process flow 800 is shown. At block 802, a wafer pattern is received. The wafer pattern may correspond to a surface map used to represent an OPD pattern across a substrate. The wafer pattern may correspond to an OPD on an existing substrate under a particular processing example.

[0081] At block 804, a stress relief pattern is calculated based on the wafer image to apply the stress relief pattern to the substrate. The stress relief pattern can be determined as an equivalent pattern for OPD modification and can be further used to determine an ion implantation pattern, which will be implanted into the stress compensation layer to achieve OPD modification. This ion implantation pattern can take into account ion species, ion energy, ion dose, the composition of the stress compensation layer, and other characteristics. Specifically, the stress relief pattern will generate an ion dose map to be applied to the stress compensation layer, which varies depending on its location on the substrate.

[0082] At block 806, a stress compensation layer is provided on the main surface of the substrate. Note that this operation can be performed after, before, or simultaneously with the operation at block 804.

[0083] At block 808, a resist layer is provided on the stress compensation layer. In some embodiments, the resist layer may be a gray-toned resist layer. In other embodiments, the resist layer may be a binary resist or other known resists.

[0084] At block 810, the resist layer is patterned according to a stress relief pattern to form a patterned resist layer. This patterning can be performed to form a pattern of one or more regions having varying resist thicknesses across the surface of the substrate. These regions are designed to selectively deliver more or less ion dose to the stress compensation layer based on their location on the main surface of the substrate. In some instances, patterning can be performed according to a digital pattern in which a series of resist lines are characterized by line pitch, wherein variable linewidths are used to create regions with varying overall resist opacity.

[0085] At block 812, exposure of the etched species is performed, wherein the etched species are guided to the main surface of the substrate with the patterned grayscale resist layer in place. For example, the etching of the species can be performed by scanning the substrate relative to an ion beam or a radical beam (e.g., a ribbon beam). In other embodiments, the etching of the species can be provided by exposure to ions and / or radicals in plasma (including in a plasma immersion chamber). In some embodiments, blanket exposure allows for selective etching of areas of the stress-compensating layer where a small or zero-thickness photoresist layer exists.

[0086] At block 814, the resist layer is removed from the substrate after blanket implantation.

[0087] Figure 9 Another exemplary process flow 900 is shown. At block 902, a wafer pattern is received. The wafer pattern may correspond to a surface map used to represent an OPD pattern across a substrate. The wafer pattern may correspond to an OPD on an existing substrate under a particular processing example.

[0088] At block 904, a stress relief pattern is calculated based on the wafer image to apply the stress relief pattern to the substrate. The stress relief pattern can be determined as an equivalent pattern for OPD modification and can be further used to determine an ion implantation pattern, which will be implanted into the stress compensation layer to achieve OPD modification. This ion implantation pattern can take into account ion species, ion energy, ion dose, the composition of the stress compensation layer, and other characteristics. Specifically, the stress relief pattern will generate an ion dose map to be applied to the stress compensation layer, which varies depending on its location on the substrate.

[0089] At block 906, a stress compensation layer is provided on the main surface of the substrate. Note that this operation can be performed after, before, or simultaneously with the operation at block 804.

[0090] At block 908, a resist layer is provided on the stress compensation layer. In some embodiments, the resist layer may be a gray-toned resist layer. In other embodiments, the resist layer may be a binary resist or other known resists.

[0091] At block 910, the resist layer is patterned according to a stress relief pattern to form a patterned resist layer. This patterning can be performed to form a pattern of one or more regions having varying resist thicknesses across the surface of the substrate. These regions are designed to selectively deliver more or less ion dose to the stress compensation layer based on their location on the main surface of the substrate. In some instances, patterning can be performed according to a digital pattern in which a series of resist lines are characterized by line pitch, wherein variable linewidths are used to create regions with varying overall resist opacity.

[0092] At block 912, patterned exposure of the processed species on the main surface is performed by scanning the processing beam in a non-uniform manner relative to the substrate. In one embodiment, the processing beam may be scanned relative to a stationary substrate, while in another embodiment, the substrate may be scanned relative to a stationary processing beam. In yet another embodiment, both the processing beam and the substrate may be scanned. The processed species may be an inert ion beam or a reactive ion beam, which is used to selectively vary the ion dose of the implanted species according to its position on the main surface. Alternatively, the processed species may be a reactive ion beam or a radical beam, which is used to selectively vary the flux of an ion etched species or a radical etched species according to its position on the main surface of the substrate. Patterned exposure is performed simultaneously with the patterned resist being in place. In this way, the combination of patterned exposure and the patterned resist layer can produce a targeted implanted pattern or etched pattern in a stress-compensating layer located beneath the patterned resist layer.

[0093] At block 914, the resist layer is removed from the substrate after patterning exposure.

[0094] This disclosure provides several advantages. As a first advantage, the relatively simple ion implantation process can reduce the two-dimensional OPD pattern on the substrate by means of a patterned grayscale resist layer or a digitally patterned resist layer. As another advantage, since the fine-scale pattern of ions implanted into the substrate can be defined by a pattern formed in the grayscale resist layer or the digitally patterned resist layer, localized OPD variations can be controlled relatively more precisely, rather than controlling the ion beam to write the implantation pattern into the wafer. In other words, the resist layer can be patterned to produce varying ion doses in a stress compensation layer at least down to the micrometer scale above the substrate surface. This type of dose variation control on the substrate surface may not be achievable by scanning an ion beam with a size on the centimeter scale. As yet another advantage, complex patterns of OPD (e.g., chip-scale OPD patterns) can be managed by creating a pattern in the resist layer that matches the OPD pattern and using blanket exposure or patterned exposure to the processed species (e.g., exposure to a scanning ion beam or a scanning radical beam).

[0095] The scope of this disclosure is not limited to the specific embodiments set forth herein. In fact, various other embodiments and modifications of this disclosure will be apparent to those skilled in the art from the foregoing description and drawings, in addition to what is set forth herein. Therefore, such other embodiments and modifications are intended to fall within the scope of this disclosure. Furthermore, this disclosure has been set forth herein in the context of specific implementations in specific environments for specific purposes; however, those skilled in the art will recognize that its usefulness is not limited thereto, and that this disclosure can be advantageously practiced in any number of environments for any number of purposes. Therefore, the claims set forth below are to be interpreted in accordance with the full scope and spirit of this disclosure set forth herein.

Claims

1. A method for stress management in a substrate, comprising: A stress compensation stack is formed on the main surface of the substrate, wherein the stress compensation stack includes a patterned resist layer and a stress compensation layer disposed beneath the patterned resist layer, the patterned resist layer being determined based on a surface pattern of the main surface of the substrate; and The processed species are directed to the stress compensation stack, wherein the stress compensation layer is selectively modified according to its location on the substrate.

2. The method according to claim 1, wherein the patterned resist layer comprises: A gray photosensitive resist layer having a resist pattern, the resist pattern being characterized by a variable resist layer thickness that varies depending on its position on the main surface of the substrate.

3. The method of claim 2, wherein the processed species is provided in an ion implantation procedure comprising exposing the substrate to an ion beam providing a uniform ion dose and uniform ion energy across the substrate, wherein at least a portion of the uniform ion dose is selectively blocked by the resist pattern.

4. The method of claim 3, wherein the ion implantation procedure includes scanning the ion beam relative to the substrate, wherein an ion beam pattern is implanted into the substrate, the ion beam pattern including a varying ion dose that varies according to the position on the substrate.

5. The method of claim 4, wherein a residual dose pattern is implanted into the stress compensation layer, the residual dose pattern being determined by applying the ion beam pattern to the resist pattern of the gray photoresist layer.

6. The method of claim 1, wherein the patterned resist layer has a variable thickness, the variable thickness being determined based on a three-dimensional surface map of the main surface of the substrate.

7. The method according to claim 2, wherein the gray photoresist layer is formed by the following steps: A blanket-type photoresist layer is deposited on the stress compensation layer; The blanket-covered photoresist layer is exposed to illumination guided by a gray-toned mask constructed according to the photoresist pattern; and The blanket-coated photoresist layer is developed after the exposure.

8. The method according to claim 2, wherein the gray photoresist layer is formed by the following steps: A blanket-coated photoresist layer is deposited on the stress compensation layer; and The blanket-type photoresist layer is embossed using an embossing mask constructed based on the resist pattern.

9. The method of claim 1, wherein the processing species is provided by exposing the substrate to a uniform dose etch species across the substrate, wherein at least a portion of the uniform dose etch species is selectively blocked from etching the stress compensation layer by the patterned resist layer.

10. The method of claim 1, wherein the patterned resist layer is a digitally patterned resist layer.

11. An ion implantation device, comprising: An ion source, used to generate an ion beam; A beamline assembly for changing the scanning of the ion beam; as well as Controller, the controller includes: processor; as well as A memory unit, coupled to the processor, includes a scanning implantation routine that operates on the processor to control the ion implanter. Surface view of the receiving substrate; and An implantation pattern is applied to the stress compensation layer on the substrate by performing scanning implantation based on the surface map.

12. The ion implanter of claim 11, wherein the substrate further comprises a gray-toned resist disposed on the stress compensation layer, wherein the scanning implantation routine is further operated to calculate the implantation pattern based on the resist pattern in the gray-toned resist.

13. The ion implanter of claim 12, wherein the resist pattern in the gray-toned resist is determined by the surface pattern of the substrate.

14. The ion implantation device according to claim 11, wherein the resist pattern is a digital resist pattern.

15. The ion implantation device according to claim 11, wherein the surface pattern includes patterns of chip-level variations in out-of-plane distortion and wafer-level variations in out-of-plane distortion.

16. A controller for an ion implantation machine, comprising: processor; as well as A memory unit, coupled to the processor, includes a scanning implantation routine that operates on the processor to control an ion implantation machine. Surface view of the receiving substrate; and An implantation pattern is applied to the stress compensation layer on the substrate by performing scanning implantation based on the surface map.

17. The controller of claim 16, wherein the substrate further comprises a grayscale resist disposed on the stress compensation layer, wherein the scanning implantation routine is further operated to calculate the implantation pattern based on the resist pattern in the grayscale resist.

18. The controller of claim 16, wherein the resist pattern in the gray-toned resist is determined by the surface pattern of the substrate.

19. The controller of claim 17, wherein the resist pattern is a digital resist pattern.

20. The ion implantation device according to claim 16, wherein the surface pattern includes patterns of chip-level variations in out-of-plane distortion and wafer-level variations in out-of-plane distortion.

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