Method of manufacturing engineered growth substrates for high quality group iii nitride semiconductors by thermal self-splitting process

Abstract

Embodiments of the present invention provide a method of manufacturing an engineered growth substrate for high-quality Group III nitride semiconductor through a thermal self-splitting process, including: a seed substrate preparation step of preparing a seed substrate to grow an epitaxial layer for forming a predetermined device; a seed substrate reforming step of irradiating a stealth laser to the seed substrate to form a reforming layer inside the seed substrate; a wafer bonding step of wafer bonding the seed substrate with a support substrate as a medium of a predetermined wafer bonding layer; a thermal self-splitting step of each of the seed substrate on both sides of the reforming layer having a quantitative difference or structural asymmetry including thermal properties of a thermal expansion coefficient, thereby being separated without an external force by thermal stress or mechanical stress formed at the reforming layer; and a planarization step of planarizing two faces of a seed region formed by separating the seed substrate with the reforming layer as a boundary from the seed substrate, which face each other.

Description

Technical Field

[0001] This invention (Disclosure) relates to a method for manufacturing engineered growth substrates for high-quality group III nitride semiconductors using a thermal self-splitting process. This method not only improves and stabilizes the physical properties of devices manufactured using engineered growth substrates, but also significantly improves economic efficiency by reducing seed substrate losses and defect rates in the manufacturing process. Background Technology

[0002] Existing substrates for growing Group III nitride semiconductors use single-material substrates.

[0003] Existing single-material growth substrates cannot simultaneously meet the quality and cost requirements of crystal defect density, surface polarity, device structure stack thickness, and heat dissipation performance.

[0004] To address this issue, engineered growth substrates with composite laminate structures have been introduced as improved growth substrates for the growth of group III nitride semiconductors.

[0005] However, such engineered growth substrates with composite material stacked structures must ensure the implementation of two core manufacturing technologies.

[0006] That is, wafer slicing technology, which obtains the seed region, which is part of the growth substrate, from the growth substrate at a thin substrate size, and wafer bonding technology, which combines the seed region with the support substrate in a manner with high bonding uniformity.

[0007] As a wafer slicing technology, methods using physical cutting techniques such as wire saws, as well as methods using ion implantation or lasers, have been introduced.

[0008] However, these methods have drawbacks such as being time-consuming or causing the seed crystal region to break due to separation forces during the slicing process.

[0009] Wafer bonding technology has the following problems: In the wafer bonding process, it is very difficult to achieve uniform bonding characteristics in a crack-free manner over the entire area opposite the supporting substrate.

[0010] In summary, there is currently no optimized manufacturing process described for engineered growth substrates with composite material stacks used for group III nitride semiconductor growth to meet their structural-functional and industrial characteristics. This has become an obstacle to the rising price of high-quality group III nitride semiconductors and the development of related industrial technologies. Summary of the Invention

[0011] Technical issues The present invention (Disclosure) aims to provide a method for manufacturing engineered growth substrates for high-quality group III nitride semiconductors via a thermal self-splitting process, which can improve the characteristics and economy of the manufactured devices.

[0012] Technical solution Embodiments of the present invention provide a method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors using a thermal self-splitting process, comprising: a seed substrate preparation step, preparing a seed substrate for growing an epitaxial layer for forming a predetermined device; a seed substrate modification step, irradiating the seed substrate with a stealth laser to form a modification layer inside the seed substrate; a wafer bonding step, wafer bonding the seed substrate and a support substrate using a predetermined wafer bonding layer as a medium; a thermal self-splitting step, wherein the seed substrates on both sides centered on the modification layer each have a quantitative difference or structural asymmetry in thermal properties including thermal expansion coefficient, thereby separating without external force due to thermal or mechanical stress formed in the modification layer; and a planarization step, planarizing two facing surfaces of the seed region formed by separating from the seed substrate with the seed substrate and the modification layer as boundaries.

[0013] An embodiment of the present invention provides that the thermal self-splitting step is performed during the cooling process of the heat supplied in the wafer bonding step, whereby the seed substrates on both sides centered on the modified layer each have a quantitative difference in thermal properties including thermal expansion coefficient or a structural asymmetry including thickness difference, thereby separating without external force.

[0014] An embodiment of the present invention provides that the seed crystal substrate is 4H-SiC material.

[0015] An embodiment of the present invention provides that: either the upper surface or the lower surface of the seed crystal substrate, and the bonding surface that is opposite to the supporting substrate and is bonded to the wafer bonding layer as a medium, is a C-polar face crystal surface, and the exposed surface of the seed crystal region is a Si-polar face crystal surface.

[0016] Embodiments of the present invention may further include: a bonding layer forming step, between the seed substrate modification step and the wafer bonding step, wherein the wafer bonding layer is formed on the surface of the supporting substrate and the bonding surface of the seed substrate respectively; a bonding layer surface polishing step, wherein surface polishing is performed to reduce the surface roughness of the wafer bonding layer provided in the bonding layer forming step; and a bonding layer surface treatment step, wherein a predetermined surface treatment is performed to improve the surface energy of the wafer bonding layer provided in the bonding layer surface polishing step.

[0017] Embodiments of the present invention may further include: after the seed substrate modification step, a splitting heat treatment step, wherein the seed substrate and the support substrate after wafer bonding are heated to a predetermined splitting heating temperature and then cooled to a splitting cooling temperature.

[0018] In embodiments of the present invention, the splitting heating temperature may be higher than the temperature at which the wafer bonding step is performed.

[0019] Embodiments of the present invention provide a method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors using a thermal self-splitting process, comprising: a seed substrate preparation step, preparing a seed substrate for growing an epitaxial layer for forming a predetermined device; a seed substrate modification step, irradiating the seed substrate with a stealth laser to form a reforming layer inside the seed substrate; a temporary substrate bonding step, bonding the seed substrate and a temporary substrate using a predetermined bonding layer as a medium before or after the seed substrate modification step; and a thermal self-splitting step, wherein the seed substrates on both sides centered on the reforming layer, each having a thermal expansion coefficient (TEC), undergo thermal expansion. The separation occurs without external force due to quantitative differences in the thermal properties of the coefficient or structural asymmetry including thickness differences; a planarization step, which planarizes the two facing surfaces of the seed region formed by separating it from the seed substrate with the seed substrate and the modified layer as the boundary; a wafer bonding step, which wafer bonds the seed region to the support substrate with a predetermined wafer bonding layer as the medium; and a temporary substrate removal step, which removes the temporary substrate to separate the seed region.

[0020] An embodiment of the present invention provides that the thermal self-splitting step is performed during the cooling process of the heat supplied in the temporary substrate bonding step, whereby the seed substrates on both sides centered on the modified layer each have a quantitative difference in thermal properties including thermal expansion coefficient or a structural asymmetry including thickness difference, thereby separating without external force.

[0021] In embodiments of the present invention, the temporary substrate and the supporting substrate may have similar or identical thermal characteristics, including the effective thermal expansion coefficient and the effective thermal conductivity.

[0022] Invention Effects According to the present invention, by utilizing wafer bonding process and thermal self-splitting technology, a thin seed region can be easily separated from the seed substrate and the formed seed region has excellent physical properties, thereby enabling the manufacture of an engineered growth substrate that can form a predetermined device with guaranteed performance and economy. Attached Figure Description

[0023] Figures 1 to 6 This is a figure illustrating one embodiment of a method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors using a thermal self-splitting process according to the present invention.

[0024] Figures 7 to 13 This is a figure illustrating another embodiment of the method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors by means of a thermal self-splitting process according to the present invention. Detailed Implementation

[0025] Hereinafter, embodiments of the method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors by means of a thermal self-splitting process according to the present invention will be described in detail with reference to the accompanying drawings.

[0026] However, the implementable forms of the intrinsic technical concept of the present invention are not limited to the embodiments described below, and it is expressly indicated that they cover the scope proposed by those skilled in the art based on the intrinsic technical concept of the present invention by substituting or modifying the embodiments described below.

[0027] Furthermore, the terminology used below is chosen for ease of explanation and should not be limited to dictionary meanings in grasping the essential technical concept of the present invention, but should be properly interpreted in accordance with the meaning of the technical concept of the present invention.

[0028] Figures 1 to 6 This is a figure illustrating one embodiment of a method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors using a thermal self-splitting process according to the present invention.

[0029] Reference Figures 1 to 6 The method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors by thermal self-splitting process according to this embodiment includes a seed substrate preparation step (S100), a seed substrate modification step (S200), a wafer bonding step (S300), a thermal self-splitting step (S400), a planarization step (S500), and a growth substrate preparation step (S600).

[0030] Seed substrate preparation step (100): Prepare a seed substrate (100) for growing an epitaxial layer (EpiLayer) for forming a predetermined device.

[0031] The intended device can be any of a variety of group III nitride semiconductor devices, namely GaN HEMT, AlN BAW Filter, AlN Resonating Sensors, and microLED.

[0032] In the seed substrate modification step (S200), a stealth laser (L) is irradiated onto the seed substrate (100) to form a reforming layer (110) inside the seed substrate (100).

[0033] The stealth laser (L) is a laser of wavelength that can pass through the seed substrate (100). It is an optical system configured to form a focal point at a specific location inside the seed substrate (100) using a separate optical system.

[0034] If the focal point of the photons of the stealth laser (L) is moved along a specific plane to form a scanning plane, a modified layer (110) is formed along the scanning plane.

[0035] Since the seed crystal region is obtained with a thin substrate size, the modified layer (110) is formed as a surface parallel to the upper surface of the seed crystal substrate (100).

[0036] In the wafer bonding step (S300), the seed substrate (100) and the support substrate (220) are bonded together using a predetermined wafer bonding layer (210) as the medium.

[0037] The wafer bonding layer (210) can be made of SiO2, SiN x , SOG (Spin-on-Glass), SiO2, SiN x The material is composed of SOG (Spin-on-Glass), AlN, and Al2O3 dielectric ceramic bonding materials. Preferably, it is performed by a permanent bonding process in which the surfaces of the seed substrate (100) and the support substrate (220) and the bonding layer (210) are irreversibly and permanently bonded.

[0038] This is because the bonding characteristics can be maintained as is, even if high-temperature heating processes are performed in subsequent processes, thus enabling the application of a wide range of process conditions in the epitaxial device-package process.

[0039] The wafer bonding step (S300) is preferably performed at a bonding temperature of 250°C or higher.

[0040] In addition, the wafer bonding layer (210) can be pre-bonded at room temperature after surface treatment of the seed substrate (100) and the support substrate (220) by plasma or solution.

[0041] As a heat treatment step to strengthen the bonding force after the pre-bonding process, the temperature is preferably up to 1,200°C.

[0042] In addition, the wafer bonding step (S300) may also include a step of removing OH and H2 bubble gas components from the dielectric ceramic bonding (bonding) material.

[0043] The supporting substrate (220) is composed of Si, SiC, AlN ceramic and SiC ceramic materials.

[0044] In the thermal self-splitting step (S400), the seed substrates (100) on both sides of the modified layer (110) are centered on the modified layer (110). Figure 3The seed crystal region (120) on the upper side of the modified layer (110) and the seed crystal substrate (100a) on the lower side of the modified layer (110) excluding the seed crystal region (120) each have quantitative differences in thermal properties including thermal expansion coefficient or structural asymmetry including thickness difference, thereby generating thermal stress or mechanical stress on the modified layer (110), thereby separating the seed crystal substrate (100a) on the lower side of the modified layer (110) excluding the seed crystal region (120) without external mechanical force.

[0045] Thermal or mechanical stress is generated during the cooling process of the heat supplied for the bonding temperature in the wafer bonding step.

[0046] Quantitative differences in thermal properties, including thermal expansion coefficient, or structural asymmetries, including thickness differences, arise on both sides of the modified layer (110).

[0047] Specifically, the seed crystal region (120) on the upper side of the modified layer (110) is in a state where a wafer bonding layer (210) is bonded to its upper side and a support substrate (220) is bonded to its upper side. Conversely, the lower side of the modified layer (110) is in a state where the thickness of the seed crystal substrate (100) before the formation of the modified layer (110) is reduced to the thickness of the seed crystal region (120).

[0048] On both sides of the modified layer (110), due to the thickness, the structure of the permanent bonding of different materials, and the physical properties of the different materials bonded, the effective thermal expansion coefficient and effective thermal conductivity of the seed crystal region (120) and the seed crystal substrate (100a) bounded by the modified layer (110) are different.

[0049] This is the factor that causes the seed crystal region (120) and the seed crystal substrate (100a) to have different degrees of thermal expansion, which results in mechanical stress on the modified layer (110) between the seed crystal region (120) and the seed crystal substrate (100a).

[0050] Therefore, it acts as a factor that allows the seed crystal region (120) and the seed crystal substrate (100a) to "separate without external force" with the modified layer (110) as the center.

[0051] The planarization step (S500) planarizes the two surfaces facing each other: the seed crystal region (120) formed by separating from the seed crystal substrate (100) with the modified layer (110) as the boundary, and the seed crystal substrate (100a).

[0052] Thus, an engineered growth substrate (200) is manufactured, comprising a support substrate (220), a seed region (120) on the upper side of the support substrate (220), and a wafer bonding layer (210) between the seed region (120) and the support substrate (220) (S600).

[0053] Furthermore, after the planarization step (S500) is performed, the seed crystal region (120) is separated, and the remaining seed crystal substrate (100a) can be repeatedly manufactured into an engineered growth substrate (200) by repeating all the aforementioned steps (S100~S500). This ensures the economic efficiency of the seed crystal substrate.

[0054] Furthermore, since the seed region (120) is supported by the wafer bonded to the support substrate (220), the physical properties of the device can be improved and stabilized in subsequent epitaxial growth and device manufacturing processes. In addition, the ease of wafer and device processing can be maximized.

[0055] In this embodiment, since the seed substrate (100) and the support substrate (220) are wafer-bonded in a thick film form, stable bonding characteristics can be ensured; the seed region (120) is already stably bonded to the support substrate (220) before being separated from the seed substrate (100), thus having the advantage that the thin seed region (120) is very easy to handle.

[0056] Moreover, since the seed region (120) is completely separated from the seed substrate (100) while firmly bonded to the support substrate (220), not only is breakage during separation not to mention the probability of defects such as microcracks that are very difficult to inspect and detect, but also becomes very low.

[0057] Therefore, this embodiment, as a technology for stabilizing engineered growth substrates with composite laminate structures, can ensure thin and wide seed areas (120) without damage under a structure that is firmly bonded to a thick support substrate (220). Thus, it can provide stable and excellent workability in subsequent processes, including planarization and device manufacturing processes, and even has the advantage of ensuring high yield.

[0058] In addition, as a technique to ensure the seed crystal region (120), the technique of using ion implantation can be cited as an example.

[0059] Ion implantation technology is based on the technique of accelerating hydrogen ions so that they can penetrate the surface of a target substrate and be buried at a specific depth.

[0060] Therefore, ion implantation technology suffers from significant damage to the seed substrate film along the path of the implanted hydrogen ions. That is, the surface and interior of the seed substrate along the hydrogen ion path inevitably suffer from hydrogen ion-induced damage (implant damage), and to recover from this damage, a separate high-temperature heat treatment (Annealing) process is required. This not only increases manufacturing costs but also lengthens the lead time due to the added process.

[0061] Furthermore, the depth to which hydrogen ions penetrate varies depending on the energy applied and the energy lost due to collisions at the surface. Therefore, there is a problem of seed crystal regions where it is difficult to ensure uniform quality.

[0062] In this embodiment, the seed substrate (100) is preferably 4H-SiC.

[0063] The 4H-SiC structure with hexagonal-Wurtzite is most suitable as a seed for the epitaxial growth of group III nitrides (GaN, AlGaN, AlN, AlGaInN).

[0064] Compared to 4H-SiC and 6H-SiC, 3C-SiC, with its cubic structure, has a smaller band gap energy (Eg), and its lattice constant is significantly larger than that of group III nitrides, making it unsuitable as a seed substrate for group III nitride growth. Furthermore, due to its low thermal conductivity, 3C-SiC is particularly unsuitable for power semiconductor devices.

[0065] In addition, ion implantation technology has the problem that it is not easy to form 4H-SiC as a seed substrate (100) or a seed region (120).

[0066] Ion implantation technology accelerates any ionized atoms and directs them toward the substrate, in this case, the surface of a SiC substrate, and uses the kinetic energy generated by the acceleration to make them penetrate to a specific depth from the surface of the SiC substrate.

[0067] At this point, severe implant damage occurs in the SiC substrate corresponding to the depth to which the ion atoms penetrate from the surface where they are projected. To recover this damage, a high-temperature heat treatment process is necessary.

[0068] However, in cases like SiC, which have multiple crystalline structures, high-temperature heat treatment processes cannot rule out the possibility of producing a side effect known as polytype conversion.

[0069] That is, after applying an ion implantation process to the seed crystal substrate (100) of 4H-SiC, a seed crystal region (120) is formed. After that, the remaining seed crystal substrate (100) must be heat-treated, and a part of the seed crystal substrate (100) may be transformed from a 4H crystal structure to a 3C crystal structure.

[0070] In particular, the seed substrate (100) with implantation damage caused by ion implantation has a higher probability of polymorphic transformation compared to the 4H-SiC substrate without implantation damage.

[0071] To eliminate the possibility of polymorphic transformation, implantation damage must be minimized, and a meticulous comparison must be made between the heat treatment temperature used to recover the damage and the polymorphic transformation temperature. Therefore, the increased process difficulty is obvious.

[0072] In contrast, in this embodiment, during the formation of the modified layer (110) on the seed substrate (100), since no damage occurs at any location on the seed substrate (100) other than the modified layer (110), there is no need to worry about the separate annuling process for polytype conversion.

[0073] The fact that it does not produce damage such as implant damage also provides the advantage that multiple seed regions (120) separated from a seed substrate (100) can maintain the same properties.

[0074] In addition, in this embodiment, more preferably, the bonding surface of the seed substrate (100) and the support substrate (220) being bonded to each other with the wafer bonding layer (210) as the medium is formed as a C-polar face crystal surface, and the exposed surface of the seed region (120) is formed as a Si-polar face crystal surface.

[0075] Thus, the surface of group III nitrides (GaN, AlGaN, AlN, AlGaInN) grown based on the seed crystal region (120) can be made into a Ga (or Al) polar face, i.e. a metal-polarity surface.

[0076] The surfaces of group III nitrides (GaN, AlGaN, AlN, AlGaInN) ending with Ga (or Al) polar faces are thermally stable, and in particular, they have significantly lower reactivity with hydroxide ion-interacting groups compared to nitrogen (N) polar crystal faces, and are therefore chemically stable as well.

[0077] In addition, in this embodiment, between the seed substrate modification step (S200) and the wafer bonding step (S300), there may be a bonding layer formation step (S210), a bonding layer surface polishing step (S220), and a bonding layer surface treatment step (S230).

[0078] In the bonding layer formation step (S210), a wafer bonding layer (210) is formed on the surface of the support substrate (220) and the bonding surface of the seed substrate (100).

[0079] The bonding layer surface polishing step (S220) involves mechanical polishing or chemical mechanical polishing to reduce the surface roughness of the wafer bonding layer (210) provided in the bonding layer formation step (S210).

[0080] The bonding layer surface treatment step (S230) performs a predetermined surface treatment to improve the surface energy of the wafer bonding layer (210) provided in the bonding layer surface polishing step (S220).

[0081] The surface energy, which is proportional to the number of dangling bonds, can vary depending on the crystalline faces exposed on the surface. That is, the surface energy can be maximized through appropriate grinding of the surface and predetermined surface treatments that expose specific crystalline faces.

[0082] Therefore, the wafer bonding layer (210) that has undergone bonding layer formation step (S210), bonding layer surface grinding step (S220) and bonding layer surface treatment step (S230) has an increased surface energy, which further enhances the bonding force between the wafer bonding layers (210) formed on the surface of the support substrate (220) and the bonding surface of the seed substrate (100).

[0083] In addition, in order to improve the bonding force between wafer bonding layers by increasing surface energy as described above, the bonding surface treatment step (S230) may be further subjected to an additional surface heat treatment process, in which case the surface heat treatment process is preferably 250°C or higher.

[0084] Surface treatment can be performed using plasma or solution and can be carried out at room temperature or above.

[0085] In addition, bonding strength can be improved by performing a pre-bonding process at room temperature (room temperature ~ 25°C) after surface treatment.

[0086] In addition, this embodiment may include a splitting heat treatment step after the seed crystal substrate modification step (S200).

[0087] The splitting heat treatment step involves heating the seed substrate (100) and the support substrate (220) after wafer bonding to a predetermined splitting heating temperature, and then cooling them to the splitting cooling temperature.

[0088] In this embodiment, the wafer bonding step (S300) is necessarily performed while maintaining a predetermined bonding temperature. Therefore, the heat energy required for "separation without external force" is supplied at the bonding temperature maintained in the wafer bonding step (S300).

[0089] Separation without external force occurs during the cooling process at the self-bonding temperature.

[0090] The splitting heat treatment step is to address the possibility that the bonding temperature may not apply enough energy to separate the seed substrate (100) from the seed region (120) without external force.

[0091] After the wafer bonding step (S300) is performed, in order to ensure the smooth progress of the thermal self-splitting step, a splitting heat treatment step can be further performed to reheat and cool the bonded seed substrate (100) and support substrate (220).

[0092] The splitting heating temperature is preferably higher than the temperature at which the wafer bonding step (S300) is performed.

[0093] This is because the wafer bonding layer (210) is already in an irreversible reactive fusion bond with the support substrate (220) and the seed substrate (100), so it will not separate even if it is heated to above the bonding temperature.

[0094] Conversely, since the seed crystal region (120) does not separate in the thermal self-splitting step even after being heated to the bonding temperature in the wafer bonding step (S300), the splitting heating temperature is preferably set to be higher than the bonding temperature.

[0095] Figures 7 to 13 This is a figure illustrating another embodiment of the method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors by means of a thermal self-splitting process according to the present invention.

[0096] This embodiment includes a seed substrate preparation step (S1100), a seed substrate modification step (S1200), a temporary substrate bonding step (S1300), a thermal self-splitting step (S1400), a planarization step (S1500), a wafer bonding step (S1600), and a temporary substrate removal and growth substrate preparation step (S1700).

[0097] Seed substrate preparation step (S110): Prepare the seed substrate (1100) for growing the epitaxial layer used to form the device.

[0098] The device can be any of a variety of group III nitride semiconductor devices, namely GaN HEMT, AlN BAW Filter, AlN Resonating Sensors, and microLED.

[0099] In the seed substrate modification step (S1200), a stealth laser (L) is irradiated onto the seed substrate (1100) to form a modification layer (1110) inside the seed substrate.

[0100] After the seed substrate modification step (S1200) is performed, the temporary substrate bonding step (S1300) is performed by bonding the seed substrate (1100) and the temporary substrate (1300) with a predetermined bonding layer (1200) as the medium.

[0101] In the thermal self-splitting step (S1400), the seed substrates (1100a, 1120) on both sides of the modified layer (1110) separate without external force due to quantitative differences in thermal properties including thermal expansion coefficient or structural asymmetry including thickness difference.

[0102] The thermal self-splitting step (S1400) is a process in which the heat supplied in the temporary substrate bonding step (S1300) is cooled, and the separation occurs without external force due to the quantitative difference in thermal properties, including the thermal expansion coefficient, or the structural asymmetry, including the thickness difference, on both sides centered on the modified layer (1110).

[0103] The planarization step (S1500) planarizes the two facing surfaces of the seed crystal region (1120) formed by separating it from the seed crystal substrate (1100a) with the seed crystal substrate (1100a) and the modified layer (1110) as the boundary.

[0104] In the wafer bonding step (S1600), the seed crystal region (1120) and the support substrate (2100) located on the opposite side of the temporary substrate with the seed crystal region (1120) as a reference are bonded (joined) with the wafer bonding layer (1130) as a medium.

[0105] Finally, the temporary substrate (1300) is removed to separate the seed region (1120), and an engineered growth substrate (2000) (S1700) is manufactured, including a support substrate (2100), the seed region (1120) on the upper side of the support substrate (2100), and a wafer bonding layer (1130) between the seed region (1120) and the support substrate (2100).

[0106] In this embodiment, an engineered growth substrate (2000) is formed after performing two wafer bonding (bonding, adhesion, joining) processes.

[0107] The two-stage wafer bonding process is a process that uses a seed substrate (1100) with a surface formed as a Si-polar face to form an engineered growth substrate (2000) with the exposed surface of the seed region (1120) becoming a Si-polar face.

[0108] In this embodiment, the temporary substrate (1300) is preferably selected to have similar or identical thermal characteristics to the supporting substrate (2100), including the effective thermal expansion coefficient and the effective thermal conductivity.

[0109] Furthermore, both the temporary substrate (1300) and the support substrate (2100) preferably have a single crystal structure.

[0110] This aims to ensure normal and excellent bonding characteristics between the support substrate (2100) and the seed region (1120) in the wafer bonding step (S1600).

[0111] Reference Figure 11 During the wafer bonding step (S1600), the temporary substrate (1300) and the seed crystal region (1120) are already bonded together with a predetermined adhesive layer as the medium.

[0112] Therefore, among the factors affecting the substantial thermal properties including the thermal expansion rate of the seed crystal region (1120), the thermal properties caused by the properties of the temporary substrate (1300) are the dominant factor compared to the thermal properties caused by the properties of the seed crystal region (1120) itself.

[0113] That is, such as Figure 11 As confirmed, the wafer bonding step (S1600) of this embodiment can be analyzed as a bonding process of a structure and a support substrate (2100) that is thermally approximated as a temporary substrate (1300) and bonded to a seed crystal region (1120).

[0114] Typical wafer bonding processes are performed after heating the substrate and bonding layer to a predetermined temperature; this is one of the usual process conditions.

[0115] Therefore, if there is a large difference in the thermal properties between the temporary substrate (1300) and the support substrate (2100), the shrinkage characteristics of the interface between the support substrate (2100) and the seed crystal region (1120) will differ during the bonding process, and thus stable bonding (joining) characteristics cannot be expected.

[0116] In particular, the temporary substrate (1200) and the seed crystal region (1120) have a strong adhesive force with the predetermined bonding layer (1200) as the medium.

[0117] Furthermore, unlike the wafer bonding layer (1130), the predetermined bonding layer (1200) that strongly bonds the temporary substrate (1200) to the seed region (1120) is a reversible, temporary wafer bonding layer. Preferred materials for this bonding layer are organic polymers such as resin, epoxy, SU-8, and BCB, and metallic substances such as Sn, In, Zn, Ga, Au, Ni, Ag, and Cu, which can be easily removed and separated from the temporary substrate (1200) in subsequent processes (S1700). However, depending on the circumstances, SiO2 and SiN may also be used. x Dielectric ceramic materials such as SOG (Spin-on-Glass), AlN, Al2O3, ITO, GaN, InGaN, AlGaN, AlGaInN, ZnO, and ZITO can also be used.

[0118] However, the wafer bonding process between the support substrate (2100) and the seed region (1120) is affected by the use of SiO2 and SiN. x Using dielectric ceramic materials such as SOG (Spin-on-Glass), AlN, and Al2O3 as the medium for wafer bonding, it is preferable to have a smooth surface with a possible surface roughness of less than 1 nm before bonding. Maintaining the state of surface treatment such as plasma or solution to improve surface energy is one of the most important factors for obtaining excellent bonding properties.

Claims

1. A method for manufacturing engineered growth substrates for high-quality group III nitride semiconductors using a thermal self-splitting process, characterized in that, include: Seed substrate preparation step: Prepare a seed substrate for growing an epitaxial layer to form a predetermined device. The seed crystal substrate modification step involves irradiating the seed crystal substrate with a stealth laser to form a reforming layer inside the seed crystal substrate. In the wafer bonding step, the seed substrate and the support substrate are bonded together using a predetermined wafer bonding layer as a medium. In the thermal self-splitting step, the seed crystal substrates on both sides of the modified layer have quantitative differences or structural asymmetries in thermal properties, including thermal expansion coefficients, thereby separating without external force through thermal or mechanical stresses formed in the modified layer. as well as The planarization step involves planarizing the two facing surfaces of the seed crystal region formed by separating it from the seed crystal substrate, with the seed crystal substrate and the modified layer as the boundaries.

2. The method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors via a thermal self-splitting process according to claim 1, characterized in that, The thermal self-splitting step is a process in which the seed substrates on both sides of the modified layer separate without external force during the cooling process of the heat supplied in the wafer bonding step. This separation is due to quantitative differences in thermal properties, including thermal expansion coefficients, or structural asymmetry, including thickness differences.

3. The method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors via a thermal self-splitting process according to claim 1, characterized in that, The seed crystal substrate is made of 4H-SiC material.

4. The method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors via a thermal self-splitting process according to claim 1, characterized in that, The bonding surface of either the upper or lower surface of the seed substrate, which is opposite to the supporting substrate and is bonded to the wafer bonding layer as a medium, is the C-polar face crystal surface. The exposed surface of the seed crystal region is the crystallization surface of the Si-polar face.

5. The method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors via a thermal self-splitting process according to claim 1, characterized in that, Between the seed substrate modification step and the wafer bonding step, the following is also included: In the bonding layer formation step, the wafer bonding layer is formed on the surface of the support substrate and the bonding surface of the seed substrate, respectively. A bonding layer surface polishing step is performed to reduce the surface roughness of the wafer bonding layer provided in the bonding layer formation step. The bonding layer surface treatment step involves performing a predetermined surface treatment to improve the surface energy of the wafer bonding layer provided in the bonding layer surface polishing step.

6. The method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors via a thermal self-splitting process according to claim 1, characterized in that, After the seed substrate modification step is performed, the following steps are also included: The splitting heat treatment step involves heating the seed substrate and the support substrate after wafer bonding to a splitting heating temperature higher than the temperature at which the wafer bonding step is performed, and then cooling them to the splitting cooling temperature.

7. A method for manufacturing engineered growth substrates for high-quality group III nitride semiconductors via a thermal self-splitting process, characterized in that, include: Seed substrate preparation step: Prepare a seed substrate for growing an epitaxial layer to form a predetermined device. The seed crystal substrate modification step involves irradiating the seed crystal substrate with a stealth laser to form a reforming layer inside the seed crystal substrate. The temporary substrate bonding step involves bonding the seed crystal substrate and the temporary substrate together using a predetermined adhesive layer as a medium, either before or after the seed crystal substrate modification step. In the thermal self-splitting step, the seed crystal substrates on both sides of the modified layer separate without external force due to quantitative differences in thermal properties, including thermal expansion coefficient, or structural asymmetry, including thickness differences. The planarization step involves planarizing the two facing surfaces of the seed crystal region formed by separating it from the seed crystal substrate with the seed crystal substrate and the modified layer as the boundary. as well as In the wafer bonding step, the seed crystal region and the support substrate are bonded together using a predetermined wafer bonding layer as the medium. The temporary substrate removal step removes the temporary substrate to separate the seed crystal region.

8. The method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors via a thermal self-splitting process according to claim 7, characterized in that, The thermal self-splitting step is the separation of the seed substrates on both sides of the modified layer without external force during the cooling process of the heat supplied in the temporary substrate bonding step. This separation is due to quantitative differences in thermal properties, including thermal expansion coefficients, or structural asymmetry, including thickness differences.

9. The method for manufacturing an engineered growth substrate for high-quality group III nitride semiconductors via a thermal self-splitting process according to claim 7, characterized in that, The thermal characteristics of the temporary substrate and the supporting substrate, including the effective thermal expansion coefficient and the effective thermal conductivity, are similar or identical to each other.

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