A dual-drive PWM fault emergency multi-speed fan control circuit

Abstract

This invention discloses a dual-drive PWM fault emergency multi-speed fan control circuit, comprising: a power input and filtering module, used to provide stable operating power to each functional module and realize input-side electrical protection; a control unit module, used to receive signals from each sampling module and output corresponding control signals to each controlled module based on preset logic; a PWM signal detection module, used to collect the PWM speed regulation signal output by the ECU, and transmit it to the control unit module after preprocessing. The control unit module realizes normal speed regulation and fault status identification based on the collected PWM signal. Safety redundancy upgrade, continuous operation during faults: overcoming the defect of existing technology where PWM faults cause immediate shutdown, the fan end autonomously detects faults and triggers hardware-level emergency drive, core component heat dissipation is continuous and uninterrupted, avoiding overheating safety risks from the source, and emergency reliability is not affected by the ECU status.

Description

Technical Field

[0001] This invention relates to the field of automotive cooling fan control technology, specifically a dual-drive PWM fault emergency multi-speed fan control circuit. Background Technology

[0002] Current automotive three-phase brushless DC fan control technology is based on PWM speed regulation, with the mainstream being pure PWM square wave control (accounting for approximately 75%) and PWM+FOC vector control (accounting for approximately 20%). Both rely on the PWM signal output by the vehicle's ECU to achieve speed regulation, and electronic commutation is completed through Hall sensors or back EMF estimation. This technology is widely used in engine, motor, and battery cooling scenarios. However, existing technologies have the following key shortcomings, making it difficult to meet automotive-grade safety and mass production requirements.

[0003] 1. Prominent safety hazards due to PWM failure: When the PWM signal is short-circuited, disconnected, or the ECU output fails, the fan lacks autonomous emergency drive capability and stops directly, causing the core component to fail to dissipate heat, leading to overheating, shutdown, or even fire risk; the existing emergency solution relies on redundant control on the ECU side, and the emergency function is completely ineffective when the ECU fails.

[0004] 2. Redundancy and unreliability of emergency and switching solutions: Emergency solutions for the fan end often require additional NTC temperature sampling, multiple ADCs and complex algorithms, which increases hardware costs by more than 30% and increases the software failure rate; some solutions lack hardware mutual exclusion mechanisms between PWM drive and emergency drive, resulting in voltage backflow and mutual interference problems, which can easily burn out the drive chip; software control switching has the risk of delay and logic conflict, and motor jitter and commutation failure during switching.

[0005] 3. Insufficient protection mechanisms and automotive-grade compatibility: When hardware-level protection such as PWM fault detection and voltage reverse flow protection is generally lacking, and only software protection is relied upon, the probability of failure is high; high-frequency PWM drive causes EMI interference and local hotspot problems, making heat dissipation design difficult; redundant design increases the size of the circuit, making it unsuitable for the small space of the engine compartment, and most solutions require modification of the vehicle ECU program or addition of wiring harnesses, making it difficult to directly replace the existing fan drive.

[0006] 4. Imbalance between cost and reliability: Although the FOC solution has excellent performance, it is expensive and has a long development cycle; the pure square wave solution is inexpensive but lacks safety redundancy. Existing technologies cannot simultaneously meet automotive-grade safety requirements and mass production low-cost needs.

[0007] In summary, existing technologies cannot resolve the core contradictions of "uninterrupted operation during PWM faults, reliable hardware-level switching, extreme simplicity and no redundancy, low cost, and automotive-grade compatibility," necessitating a simple, safe, and reliable three-phase brushless DC fan control circuit. Therefore, a dual-drive PWM fault emergency multi-speed fan control circuit is proposed. Summary of the Invention

[0008] The purpose of this invention is to provide a dual-drive PWM fault emergency multi-speed fan control circuit to solve the problems mentioned in the background art.

[0009] To achieve the above objectives, the present invention provides the following technical solution: a dual-drive PWM fault emergency multi-speed fan control circuit, comprising:

[0010] The power input and filtering module is used to provide a stable operating power supply for each functional module and to realize electrical protection on the input side;

[0011] The control unit module is used to receive signals from each sampling module and output corresponding control signals to each controlled module based on preset logic.

[0012] The PWM signal detection module is used to acquire the PWM speed control signal output by the ECU, perform preprocessing, and then transmit it to the control unit module. The control unit module uses the acquired PWM signal to realize normal speed control and fault status identification.

[0013] The fixed voltage emergency drive module is used to receive emergency control commands from the control unit module and output multi-level fixed regulated emergency drive voltage to the mode switching module.

[0014] The mode switching module is used to receive mode switching instructions from the control unit module and realize hardware-level mutual exclusion switching between normal PWM drive and fault emergency drive.

[0015] The three-phase drive and current sampling module is used to receive the drive voltage output by the mode switching module, complete the electronic commutation drive of the fan motor, and collect the operating current signal to transmit to the control unit module to realize overcurrent protection.

[0016] The protection and alarm module is used to receive fault alarm commands and realize audible and visual indication and alarm of fault status.

[0017] Preferably, the mode switching module includes transistor Q2, diode D2, diode D16, MOSFET Q4, resistor R25, resistor R6, and resistor R26;

[0018] The collector of transistor Q2 is connected to the power input and the output of the filter module VBAT, the base is connected to the IO_MODE control terminal of the control unit module via resistor R25, and the emitter is connected to the anode of diode D2.

[0019] The cathode of diode D2 is connected to the V_DRIVE_IN node via resistor R26. The V_DRIVE_IN node is the output terminal of the mode switching module.

[0020] The drain of the MOSFET Q4 is connected to the V_DRIVE_IN node, the source is grounded, and the gate is connected to the IO_RETRY control terminal of the control unit module via resistor R6.

[0021] The anode of diode D16 is connected to the V_EMERGENCY node output by the fixed voltage emergency drive module, and the cathode is connected to the V_DRIVE_IN node.

[0022] Preferably, diode D2 and diode D16 form a unidirectional isolated mutually exclusive topology, which, together with the switching control of transistor Q2 and MOSFET Q4, achieves 100% electrical isolation between the PWM drive path and the emergency drive path;

[0023] The MOSFET Q4, along with resistors R6 and R26, constitutes a soft-start submodule. The control unit module outputs a PWM signal with a gradually changing duty cycle from 0 to 100% through the IO_RETRY terminal, controlling the conduction level of the MOSFET Q4 to gradually change, so that the voltage at the V_DRIVE_IN node smoothly transitions from the emergency fixed voltage to the normal PWM drive voltage, thus achieving a shockless soft start for mode switching.

[0024] Preferably, the fixed voltage emergency drive module includes at least two independent gear drive branches, and each gear drive branch includes an NPN transistor, a Zener diode, an isolation diode and a current limiting resistor;

[0025] In each branch, the collector of the NPN transistor is connected to the power input and the output of the filter module VBAT, the base is connected to the corresponding gear control terminal of the control unit module through the current limiting resistor, and the emitter is grounded through the Zener diode. At the same time, the emitter is connected to the anode of the isolation diode.

[0026] The cathodes of the isolation diodes of each branch are connected to the V_EMERGENCY node, forming a multi-level fixed voltage regulated output structure, and the control unit module controls only one level drive branch to be turned on at the same time.

[0027] Preferably, the fixed voltage emergency drive module includes three sets of gear drive branches: high speed, medium speed, and low speed.

[0028] The high-speed branch includes an NPN transistor Q1, a 12V Zener diode D1, an isolation diode D3, and a current-limiting resistor R1, outputting a fixed 12V voltage, corresponding to a fan speed ≥3600rpm.

[0029] The medium-speed branch includes an NPN transistor Q3, an 8V Zener diode D6, an isolation diode D14, and a current-limiting resistor R4, outputting a fixed 8V voltage, corresponding to a fan speed ≥2400rpm.

[0030] The low-speed branch includes an NPN transistor Q6, a 5V Zener diode D7, an isolation diode D15, and a current-limiting resistor R7, outputting a fixed 5V voltage, corresponding to a fan speed ≥1500rpm.

[0031] Preferably, the PWM signal detection module includes resistor R2, resistor R5, capacitor C3, diode D4, and resistor R27;

[0032] The PWM signal input terminal is connected to the voltage divider node via resistor R2. Resistor R5 and capacitor C3 are connected in parallel and then connected across the voltage divider node and ground. The anode of diode D4 is connected to the voltage divider node, and the cathode is connected to the ADC sampling terminal of the control unit module via resistor R27.

[0033] The resistors R2 and R5 form a voltage divider network, which divides the input 5V / 12V PWM signal to a sampling range of less than 3.3V. The capacitor C3 and resistor R27 form an RC low-pass filter circuit, which converts the PWM pulse signal into a DC average voltage with the corresponding duty cycle. The diode D4 enables unidirectional signal transmission and prevents backflow of voltage in the subsequent stage.

[0034] Preferably, the power input and filtering module includes power input terminals B+ and B-, diode ZD1, MOSFET Q5, gate control unit, π-type filter unit and energy storage capacitor E1;

[0035] The diode ZD1 is connected between B+ and B- for surge voltage clamping. The source of the MOSFET Q5 is connected to B-, the drain is connected to the subsequent ground circuit, and the gate is connected to the gate control unit composed of resistor R3, capacitor C4 and diode D5 to realize reverse power connection protection and overvoltage shutdown.

[0036] The π-type filter unit consists of an inductor L1 and capacitors C1 and C2, connected between B+ and the power supply terminal of the subsequent stage, and is used to conduct interference suppression. The energy storage capacitor E1 is connected in parallel between the power supply terminal and ground, and is used to stabilize the power supply voltage and cope with sudden changes in load current.

[0037] Preferably, the three-phase drive and current sampling module includes a pre-drive chip U2, a three-phase full-bridge MOS transistor array, a current sampling resistor R24, a Hall sensor interface U3, and a freewheeling diode group;

[0038] The enable terminal of the pre-drive chip U2 is connected to the IO_DRIVE_EN control terminal of the control unit module, the fault feedback terminal is connected to the IO_OVERCURRENT input terminal of the control unit module, the Hall signal input terminal is connected to the Hall sensor interface U3, and the six drive output terminals are respectively connected to the corresponding gates of the three-phase full-bridge MOS transistor array through the gate current limiting resistor.

[0039] The V_DRIVE_IN node output by the drain connection mode switching module of the upper bridge arm of the three-phase full-bridge MOS transistor array is connected to the U, V, and W phase windings of the three-phase brushless DC fan motor at the midpoint of the three-phase bridge arm respectively.

[0040] The current sampling resistor R24 ​​is connected in series between the source of the lower bridge arm of the three-phase full-bridge MOS transistor array and ground, and the sampling terminal is connected to the overcurrent detection terminal of the pre-driver chip U2.

[0041] Each diode in the freewheeling diode group is connected in reverse parallel between the drain and source of each MOS transistor in the three-phase full-bridge MOS transistor array to absorb the back electromotive force during turn-off.

[0042] Preferably, the protection and alarm module includes an indicator light LED1, a resistor R8, a buzzer BZ1, and a resistor R10;

[0043] The anode of the indicator LED1 is connected to the IO_LED control terminal of the control unit module via resistor R8, and the cathode is grounded. The signal input terminal of the buzzer BZ1 is connected to the IO_BUZZER control terminal of the control unit module via resistor R10, and the ground terminal is grounded.

[0044] When the control unit module experiences a PWM fault or an overcurrent fault, the drive indicator LED1 remains constantly lit and the buzzer BZ1 continuously sounds. After the fault is resolved, the drive indicator LED1 flashes after a delay, the volume of the buzzer BZ1 gradually decreases, and the alarm is turned off after 3 seconds.

[0045] Compared with the prior art, the beneficial effects of the present invention are:

[0046] 1. Enhanced safety redundancy, uninterrupted operation in case of failure: Overcoming the shortcomings of existing technology where PWM failures cause the fan to stop, the fan can autonomously detect faults and trigger hardware-level emergency drives, ensuring continuous and uninterrupted heat dissipation of core components, avoiding overheating safety risks from the source, and ensuring emergency reliability is not affected by the ECU status.

[0047] 2. Extremely simple hardware with no redundancy, resulting in significant cost advantages: No additional NTC temperature measurement, complex algorithms, or redundant ECU design are required. The drive mode switching is achieved through a simple structure of PNP tube and dual diodes, reducing hardware costs by more than 30% and significantly lowering the failure rate, making it fully compatible with mass production requirements.

[0048] 3. Stable switching and anti-interference, automotive-grade reliability: Adopting hardware-level mutual exclusion and unidirectional isolation design, it completely eliminates voltage backflow and signal interference, with zero switching delay and no motor jitter; it integrates multiple hardware protections such as PWM fault detection, overcurrent, and freewheeling, and has strong anti-EMI capabilities.

[0049] 4. Seamlessly adapts to existing architecture and has strong mass production compatibility: It can directly replace the existing fan drive circuit without modifying the vehicle ECU program, adding wiring harnesses or interfaces; the circuit is small in size and fits the narrow space of the engine compartment, without the need to adjust the vehicle installation layout, and has high mass production adaptation efficiency.

[0050] 5. Balanced performance and cost, with outstanding practicality: It retains the low-cost advantage of pure PWM square wave control while making up for its lack of safety redundancy; it can achieve seamless connection between normal PWM speed regulation and emergency fault response without the complex design of FOC scheme, taking into account performance, safety and cost. Attached Figure Description

[0051] Figure 1 This is a system architecture diagram of the present invention;

[0052] Figure 2 This is a circuit diagram of the mode switching module of the present invention;

[0053] Figure 3 This is a circuit diagram of the fixed voltage emergency drive module of the present invention;

[0054] Figure 4 This is a circuit diagram of the PWM signal detection module of the present invention;

[0055] Figure 5 This is a circuit diagram of the power input and filtering module of the present invention;

[0056] Figure 6 This is a circuit diagram of the pre-drive chip in the three-phase drive and current sampling module of the present invention;

[0057] Figure 7 This is a circuit diagram of the Hall sensor interface in the three-phase drive and current sampling module of the present invention;

[0058] Figure 8 This is a circuit diagram of the driving and current sampling in the three-phase driving and current sampling module of the present invention;

[0059] Figure 9 This is a circuit diagram of the protection and alarm module of the present invention. Detailed Implementation

[0060] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0061] Please see Figure 1-9 The present invention provides a technical solution: a dual-drive PWM fault emergency multi-speed fan control circuit, including a power input and filtering module, a PWM signal detection module, a control unit module, a fixed voltage emergency drive module, a mode switching module, a three-phase drive and current sampling module, and a protection and alarm module.

[0062] I. Power Input and Filtering Module

[0063] 1. Core hardware components: power input terminals B+ / B-, TVS diode ZD1 (SM5S30CA), reverse connection protection NMOS transistor Q5 (DMTH41M2SPSQ), current limiting voltage divider resistor R3 (10K), filter capacitor C4 (10nF), Zener diode D5 (LMBZ5245BLT1G) for protecting MOSVGS, π-type filter unit (inductor L1 (1uH) + capacitors C1 and C2 (100uF)), large-capacity aluminum electrolytic capacitor E1 (1200uF).

[0064] 2. Connection Relationship: The positive power input (B+) is connected to the upper end of transient voltage suppressor diode ZD1, the upper end of current-limiting resistor R3, and the left end of inductor L1. The negative power input (B-, ground) is connected to the lower end of ZD1, the source of MOSFET Q5, and the ground (GND) reference point of the entire circuit. The bidirectional transient voltage suppressor diode ZD1 is connected across B+ and B- to clamp surge voltage and protect subsequent circuits. Resistor R3 is connected in series between B+ and the gate control circuit of Q5, serving as a current limiter and voltage divider. The N-channel MOSFET Q5 (as a power switch / reverse connection protection) has its source connected to B- and its drain connected to the subsequent ground circuit. Its gate is driven by the control network composed of R3, C4, and D5. Capacitor C4 is connected in parallel between the gate of Q5 and ground to filter gate noise, delay switching action, and prevent false triggering. Zener diode D5 is connected in reverse parallel between the gate of Q5 and ground to clamp the gate voltage and prevent overvoltage from damaging the MOSFET gate oxide layer.

[0065] 3. Core Functions

[0066] 3.1 Input Protection: Surge / overvoltage of the B+ input is clamped by ZD1. At the same time, the gate control circuit composed of R3, C4, and D5 drives Q5 to turn off under abnormal voltage, cutting off the ground loop and realizing power supply protection.

[0067] 3.2 Filtering and Energy Storage: During normal operation, L1, C1, and C2 form an LC low-pass filter to suppress conducted interference, and E1 acts as a large-capacity energy storage capacitor to stabilize the VBAT voltage and cope with sudden changes in load current.

[0068] II. PWM Signal Detection Module

[0069] 1. Core hardware components: PWM input terminal PWM_IN, resistors R2 (20K), R5 (10K), R27 (1K), capacitor C3, diode D4 (BAS316).

[0070] 2. Connection Relationship: PWM_IN serves as the PWM signal input terminal. After being connected in series with current-limiting resistor R2, it forms a voltage divider network with voltage divider resistor R5. Resistor R2 is connected in series between PWM_IN and the voltage divider node to limit current and prevent signal overload. The lower end of resistor R5 is grounded (GND), forming a voltage divider circuit with R2 to adjust the high-level amplitude of the input PWM signal to the acceptable voltage range of the subsequent ADC. Capacitor C3 is connected in parallel across R5 (i.e., between the voltage divider node and ground), forming an RC low-pass filter circuit with R27 to smooth the PWM pulse signal into a DC average voltage, realizing the conversion of duty cycle to voltage. Diode D4's anode is connected to the voltage divider filter node, and its cathode output is to the ADC_PWM port. Its function is unidirectional conduction, preventing interference from the subsequent ADC circuit's charging and discharging of the front-end filter capacitor, while also isolating reverse voltage. The analog voltage output terminal of ADC_PWM after voltage division, filtering, and diode isolation is connected to the MCU's ADC pin to detect the PWM signal's duty cycle. GND serves as the reference ground for the entire module, providing a potential reference for R5 and C3.

[0071] 3. Core Functions

[0072] 3.1 Voltage divider adaptation: R2 / R5 divides the 5V / 12V PWM signal output by the ECU to the 3.3V range that the control unit U1 can sample.

[0073] 3.2 Anti-interference filtering: The RC filter circuit C3 and R27 filter out high-frequency noise in the PWM signal to ensure detection accuracy.

[0074] 3.3 Unidirectional isolation: D4 prevents signals from the control unit side from flowing back to the ECU, while also enabling unidirectional transmission of PWM signals.

[0075] 3.4 Fault Detection and Recovery Identification: U1 identifies faults by sampling the amplitude (0V / power supply voltage when short-circuited, no fluctuation when disconnected) and frequency (deviation from 10Hz to 1kHz is abnormal) of the ADC_PWM signal. When the signal recovers to the normal range and is stable for ≥50ms, it is determined to be PWM recovery and the IO_RETRY signal is triggered.

[0076] III. Control Unit Module

[0077] 1. Core hardware components: The main chip control unit U1 (DSPIC33CK64MC105-H / PT) mainly includes power supply (VDD), ground (GND), ADC sampling terminal, and GPIO output terminal.

[0078] 2. Connection relationship:

[0079] VDD (pin 1): Connects to VLR_3.3V output from the pre-driver chip U2 to provide 3.3V core power to the MCU.

[0080] ADC1 / ADC_PWM (Pin 2): Cathode D4 of the PWM signal detection module. Receives the analog voltage output from the PWM detection module for measuring the PWM duty cycle.

[0081] GPIO1 / IO_MODE (pin 5): Connects to the current-limiting resistor R25 before the base of the mode switching module Q2.

[0082] GPIO2 / O_HIGH (pin 6): Connects to the current-limiting resistor R1 before the base of the fixed voltage emergency drive module Q1.

[0083] GPIO3 / O_MID (pin 7): Connects to the current-limiting resistor R4 before the base of the fixed voltage emergency drive module Q3.

[0084] GPIO4 / O_LOW (pin 8): Connects to the current-limiting resistor R7 before the base of the fixed voltage emergency drive module Q6.

[0085] GPIO5 / AI_TEMP_check (pin 9): Acquires the temperature signal of the AI ​​module for over-temperature protection monitoring.

[0086] GPIO6 / AI_PWO_check (pin 10): Connects to the voltage after the voltage divider resistor R11 is filtered by C5 to confirm whether the power supply is normal.

[0087] GPIO7 / IO_DRIVE_EN (pin 11): Connects to the EN enable pin (pin 2) of the pre-driver chip U2.

[0088] GPIO8 / IO_OVERCURRENT (pin 12): Connects to the FAULT fault feedback terminal (pin 4) of the pre-driver chip U2.

[0089] GPIO9 / IO_LED (pin 13): Connects to the LED1 current-limiting resistor R8 of the protection and alarm module.

[0090] GPIO10 / IO_BUZZER (pin 14): Connects to the buzzer current-limiting resistor R10 of the protection and alarm module.

[0091] GPIO11 / IO_RETRY (pin 15): Connects to the gate of the soft-start switch Q4 of the mode switching module (via current-limiting resistor R6).

[0092] 3. Core Functions

[0093] 3.1 Signal Judgment: Complete the identification of normal / fault status of PWM within 10ms, with a response delay of ≤20ms, and a stability detection of ≥50ms after PWM recovery to avoid false triggering.

[0094] 3.2 Mode Control: The output IO_MODE signal switches the drive mode, and the hardware-level logic eliminates the risk of software crashes.

[0095] 3.3 Emergency Gear Control: In case of PWM failure, select one of the outputs IO_LOW / IO_MID / IO_HIGH to select the low / medium / high emergency gear.

[0096] 3.4 Soft start control: After PWM recovers, the IO_RETRY signal is output (PWM duty cycle gradually changes from 0 to 100%, and the change time is 100 to 300ms), which controls Q4 to turn on slowly to achieve smooth switching.

[0097] 3.5 Protection Response: Upon receiving an overcurrent feedback signal, the protection action is triggered within 5ms.

[0098] 3.6 Alarm Control: When a fault occurs, a high level is output to drive the audible and visual alarm (LED flashing frequency 2Hz, buzzer sounding frequency 1Hz). After PWM is restored, the alarm signal is turned off after a 3-second delay.

[0099] IV. Fixed Voltage Emergency Drive Module

[0100] 1. Core hardware components: NPN transistors Q1 / Q3 / Q6 (S-LMBT5551LT1G), Zener diodes D1 (LMBZ5242BLT1G), D6 (LMBZ5237BLT1G), D7 (LMBZ5231BLT1G), isolation diodes D3, D14 and D15 (BAS316), and current-limiting resistors R1, R4 and R7 (1K).

[0101] 2. Connection Relationship: Transistors (Q1 / Q3 / Q6): NPN type, collector connected to VBAT, base connected to the MCU control pin via a 1kΩ current-limiting resistor (R1 / R4 / R7), emitter connected to the corresponding Zener diode. Zener diodes (D1 / D6 / D7) are connected in reverse series between the emitter of the transistor and ground to clamp the output voltage and achieve a fixed voltage output.

[0102] 3. Core Functions

[0103] 3.1 Voltage regulation: D1 outputs 12V (high-speed emergency, fan speed ≥3600rpm), D6 outputs 8V (medium-speed emergency, fan speed ≥2400rpm), D7 outputs 5V (low-speed emergency, fan speed ≥1500rpm), to meet different heat dissipation needs.

[0104] 3.2 Switching Control: Q1 / Q3 / Q6 are controlled by U1, with only one gear conducting at a time to avoid gear conflict. After PWM recovery, U1 synchronously shuts down Q1 / Q3 / Q6 to ensure that emergency drive and normal drive do not overlap.

[0105] 3.3 Isolation bus: D3 / D14 / D15 prevents mutual interference between the three voltage levels. After busing, V_EMERGENCY ripple is ≤100mV, ensuring stable operation of the motor.

[0106] V. Mode Switching Module

[0107] 1. Core hardware components: PNP transistor Q2 (S-LMBT5401LT1G), first unidirectional conduction diode D2 (BAS316), second unidirectional conduction diode D16 (BAS316), soft-start switch N-channel MOSFET Q4 (DMTH41M2SPSQ), current limiting resistors R6 and R25 (1K), R26 (10Ω).

[0108] 2. Connection Relationship: The collector of Q2 is connected to VBAT, the base is connected to IO_MODE via R25, and the emitter is connected to D2. The anode of D2 is connected to the emitter of Q2, and the cathode is connected to R26. The upper end of R26 is connected to the cathode of D2, and the lower end is connected to the V_DRIVE_IN node. The drain of Q4 is connected to the V_DRIVE_IN node, the source is connected to GND, and the gate is connected to IO_RETRY via R6. The anode of D16 is connected to V_EMERGENCY, and the cathode is connected to V_DRIVE_IN. R25 / R6 are connected in series between the base of IO_MODE / Q2 and the gate of IO_RETRY / Q4, respectively.

[0109] 3. Core Functions

[0110] 3.1 PWM Normal Mode (Steady State): U1 outputs IO_MODE = low level, turning on Q2 and D2. IO_RETRY outputs high level (100% duty cycle), turning on Q4 fully. Because V_PWM_DRIVE (average PWM voltage) > V_EMERGENCY, D16 is cut off. At this time, V_DRIVE_IN = PWM drive voltage, achieving stepless speed regulation.

[0111] 3.2 PWM Fault Mode: When U1 outputs IO_MODE high, Q2 is cut off, and D2 is cut off due to lack of forward voltage. IO_RETRY outputs low, cutting off Q4. V_EMERGENCY is forward-biased through D16, enabling V_DRIVE_IN to be an emergency fixed voltage, achieving fault emergency drive (switching time ≤ 1ms, no motor jitter).

[0112] 3.3 PWM Recovery Soft-Start Mode: When U1 detects PWM recovery and it stabilizes for ≥50ms, IO_MODE switches to low level, turning on Q2 and D2. Simultaneously, IO_RETRY outputs a gradual PWM signal (0~100%, 100~300ms) to gradually change the gate voltage of Q4, causing the drain-source current to increase slowly. V_DRIVE_IN smoothly transitions from the emergency voltage to the PWM drive voltage. During this period, D16 naturally turns off as V_PWM_DRIVE gradually exceeds V_EMERGENCY, achieving a shockless switching.

[0113] 3.4 Anti-backflow and mutual exclusion: The unidirectional conduction characteristics of D2 / D16 and the switching control of Q4 ensure three-way electrical isolation (100% mutual exclusion) during PWM drive, emergency drive and soft start, completely eliminating voltage backflow and signal interference, and preventing the driver chip from burning out.

[0114] VI. Three-phase drive and current sampling module

[0115] 1. Core hardware components: pre-driver chip U2 (AMT49105KEVTR-J), three-phase upper bridge arm NMOS transistors Q7~Q9 (DMTH41M2SPSQ), three-phase lower bridge arm MOS transistors Q10~Q12 (DMTH41M2SPSQ), gate current limiting resistors R12~R14, R18~R20 (10Ω), current sampling resistor R24 ​​(0.5mΩ / 2W), freewheeling diodes D8~D13 (BAS316), Hall sensor interface U3 (MLX90217).

[0116] 2. Connection relationship

[0117] Power input: V_DRIVE_IN is connected to the drain of MOSFETs Q7 to Q9.

[0118] Commutation drive: UH / VH / WH of U2 are connected to R12 to R14 respectively, and then to the gates of Q7 to Q9. UL / VL / WL of U2 are connected to R15 to R17, and then to the gates of Q10 to Q12.

[0119] Motor connection: Connect the source of Q7 and the drain of Q10 to the U phase. Connect the source of Q8 and the drain of Q11 to the V phase. Connect the source of Q9 and the drain of Q12 to the W phase.

[0120] Overcurrent detection: The sources of Q10 to Q12 are connected to the upper end of R24, and the lower end of R24 is connected to GND. The upper end of R24 is connected to the S_N of U2. The FAULT of U2 is connected to the IO_OVERCURRENT of U1.

[0121] Hall effect interface: Connect H1 / H2 / H3 of U3 to the Hall effect input terminal of U2. Connect VCC of U3 to VLR_3.3V of U2. Connect GND of J3 to system ground. Freewheeling protection: D8~D13 are connected in reverse parallel between the drain and source of Q7~Q12.

[0122] 3. Core Functions

[0123] Electronic commutation: U2 controls the MOSFETs to conduct alternately based on Hall signals (H1 / H2 / H3), with a commutation frequency of 10Hz to 1kHz, adapting to fan speeds of 500 to 3500 rpm. During soft start, the commutation frequency is smoothly adjusted with the voltage to avoid torque pulsation.

[0124] Power amplification: Maximum output drive current ≥10A, meeting the power requirements of 12V / 24V automotive-grade fans.

[0125] Overcurrent protection: When the motor experiences overcurrent (≥15A), R24 generates a voltage drop, U2 outputs a FAULT signal, and U1 triggers the protection, with a response time ≤5ms. During soft start, the overcurrent threshold is temporarily relaxed to 20A to avoid false protection.

[0126] Freewheeling protection: D8~D13 absorbs the back electromotive force of the MOSFET (peak value ≤60V), protecting power devices and extending circuit life.

[0127] VII. Protection and Alarm Module

[0128] 1. Core hardware components: fault indicator LED1 (red: LSL296), current limiting resistor R8 (220Ω), active buzzer BZ1 (TMB12A05), current limiting resistor R10 (1K).

[0129] 2. Connection relationship: U1's IO_LED is connected to the anode of LED1 via R8, and the cathode of LED1 is connected to GND. U1's IO_BUZZER is connected to the IN signal terminal of BZ1 via R9, and the ground terminal of BZ1 is connected to GND.

[0130] 3. Core Functions

[0131] 3.1 Fault Indication: LED1 remains constantly lit when there is a PWM fault or overcurrent. After PWM recovery, LED1 will flash (frequency 5Hz) and then turn off after 3 seconds.

[0132] 3.2 Audible and visual alarm: BZ1 will continuously sound an alarm (sound pressure ≥ 85dB) when a fault occurs. After PWM is restored, the buzzer will gradually decrease in volume (from 85dB to 0dB within 3 seconds) to indicate that the fault has been resolved.

[0133] Working principle:

[0134] 1. System power-on initialization phase (0-50ms)

[0135] An external 12V DC power supply VIN is connected via B+ / B-. After voltage division by the current-limiting resistor R3, the body diode of NMOS transistor Q5 can form a path. When the voltage VGS between the gate and source of Q5 is greater than its conduction threshold VGS(th), Q5 starts to conduct. The input voltage VIN is filtered by L1, C1, and C2 to output a stable VBAT (12V). E1 acts as a large-capacity energy storage capacitor to stabilize the VBAT voltage and cope with sudden changes in load current. VBAT is stably output at 3.3V via the LDO inside the pre-driver chip U2, powering U1 and the Hall sensor U3.

[0136] After power-on, U1 initializes all GPIO pins: IO_MODE = high level (PNPQ2 off), IO_LOW / IO_MID / IO_HIGH = low level (emergency drive off), IO_RETRY = low level (NMOSQ4 off), IO_DRIVE_EN = low level (U2 disabled), IO_LED / IO_BUZZER = low level (alarm off). U1 starts ADC sampling and begins detecting the ADC_PWM signal (output of the PWM detection module).

[0137] 2. Implementation of normal PWM speed control mode (steady state)

[0138] The vehicle ECU outputs a PWM signal (e.g., 50% duty cycle, 500Hz), which is connected to the PWM detection module via the PWM_IN port. After voltage division by R2 (20kΩ) and R5 (10kΩ), the signal amplitude drops from 5V to 1.67V (adapting to U1's 3.3V sampling range). R27 (1kΩ) and C3 (0.1μF) form an RC filter circuit (time constant 0.1ms) to filter out high-frequency noise. D4 conducts unidirectionally, outputting a stable ADC_PWM signal to the ADC sampling terminal of U1. U1 samples the ADC_PWM signal.

[0139] Judgment conditions: Amplitude 1.67V (meets 50% duty cycle), frequency 500Hz (within the range of 10Hz to 1kHz), continuous detection for 10ms without abnormality, PWM is judged to be normal.

[0140] U1 outputs control signals: IO_MODE = low level (via a 1kΩ current-limiting resistor) pulls the base of Q2 low, turning on the PNP transistor Q2 (emitter VBAT = 12V, collector output 12V). IO_RETRY = high level (100% duty cycle) energizes the gate of Q4, turning on the NMOS transistor Q4 (drain connected to the cathode of D2 via R26, source connected to V_DRIVE_IN). IO_DRIVE_EN = high level enables U2, starting the reception of Hall signals.

[0141] The mode switching module operates as follows: Q2 conducts, energizing the anode of D2 (12V). D2 conducts, causing the voltage to be output to V_DRIVE_IN via R26 (10Ω) and Q4. At this time, V_PWM_DRIVE (average PWM voltage = 12V × 50% = 6V) > V_EMERGENCY (0V, emergency drive off), D16 is reverse cut off, and there is no voltage backflow.

[0142] The three-phase bridge drive module operates as follows: Hall sensor U3 outputs position signals H1, H2, and H3 (e.g., H1=high, H2=low, H3=high). U2 outputs drive signals UH=high, UL=low, VH=low, VL=high, WH=high, and WL=low based on these signals. After current limiting by gate resistors R12-R14 and R18-R20, the drive signals control Q7 (on), Q10 (off), Q8 (off), Q11 (on), Q9 (on), and Q12 (off). The three-phase current flows in through phase U, out through phase V, and in through phase W, causing the motor to operate at a speed corresponding to a 50% duty cycle (1500 rpm).

[0143] Continuous monitoring: U1 samples the ADC_PWM signal every 10ms and monitors the overcurrent signal through IO_OVERCURRENT. If no abnormality is found, this mode is maintained.

[0144] 3. Implementation of PWM fault emergency mode (fault triggering)

[0145] Fault Simulation: The PWM signal line is disconnected, the ADC_PWM signal amplitude becomes 0V and remains unchanged for 10ms. U1 determines a PWM fault and immediately outputs control signals: IO_MODE=high level pulls the base of Q2 high, turning off the PNP transistor Q2 (no output at the collector, D2 is off). IO_RETRY=low level de-energizes the gate of Q4, turning off Q4 (PWM drive path disconnected). IO_LOW=high level (selects low-speed emergency, can be preset by the program or configured by an external pin) energizes the base of Q6, turning on Q6. IO_DRIVE_EN=high level is maintained (U2 remains enabled). IO_LED=high level and IO_BUZZER=high level keep LED1 constantly lit and BZ1 constantly beeping (sound pressure 85dB).

[0146] Fixed voltage emergency drive module operation: Q6 conducts, causing VBAT (12V) to flow through D7 (5V Zener diode), and D7 clamps the output to 5V. The 5V voltage is then fed into the V_EMERGENCY node via D15 (isolation), outputting a stable 5V emergency voltage.

[0147] Mode switching module operation: D2 is off, V_EMERGENCY (5V) is forward-biased through D16 to output to V_DRIVE_IN (power input of the three-phase drive module). At this time, V_EMERGENCY (5V) > V_PWM_DRIVE (0V), D16 is unidirectionally turned on, and there is no risk of backflow.

[0148] Emergency motor operation: U2 continues to receive Hall signals and runs continuously at the speed (1500rpm) corresponding to the emergency voltage of 5V to ensure heat dissipation of core components.

[0149] Fault recovery monitoring: U1 samples the ADC_PWM signal every 10ms and waits for PWM to recover.

[0150] 4. PWM recovery soft-start mode implementation (fault recovery)

[0151] Fault Recovery: The PWM signal line is reconnected, and the ADC_PWM signal recovers to a 50% duty cycle, 500Hz, and remains stable for 50ms. U1 determines PWM recovery and initiates the soft-boot process:

[0152] Step 1 (0ms): IO_LOW = low level turns off Q6, disconnecting the emergency drive path (V_EMERGENCY becomes 0V).

[0153] Step 2 (0-200ms): IO_MODE = low level → Q2 turns on (D2 turns on), and simultaneously IO_RETRY outputs a gradual PWM signal: 0ms: duty cycle 0% (Q4 off). 50ms: duty cycle 25% (Q4 partially on, V_DRIVE_IN = 1.5V). 100ms: duty cycle 50% (Q4 half-on, V_DRIVE_IN = 3V). 150ms: duty cycle 75% (Q4 mostly on, V_DRIVE_IN = 4.5V). 200ms: duty cycle 100% (Q4 fully on, V_DRIVE_IN = 6V).

[0154] Step 3 (0-3000ms): IO_LED = high level (blinking, frequency 5Hz), IO_BUZZER = high level (volume gradually changes from 85dB to 0dB).

[0155] Mode switching and motor transition: During soft start, V_DRIVE_IN smoothly rises from 0V to 5V (average PWM voltage), and D16 naturally cuts off as V_DRIVE_IN gradually exceeds V_EMERGENCY (0V). U2 adjusts the commutation frequency according to the Hall signal, and the motor speed smoothly transitions from 1500rpm (emergency) to 1500rpm (normal PWM) without jitter or shock.

[0156] Soft start ends (200ms): IO_RETRY maintains a 100% duty cycle, and the system fully resumes normal PWM speed control mode.

[0157] Alarm off (3000ms): IO_LED = low level (off), IO_BUZZER = low level (mute).

[0158] 5. Overcurrent protection mode implementation (overload trigger)

[0159] Overload simulation: The motor stalls, and the three-phase bridge output current suddenly increases to 20A. Overcurrent detection: Current flows into R24 (0.01Ω) through the sources of Q10~Q12, resulting in a voltage drop across R24 = 20A × 0.01Ω = 0.2V. U2 detects that the voltage drop across R24 is ≥0.1V (overcurrent threshold) and immediately outputs a FAULT signal (high level) to U1's IO_OVERCURRENT. U1 receives the FAULT signal and outputs protection signals within 5ms: IO_DRIVE_EN = low level de-energizes U2, stopping the output drive signal. IO_LOW / IO_HIGH / IO_HIGH = low level cuts off Q1 / Q3 / Q6, shutting down the emergency drive. IO_RETRY = low level cuts off Q4, disconnecting the PWM drive path. IO_LED = high level and IO_BUZZER = high level trigger continuous audible and visual alarms.

[0160] Troubleshooting and Reset: After the stall fault is cleared by personnel, the motor current returns to normal (<15A), the voltage drop of R24 is <0.1V, and the FAULT signal of U2 goes low. After detecting the low level of the FAULT signal, U1 automatically resets after a 100ms delay and re-enters the power-on initialization phase.

[0161] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A dual-drive PWM fault emergency multi-speed fan control circuit, characterized in that, include: The power input and filtering module is used to provide a stable operating power supply for each functional module and to realize electrical protection on the input side; The control unit module is used to receive signals from each sampling module and output corresponding control signals to each controlled module based on preset logic. The PWM signal detection module is used to acquire the PWM speed control signal output by the ECU, perform preprocessing, and then transmit it to the control unit module. The control unit module uses the acquired PWM signal to realize normal speed control and fault status identification. The fixed voltage emergency drive module is used to receive emergency control commands from the control unit module and output multi-level fixed regulated emergency drive voltage to the mode switching module. The mode switching module is used to receive mode switching instructions from the control unit module and realize hardware-level mutual exclusion switching between normal PWM drive and fault emergency drive. The three-phase drive and current sampling module is used to receive the drive voltage output by the mode switching module, complete the electronic commutation drive of the fan motor, and collect the operating current signal to transmit to the control unit module to realize overcurrent protection. The protection and alarm module is used to receive fault alarm commands and realize audible and visual indication and alarm of fault status.

2. A dual drive PWM failsafe multi-speed fan control circuit according to claim 1, wherein: The mode switching module includes transistor Q2, diode D2, diode D16, MOSFET Q4, resistor R25, resistor R6, and resistor R26; The collector of transistor Q2 is connected to the power input and the output of the filter module VBAT, the base is connected to the IO_MODE control terminal of the control unit module via resistor R25, and the emitter is connected to the anode of diode D2. The cathode of diode D2 is connected to the V_DRIVE_IN node via resistor R26. The V_DRIVE_IN node is the output terminal of the mode switching module. The drain of the MOSFET Q4 is connected to the V_DRIVE_IN node, the source is grounded, and the gate is connected to the IO_RETRY control terminal of the control unit module via resistor R6. The anode of diode D16 is connected to the V_EMERGENCY node output by the fixed voltage emergency drive module, and the cathode is connected to the V_DRIVE_IN node.

3. A dual drive PWM failsafe multi-speed fan control circuit according to claim 2, wherein: The diodes D2 and D16 form a unidirectional isolated mutually exclusive topology, which, together with the switching control of transistor Q2 and MOSFET Q4, achieves 100% electrical isolation between the PWM drive path and the emergency drive path. The MOSFET Q4, along with resistors R6 and R26, constitutes a soft-start submodule. The control unit module outputs a PWM signal with a gradually changing duty cycle from 0 to 100% through the IO_RETRY terminal, controlling the conduction level of the MOSFET Q4 to gradually change, so that the voltage at the V_DRIVE_IN node smoothly transitions from the emergency fixed voltage to the normal PWM drive voltage, thus achieving a shockless soft start for mode switching.

4. The dual-drive PWM fault emergency multi-speed fan control circuit according to claim 1, characterized in that: The fixed voltage emergency drive module includes at least two independent gear drive branches, each of which includes an NPN transistor, a Zener diode, an isolation diode, and a current-limiting resistor. In each branch, the collector of the NPN transistor is connected to the power input and the output of the filter module VBAT, the base is connected to the corresponding gear control terminal of the control unit module through the current limiting resistor, and the emitter is grounded through the Zener diode. At the same time, the emitter is connected to the anode of the isolation diode. The cathodes of the isolation diodes of each branch are connected to the V_EMERGENCY node, forming a multi-level fixed voltage regulated output structure, and the control unit module controls only one level drive branch to be turned on at the same time.

5. The dual-drive PWM fault emergency multi-speed fan control circuit according to claim 4, characterized in that: The fixed voltage emergency drive module includes three sets of gear drive branches: high speed, medium speed, and low speed. The high-speed branch includes an NPN transistor Q1, a 12V Zener diode D1, an isolation diode D3, and a current-limiting resistor R1, outputting a fixed 12V voltage, corresponding to a fan speed ≥3600rpm. The medium-speed branch includes an NPN transistor Q3, an 8V Zener diode D6, an isolation diode D14, and a current-limiting resistor R4, outputting a fixed 8V voltage, corresponding to a fan speed ≥2400rpm. The low-speed branch includes an NPN transistor Q6, a 5V Zener diode D7, an isolation diode D15, and a current-limiting resistor R7, outputting a fixed 5V voltage, corresponding to a fan speed ≥1500rpm.

6. The dual-drive PWM fault emergency multi-speed fan control circuit according to claim 1, characterized in that: The PWM signal detection module includes resistor R2, resistor R5, capacitor C3, diode D4, and resistor R27; The PWM signal input terminal is connected to the voltage divider node via resistor R2. Resistor R5 and capacitor C3 are connected in parallel and then connected across the voltage divider node and ground. The anode of diode D4 is connected to the voltage divider node, and the cathode is connected to the ADC sampling terminal of the control unit module via resistor R27. The resistors R2 and R5 form a voltage divider network, which divides the input 5V / 12V PWM signal to a sampling range of less than 3.3V. The capacitor C3 and resistor R27 form an RC low-pass filter circuit, which converts the PWM pulse signal into a DC average voltage with the corresponding duty cycle. The diode D4 enables unidirectional signal transmission and prevents backflow of voltage in the subsequent stage.

7. The dual-drive PWM fault emergency multi-speed fan control circuit according to claim 1, characterized in that: The power input and filtering module includes power input terminals B+ and B-, diode ZD1, MOSFET Q5, gate control unit, π-type filter unit and energy storage capacitor E1. The diode ZD1 is connected between B+ and B- for surge voltage clamping. The source of the MOSFET Q5 is connected to B-, the drain is connected to the subsequent ground circuit, and the gate is connected to the gate control unit composed of resistor R3, capacitor C4 and diode D5 to realize reverse power connection protection and overvoltage shutdown. The π-type filter unit consists of an inductor L1 and capacitors C1 and C2, connected between B+ and the power supply terminal of the subsequent stage, and is used to conduct interference suppression. The energy storage capacitor E1 is connected in parallel between the power supply terminal and ground, and is used to stabilize the power supply voltage and cope with sudden changes in load current.

8. The dual-drive PWM fault emergency multi-speed fan control circuit according to claim 1, characterized in that: The three-phase drive and current sampling module includes a pre-drive chip U2, a three-phase full-bridge MOSFET array, a current sampling resistor R24, a Hall sensor interface U3, and a freewheeling diode group. The enable terminal of the pre-drive chip U2 is connected to the IO_DRIVE_EN control terminal of the control unit module, the fault feedback terminal is connected to the IO_OVERCURRENT input terminal of the control unit module, the Hall signal input terminal is connected to the Hall sensor interface U3, and the six drive output terminals are respectively connected to the corresponding gates of the three-phase full-bridge MOS transistor array through the gate current limiting resistor. The V_DRIVE_IN node output by the drain connection mode switching module of the upper bridge arm of the three-phase full-bridge MOS transistor array is connected to the U, V, and W phase windings of the three-phase brushless DC fan motor at the midpoint of the three-phase bridge arm respectively. The current sampling resistor R24 ​​is connected in series between the source of the lower bridge arm of the three-phase full-bridge MOS transistor array and ground, and the sampling terminal is connected to the overcurrent detection terminal of the pre-driver chip U2. Each diode in the freewheeling diode group is connected in reverse parallel between the drain and source of each MOS transistor in the three-phase full-bridge MOS transistor array to absorb the back electromotive force during turn-off.

9. The dual-drive PWM fault emergency multi-speed fan control circuit according to claim 1, characterized in that: The protection and alarm module includes indicator light LED1, resistor R8, buzzer BZ1 and resistor R10; The anode of the indicator LED1 is connected to the IO_LED control terminal of the control unit module via resistor R8, and the cathode is grounded. The signal input terminal of the buzzer BZ1 is connected to the IO_BUZZER control terminal of the control unit module via resistor R10, and the ground terminal is grounded. When the control unit module experiences a PWM fault or an overcurrent fault, the drive indicator LED1 remains constantly lit and the buzzer BZ1 continuously sounds. After the fault is resolved, the drive indicator LED1 flashes after a delay, the volume of the buzzer BZ1 gradually decreases, and the alarm is turned off after 3 seconds.

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