On-chip load current monitoring and digital feedback system for LDO

Abstract

This application relates to the technical field of load current monitoring, and discloses an on-chip load current monitoring and digital feedback system for LDOs, including: a VSD sampling and amplification module for real-time acquisition and amplification of the power transistor drain-source voltage; a VSG sampling module for real-time acquisition of the power transistor gate voltage; a temperature sensor for real-time acquisition of ambient temperature; an analog-to-digital converter for sequentially converting the power transistor drain-source voltage, power transistor gate voltage, and temperature into numerical signals via analog switches; and a digital engine for temperature compensation of the load current based on the numerical signals of the power transistor drain-source voltage, power transistor gate voltage, and ambient temperature. This invention establishes a comprehensive on-resistance model that reflects the physical characteristics of the power transistor's on-resistance and integrates multi-dimensional influencing factors such as temperature, gate voltage, and self-heating effects, enabling high-precision, non-destructive on-chip load current monitoring without the need for additional power components.

Description

Technical Field

[0001] This application relates to the technical field of load current monitoring, and in particular to an on-chip load current monitoring and digital feedback system for LDOs. Background Technology

[0002] Low-dropout linear regulators (LDOs), as one of the core modules of power management integrated circuits, are widely used in various electronic systems due to their characteristics such as low noise, fast response, simple structure, and ease of integration. In SoCs, LDOs typically undertake the critical task of providing independent, stable, and low-noise power rails for different functional modules such as CPU, GPU, memory, RF modules, and sensors. With the continuous miniaturization of integrated circuit manufacturing processes and the continuous improvement of system integration, the number of power rails required by a single SoC is growing rapidly. Taking server processors as an example, modern multi-core CPUs require more than 25 power rails, which places extremely high demands on the complexity, flexibility, and monitorability of power management systems.

[0003] Real-time and accurate monitoring of load current is a prerequisite for achieving refined power management. By continuously observing the load current, the system can obtain real-time power consumption information of each functional module for critical tasks such as load status analysis, fault diagnosis, and overcurrent protection. In existing technologies, there are sampling schemes based on series sensing resistors and detection schemes based on the on-resistance of power transistors. Among them, the sampling scheme based on series sensing resistors is simple in principle and highly accurate, but the series resistor introduces additional power loss and voltage drop, reducing the overall efficiency of the LDO. In addition, integrating precision resistors on the LDO chip requires a large chip area, increasing manufacturing costs. On the other hand, the detection scheme based on the on-resistance of power transistors does not introduce additional power consumption and does not occupy additional chip area, and has significant advantages in terms of integration and energy efficiency. However, the on-resistance of power transistors is affected by multiple factors, leading to a high error in the detection results. Therefore, how to accurately compensate for the on-resistance of power transistors to achieve accurate monitoring of load current is the fundamental problem to be solved by this invention. Summary of the Invention

[0004] To accurately compensate for the on-resistance of the power transistor and thus achieve accurate monitoring of the load current, this application provides an on-chip load current monitoring and digital feedback system for an LDO, employing the following technical solution: On-chip load current monitoring and digital feedback system for LDOs includes: The VSD sampling and amplification module is used to acquire and amplify the drain-source voltage of the power transistor in real time. The VSG sampling module is used to acquire the gate voltage of the power transistor in real time. Temperature sensor, used to collect ambient temperature in real time; An analog-to-digital converter is used to sequentially convert the drain-source voltage, gate voltage, and temperature of a power transistor into numerical signals via analog switches. The digital engine is used to perform temperature compensation on the load current based on numerical signals of the power transistor drain-source voltage, power transistor gate voltage, and ambient temperature.

[0005] Optionally, the process of temperature compensation for the load current includes: Establish a model of on-resistance under arbitrary temperature and power transistor gate voltage; An equation is established based on the temperature rise relationship between the ambient temperature and the actual junction temperature of the power transistor, and the difference between the junction temperature of the power transistor and the ambient temperature is obtained through iteration. Obtain the multidimensional calibration parameters of the LDO based on historical calibration data; The load current is calculated based on the on-resistance model, the difference between the power transistor junction temperature and the ambient temperature, multidimensional correction parameters, ambient temperature, and the power transistor gate voltage.

[0006] Optionally, the process of establishing the on-resistance model includes: At standard temperature The absolute value of the threshold voltage is obtained by detection. ; At standard temperature and preset power transistor gate voltage The reference on-resistance is obtained by detecting the magnitude. ; Setting the migration temperature index Set the threshold voltage temperature coefficient according to the process type. ; Power transistor junction temperature and power transistor gate voltage As a variable, standard temperature absolute value of threshold voltage Preset power transistor gate voltage and reference on-resistance As a reference value, the mobility temperature index and threshold voltage temperature coefficient As coefficients, a conduction resistance model is established.

[0007] Optionally, the power transistor junction temperature With ambient temperature Difference The acquisition process includes: Obtain the equivalent thermal resistance from the power transistor channel to the temperature sensor ; Establish equations The difference is obtained by using the fixed-point iteration method. .

[0008] Optionally, the process of solving the problem using the fixed-point iteration method includes: Calculate the room temperature reference resistance based on the power transistor gate voltage, estimate the initial current based on the room temperature reference resistance and the power transistor drain-source voltage, and estimate the initial junction temperature based on the room temperature reference resistance and the initial current. For the k-th iteration, the on-resistance at the current power transistor junction temperature and the current load current are calculated based on the on-resistance model, and the current load current is updated using the on-resistance and the current load current. ; After a fixed number of iterations, check for convergence. Then the loop will exit. The difference is obtained based on the preset value. .

[0009] Optionally, the multidimensional calibration parameters include gain error calibration coefficient, offset voltage calibration coefficient, and higher-order temperature nonlinearity calibration coefficient; The gain error calibration coefficient is used to correct the deviation of the amplifier gain; The offset voltage calibration coefficient is used to correct the input offset. The higher-order temperature nonlinear calibration coefficients are used to correct uncovered higher-order effects.

[0010] Optionally, the calculation process for the load current includes: Obtain the voltage difference between the drain-source voltage of the power transistor and the offset voltage calibration coefficient, and obtain the ratio of the voltage difference to the output result of the on-resistance model; Obtain the temperature difference between the current power transistor junction temperature and the reference absolute temperature, and obtain the adjustment coefficient through the high-order temperature nonlinearity calibration coefficient and the temperature difference; The load current is calculated by multiplying the ratio of the voltage difference to the on-resistance model output, the adjustment coefficient, and the gain error calibration coefficient.

[0011] Optionally, the higher-order temperature nonlinear calibration coefficients include C1 and C2; The calculation process of the adjustment coefficient includes: pass Calculate the adjustment coefficient , This represents the temperature difference between the current junction temperature of the power transistor and the reference absolute temperature.

[0012] In summary, this application includes at least one of the following beneficial technical effects: This invention establishes a comprehensive on-resistance model that reflects the physical characteristics of the power transistor's on-resistance and integrates multi-dimensional influencing factors such as temperature, gate voltage, and self-heating effects, achieving accurate compensation for offset. It enables high-precision, non-destructive on-chip load current monitoring without the need for additional power components, maintaining stable and accurate detection performance across the entire temperature range, load range, and process curve conditions. Attached Figure Description

[0013] Figure 1 This is a logic diagram of the on-chip load current monitoring and digital feedback system in this invention. Detailed Implementation

[0014] The embodiments of this application are described in detail below, and examples of the embodiments are shown in the accompanying drawings.

[0015] In the description of this specification, the references to "certain embodiments," "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples" refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0016] This application discloses an on-chip load current monitoring and digital feedback system for LDOs, referring to... Figure 1 It includes a VSD sampling and amplification module, a VSG sampling module, a temperature sensor, an analog-to-digital converter (ADC), and a digital engine.

[0017] The VSD sampling and amplification module is used to acquire and amplify the drain-source voltage of the power transistor in real time. Since the drain-source voltage of the power transistor is typically in the range of tens to hundreds of mV when it is turned on, it needs to be amplified to the full scale of the analog-to-digital converter (ADC). In this embodiment, the VSD sampling and amplification module uses a high-side sampling structure with current mirror clamping to ensure that the drain voltages of the power transistor and the detection transistor are equal. The amplifier uses a chopper-stabilized instrumentation amplifier to reduce the input offset voltage to < 50µV. The VSG sampling module is used to acquire the gate voltage of the power transistor in real time. The VSG can be converted to the ADC range using a resistor divider or a level shifter. The temperature sensor is used to acquire the ambient temperature in real time. The ADC sequentially converts the drain-source voltage, gate voltage, and temperature of the power transistor into numerical signals using analog switches. In this embodiment, the ADC uses a 12-bit successive approximation (SAR) type. The ADC, or Digital Engine, is used to perform temperature compensation on the load current based on numerical signals of the power transistor's drain-source voltage, gate voltage, and ambient temperature. As can be seen, this embodiment achieves temperature compensation based on the physical mechanism of the MOSFET by using ambient temperature and the power transistor's gate voltage. This enables high-precision, non-destructive on-chip load current monitoring without the need for additional power components. It maintains stable and accurate detection performance across the entire temperature range, load range, and process angle, thus achieving accurate monitoring of the load current.

[0018] In one embodiment, the process of temperature compensation for load current includes: firstly establishing an on-resistance model at arbitrary temperature and power transistor gate voltage; this process includes: firstly at a standard temperature The absolute value of the threshold voltage is obtained by detection. At standard temperature and preset power transistor gate voltage The reference on-resistance is obtained by detecting the magnitude. Set the migration temperature index Its value ranges from 1.5 to 2. The mobility temperature index in this embodiment... Set it to 1.5, then set the threshold voltage temperature coefficient according to the process type. This coefficient can be obtained by determining the chip process corner type and then using a lookup table to obtain the threshold voltage temperature coefficient corresponding to different chip process corner types. The table below shows the chip process corner and threshold voltage temperature coefficient. A comparison table; Then the junction temperature of the power transistor will be adjusted. and power transistor gate voltage As a variable, standard temperature absolute value of threshold voltage Preset power transistor gate voltage and reference on-resistance As reference values, the mobility temperature index k and the threshold voltage temperature coefficient As a coefficient, establish the on-resistance model: Due to the junction temperature of the power transistor Unknown, needs to be determined by the ambient temperature The relationship is determined, and at the same time, the power transistor junction temperature With ambient temperature The relationship is related to the on-resistance. Therefore, this embodiment establishes an equation based on the temperature rise relationship between the ambient temperature and the actual junction temperature of the power transistor, and obtains the difference between the junction temperature of the power transistor and the ambient temperature through iteration. This process includes: first, obtaining the equivalent thermal resistance from the power transistor channel to the temperature sensor. This parameter can be obtained by using thermal simulation tools to perform finite element analysis on the chip layout and packaging substrate to extract the thermal resistance from the center of the power transistor to the temperature sensor location, or it can be obtained through the factory calibration process.

[0019] Then establish the equation The solution is obtained using a fixed-point iterative method. This process includes: calculating the room-temperature reference resistance based on the power transistor gate voltage. The calculation process is as follows: ,in, The power transistor gate voltage is used as the calibration point. Through this process, the issue caused by the power transistor gate voltage can be corrected. This results in data offset.

[0020] Then, an initial current estimate is made based on the room temperature reference resistor and the drain-source voltage of the power transistor. The initial junction temperature is estimated based on the room-temperature reference resistance and the initial current; that is, the obtained room-temperature reference resistance and initial current are substituted into the established equation to obtain... .

[0021] Then, for the k-th iteration, the on-resistance at the current power transistor junction temperature is calculated based on the on-resistance model. and the current load current The specific equation is: Then update using the on-resistance and the current load current. The specific equation is: After a fixed number of iterations, convergence is checked. In this embodiment, the fixed number of iterations is set to 3. Then the loop will exit. As a preset value, this embodiment sets it to 0.1℃ to obtain the difference. The table below shows the recorded data from the iteration (based on the power transistor junction temperature). For reference only. ): By obtaining By combining the obtained ambient temperature, the junction temperature of the power transistor can be accurately determined. The junction temperature of the power transistor is equal to the ambient temperature and... The sum of the values; under high current conditions, the self-heating effect of the power transistor causes the channel junction temperature to be significantly higher than the ambient temperature; since the on-resistance model itself depends on the unknown junction temperature, and the junction temperature depends on the on-resistance model and the load current, this application achieves compensation for the local self-heating effect caused by the power transistor's own power consumption through an iterative approach, thereby improving the accuracy of load current monitoring.

[0022] It should be noted that, During calculations, temperature-related parameters (power transistor junction temperature and standard temperature) need to be converted to absolute temperatures for calculation.

[0023] In addition, the process of temperature compensation for load current includes obtaining multi-dimensional calibration parameters of the LDO based on historical calibration data. These multi-dimensional calibration parameters include gain error calibration coefficients, offset voltage calibration coefficients, and higher-order temperature nonlinearity calibration coefficients. The gain error calibration coefficients are used to correct amplifier gain deviations; the offset voltage calibration coefficients are used to correct input offset; and the higher-order temperature nonlinearity calibration coefficients are used to correct uncovered higher-order effects. It should be noted that the role of the multi-dimensional calibration parameters is to correct process deviations and unmodeled non-ideal factors, and they are determined based on factory calibration, which will not be detailed here.

[0024] Finally, the load current is calculated based on the on-resistance model, the difference between the power transistor junction temperature and the ambient temperature, multidimensional correction parameters, ambient temperature, and the power transistor gate voltage. This process includes: first, obtaining the voltage difference between the power transistor drain-source voltage and the offset voltage calibration coefficient. Then obtain the ratio of the voltage difference to the on-resistance model output. ; Obtain the temperature difference between the current power transistor junction temperature and the reference absolute temperature. The adjustment coefficient is obtained through higher-order temperature nonlinearity calibration coefficients and temperature difference; the higher-order temperature nonlinearity calibration coefficients include C1 and C2; the calculation process of the adjustment coefficient includes: through... Calculate the adjustment coefficient , This represents the temperature difference between the current power transistor junction temperature and the reference absolute temperature; the ratio of the voltage difference to the on-resistance model output, the adjustment factor, and the gain error calibration factor are used. The cumulative product is used to calculate the load current, i.e. Through the above process, high-precision, non-destructive on-chip load current monitoring without additional power components can be achieved, maintaining stable and accurate detection performance across the entire temperature range, load range, and process angle. By establishing a comprehensive on-resistance model that reflects the physical characteristics of the power transistor's on-resistance and integrating multi-dimensional influencing factors such as temperature, gate voltage, and self-heating effect, accurate compensation for offset is achieved.

[0025] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An on-chip load current monitoring and digital feedback system for an LDO, characterized in that, include: The VSD sampling and amplification module is used to acquire and amplify the drain-source voltage of the power transistor in real time. The VSG sampling module is used to acquire the gate voltage of the power transistor in real time. Temperature sensor, used to collect ambient temperature in real time; An analog-to-digital converter is used to sequentially convert the drain-source voltage, gate voltage, and temperature of a power transistor into numerical signals via analog switches. The digital engine is used to perform temperature compensation on the load current based on numerical signals of the power transistor drain-source voltage, power transistor gate voltage, and ambient temperature.

2. The on-chip load current monitoring and digital feedback system for an LDO of claim 1, wherein, The process of temperature compensation for load current includes: Establish a model of on-resistance under arbitrary temperature and power transistor gate voltage; An equation is established based on the temperature rise relationship between the ambient temperature and the actual junction temperature of the power transistor, and the difference between the junction temperature of the power transistor and the ambient temperature is obtained through iteration. Obtain the multidimensional calibration parameters of the LDO based on historical calibration data; The load current is calculated based on the on-resistance model, the difference between the power transistor junction temperature and the ambient temperature, multidimensional correction parameters, ambient temperature, and the power transistor gate voltage.

3. The on-chip load current monitoring and digital feedback system for an LDO of claim 2, wherein, The process of establishing the on-resistance model includes: At standard temperature The threshold voltage absolute value is obtained by detection ; At standard temperature and a preset power tube gate voltage of a certain size ; Setting mobility temperature index Setting threshold voltage temperature coefficient according to process type ; Power tube junction temperature and power tube gate voltage as a variable, standard temperature , threshold voltage absolute value , preset power tube gate voltage and reference on-resistance as a reference quantity, mobility temperature index and threshold voltage temperature coefficient as a coefficient, on-resistance model is established.

4. The on-chip load current monitoring and digital feedback system for LDO according to claim 2, characterized in that, Power tube junction temperature Ambient temperature Difference The acquisition process includes: Acquiring equivalent thermal resistance of power tube channel to temperature sensor ; Establishing the equation , and using the fixed-point iteration method to solve the difference , where I is the load current, is the on-resistance model.

5. The on-chip load current monitoring and digital feedback system for an LDO of claim 4, wherein, The process of solving the problem using the fixed-point iteration method includes: Calculate the room temperature reference resistance based on the power transistor gate voltage, estimate the initial current based on the room temperature reference resistance and the power transistor drain-source voltage, and estimate the initial junction temperature based on the room temperature reference resistance and the initial current. For the k-th iteration, the on-resistance at the current power transistor junction temperature and the current load current are calculated based on the on-resistance model, and the current load current is updated using the on-resistance and the current load current. ; After a fixed number of iterations, check for convergence. Then the loop will exit. The difference is obtained based on the preset value. .

6. The on-chip load current monitoring and digital feedback system for LDO according to claim 5, characterized in that, The multidimensional calibration parameters include gain error calibration coefficient, offset voltage calibration coefficient, and higher-order temperature nonlinearity calibration coefficient. The gain error calibration coefficient is used to correct the deviation of the amplifier gain; The offset voltage calibration coefficient is used to correct the input offset. The higher-order temperature nonlinear calibration coefficients are used to correct uncovered higher-order effects.

7. The on-chip load current monitoring and digital feedback system for LDO according to claim 6, characterized in that, The calculation process for load current includes: Obtain the voltage difference between the drain-source voltage of the power transistor and the offset voltage calibration coefficient, and obtain the ratio of the voltage difference to the output result of the on-resistance model; Obtain the temperature difference between the current power transistor junction temperature and the reference absolute temperature, and obtain the adjustment coefficient through the high-order temperature nonlinearity calibration coefficient and the temperature difference; The load current is calculated by multiplying the ratio of the voltage difference to the on-resistance model output, the adjustment coefficient, and the gain error calibration coefficient.

8. The on-chip load current monitoring and digital feedback system for LDO according to claim 7, characterized in that, The higher-order temperature nonlinear calibration coefficients include C1 and C2; The calculation process of the adjustment coefficient includes: pass Calculate the adjustment coefficient , This represents the temperature difference between the current junction temperature of the power transistor and the reference absolute temperature.

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