Chip voltage monitoring method and device, chip, storage medium and program product

Abstract

This application provides a method, apparatus, chip, storage medium, and program product for monitoring chip voltage. In the digital voltage sensor configured in the chip, its first delay path is configured as a reference path for persistent hold-time violations. The method includes: acquiring multiple pre-configured voltages by setting the first delay path of the digital voltage sensor as the reference path for persistent hold-time violations; for any voltage, acquiring ring oscillator parameter information corresponding to a second delay path under that voltage; determining the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer based on the ring oscillator parameter information; determining the hold-time corresponding to the voltage in the second delay path based on the first / second delay data; and generating voltage monitoring configuration data based on the hold-time corresponding to each voltage in the second delay path to monitor the real-time voltage of the chip. This application improves the efficiency of chip voltage monitoring.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, device, chip, storage medium, and program product for monitoring chip voltage. Background Technology

[0002] With increasing chip integration and power consumption demands, the problem of resistive voltage drop (IR drop) caused by dynamic load changes within the chip is becoming increasingly serious. IR drop can significantly affect chip operating speed; therefore, it is necessary to monitor the chip voltage.

[0003] In related technologies, a digital voltage sensor (DVS) is typically used, whose internal analog-to-digital converter is responsible for converting analog voltage into digital values. To improve measurement accuracy and suppress random noise, each preset voltage point is typically sampled 512 times, and then the arithmetic mean of these 512 samples is calculated. The final mean is then used as the measured result for that voltage point.

[0004] However, the above methods result in low monitoring efficiency. Summary of the Invention

[0005] This application provides a method, apparatus, chip, storage medium, and program product for monitoring chip voltage, in order to achieve the technical effect of improving monitoring efficiency.

[0006] In a first aspect, embodiments of this application provide a method for use in a chip, the chip being configured with a digital voltage sensor, the digital voltage sensor including a first delay path, a second delay path, and multiple ring oscillators, each ring oscillator including multiple multiplexers and multiple delay units, the first delay path being configured as a reference path for persistent hold-time violations, the method including:

[0007] Obtain multiple pre-configured voltages;

[0008] For any voltage, obtain the ring oscillator parameter information corresponding to the second delay path under the voltage;

[0009] Based on the ring oscillator parameter information, determine the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer;

[0010] Based on the first delay data and the second delay data, determine the holding time of the voltage in the second delay path;

[0011] Based on the holding time of each voltage in the second delay path, voltage monitoring configuration data is generated;

[0012] The real-time voltage of the chip is monitored based on the voltage monitoring configuration data.

[0013] In one possible implementation, the ring oscillator parameter information includes the clock frequency of each ring oscillator, the total number of ring oscillators, the clock frequency of each ring oscillator cascaded with multiple multiplexers, and the total number of multiplexers.

[0014] The step of determining the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer based on the ring oscillator parameter information includes:

[0015] Based on the clock frequency of each ring oscillator and the total number of ring oscillators, determine the first delay data of each delay unit in the ring oscillator;

[0016] The second delay data of the multiplexer is determined based on the clock frequency of each ring oscillator cascaded with multiple multiplexers, the first delay data, and the total number of multiplexers.

[0017] In one possible implementation, the second delay path includes a transmission delay path, a data delay path, and a capture delay path; the first delay data includes first data of the transmission delay path, first data of the data delay path, and first data of the capture delay path; and the second delay data includes second data of the transmission delay path, second data of the data delay path, and second data of the capture delay path.

[0018] The step of determining the holding time of the voltage in the second delay path based on the first delay data and the second delay data includes:

[0019] Based on the first data of the transmission delay path, the second data of the transmission delay path, and the total number of delay units in the transmission delay path, the third delay data of the transmission delay path is determined;

[0020] The fourth delay data of the data delay path is determined based on the first data of the data delay path, the second data of the data delay path, and the total number of delay units in the data delay path;

[0021] The fifth delay data of the capture delay path is determined based on the second data of the capture delay path, the second data of the capture delay path, and the total number of delay units in the capture delay path;

[0022] Based on the third delay data, the fourth delay data, and the fifth delay data, the holding time of the voltage in the second delay path is determined.

[0023] In one possible implementation, monitoring the real-time voltage of the chip based on the voltage monitoring configuration data includes:

[0024] In response to the user's selection of one of the pre-configured voltages, a target voltage is determined;

[0025] Based on the target voltage, determine the configuration data corresponding to the target voltage from the voltage monitoring configuration data;

[0026] Under the configured data, based on the monitoring signal output by the digital voltage sensor and using the target voltage as the monitoring reference, the real-time voltage of the chip is monitored to obtain the voltage monitoring result.

[0027] In one possible implementation, the step of monitoring the real-time voltage of the chip based on the monitoring signal output by the digital voltage sensor, using the target voltage as a monitoring reference, under the configuration data, to obtain a voltage monitoring result includes:

[0028] Under the configuration data, the real-time voltage of the chip is monitored based on the monitoring signal output by the digital voltage sensor;

[0029] The real-time voltage is compared with the target voltage, which serves as the monitoring benchmark;

[0030] If the comparison result indicates that the real-time voltage is greater than the target voltage, then output the voltage monitoring result indicating that the voltage exceeds the limit;

[0031] If the comparison result indicates that the real-time voltage is less than or equal to the target voltage, then a voltage monitoring result indicating that the voltage does not exceed the limit is output.

[0032] In one possible implementation, it also includes:

[0033] If the output is a voltage monitoring result used to indicate that the voltage is over the limit, then an early warning message is output, and after a preset period, a reset operation is performed on the register of the digital voltage sensor to reset the current monitoring signal.

[0034] The reset digital voltage sensor then outputs a monitoring signal to continuously monitor the real-time voltage of the chip.

[0035] Secondly, embodiments of this application provide a chip voltage monitoring device applied to a chip. The chip is equipped with a digital voltage sensor, which includes a first delay path, a second delay path, and multiple ring oscillators. Each ring oscillator includes multiple multiplexers and multiple delay units. The first delay path is configured as a reference path for persistent hold-time violations. The device includes:

[0036] The acquisition module is used to acquire multiple pre-configured voltages;

[0037] The acquisition module is further configured to acquire, for any voltage, the ring oscillator parameter information corresponding to the second delay path under the voltage;

[0038] The determining module is used to determine the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer based on the ring oscillator parameter information.

[0039] The determining module is further configured to determine the holding time of the voltage in the second delay path based on the first delay data and the second delay data;

[0040] The generation module is used to generate voltage monitoring configuration data based on the holding time of each voltage in the second delay path.

[0041] The monitoring module is used to monitor the real-time voltage of the chip according to the voltage monitoring configuration data.

[0042] Thirdly, embodiments of this application provide a chip, including: a digital voltage sensor and a memory, wherein the digital voltage sensor includes a first delay path, a second delay path and a plurality of ring oscillators, and each ring oscillator includes a plurality of multiplexers and a plurality of delay units;

[0043] The memory stores computer-executed instructions;

[0044] The digital voltage sensor executes computer execution instructions stored in the memory, causing the digital voltage sensor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0045] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0046] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0047] The chip voltage monitoring method, apparatus, chip, storage medium, and program product provided in this application embodiment set the first delay path of the digital voltage sensor as the reference path for persistent hold time violations, obtains the ring oscillator parameter information corresponding to the second delay path under each preset voltage, determines the first delay data of the delay unit and the second delay data of the multiplexer based on the parameter information, and then calculates the hold time of the corresponding voltage under the second delay path from the two types of delay data. Voltage monitoring configuration data is generated using the hold time corresponding to each voltage, and real-time chip voltage monitoring is achieved based on this monitoring configuration data. The method of this application eliminates the need to repeatedly traverse each voltage point 512 times, reducing the amount of monitoring data and thus significantly improving the chip voltage monitoring efficiency. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0049] Figure 1 A schematic flowchart illustrating a chip voltage monitoring method provided in an embodiment of this application;

[0050] Figure 2 This application provides a schematic diagram of the architecture of a digital voltage sensor.

[0051] Figure 3 A flowchart illustrating a method for determining the holding time of a voltage in a second delay path, provided in an embodiment of this application;

[0052] Figure 4 This is a schematic diagram of the structure of a ring oscillator provided in an embodiment of this application;

[0053] Figure 5 A flowchart illustrating a method for monitoring the real-time voltage of a chip, provided in an embodiment of this application;

[0054] Figure 6 A schematic diagram of a continuous monitoring loop provided in an embodiment of this application;

[0055] Figure 7 A monitoring timing diagram provided for an embodiment of this application;

[0056] Figure 8 A schematic diagram of a chip voltage monitoring device provided in an embodiment of this application;

[0057] Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of this application.

[0058] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0059] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0060] With the continuous development of semiconductor technology, chips are becoming increasingly complex. In high-performance digital chips using advanced processes, such as system-on-chips (SoCs), high-performance central processing units (CPUs), graphics processing units (GPUs), artificial intelligence (AI) chips, and baseband chips for fourth-generation (4G) and fifth-generation (5G) mobile communication technologies, the resistive voltage drop problem caused by dynamic load changes within the chip is becoming increasingly serious due to the increase in chip integration and power consumption requirements. In this application, resistive voltage drop can also be simply referred to as voltage drop.

[0061] Voltage drops significantly impact the operating speed of a chip's critical paths. For example, a high-performance CPU designed for a 2GHz frequency might only be able to maintain an actual operating frequency of 1.8GHz due to voltage drops, drastically reducing chip performance. Furthermore, during intensive computation in high-computing modules such as AI chips and GPUs, localized voltage fluctuations can trigger hold-time violations, leading to data errors or system crashes. Therefore, timely identification of severe voltage drop anomalies during chip operation monitoring allows for immediate responses. Voltage compensation and frequency reduction can suppress voltage drop deterioration, mitigating timing shifts and performance degradation caused by voltage dips, and reducing the negative impact of voltage drops on chip stability and performance. This underscores the necessity of real-time online monitoring of the chip's internal operating voltage.

[0062] In related technologies, when monitoring chip voltage, a digital voltage sensor with a built-in analog-to-digital converter is typically used to monitor the chip voltage. The analog-to-digital converter converts the chip's analog voltage signal into a digital voltage value. To improve voltage measurement accuracy and suppress random noise during the sampling process, 512 sampling operations need to be repeated for each preset voltage point, and all sampled values ​​are then arithmetically averaged to obtain the effective measured result for that voltage point.

[0063] However, in the above method, each preset voltage point needs to be traversed 512 times, which involves a large amount of data processing and results in a lengthy monitoring process, greatly reducing the monitoring efficiency of the chip voltage.

[0064] To address the aforementioned problems in related technologies, this application proposes a chip voltage monitoring method. Specifically, by configuring a digital voltage sensor integrating a first delay path, a second delay path, multiple ring oscillators (ROs), a multiplexer, and delay units within the chip, and setting the first delay path as the reference path for persistent hold-time violations, and relying on the parameter correlation characteristics between the hardware timing path and the ring oscillators, the delay data corresponding to the delay units and multiplexers can be determined sequentially by acquiring the ring oscillator parameter information corresponding to the second delay path under each preset voltage. This allows for the calculation of the hold-time of the second delay path under different voltages. Finally, dedicated voltage monitoring configuration data is generated based on the hold-times corresponding to multiple voltages, and this configuration data is used to complete the subsequent real-time voltage monitoring of the chip. This eliminates the need for multiple traversal sampling and extensive arithmetic operations for each voltage point, avoiding the redundancy overhead caused by repeated sampling. While ensuring monitoring reliability, it fundamentally reduces monitoring time, thereby improving voltage monitoring efficiency.

[0065] This application is applicable to scenarios such as chip mass production monitoring and on-chip real-time voltage monitoring. It achieves monitoring through a digital voltage sensor with a built-in dual-delay path and a ring oscillator, using the method described in this application. It eliminates the need for multiple sampling iterations, thus adapting to mass production batch monitoring and continuous voltage monitoring during long-term chip operation.

[0066] It is understood that the above application scenarios are for illustrative purposes only and do not limit this application.

[0067] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0068] Please see Figure 1 , Figure 1This is a flowchart illustrating a chip voltage monitoring method provided in an embodiment of this application. The execution subject of this method can be a chip voltage monitoring device, such as a chip, processor, or controller. Figure 1 As shown, the method may include the following steps:

[0069] S101, Obtain multiple pre-configured voltages.

[0070] In this embodiment, taking a chip as the execution subject, the chip is equipped with a digital voltage sensor, which includes a first delay path, a second delay path and multiple ring oscillators. Each ring oscillator includes multiple multiplexers and multiple delay units.

[0071] To facilitate understanding of the method in this embodiment, the following is combined with... Figure 2 To explain, Figure 2 This is a schematic diagram of the architecture of a digital voltage sensor provided in an embodiment of this application. The first delay path and the second delay path can be as follows: Figure 2 As indicated by the annotations in the document.

[0072] like Figure 2 As shown, the digital voltage sensor can be controlled by the global reset signal (RESET) B. Starting from the signal source, two parallel signal transmission paths are constructed, namely the first delay path and the second delay path. The abnormality monitoring of the circuit is realized through logic comparison.

[0073] The core of the circuit may include Figure 2 The three ring oscillators can be configured via Select (SEL) [0-2]. Different configurations correspond to different selection configuration delay durations, thereby providing an adjustable timing environment for signal transmission and adapting to different setup and hold time verification requirements.

[0074] After the signal is emitted from the signal source, it splits into two paths and is sent to the launch delay path, namely the launch D flip-flop or register (Launch D Flip-Flop, Launch DFF) A and Launch DFF B, respectively, to begin transmission along the first and second delay paths. In the first delay path, the signal undergoes timing adjustments through delay units and is finally captured by Capture DFF A in the capture delay path. The second delay path is a completely symmetrical parallel path. After the signal is emitted by Launch DFF B, it passes through delay units with the same configuration and is finally captured by Capture DFF B. The capture results of the two paths are used as sensitive signals and compared with an exclusive OR (XOR) gate. If the two signals are delayed or the data states are inconsistent, the XOR gate will output a high level, triggering the subsequent flip-flops to generate an alarm fault signal (CFAIL), thereby indicating the timing deviation or functional abnormality in the circuit in real time. For example, if neither of the DFFs captured by the two paths has a hold violation or both have a hold violation, then the final output CFAIL is 0. If one path captures a DFF with a hold violation while the other does not, then the final output CFAIL will be 1.

[0075] The global reset signal RESETB provides initialization control for all flip-flops and timing units, ensuring stable startup after power-on and avoiding misjudgments caused by unknown states.

[0076] This circuit, through its dual-path parallel transmission, programmable delay control, and logic comparison design, achieves accurate verification of timing consistency and real-time fault monitoring of digital circuits. It can effectively identify problems such as setup time violations, hold time violations, and signal interference, thereby ensuring the timing stability and reliability of the circuit.

[0077] Based on the above architecture, in this embodiment, the first delay path is pre-configured as the reference path for maintaining hold violations. Its state does not change with changes in the monitored voltage or switching of the monitoring scenario, and it serves as the timing reference during the voltage monitoring process. The second delay path is configured as the monitoring path.

[0078] Optionally, the second delay path can be configured as the baseline path and the first delay path can be configured as the monitoring path; this application does not impose any limitations on this.

[0079] In this embodiment, one possible way to acquire the voltage is to retrieve multiple preset monitoring voltages pre-stored in the chip's internal or external monitoring control unit. These preset voltages can be divided according to the chip's rated operating voltage range, voltage fluctuation tolerance range, or extreme operating voltage boundary, thereby obtaining a voltage sample set covering various operating conditions of the chip, including normal operation, critical operation, and abnormal operation. This ensures that monitoring covers all possible voltage operating scenarios of the chip and reduces monitoring blind spots.

[0080] S102. For any voltage, obtain the ring oscillator parameter information corresponding to the second delay path under the voltage.

[0081] For each preset monitoring voltage, collect the ring oscillator parameter information related to the second delay path under that voltage condition.

[0082] Optionally, the ring oscillator parameter information includes, but is not limited to: the clock frequency of each ring oscillator, the total number of ring oscillators, the clock frequency of each ring oscillator cascaded with multiple multiplexers (MUX), and the total number of multiplexers.

[0083] These parameters directly reflect the timing characteristics of the delay units and multiplexers. By analyzing the clock frequency and total number of ring oscillators, the delay value of a single delay unit, i.e., the first delay data, can be calculated. Combining the clock frequency and total number of multiplexers, the additional delay introduced by the cascaded multiplexers, i.e., the second delay data, can be further quantified.

[0084] The acquisition and analysis of the above parameter information provides a basis for the subsequent calculation of the holding time, ensuring the accuracy of the voltage monitoring configuration data and thus improving the reliability of the monitoring results.

[0085] S103. Based on the ring oscillator parameter information, determine the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer.

[0086] By combining the collected ring oscillator parameter information, the first delay data of each delay unit and the second delay data after the cascaded multiplexer are calculated and determined according to the timing transmission law, thereby clarifying the timing loss characteristics of the delay unit under different voltages.

[0087] S104. Based on the first delay data and the second delay data, determine the holding time of the voltage corresponding to the second delay path.

[0088] Based on the hardware structure of the second delay path, the timing transmission pattern of the second delay path under the voltage is analyzed according to the first delay data and the second delay data, and then the holding time corresponding to the voltage is determined, thereby establishing the correspondence between voltage and holding time.

[0089] S105. Generate voltage monitoring configuration data based on the holding time of each voltage in the second delay path.

[0090] After completing the hold time calibration for each preset voltage, the hold time and delay data corresponding to each voltage are systematically organized and normalized. According to the preset parameter association rules, the voltage, delay data, and hold time are bound and integrated to generate voltage monitoring configuration data adapted to the chip.

[0091] The voltage monitoring configuration data includes complete timing parameters and hold time parameters for each voltage, which can be directly used for subsequent real-time voltage monitoring.

[0092] S106. Monitor the real-time voltage of the chip according to the voltage monitoring configuration data.

[0093] Then, based on the generated voltage monitoring configuration data, the real-time monitoring function of the digital voltage sensor is activated to continuously monitor and determine the real-time voltage and status of the chip.

[0094] Optionally, in this embodiment, the chip can be further divided into multiple voltage domains. Each voltage domain, such as the CPU core, GPU, AI accelerator, etc., is independently configured with a digital voltage sensor and feedback loop system. The digital voltage sensor in each voltage domain monitors its local voltage fluctuations through two symmetrical paths (reference path and test path) and triggers targeted responses, such as voltage compensation and frequency reduction.

[0095] Monitoring results from different voltage domains can be used as a reference to optimize the overall strategy. For example, when the CPU core experiences a voltage drop due to high load, only local voltage compensation is triggered to avoid interference with other modules, such as the GPU.

[0096] In the above embodiments of this application, the first delay path of the digital voltage sensor is configured as a reference path for persistent hold-time violations, ensuring that it does not change with variations in the monitored voltage. The second delay path dynamically adjusts the configuration of the delay unit and the multiplexer according to the voltage. By acquiring the ring oscillator parameter information and calculating the delay data, the hold-time of the second delay path under different voltages can be accurately determined, thereby generating voltage monitoring configuration data. This configuration data directly maps the correspondence between voltage and hold-time, eliminating the need for 512 repeated samplings at each voltage point; monitoring can be completed solely based on the delay data. Therefore, the method of this embodiment significantly reduces the amount of data processing and improves voltage monitoring efficiency.

[0097] Furthermore, based on the above embodiments, the following embodiments illustrate the process of determining the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer according to the ring oscillator parameter information, and determining the holding time of the voltage corresponding to the second delay path according to the first delay data and the second delay data.

[0098] Please see Figure 3 , Figure 3 A flowchart illustrating a method for determining the holding time of a voltage in a second delay path, provided in an embodiment of this application, includes the following steps:

[0099] S301. Determine the first delay data of each delay unit in the ring oscillator based on the clock frequency of each ring oscillator and the total number of ring oscillators.

[0100] To facilitate understanding of the method in this embodiment, the following is combined with... Figure 4 To explain, Figure 4 This is a schematic diagram of a ring oscillator provided in an embodiment of this application. The ring oscillator can be an adjustable delay ring oscillator with a fixed delay.

[0101] In this embodiment, the delay unit is as follows: Figure 4 As shown, their number can be odd to form a ring oscillator.

[0102] Optionally, the first delay data of each delay unit It can be determined by the following formula (1):

[0103]

[0104] in, This indicates the clock frequency of the ring oscillator.

[0105] In this embodiment, the second delay path includes a transmission delay path, a data delay path, and an acquisition delay path, which can be specifically as follows: Figure 2 As shown, the first delay data may include the first data of the transmission delay path, the first data of the data delay path, and the first data of the capture delay path.

[0106] Specifically, based on the above formula, the first data of the transmission delay path can be determined according to the clock frequency of each ring oscillator on the transmission delay path and the total number of ring oscillators. .

[0107] Based on the clock frequencies of each ring oscillator along the data delay path and the total number of ring oscillators, the first data in the data delay path can be determined. .

[0108] Based on the clock frequencies of each ring oscillator on the capture delay path and the total number of ring oscillators, the first data of the capture delay path can be determined. .

[0109] S302. Determine the second delay data of the multiplexer based on the clock frequency of each ring oscillator cascaded with multiple multiplexers, the first delay data, and the total number of multiplexers.

[0110] In this embodiment, as Figure 4 As shown, the number of multiplexers can be illustrated by taking four as an example. Based on the monitoring of multiple multiplexers cascaded with each ring oscillator, i.e., RO+MUX, the second delay data of the cascaded four MUXs can be determined.

[0111] Optionally, the second delay data of the multiplexer It can be determined by the following formula (2):

[0112]

[0113] in, This indicates the total number of multiplexers.

[0114] Accordingly, since the second delay path includes a transmission delay path, a data delay path, and a capture delay path, the second delay data may include second data from the transmission delay path, second data from the data delay path, and second data from the capture delay path.

[0115] Specifically, based on the above formula, and according to the clock frequencies of the multiple multiplexers cascaded on each ring oscillator in the transmit delay path, the first data of the transmit delay path, and the total number of multiplexers, the second data of the transmit delay path can be determined. .

[0116] Based on the clock frequencies of the multiple multiplexers cascaded on each ring oscillator along the data delay path, the first data in the data delay path, and the total number of multiplexers, the second data in the data delay path can be determined. .

[0117] Based on the clock frequencies of the multiple multiplexers cascaded on each ring oscillator in the capture delay path, the first data in the capture delay path, and the total number of multiplexers, the second data in the capture delay path can be determined. .

[0118] S303. Based on the first delay data and the second delay data, determine the holding time of the voltage corresponding to the second delay path.

[0119] Based on the first data of the launch delay path, the second data of the launch delay path, and the total number of delay units in the launch delay path. The third delay data determines the launch delay path.

[0120] Optionally, the third delay data PL of the transmit delay path can be determined by the following formula (3):

[0121]

[0122] Based on the first data in the data delay path, the second data in the data delay path, and the total number of delay units in the data delay path. The fourth delay data in the data delay path is determined.

[0123] Optionally, the fourth delay data PD of the data delay path can be determined by the following formula (4):

[0124]

[0125] Based on the second data of the capture delay path, the second data of the capture delay path, and the total number of delay units in the capture delay path. The fifth delay data of the capture delay path is determined.

[0126] Optionally, the fifth delay data PC of the capture delay path can be determined by the following formula (5):

[0127]

[0128] Based on the third, fourth, and fifth delay data, determine the holding time of the voltage in the second delay path.

[0129] Optionally, the holding time of the voltage in the second delay path can be determined by the following formula (6). :

[0130]

[0131] When a digital voltage sensor monitors voltage, in the characterized test mode, the first delay path serves as the reference path. If the second delay path The corresponding CFAIL result is 0 if the second delay path... If so, the corresponding CFAIL result is 1.

[0132] By independently calculating the third delay data of the transmit path, the fourth delay data of the data path, and the fifth delay data of the acquisition path, the complete timing chain of signal transmission can be fully covered. The final hold time is determined by all three, ensuring that the voltage monitoring results can reflect the complete timing characteristics of signal transmission in the actual circuit and reducing the overall monitoring deviation caused by local path errors.

[0133] In the above embodiments of this application, by accurately calculating the first delay data corresponding to each delay unit inside the ring oscillator based on the clock frequency of each ring oscillator and the total number of ring oscillators, the inherent timing delay characteristics of the delay unit can be accurately characterized. Combined with the clock frequency of each ring oscillator after cascading into a multiplexer, the acquired first delay data, and the total number of multiplexers, the second delay data corresponding to the multiplexer can be reliably calculated, effectively quantifying the additional timing loss introduced by the multiplexer cascading link. Furthermore, based on the first and second delay data, the hold time of the corresponding voltage in the second delay path is accurately calibrated, establishing a stable and reliable correlation mapping relationship between voltage and timing hold parameters. In this embodiment, for each preset voltage, the delay data calculation and hold time calibration are completed according to the above process, ensuring that the timing parameters and hold time corresponding to each voltage are accurate, thereby generating high-precision voltage test configuration data, providing more accurate parameter support for subsequent real-time voltage detection, and further improving the accuracy and reliability of chip voltage testing.

[0134] Below, based on any of the above embodiments, the process of monitoring the real-time voltage of a chip according to voltage monitoring configuration data will be described through the following examples.

[0135] Please see Figure 5 , Figure 5 The following is a flowchart illustrating a method for monitoring the real-time voltage of a chip, provided as an embodiment of this application. The method may include the following steps:

[0136] S501, in response to the user's selection of multiple pre-configured voltages, determines the target voltage.

[0137] Before monitoring, the generated voltage test configuration data is imported into the configuration register of the digital voltage sensor to ensure that the digital voltage sensor can perform the test according to the preset parameters.

[0138] Responding to user operation commands, the system receives user selection of test voltage. Users can select the target voltage from multiple preset voltages according to actual test requirements.

[0139] S502. Based on the target voltage, determine the configuration data corresponding to the target voltage from the voltage monitoring configuration data.

[0140] After the user selects the target voltage, the system automatically matches the corresponding configuration parameters from the voltage monitoring configuration data. This configuration data can be quickly retrieved through a pre-defined mapping table, ensuring that no additional calibration is required during the monitoring process.

[0141] Based on the target voltage selected by the user, if a Hold violation occurs in the first delay path, the second delay path is configured as the test path. The test configuration data corresponding to the voltage is automatically retrieved, including the delay data and hold time parameters, to complete the rapid matching of test parameters.

[0142] It should be noted that the target voltage selected at this time has a second delay path that is a delay configuration that just avoids Hold violations.

[0143] S503. Under the configuration data, based on the monitoring signal output by the digital voltage sensor, and with the target voltage as the monitoring reference, the real-time voltage of the chip is monitored to obtain the voltage monitoring result.

[0144] Once the configuration data takes effect, the digital voltage sensor initiates monitoring based on the target voltage delay configuration. By comparing the real-time voltage with the target voltage, it outputs accurate monitoring results. This allows users to flexibly select different voltage references and quickly complete monitoring tasks.

[0145] Optionally, under the configuration data, the real-time voltage of the monitoring chip is monitored based on the monitoring signal output by the digital voltage sensor, and the real-time voltage is compared with the target voltage used as a monitoring reference.

[0146] If the comparison result indicates that the real-time voltage is greater than the target voltage, the output voltage monitoring result (CFAIL) indicating that the voltage exceeds the limit is 1. If the comparison result indicates that the real-time voltage is less than or equal to the target voltage, the output voltage monitoring result (CFAIL) indicating that the voltage does not exceed the limit is 0.

[0147] In the above embodiments of this application, a target voltage is selected in response to a user's selection operation of multiple preset voltages. Based on this target voltage, corresponding dedicated configuration data is retrieved from the voltage monitoring configuration data. Supported by the matched configuration data, the target voltage serves as a unified monitoring benchmark. Real-time voltage monitoring of the chip is completed using the monitoring signal output by the digital voltage sensor, and the monitoring results are output. This allows for flexible selection of different voltage benchmarks and adaptive configuration parameters according to actual monitoring needs, achieving rapid association and matching between the monitoring benchmark and configuration data. No additional parameter calibration or benchmark calibration process is required, simplifying the configuration process and operation steps of real-time voltage monitoring, thereby improving the flexibility, adaptability, and monitoring reliability of the chip's real-time voltage monitoring.

[0148] If the output is used to indicate voltage over-limit voltage monitoring results, it can also output early warning information.

[0149] In related technologies, voltage monitoring schemes are mostly static or semi-static designs, which can only determine whether the actual monitored voltage drops beyond the target voltage within a certain period of time, and cannot respond to voltage fluctuations in real time. However, the present application can also achieve continuous voltage monitoring.

[0150] Please see Figure 6 , Figure 6 A schematic diagram of a continuous monitoring loop is provided for an embodiment of this application, such as... Figure 6 As shown, if the output voltage monitoring result used to indicate voltage over-limit is CFAIL result 1, a voltage drop improvement operation is performed based on a preset improvement strategy. After receiving the information that CFAIL result is 1, a reset operation is performed on the register of the digital voltage sensor after a preset period to reset the current monitoring signal.

[0151] The reset digital voltage sensor then outputs a monitoring signal to continuously monitor the chip's real-time voltage.

[0152] Its timing diagram can be as follows Figure 7 As shown, Figure 7 This application provides a monitoring timing diagram, from which... Figure 7 As can be seen, when CFAIL is low (0), it means that no voltage abnormality has been detected and the system is in a normal state. The reset signal is low, indicating that the system has not been reset and remains in the default state.

[0153] When CFAIL goes high (1), it indicates that an alarm has been triggered. When the reset signal goes high, the register inside the digital voltage sensor will be forcibly cleared to remove the overvoltage alarm state and prepare for the next monitoring.

[0154] When CFAIL goes low (0), the reset is complete. After the reset is complete, the reset signal is pulled low, the digital voltage sensor resumes operation, and the next round of voltage detection begins.

[0155] Because CFAIL is a latched signal, once an anomaly is detected, it will remain high and will not automatically revert to its previous level. Without a reset signal, even if the voltage later returns to normal, CFAIL will remain at 1, mistakenly indicating that the voltage has been exceeding the limit. Therefore, it needs to be actively cleared to zero via a reset signal to allow the digital voltage sensor to continue operating and thus achieve continuous monitoring of the chip voltage.

[0156] The reset operation clears the states of all triggers and timing units by pulling a global reset signal high, and forces the digital voltage sensor registers back to their default configuration. After the reset, the voltage monitoring configuration data corresponding to the user-selected target voltage must be reloaded to ensure that the monitoring signal is output based on the latest configuration parameters. This process can reduce abnormal monitoring results caused by failure to update the configuration after a reset.

[0157] When the output voltage exceeds the limit (CFAIL=1), a warning message is triggered, and a reset operation is performed on the digital voltage sensor's register after a preset period. The reset operation clears the state of all triggers and timing units by pulling a global reset signal high, restoring the digital voltage sensor to its default configuration. After the reset is complete, the monitoring signal is output again to continuously monitor the chip voltage. This reset mechanism ensures that the monitoring process can be executed cyclically, avoiding system lock-up due to a single anomaly, thus achieving dynamic and continuous monitoring.

[0158] In this application, during the operation of various high-performance digital chips, the actual operating voltage of each functional module and the internal system of the chip can be dynamically monitored in real time by relying on the built-in digital voltage sensor and timing delay calibration mechanism. This allows for accurate identification of voltage drop and voltage fluctuations, and the monitoring results are fed back to the chip's main control system, such as a processor. The processor can then promptly adopt adaptive strategies such as voltage compensation and operating frequency reduction based on the feedback results, thereby achieving online dynamic monitoring and adaptive control of the chip's voltage state.

[0159] This application can be applied to chip application scenarios such as industrial-grade, automotive-grade, and high-performance CPUs, which have stringent requirements for operational stability and timing margins and prominent voltage drop issues. At the same time, it eliminates the need for extensive repeated sampling and calibration of the same voltage, thereby shortening the chip voltage characterization and testing time and reducing chip testing costs.

[0160] Furthermore, the digital voltage sensor used in this application can measure the voltage drop data of batch chips under actual operating conditions. The measured real results are compared with static timing analysis and simulation data for correlation analysis. By comparing the deviation between the measured and simulated data, the analysis conclusions are fed back to the front-end simulation modeling process to guide the optimization and iteration of simulation parameters, topology models and constraints, gradually reducing the deviation between simulation and actual chip operating conditions, and improving the accuracy of subsequent chip design and simulation prediction.

[0161] Furthermore, this application relies on a digital voltage sensor to generate voltage test configuration data by calibrating delay data and hold time under different voltages. This allows for real-time monitoring of the chip's internal voltage and threshold comparison, accurately capturing voltage drops and voltage anomalies. When the chip experiences functional abnormalities or test failures, it can synchronously correlate the voltage monitoring data at the time of the fault, quickly determining whether the failure was caused by an unexpected abnormal voltage drop. This eliminates the need to check timing, circuitry, and other factors one by one, thereby achieving rapid fault mode localization and significantly shortening debugging and troubleshooting time.

[0162] During the chip engineering verification and performance analysis phase, the actual voltage drop characteristics of the chip can be measured and collected based on this application. The highest operating voltage that the chip can actually work stably can be determined accordingly, rather than simply relying on the theoretical maximum voltage obtained by simulation. The actual measured results are used as the basis for performance evaluation, effectively exploring the chip voltage margin and performance improvement space, and providing reliable measured data support for chip performance optimization, voltage level configuration and mass production specification definition.

[0163] Please see Figure 8 , Figure 8 This is a schematic diagram of a chip voltage monitoring device provided in an embodiment of this application. Applied to a chip, the chip is equipped with a digital voltage sensor. The digital voltage sensor includes a first delay path, a second delay path, and multiple ring oscillators. Each ring oscillator includes multiple multiplexers and multiple delay units. The first delay path is configured as a reference path for persistent hold-time violations. Figure 8 As shown, the apparatus provided in this embodiment includes:

[0164] The acquisition module 801 is used to acquire multiple pre-configured voltages.

[0165] The acquisition module 801 is also used to acquire the ring oscillator parameter information corresponding to the second delay path under any voltage for any voltage.

[0166] The determination module 802 is used to determine the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer based on the ring oscillator parameter information.

[0167] The determining module 802 is also used to determine the holding time of the voltage in the second delay path based on the first delay data and the second delay data.

[0168] The generation module 803 is used to generate voltage monitoring configuration data based on the holding time of each voltage in the second delay path.

[0169] The monitoring module 804 is used to monitor the real-time voltage of the chip based on the voltage monitoring configuration data.

[0170] In one possible implementation, the ring oscillator parameter information includes the clock frequency of each ring oscillator, the total number of ring oscillators, the clock frequencies of multiple multiplexers cascaded with each ring oscillator, and the total number of multiplexers. The determination module 802 is specifically used for:

[0171] Based on the clock frequency of each ring oscillator and the total number of ring oscillators, determine the first delay data of each delay unit in the ring oscillator.

[0172] The second delay data of the multiplexer is determined based on the clock frequency of each ring oscillator cascaded with multiple multiplexers, the first delay data, and the total number of multiplexers.

[0173] In one possible implementation, the second delay path includes a transmit delay path, a data delay path, and an acquisition delay path; the first delay data includes first data from the transmit delay path, first data from the data delay path, and first data from the acquisition delay path; and the second delay data includes second data from the transmit delay path, second data from the data delay path, and second data from the acquisition delay path. The determining module 802 is specifically used for:

[0174] The third delay data of the launch delay path is determined based on the first data of the launch delay path, the second data of the launch delay path, and the total number of delay units in the launch delay path.

[0175] The fourth delay data of the data delay path is determined based on the first data of the data delay path, the second data of the data delay path, and the total number of delay units in the data delay path.

[0176] The fifth delay data of the capture delay path is determined based on the second data of the capture delay path, the second data of the capture delay path, and the total number of delay units in the capture delay path.

[0177] Based on the third, fourth, and fifth delay data, determine the holding time of the voltage in the second delay path.

[0178] In one possible implementation, the monitoring module 804 is specifically used for:

[0179] In response to the user's selection of multiple pre-configured voltages, the target voltage is determined.

[0180] Based on the target voltage, determine the configuration data corresponding to the target voltage from the voltage monitoring configuration data.

[0181] Under the configured data, based on the monitoring signal output by the digital voltage sensor, and with the target voltage as the monitoring reference, the real-time voltage of the chip is monitored to obtain the voltage monitoring result.

[0182] In one possible implementation, the monitoring module 804 is specifically used for:

[0183] Under the configured data, the real-time voltage of the monitoring chip is monitored based on the monitoring signal output by the digital voltage sensor.

[0184] The real-time voltage is compared with the target voltage, which serves as the monitoring benchmark.

[0185] If the comparison result indicates that the real-time voltage is greater than the target voltage, then the voltage monitoring result used to indicate that the voltage exceeds the limit will be output.

[0186] If the comparison result indicates that the real-time voltage is less than or equal to the target voltage, then the voltage monitoring result is output to indicate that the voltage does not exceed the limit.

[0187] In one possible implementation, the monitoring module 804 is also used for:

[0188] If the output is a voltage monitoring result used to indicate that the voltage is out of limit, an early warning message will be output, and after a preset period, a reset operation will be performed on the register of the digital voltage sensor to reset the current monitoring signal.

[0189] The reset digital voltage sensor then outputs a monitoring signal to continuously monitor the chip's real-time voltage.

[0190] The chip voltage monitoring device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0191] Figure 9 This is a schematic diagram of a chip structure provided in an embodiment of this application. Figure 9 As shown, the chip provided in this embodiment includes a digital voltage sensor and a memory.

[0192] Optionally, the chip may also include a processor and communication components. The digital voltage sensor, processor, memory, and communication components are connected via a bus.

[0193] In the specific implementation process, the digital voltage sensor executes the computer execution instructions stored in the memory, causing at least one digital voltage sensor to perform the above method.

[0194] The specific implementation process of the digital voltage sensor can be found in the above method embodiment, and its implementation principle and technical effect are similar, so it will not be repeated here.

[0195] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0196] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0197] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0198] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0199] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0200] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory, electrically erasable programmable read-only memory, erasable programmable read-only memory, programmable read-only memory, read-only memory, magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0201] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0202] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0203] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0204] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0205] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0206] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0207] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method of monitoring a voltage of a chip, characterized by, The method is applied to a chip equipped with a digital voltage sensor, the digital voltage sensor including a first delay path, a second delay path, and multiple ring oscillators, each ring oscillator including multiple multiplexers and multiple delay units, the first delay path being configured as a reference path for persistent hold-time violations, the method including: Obtain multiple pre-configured voltages; For any voltage, obtain the ring oscillator parameter information corresponding to the second delay path under the voltage; Based on the ring oscillator parameter information, determine the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer; Based on the first delay data and the second delay data, determine the holding time of the voltage in the second delay path; Based on the holding time of each voltage in the second delay path, voltage monitoring configuration data is generated; The real-time voltage of the chip is monitored based on the voltage monitoring configuration data.

2. The method of claim 1, wherein, The ring oscillator parameter information includes the clock frequency of each ring oscillator, the total number of ring oscillators, the clock frequency of multiple multiplexers cascaded with each ring oscillator, and the total number of multiplexers. The step of determining the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer based on the ring oscillator parameter information includes: Based on the clock frequency of each ring oscillator and the total number of ring oscillators, determine the first delay data of each delay unit in the ring oscillator; The second delay data of the multiplexer is determined based on the clock frequency of each ring oscillator cascaded with multiple multiplexers, the first delay data, and the total number of multiplexers.

3. The method of claim 2, wherein, The second delay path includes a transmission delay path, a data delay path, and a capture delay path; the first delay data includes first data of the transmission delay path, first data of the data delay path, and first data of the capture delay path; and the second delay data includes second data of the transmission delay path, second data of the data delay path, and second data of the capture delay path. The step of determining the holding time of the voltage in the second delay path based on the first delay data and the second delay data includes: Based on the first data of the transmission delay path, the second data of the transmission delay path, and the total number of delay units in the transmission delay path, the third delay data of the transmission delay path is determined; The fourth delay data of the data delay path is determined based on the first data of the data delay path, the second data of the data delay path, and the total number of delay units in the data delay path; The fifth delay data of the capture delay path is determined based on the second data of the capture delay path, the second data of the capture delay path, and the total number of delay units in the capture delay path; Based on the third delay data, the fourth delay data, and the fifth delay data, the holding time of the voltage in the second delay path is determined.

4. The method according to any one of claims 1 to 3, characterized in that, The step of monitoring the real-time voltage of the chip according to the voltage monitoring configuration data includes: In response to the user's selection of one of the pre-configured voltages, a target voltage is determined; Based on the target voltage, determine the configuration data corresponding to the target voltage from the voltage monitoring configuration data; Under the configured data, based on the monitoring signal output by the digital voltage sensor and using the target voltage as the monitoring reference, the real-time voltage of the chip is monitored to obtain the voltage monitoring result.

5. The method of claim 4, wherein, Under the configured data, based on the monitoring signal output by the digital voltage sensor and using the target voltage as the monitoring reference, the real-time voltage of the chip is monitored to obtain the voltage monitoring result, including: Under the configuration data, the real-time voltage of the chip is monitored based on the monitoring signal output by the digital voltage sensor; The real-time voltage is compared with the target voltage, which serves as the monitoring benchmark; If the comparison result indicates that the real-time voltage is greater than the target voltage, then output the voltage monitoring result indicating that the voltage exceeds the limit; If the comparison result indicates that the real-time voltage is less than or equal to the target voltage, then a voltage monitoring result indicating that the voltage does not exceed the limit is output.

6. The method of claim 5, wherein, Also includes: If the output is a voltage monitoring result used to indicate that the voltage is over the limit, then an early warning message is output, and after a preset period, a reset operation is performed on the register of the digital voltage sensor to reset the current monitoring signal. The reset digital voltage sensor then outputs a monitoring signal to continuously monitor the real-time voltage of the chip.

7. A monitoring device for a chip voltage, characterized by The device is applied to a chip equipped with a digital voltage sensor, the digital voltage sensor including a first delay path, a second delay path, and multiple ring oscillators, each ring oscillator including multiple multiplexers and multiple delay units, the first delay path being configured as a reference path for persistent hold-time violations, the device comprising: The acquisition module is used to acquire multiple pre-configured voltages; The acquisition module is further configured to acquire, for any voltage, the ring oscillator parameter information corresponding to the second delay path under the voltage; The determining module is used to determine the first delay data of each delay unit in the ring oscillator and the second delay data of the multiplexer based on the ring oscillator parameter information. The determining module is further configured to determine the holding time of the voltage in the second delay path based on the first delay data and the second delay data; The generation module is used to generate voltage monitoring configuration data based on the holding time of each voltage in the second delay path. The monitoring module is used to monitor the real-time voltage of the chip according to the voltage monitoring configuration data.

8. A chip, characterized by include: A digital voltage sensor and a memory, wherein the digital voltage sensor includes a first delay path, a second delay path and multiple ring oscillators, and each ring oscillator includes multiple multiplexers and multiple delay units; The memory stores computer-executed instructions; The digital voltage sensor executes computer execution instructions stored in the memory, causing the digital voltage sensor to perform the method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.

10. A computer program product, characterised in that, Includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-6.

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