Clock synchronization-based substation surge arrester centralized monitoring system and method

Abstract

This invention belongs to the field of substation monitoring, and particularly relates to a centralized monitoring system and method for substation surge arresters based on clock synchronization. The system includes: distributing synchronization pulses in parallel to current or voltage acquisition nodes distributed across all voltage levels and intervals of the substation via a clock synchronization module to force sampling edge alignment; the centralized monitoring host performing windowed fast Fourier transform on leakage current and bus voltage signals carrying the same timestamp and extracting the fundamental component of resistive current based on the fundamental phase projection of the bus voltage; then performing spatial constraint verification based on the vector synthesis result of the fundamental vector of leakage current within the three-phase surge arrester group to eliminate invalid data caused by electromagnetic interference; finally, collecting the verified and marked valid fundamental components of resistive current, statistically analyzing their average value and growth rate according to a preset period, and generating an early warning signal based on dual safety limits.

Description

Technical Field

[0001] This invention belongs to the field of substation monitoring, and particularly relates to a centralized monitoring system and method for substation surge arresters based on clock synchronization. Background Technology

[0002] In substation operation, metal oxide surge arresters are key devices for limiting overvoltage and protecting insulation coordination. Their operating status is mainly determined by online monitoring of leakage current and extracting the resistive component. Due to the large number and wide distribution of surge arresters throughout the substation, and the complex electromagnetic environment, the weak resistive current in the leakage current is easily overwhelmed by the capacitive current background and harmonic interference. Therefore, how to achieve centralized and high-precision online monitoring of multiple surge arresters throughout the substation has always been a technical challenge in this field.

[0003] In the prior art, patent application CN114301168A discloses an intelligent surge arrester system suitable for substations. This system independently configures a data acquisition module and an EMI filter on each surge arrester. After acquiring and filtering leakage current and voltage signals, it uses a resistive current calculation module to calculate the resistive current value based on IR = I × cosα and compares it with a preset threshold to determine anomalies. This scheme also uses an infrared thermal imager to assist in detecting surface temperature differences. However, this scheme only achieves independent monitoring of a single surge arrester. There is a lack of unified high-precision clock synchronization and centralized processing mechanisms between monitoring units, resulting in the inability to perform cross-bay mutual verification and correlation analysis of the measurement data from each surge arrester. When the grid voltage fluctuates or complex harmonics exist, the simple phase angle-based calculation method is prone to introducing large errors, and the EMI filter cannot completely eliminate the interference of strong electromagnetic environments on phase measurements, easily leading to misjudgments.

[0004] Patent application CN112098763A discloses a method for live detection and online monitoring of surge arresters in substations. This method synchronously measures the grounding lead current of each phase within the same three-phase surge arrester group, utilizes the phase angle difference locking relationship between the three-phase leakage currents, and calculates resistive current and power data using high-order FFT, avoiding the short-circuit risk associated with obtaining voltage signals from voltage transformers. While this method achieves correlation analysis within a single three-phase group, its synchronous measurement and correlation calculation are limited to a few surge arresters within the same three-phase group and cannot be extended to all surge arresters of different voltage levels and intervals within the substation. Furthermore, its resistive current calculation relies on the assumption of three-phase voltage symmetry; when the system operates asymmetrically or contains abundant interharmonics, the calculation accuracy will significantly decrease. In addition, this method does not address high-precision synchronization methods between multiple widely distributed acquisition points across the entire substation, nor does it address the centralized fusion of multi-source data, making it difficult to meet the needs of centralized online monitoring across the entire substation for multi-point redundancy verification and comprehensive status assessment.

[0005] Chinese patent CN113608031B discloses a method for monitoring the impulse impedance of surge arresters in substations. It determines the presence of lightning by acquiring the electric field value of high-altitude clouds. When lightning is present, the impulse impedance is calculated based on measured current and voltage; when no lightning is present, the impulse impedance is simulated using the finite-difference time-domain method. This method falls under the category of monitoring transient impulse parameters and cannot be applied to continuous online monitoring of the slow aging process of surge arrester varistors under power frequency operating voltage.

[0006] In summary, how to construct a centralized monitoring architecture capable of high-precision synchronous aggregation and spatial correlation analysis of dispersed leakage current signals from multiple intervals and voltage levels in a strong electromagnetic interference environment with wide-area distribution across the entire station, in order to overcome the problems of low resistive current extraction accuracy and high state misjudgment rate caused by the lack of redundancy verification in independent monitoring and the reliance of algorithms on ideal operating conditions, still needs to be solved. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention proposes a centralized monitoring system and method for substation surge arresters based on clock synchronization. The system includes: distributing synchronization pulses in parallel to current or voltage acquisition nodes distributed across all voltage levels and intervals in the substation via a clock synchronization module to force sampling edge alignment; the centralized monitoring host performing windowed fast Fourier transform on leakage current and bus voltage signals carrying the same timestamp and extracting the fundamental component of resistive current based on the fundamental phase projection of the bus voltage; then performing spatial constraint verification based on the vector synthesis result of the fundamental vector of leakage current within the three-phase surge arrester group to eliminate invalid data caused by electromagnetic interference; finally, collecting the verified and marked valid fundamental components of resistive current, statistically analyzing their average value and growth rate according to a preset period, and generating early warning signals based on dual safety limits.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] A clock-synchronized centralized monitoring system for substation surge arresters includes:

[0010] The clock synchronization module is used to generate a unified time synchronization pulse and distribute the time synchronization pulse in parallel to all current acquisition nodes or voltage acquisition nodes in the entire station, so as to force the sampling edges of each current acquisition node or voltage acquisition node to be aligned.

[0011] The current acquisition module is configured with m current acquisition nodes to acquire m leakage current digital signals with a first timestamp.

[0012] The voltage acquisition module is configured with n voltage acquisition nodes to acquire n digital voltage signals with the first timestamp attached.

[0013] The centralized monitoring host is configured to: acquire the leakage current digital signal and the voltage digital signal carrying the same first timestamp; perform windowed fast Fourier transform on the leakage current digital signal and the voltage digital signal within the same time window; and extract the leakage current fundamental vector constructed by the leakage current fundamental amplitude and leakage current fundamental phase of each surge arrester, as well as the bus voltage fundamental amplitude and bus voltage fundamental phase from the transformation result.

[0014] Using the fundamental phase of the bus voltage as a reference phase, the fundamental vector of the leakage current of each surge arrester is projected onto the direction determined by the reference phase, and the real part of the projection is taken as the fundamental component of the current resistive current of the corresponding surge arrester.

[0015] Based on the electrical bay assignment relationship of surge arresters in the substation, all surge arresters in the substation are divided into multiple three-phase surge arrester groups. For any three-phase surge arrester group, the leakage current fundamental vectors of the A-phase surge arrester, B-phase surge arrester and C-phase surge arrester in the corresponding group are obtained at the same sampling time, and the three leakage current fundamental vectors are vector synthesized to obtain the synthesized vector.

[0016] Specifically, the centralized monitoring host is also configured as follows:

[0017] The magnitude of the synthesized vector is calculated and compared with a preset zero-sequence deviation allowable threshold. If the magnitude is greater than the zero-sequence deviation allowable threshold, it is determined that the measurement of the group is subject to electromagnetic interference, and the fundamental component of the resistive current obtained by all surge arresters in the group is marked as invalid data; otherwise, it is marked as valid data.

[0018] The fundamental component of resistive current, which is marked as valid data from the entire station, is collected. According to the preset evaluation period, the average resistive current and the resistive current growth rate within the corresponding evaluation period are calculated for each surge arrester. When the average resistive current of any surge arrester exceeds the first safety limit or the resistive current growth rate exceeds the second safety limit, an early warning signal is generated.

[0019] Specifically, the sampling edges of each current acquisition node or voltage acquisition node are forced to align, including:

[0020] A reference synchronization pulse is generated as the basis for the time synchronization pulse, and the reference synchronization pulse is distributed to all current acquisition nodes or voltage acquisition nodes in the entire station via a transmission link;

[0021] The propagation delay of the reference synchronization pulse on each transmission link is measured to obtain the relative delay difference between each transmission link and the reference link.

[0022] For each transmission link, the reference synchronization pulse is pre-delayed based on the relative time delay difference, so that the time deviation of the compensated reference synchronization pulse arriving at each current acquisition node or voltage acquisition node falls within the preset synchronization error tolerance.

[0023] Specifically, forcing the sampling edges of each current or voltage acquisition node to align also includes:

[0024] Each current acquisition node or voltage acquisition node receives a reference synchronization pulse after pre-delay compensation. The edge of the reference synchronization pulse triggers the local phase-locked loop of the node. The phase-locked loop filters out electromagnetic interference jitter coupled by the transmission link and regenerates a local sampling clock that is fixed to the edge of the reference synchronization pulse.

[0025] The analog-to-digital conversion circuit of each current or voltage acquisition node performs sampling at the effective edge of the local sampling clock, so that the sampling points of all current or voltage acquisition nodes in the entire station are aligned on the absolute time axis.

[0026] Specifically, the leakage current digital signal and the voltage digital signal within the same time window are subjected to windowed Fast Fourier Transform, including:

[0027] From the leakage current digital signal and the voltage digital signal carrying the same first timestamp, extract leakage current data sequence and voltage data sequence with a time length equal to an integer multiple of the power frequency period;

[0028] The leakage current data sequence is segmented according to the power frequency cycle, and the root mean square value of each power frequency cycle segment is calculated. The power frequency cycle segment whose root mean square value exceeds a preset multiple of the root mean square value of the entire leakage current data sequence is determined as a transient interference pollution segment, and the data points in the leakage current data sequence and the voltage data sequence corresponding to the transient interference pollution segment are set to zero.

[0029] The leakage current data sequence and the voltage data sequence after being zeroed are multiplied point by point by the Hanning window function to obtain the windowed leakage current data sequence and the windowed voltage data sequence.

[0030] Specifically, performing windowed fast Fourier transforms on the leakage current digital signal and the voltage digital signal within the same time window further includes:

[0031] For the windowed leakage current data sequence and the windowed voltage data sequence, respectively, perform radix-2 time decimation fast Fourier transform to obtain the complex spectrum sequence of leakage current and the complex spectrum sequence of voltage;

[0032] In the complex spectrum sequence of the leakage current, the three consecutive frequency points with the largest modulus are selected. The modulus values ​​of the three frequency points and the corresponding frequency values ​​are substituted into the three-point amplitude interpolation correction formula to calculate the fundamental frequency, fundamental amplitude and fundamental phase of the leakage current.

[0033] Using the calculated fundamental frequency of the leakage current as the index frequency, the frequency point closest to the corresponding index frequency is selected in the complex spectrum sequence of the voltage. Three-point phase interpolation correction is performed on the complex spectrum values ​​of the frequency point and its two adjacent frequency points to obtain the fundamental amplitude and phase of the bus voltage.

[0034] Specifically, projecting the fundamental vector of the leakage current of each surge arrester onto the direction determined by the reference phase includes:

[0035] Read the fundamental amplitude of the leakage current, the fundamental phase of the leakage current, the fundamental amplitude of the bus voltage, and the fundamental phase of the bus voltage;

[0036] Read the pre-calibrated first fixed phase hysteresis and the second fixed phase hysteresis;

[0037] Subtracting the first fixed phase lag from the fundamental phase of the leakage current yields the corrected fundamental phase of the leakage current.

[0038] Subtracting the second fixed phase lag from the fundamental phase of the bus voltage yields the corrected fundamental phase of the bus voltage.

[0039] Subtracting the corrected fundamental phase of the bus voltage from the corrected fundamental phase of the leakage current yields the voltage-current phase difference.

[0040] Calculate the cosine value of the phase difference between the voltage and current;

[0041] Multiply the fundamental amplitude of the leakage current by the cosine of the phase difference between the voltage and current, and the resulting product is taken as the fundamental component of the current resistive current of the surge arrester.

[0042] Specifically, for each surge arrester, the average resistive current and the resistive current growth rate within the corresponding evaluation period are calculated, including:

[0043] For each surge arrester, with a preset evaluation period as the time window, all fundamental components of resistive current marked as valid data within the current evaluation period are extracted from the historical resistive current data table of the surge arrester to form an evaluation sample sequence.

[0044] The number of sample points in the evaluation sample sequence is counted. When the number of sample points is less than the preset minimum sample number threshold, the calculation of the average resistive current and the resistive current growth rate for this evaluation period is abandoned, and a data shortage mark is generated.

[0045] When the number of sample points is greater than or equal to the minimum sample number threshold, the fundamental components of resistive current in the evaluation sample sequence are sorted according to their numerical values, and the first preset proportion of sample points with the largest values ​​and the second preset proportion of sample points with the smallest values ​​are removed from the sorted sequence to obtain the extreme value removal sample sequence.

[0046] Specifically, for each surge arrester, the calculation of the average resistive current and the resistive current growth rate within the corresponding evaluation period also includes:

[0047] Calculate the arithmetic mean of the extreme value sample sequence as the average resistive current for this evaluation period, and store the average resistive current in the historical sequence of the average resistive current of the surge arrester.

[0048] When the number of consecutively stored resistive current average values ​​in the historical sequence of resistive current average values ​​reaches the preset fitting window length, the least squares linear fitting is performed on the most recent resistive current average values ​​within the fitting window length, with the storage sequence number in the historical sequence of resistive current average values ​​as the horizontal axis and the resistive current average value as the vertical axis. The slope of the fitted straight line is then used as the resistive current growth rate for the current evaluation period.

[0049] A centralized monitoring method for substation surge arresters based on clock synchronization includes:

[0050] A unified time synchronization pulse is generated and distributed in parallel to all current acquisition nodes or voltage acquisition nodes in the entire station to force the sampling edges of each current acquisition node or voltage acquisition node to align.

[0051] Acquire m digital leakage current signals with their first timestamps;

[0052] Acquire n digital voltage signals with the first timestamp attached;

[0053] Obtain the leakage current digital signal and the voltage digital signal carrying the same first timestamp, perform windowed fast Fourier transform on the leakage current digital signal and the voltage digital signal within the same time window, and extract the leakage current fundamental vector constructed by the leakage current fundamental amplitude and leakage current fundamental phase of each surge arrester, as well as the bus voltage fundamental amplitude and bus voltage fundamental phase from the transformation result.

[0054] Using the fundamental phase of the bus voltage as a reference phase, the fundamental vector of the leakage current of each surge arrester is projected onto the direction determined by the reference phase, and the real part of the projection is taken as the fundamental component of the current resistive current of the surge arrester.

[0055] Specifically, centralized monitoring methods for surge arresters in substations also include:

[0056] Based on the electrical bay assignment relationship of surge arresters in the substation, all surge arresters in the substation are divided into multiple three-phase surge arrester groups. For any three-phase surge arrester group, the leakage current fundamental vectors of the A-phase surge arrester, B-phase surge arrester and C-phase surge arrester in the group are obtained at the same sampling time, and the three leakage current fundamental vectors are vector synthesized to obtain the synthesized vector.

[0057] Calculate the magnitude of the synthesized vector and compare it with a preset zero-sequence deviation allowable threshold. If the magnitude is greater than the zero-sequence deviation allowable threshold, it is determined that the measurement of this group is subject to electromagnetic interference, and the fundamental component of the resistive current obtained by all surge arresters in this group is marked as invalid data; otherwise, it is marked as valid data.

[0058] The fundamental component of resistive current, which is marked as valid data from the entire station, is collected. According to the preset evaluation period, the average resistive current and the resistive current growth rate within the evaluation period are calculated for each surge arrester. When the average resistive current of any surge arrester exceeds the first safety limit or its resistive current growth rate exceeds the second safety limit, an early warning signal is generated.

[0059] Compared with the prior art, the beneficial effects of the present invention are:

[0060] This invention establishes a unified high-precision clock synchronization mechanism across the entire station, forcing current or voltage acquisition nodes distributed across different electrical bays to sample synchronously under the same time reference. This eliminates time mismatch errors between widely distributed nodes, providing a precise time-scale basis for vector synthesis and phase projection of cross-bay leakage current. The centralized monitoring host performs a windowed fast Fourier transform using leakage current and bus voltage signals with the same timestamp, projecting the fundamental vector of the leakage current with the fundamental phase of the bus voltage as a reference. This accurately extracts the weak resistive current fundamental component from a strongly capacitive background, effectively suppressing measurement errors introduced by grid harmonics and phase drift. In particular, a spatial constraint verification is constructed based on the three-phase electrical bay assignment of the surge arresters throughout the station, and vector synthesis of the three-phase leakage current fundamental vector within the group is performed. The comparison between the synthetic vector magnitude and the zero-sequence deviation allowable threshold serves as a criterion for data validity. This allows for the automatic identification and elimination of abnormal measurement data affected by electromagnetic interference or three-phase transient imbalance, retaining only reliable data that conforms to Kirchhoff's current law for subsequent analysis. This fundamentally overcomes the inherent defects of single-point independent monitoring, which cannot perform redundant verification and is prone to misjudgment. During long-term operation, the system collects the fundamental components of resistive current that are marked as valid after spatial constraint verification across the entire substation. By statistically analyzing the average value and growth rate of resistive current according to a preset evaluation cycle and setting dual safety limits for early warning, the system can sensitively capture the slow growth trend of resistive current caused by progressive insulation defects such as moisture and aging of valve plates. This enables highly reliable and accurate centralized online monitoring and early risk warning of the operating status of surge arresters throughout the substation. Attached Figure Description

[0061] Figure 1 This is a logic diagram of a clock-synchronized centralized monitoring system for substation surge arresters according to an embodiment of the present invention.

[0062] Figure 2 This is a flowchart of the fast Fourier transform (FFT) process performed on the digital leakage current signal and the digital voltage signal within the same time window in Embodiment 2 of the present invention.

[0063] Figure 3 This is a flowchart of Example 4 of the present invention, which calculates the average resistive current and the resistive current growth rate for each surge arrester during the evaluation period. Detailed Implementation

[0064] Example 1

[0065] Please see Figure 1 One embodiment of the present invention provides a clock-synchronized centralized monitoring system for substation surge arresters, comprising:

[0066] The clock synchronization module is used to generate a unified time synchronization pulse and distribute the time synchronization pulse in parallel to all current acquisition nodes or voltage acquisition nodes in the entire station, so as to force the sampling edges of each current acquisition node or voltage acquisition node to be aligned.

[0067] The current acquisition module is configured with m current acquisition nodes, which are installed one-to-one on the grounding lead of each surge arrester in the substation. Each current acquisition node includes a current sensor and a first analog-to-digital conversion circuit. The first analog-to-digital conversion circuit synchronously samples the leakage current under the trigger of the time synchronization pulse and acquires m leakage current digital signals with a first timestamp; where m is an integer greater than 1.

[0068] The voltage acquisition module is configured with n voltage acquisition nodes, the input of which is connected to the secondary side of the substation bus voltage transformer. Each voltage acquisition node includes a second analog-to-digital converter circuit. The second analog-to-digital converter circuit synchronously samples the bus voltage under the trigger of the time synchronization pulse and acquires n voltage digital signals with the first timestamp attached; where n is an integer greater than or equal to 1.

[0069] A centralized monitoring host is connected to the current or voltage acquisition node via a communication network, and the centralized monitoring host is configured to perform the following operations:

[0070] Obtain the leakage current digital signal and the voltage digital signal carrying the same first timestamp, perform windowed fast Fourier transform on the leakage current digital signal and the voltage digital signal within the same time window, and extract the leakage current fundamental vector constructed by the leakage current fundamental amplitude and leakage current fundamental phase of each surge arrester, as well as the bus voltage fundamental amplitude and bus voltage fundamental phase from the transformation result.

[0071] Using the fundamental phase of the bus voltage as a reference phase, the fundamental vector of the leakage current of each surge arrester is projected onto the direction determined by the reference phase, and the real part of the projection is taken as the fundamental component of the current resistive current of the surge arrester.

[0072] Based on the electrical bay assignment relationship of surge arresters in the substation, all surge arresters in the substation are divided into multiple three-phase surge arrester groups. For any three-phase surge arrester group, the leakage current fundamental vectors of the A-phase surge arrester, B-phase surge arrester and C-phase surge arrester in the group are obtained at the same sampling time, and the three leakage current fundamental vectors are vector synthesized to obtain the synthesized vector.

[0073] Calculate the magnitude of the synthesized vector and compare it with a preset zero-sequence deviation allowable threshold. If the magnitude is greater than the zero-sequence deviation allowable threshold, it is determined that the measurement of this group is subject to electromagnetic interference, and the fundamental component of the resistive current obtained by all surge arresters in this group is marked as invalid data; otherwise, it is marked as valid data.

[0074] The fundamental component of resistive current, which is marked as valid data from the entire station, is collected. According to the preset evaluation period, the average resistive current and the resistive current growth rate within the evaluation period are calculated for each surge arrester. When the average resistive current of any surge arrester exceeds the first safety limit or its resistive current growth rate exceeds the second safety limit, an early warning signal is generated.

[0075] As a concrete example, the complete operation of a centralized online monitoring system for surge arresters in a 220kV substation at 10:00 AM on a certain day will be used for illustration. This substation has 36 zinc oxide surge arresters distributed across eight electrical bays at three voltage levels: 220kV, 110kV, and 10kV. Each surge arrester has a current acquisition node installed on its grounding lead. Additionally, one voltage acquisition node is installed on the secondary side of each of the 220kV and 110kV bus voltage transformers, for a total of 38 acquisition nodes. The clock synchronization module is installed in the main control room cabinet and contains a disciplined chip-level atomic clock. It undergoes long-term frequency calibration by receiving timing signals from the BeiDou satellite navigation system. After calibration, the output reference synchronization pulse is a square wave with a rise time of approximately 800 picoseconds and a repetition frequency of 1 Hz. The rise time of each pulse is aligned with the exact second of Coordinated Universal Time (UTC), achieving a long-term frequency accuracy on the order of ±1×10⁻¹². The reference synchronization pulse is distributed to all acquisition nodes in the station via 38 single-mode optical fibers of varying lengths. During the system initialization phase, the clock synchronization module measures the unidirectional propagation delay of each optical fiber link through a link-by-link loopback test. Using the optical fiber connected to the acquisition node of the main transformer as the reference link, the relative delay difference of each link is calculated and stored in a register. Under normal operation, the clock synchronization module adjusts the delay of the corresponding programmable delay line in real time according to the relative delay difference of each link, so that the time deviation of the 38 synchronization pulses arriving at the input of the photoelectric converter of each remote acquisition node is controlled within ±8 nanoseconds, which meets the preset ±10 nanosecond synchronization error tolerance requirement. The preset ±10 nanosecond synchronization error tolerance is based on the following: Since the residual time deviation of the sampling time of each current acquisition node in the entire station will be directly converted into the phase measurement error between the fundamental wave vectors of the leakage current of each phase in the three-phase surge arrester group, this phase error will generate a false residual composite vector during vector synthesis. In order to ensure that the magnitude of this false residual composite vector is much smaller than the zero-sequence deviation allowable threshold used for discrimination under normal operating conditions, and to avoid the misjudgment of valid data as invalid due to synchronization error, the synchronization deviation between each acquisition node needs to be controlled at the nanosecond level. After analysis, for a power system with a rated frequency of 50 Hz, the power frequency fundamental wave phase error caused by a ±10 nanosecond time deviation is only ±0.00018 degrees. The resulting fluctuation in the magnitude of the three-phase leakage current fundamental wave vector synthesis is negligible compared to the preset zero-sequence deviation allowable threshold, thus ensuring the reliability of the spatial constraint verification. Therefore, the synchronization error tolerance is preset to ±10 nanoseconds.

[0076] After receiving the time-delay-compensated reference synchronization pulse, each acquisition node regenerates its clock using an internal digital phase-locked loop (PLL). The loop filter cutoff frequency of this PLL is set to 0.8 Hz, providing approximately 45 dB of attenuation and suppression for high-frequency pulse edge jitter components introduced by inductive coupling through the fiber optic sheath during disconnection operations. This regenerates a local sampling clock locked at 12.8 kHz, meaning 256 sampling points correspond to each power frequency cycle. When the rising edge of the local sampling clock arrives, the 16-bit successive approximation analog-to-digital converter (ADC) within each acquisition node completes sampling, holding, and quantization encoding of the analog input signal within approximately 2 nanoseconds of aperture time, outputting a 16-bit digital signal with the first timestamp corresponding to that exact second. At exactly 10:00:00, all 38 acquisition nodes in the station complete synchronous sampling at the same absolute time. Each node then uploads its leakage current and voltage digital signals, carrying the same first timestamp, to the centralized monitoring host via industrial Ethernet.

[0077] The centralized monitoring host retrieves the data of the three-phase surge arrester group corresponding to the first timestamp from the memory buffer pool. This group consists of surge arrester number P01 for phase A, surge arrester number P02 for phase B, and surge arrester number P03 for phase C. The centralized monitoring host extracts 2560 sampling points within a 200-millisecond time window starting from the first timestamp. The leakage current data sequence is divided into 10 power frequency cycle segments of 256 points each for root mean square (RMS) value statistics. The RMS values ​​of the 10 cycle segments are all between 1.0 mA and 1.5 mA, and the RMS value of the entire segment is 1.2 mA. The preset multiple is 2.5 times, and the calculated judgment threshold is 3.0 mA. The RMS values ​​of the 10 cycle segments do not exceed this judgment threshold, no transient interference pollution segment is detected, and all 2560 data points remain unchanged. The centralized monitoring host performs a radix-2 decimation-time Fast Fourier Transform on the leakage current and voltage data sequences point by point using a Hanning window function, resulting in a complex spectrum sequence with a frequency interval of 5 Hz. For phase A surge arrester P01, the magnitude is largest at frequency point 10 in the leakage current spectrum sequence, at 1.62 mA. The magnitude at the preceding frequency point 9 is 0.78 mA, and the magnitude at the following frequency point 11 is 0.95 mA. After three-point amplitude interpolation correction, the fundamental frequency of the leakage current is calculated to be 50.4 Hz, the fundamental amplitude is 1.68 mA, and the fundamental phase is 0.41 radians. Using 50.4 Hz as the index frequency, the centralized monitoring host takes frequency point 10 in the voltage spectrum sequence as the reference frequency, with a frequency correction term of +0.08, and calculates the fundamental amplitude of the bus voltage to be 58.2 V and the fundamental phase of the bus voltage to be 0.03 radians. The same process was used to process the surge arresters of phases B and C. The calculated fundamental amplitude of the leakage current of phase B was 1.55 mA and the fundamental phase was 2.51 radians. The fundamental amplitude of the leakage current of phase C was 1.61 mA and the fundamental phase was 4.60 radians.The basis for setting the preset multiple to 2.5 times is as follows: Under steady-state operation of the surge arrester in a substation, the leakage current flowing through the metal oxide varistor is mainly a capacitive fundamental component. The normal fluctuation range of its root mean square (RMS) value within one power frequency cycle interval typically does not exceed ±1.2 times its mean value, meaning the ratio of the RMS value of adjacent cycle intervals to the overall RMS value is stable at around 1.0. When sudden electromagnetic transient processes such as disconnector operation, corona discharge, or lightning surge occur, the RMS value of the contaminated power frequency cycle interval will instantly jump to several times or even tens of times the steady-state value. To reliably distinguish between steady-state normal fluctuations and transient impact events, the same... To avoid misjudging minute current changes caused by normal grid load switching as interference, after statistical analysis of measured leakage current waveform data from multiple substations, a threshold of approximately twice the upper limit of steady-state normal fluctuations was selected as the judgment threshold. This 2.5 times threshold ensures sensitive detection and accurate zeroing of transient interference pollution segments with significantly increased amplitude, thereby eliminating its impact on broadband noise rise in subsequent windowed fast Fourier transform spectrum analysis. It also prevents the loss of effective sample size due to the erroneous removal of normal data caused by setting the threshold too low, thus ensuring the accuracy of resistive current fundamental component extraction and the data integrity of three-phase spatial constraint verification.

[0078] The centralized monitoring host retrieves the first fixed phase lag of the current acquisition node connected to P01 from the channel phase calibration sub-table. The lag is 0.04 radians for P02, 0.03 radians for P03, and 0.05 radians for the 220kV voltage acquisition node. The second fixed phase lag is 0.02 radians. After channel phase differential compensation, the corrected fundamental phase of the leakage current is 0.37 radians for phase A, 2.48 radians for phase B, and 4.55 radians for phase C. The corrected fundamental phase of the bus voltage is 0.01 radians. Using the corrected fundamental phase of the bus voltage as the reference phase, the phase difference between phase A voltage and current is 0.36 radians, with a cosine value of 0.936, and the fundamental component of the resistive current is 1.68 mA multiplied by 0.936, which equals 1.57 mA; the phase difference between phase B voltage and current is 2.47 radians, with a cosine value of -0.780, and the fundamental component of the resistive current is -1.21 mA; the phase difference between phase C voltage and current is 4.54 radians, with a cosine value of -0.175, and the fundamental component of the resistive current is -0.28 mA.

[0079] The centralized monitoring host confirms from the electrical bay configuration table that P01, P02, and P03 belong to the same three-phase surge arrester group. Using a phase A magnitude of 1.68 mA and a corrected phase of 0.37 radians, the real part of the phase A vector is calculated to be 1.57 and the imaginary part to be 0.61. Using a phase B magnitude of 1.55 mA and a corrected phase of 2.48 radians, the real part of the phase B vector is calculated to be -1.23 and the imaginary part to be 0.95. Using a phase C magnitude of 1.61 mA and a corrected phase of 4.55 radians, the real part of the phase C vector is calculated to be -0.26 and the imaginary part to be -1.59. The sum of the real parts of the three is 0.08, the sum of the imaginary parts is -0.03, and the magnitude of the composite vector is 0.085 mA. The preset zero-sequence deviation threshold of the centralized monitoring host is 0.15 mA. The synthetic vector magnitude of this measurement is 0.085 mA, which is less than this threshold. Therefore, it is determined that this measurement was not subject to significant electromagnetic interference. The fundamental components of the resistive currents calculated from the three surge arresters were all marked as valid data. The resistive currents of phase A (1.57 mA), phase B (-1.21 mA), and phase C (-0.28 mA) were written into the historical resistive current data table. The zero-sequence deviation allowable threshold is preset to 0.15 mA. This is based on the ideal operating condition where the three-phase power system of a substation operates symmetrically and all three surge arresters in the arrester group are unaffected by electromagnetic interference. Under these conditions, the fundamental vector amplitudes of the leakage currents in phases A, B, and C are equal, and their phases differ by 120°. The theoretical vector synthesis result should be a zero vector. However, in actual operation, even in environments without strong electromagnetic interference, factors such as the inherent voltage asymmetry of the power grid (usually less than 2%), slight individual differences in the valve plate parameters of the three surge arresters, and residual nanosecond-level synchronization errors and amplitude linearity deviations in each current acquisition channel after factory calibration compensation can all cause the three-phase leakage current fundamental vectors to be unable to achieve absolute symmetry. The synthesized vector magnitude will exhibit a non-zero but small inherent background residual. This is further supported by data collected from multiple three-phase surge arrester groups in multiple substations during steady-state operation without operation or lightning strikes. Statistical analysis of measured data revealed that the magnitude fluctuation of this inherent residual quantity mainly falls within 0.10 mA, with a very small number reaching 0.12 mA. To reliably cover the statistical upper limit of this inherent residual quantity and reserve necessary safety margins to absorb additional minor asymmetric components introduced by normal load fluctuations, the zero-sequence deviation allowable threshold is set at 0.15 mA. When the synthetic vector magnitude of any three-phase surge arrester group exceeds this 0.15 mA threshold, it can be determined that the measurement of this group must have been significantly contaminated by sudden electromagnetic transient processes such as disconnecting switch operation and corona discharge. Its resistive current extraction value has deviated from the actual valve plate state and should be marked as invalid data. This achieves an optimal balance between avoiding the erroneous rejection of normal operating condition data due to an overly strict threshold and the leakage of interference data due to an overly lenient threshold, ensuring the purity of the fundamental component dataset of resistive current across the entire station and the confidence level of subsequent long-term trend analysis.

[0080] After 30 consecutive days of operation, the centralized monitoring host performed the evaluation cycle calculation for the 30th day for Phase A surge arrester P01. The preset evaluation cycle length is 24 hours, and the theoretical maximum number of samplings for this surge arrester within the daily evaluation cycle is 86,400. The centralized monitoring host extracted 78,200 fundamental resistive current components marked as valid data from the historical resistive current data table, representing approximately 90.5% of the data. The minimum sample size threshold was set to 50% of the theoretical maximum sampling count, i.e., 43,200 samples. The actual number of valid samples far exceeded this threshold, meeting the statistical reliability requirements. The centralized monitoring host sorted the 78,200 fundamental resistive current component values ​​in ascending order, removed 7,820 maximum values ​​and 7,820 minimum values ​​at a ratio of 10% at the beginning and 10% at the end, and calculated the arithmetic mean of the remaining 62,560 samples, obtaining the daily average resistive current of 1.62 mA. This value was appended to the historical resistive current average value sequence of P01. The reason for setting the preset evaluation period to 24 hours is as follows: the increase in resistive current caused by moisture or aging of metal oxide surge arrester varistors is a slow and gradual insulation degradation process, and its time scale is much larger than seconds or minutes. If the evaluation period is set too short, the effective sample size accumulated in a single period will be insufficient, and the statistically obtained average resistive current will be easily affected by residual random measurement noise and short-term fluctuations in grid load, resulting in significant dispersion. This leads to frequent jumps in the sign and amplitude of the calculated resistive current growth rate, making it difficult to truly reflect the long-term aging trend of the varistors. If the evaluation period is set too long, the evaluation conclusion will be too lagging, which may delay the early detection of signs of accelerated degradation. Statistical analysis of historical online monitoring data of surge arresters in multiple substations shows that the grid load exhibits a natural day cycle with a 24-hour period. The cyclical pattern means that within a complete natural day, surge arresters experience periods of high and low grid voltage, as well as periods of heavy and light load. The electromagnetic interference environment of the entire station also exhibits diurnal alternation. By taking a statistical average of the resistive current using a 24-hour window, the above-mentioned periodic fluctuations can be fully covered. This effectively smooths the modulating effect of diurnal variations in load and environment on the resistive current, ensuring that the average resistive current value corresponding to the evaluation period stably reflects the true insulation level of the surge arrester on that day. At the same time, the sample size provided by the 24-hour evaluation period, after deducting invalid data removed by spatial constraint verification, still fully meets the minimum sample size threshold requirement. This provides statistically reliable basic data for subsequent multi-period least squares linear fitting estimation of the resistive current growth rate, thus achieving an optimal balance between the accuracy of trend assessment and the timeliness of early warning.

[0081] The preset fitting window length parameter is 7 evaluation periods. The centralized monitoring host retrieves the historical sequence of the average resistive current of P01. This sequence has continuously stored the average resistive current for the most recent seven natural days, in chronological order: 1.48 mA, 1.51 mA, 1.53 mA, 1.56 mA, 1.58 mA, 1.60 mA, and 1.62 mA for the current day. The centralized monitoring host assigns storage numbers from 0 to 6 to these seven data points, performs least-squares linear fitting, and calculates the slope of the fitted line to be 0.022 mA per day, which is taken as the resistive current growth rate for this evaluation period. The preset second safety limit, i.e., the resistive current growth rate threshold, is 0.020 mA per day. The resistive current growth rate calculated in this case is 0.022 mA per day, which is greater than this threshold. At the same time, the average resistive current of the day is 1.62 mA, which is less than the preset first safety limit of 2.50 mA. The centralized monitoring host determines that the resistive current growth rate of the surge arrester exceeds the second safety limit and generates an early warning signal. The warning message is: "The resistive current growth rate of phase A surge arrester P01 exceeds the limit. The current growth rate is 0.022 mA per day, which exceeds the threshold of 0.020 mA per day. It is recommended to pay attention to the accelerated aging trend of the valve plate." This early warning signal is sent to the substation monitoring backend through the communication network, completing the complete processing flow of this centralized online monitoring of surge arresters throughout the station. In this embodiment, the preset fitting window length parameter is set to 7 evaluation periods because: the aging of metal oxide surge arrester varistors is a slow and gradual insulation degradation process, and the true trend of its resistive current growth rate needs to be separated from random statistical fluctuations over a sufficiently long time span; if the fitting window is set too short, such as only 2 to 3 evaluation periods, the residual zero-mean random measurement noise and the pulling effect of occasional fluctuations in grid load on the average resistive current in a single period will be significantly amplified in finite difference or short sequence fitting, resulting in frequent alternation of positive and negative signs and violent oscillations in the amplitude of the calculated resistive current growth rate, which is very likely to trigger false alarms; if the fitting window is set too long, the inertia of the trend estimation is too large, which will affect the early signs of moisture absorption or accelerated aging of the varistors. Slow response may lead to missed opportunities for early warning. Statistical analysis of historical data from long-term online monitoring of surge arresters in multiple substations, using seven consecutive natural days as a complete observation window, effectively smooths out the minute fluctuations in the average resistive current value caused by environmental factors such as differences in load patterns between weekdays and rest days and cyclical changes in temperature and humidity within a week in the least squares linear fitting. This ensures that the fitting slope robustly reflects the overall aging direction and rate of development of the surge arresters on a weekly scale. At the same time, the number of fitting sample points provided by the seven evaluation periods is statistically sufficient to converge the confidence interval of the fitted line slope to a reasonable range, ensuring the reliability of the resistive current growth rate estimation results. Thus, an optimal balance is achieved between the statistical robustness of trend assessment and the sensitivity of early warning response.In this embodiment, the preset second safety limit, i.e., the resistive current growth rate threshold, is set at 0.020 mA / day. This is based on the following: Under normal operating conditions, the natural aging process of the varistors of metal oxide surge arresters due to long-term electrothermal stress is extremely slow. The annual growth rate of the fundamental component of the resistive current is typically only a few percentage points per year, which translates to a daily growth rate far less than 0.010 mA / day. When the varistors become damp due to sealing failure, or experience accelerated deterioration of nonlinear resistance characteristics due to prolonged exposure to temporary overvoltage, the resistive current will exhibit a continuous monotonically increasing trend, and the daily growth rate will significantly exceed the aforementioned natural aging background value. Through retrospective analysis of online monitoring historical data from multiple substations where surge arresters with dampness or varistor deterioration defects were confirmed through disassembly, this type of defective surge arrester… After the device enters the accelerated degradation stage, its resistive current daily growth rate generally exceeds 0.020 mA per day, and the growth trend is continuous and irreversible. If the threshold is set too high, it will be insensitive to the weak acceleration signals of early slow moisture absorption or localized degradation, delaying the detection time. If the threshold is set too low, the normal transient rise in resistive current caused by external environmental factors such as large fluctuations in grid load and continuous high temperature weather may be misidentified as accelerated aging, increasing the false alarm rate. Therefore, using 0.020 mA per day as the second safety limit can reliably distinguish the abnormal continuous growth trend caused by moisture absorption or accelerated degradation of the valve plate against the background of normal resistive current fluctuations composed of natural aging, load fluctuations and changes in ambient temperature and humidity, thereby achieving the optimal balance between early warning sensitivity and false alarm suppression.In this embodiment, the preset first safety limit of 2.50 mA is based on the following: During the normal service life of a metal oxide surge arrester, the fundamental component of its resistive current mainly originates from the weak conductivity loss of the valence grain boundary layer under the power frequency electric field. For newly commissioned or well-maintained surge arresters, the fundamental component of the resistive current measured at rated voltage is usually stable within the range of 1.0 mA to 1.8 mA, and exhibits a stable random change around a fixed center value with slight fluctuations in ambient temperature and system voltage, without a significant monotonically increasing trend. When the valence grain undergoes irreversible degradation due to long-term electrothermal aging, internal moisture, or nonlinear resistance characteristics, its resistive current will deviate from the above-mentioned normal steady-state range, exhibiting a continuous and accelerating monotonically increasing trend. Once the fundamental component of the resistive current exceeds 2.50 mA, based on online testing of surge arresters in multiple substations that have been confirmed to have significant aging or moisture defects through power outage diagnostic tests, Retrospective verification of monitoring data shows that this value significantly exceeds the statistical confidence boundary of the upper limit of normal fluctuations caused by temperature, voltage, and measurement noise throughout the entire life cycle. This indicates that the crystal boundary barrier of the valence plate has undergone substantial degradation, and the surge arrester is in a dangerous operating state with a significantly increased risk of thermal collapse. If this limit is set too low, the normal rise in resistive current caused by transient overvoltages in the power grid or high-temperature seasons may easily trigger false alarms. If it is set too high, it will lose its warning significance for early dangerous conditions that have entered the accelerated degradation stage but whose absolute value of resistive current has not yet risen sharply. Therefore, using 2.50 mA as the first safety limit can establish a clear safety boundary between the resistive current fluctuation range under normal operating conditions and the resistive current range corresponding to dangerous defects, ensuring reliable detection of dangerous conditions where the insulation performance of the surge arrester has undergone substantial damage, thereby achieving the optimal balance between the accuracy and timeliness of early warning.In this embodiment, the centralized monitoring host determines that the resistive current growth rate of the surge arrester exceeds the second safety limit based on the following: Under normal operating conditions, the resistive current of the metal oxide surge arrester increases extremely slowly due to the long-term exposure to power frequency voltage and electrothermal stress. Statistical analysis of online monitoring data from several well-functioning surge arresters in multiple substations over many years shows that the daily growth rate of the resistive current is typically stable within the range of 0.010 mA per day, exhibiting a stable random characteristic fluctuating around zero, without a clear monotonic upward direction. When the resistive current growth rate of any surge arrester, calculated using least-squares linear fitting over seven consecutive evaluation periods, exceeds 0.020 mA per day, this value significantly exceeds the limits set by natural aging and load conditions. The upper limit of the normal growth rate that can be explained by fluctuations in environmental factors such as temperature indicates that the valve plate has moved beyond the stable stage of slow natural aging and entered an abnormally monotonous growth channel caused by moisture absorption due to sealing failure or accelerated deterioration of nonlinear resistance characteristics. Once this growth trend is formed, it is usually irreversible and has self-accelerating characteristics. If not intervened in time, the valve plate will rapidly deteriorate to the critical state of thermal collapse within the following months to a year. Therefore, using whether the resistive current growth rate exceeds 0.020 mA per day as the criterion is to achieve early detection of the accelerated deterioration process by monitoring the slope of the growth trend before the absolute value of the resistive current reaches the first safety limit. This provides maintenance personnel with sufficient maintenance response time and plays a forward-looking role in trend early warning.

[0082] Example 2

[0083] It should be further explained that this embodiment forces the sampling edges of each current acquisition node or voltage acquisition node to align, including:

[0084] A101. Generate a reference synchronization pulse as the basis for the time synchronization pulse, and distribute the reference synchronization pulse to all current acquisition nodes or voltage acquisition nodes in the entire station via a transmission link. In this embodiment, the clock synchronization module includes a frequency source, which uses a high-stability temperature-controlled crystal oscillator or a chip-level atomic clock as the main oscillator, and its frequency stability in free oscillation state is better than ±1×10⁻⁻⁻⁻⁴. 9The continuous sinusoidal signal output by the main oscillator is shaped into a square wave by a comparator or a high-speed Schmitt trigger circuit. Then, a pulse shaping circuit steepens the rising or falling edge of the square wave to the sub-nanosecond level, forming a reference synchronization pulse sequence with defined edge times. The clock synchronization module is also equipped with a GNSS receiving module, which receives timing signals from the BeiDou Navigation Satellite System or GPS system, demodulates the second pulse signal from it, and ensures that the rising edge of the second pulse signal is aligned with the whole second of Coordinated Universal Time (UTC) and has a long-term accuracy better than ±1×10⁻¹². Using the second pulse signal as an external reference, the clock synchronization module periodically compares the phase of the reference synchronization pulse output by the main oscillator. When the accumulated phase difference between the edge of the reference synchronization pulse and the edge of the second pulse signal exceeds a preset frequency offset tolerance, the frequency control word of the main oscillator is adjusted to lock the long-term frequency accuracy of the reference synchronization pulse to the same level as the second pulse signal. The transmission link is a point-to-point multimode or single-mode optical fiber. The input end of each optical fiber is connected one-to-one with a pulse output port of the clock synchronization module, and the output end of the optical fiber is connected to the pulse receiving interface of each current acquisition node or voltage acquisition node distributed in different electrical bays of the substation. In this embodiment, the preset frequency offset tolerance is based on the fact that, even when using a high-stability temperature-controlled crystal oscillator or a chip-level atomic clock, the frequency stability of the main oscillator inside the clock synchronization module in a free oscillation state is better than ±1×10⁻⁶. -9While the frequency drift is on the order of magnitude, it will still experience slow frequency drift during long-term continuous operation due to factors such as device aging, changes in ambient temperature, and fluctuations in power supply voltage. This results in a monotonically accumulating phase deviation between the edge of the reference synchronization pulse and the edge of the GNSS second pulse signal. If the frequency offset tolerance is set too large, the time interval between two frequency calibration actions will be too long. During this period, the accumulated phase deviation will be directly transmitted to the local sampling clock edge of each acquisition node. The residual synchronization error after transmission link pre-delay compensation will exceed the preset ±10 nanosecond synchronization error tolerance, destroying the spatial constraint verification basis for the vector synthesis of the three-phase leakage current fundamental wave. If the frequency offset tolerance is set too small, the frequency control word will be adjusted too frequently, and the short-term phase noise of the main oscillator output clock will increase. The noise will increase due to repeated disturbances in the control loop, which will worsen the edge jitter characteristics of the reference synchronization pulse and make it difficult for the local phase-locked loop of the acquisition node to filter out electromagnetic interference jitter. After a comprehensive evaluation of the frequency aging rate, temperature-frequency characteristics and daily temperature variation range of the substation main control room of the selected master oscillator, the frequency offset tolerance is set so that the contribution of the phase error accumulated between two calibration intervals to the final sampling synchronization accuracy does not exceed ±2 nanoseconds under the worst drift rate of the master oscillator. This value accounts for only a minor share in the total budget of ±10 nanosecond synchronization error tolerance. Thus, while ensuring long-term synchronization accuracy, the free oscillation stability of the master oscillator is maintained to the maximum extent, and additional short-term phase noise is avoided due to excessive discipline.

[0085] A102. Measure the propagation delay of the reference synchronization pulse on each transmission link and obtain the relative delay difference between each transmission link and the reference link.

[0086] In this embodiment, the clock synchronization module integrates a delay measurement unit, which includes a time-to-digital converter with a resolution better than 100 ps. During propagation delay measurement, the clock synchronization module transmits a test pulse at the transmitting end of the i-th transmission link through the delay measurement unit. The edge trigger time of this test pulse is denoted as T_launch_i. After the test pulse is transmitted to a remote current or voltage acquisition node via the i-th transmission link, the photoelectric conversion and loopback circuit within that node directly loops the pulse back without local logic processing, returning it to the clock synchronization module along the same transmission link. The delay measurement unit receives the looped-back pulse and records its edge arrival time T_return_i. The delay measurement unit calculates the round-trip time interval T_rt_i = T_return_i - T_launch_i, and the one-way propagation delay value of the i-th transmission link is Td_i = T_rt_i / 2. The fixed loopback processing delay T_fix introduced by the loopback circuit within the current or voltage acquisition node is known from the factory calibration and participates in the correction calculation of Td_i, i.e., Td_i = (T_rt_i / 2) - T_fix. The delay measurement unit measures the propagation delay values ​​Td_1, Td_2, ..., Td_N of all transmission links in the entire station one by one, where N is the total number of transmission links in the entire station. One transmission link is selected from all transmission links in the entire station as a reference link. The reference link is usually a transmission link connected to the current or voltage acquisition node located at the center of the substation or the main transformer bay, and its propagation delay value is recorded as Td_ref. For the i-th transmission link, the delay measurement unit calculates the relative delay difference ΔT_i = Td_i - Td_ref of the transmission link relative to the reference link, and stores all relative delay differences ΔT_1, ΔT_2, ..., ΔT_N in the register of the clock synchronization module.

[0087] A103. For each transmission link, the reference synchronization pulse is pre-delayed based on the relative time delay difference, so that the time deviation of the compensated reference synchronization pulse arriving at each current acquisition node or voltage acquisition node falls within the preset synchronization error tolerance.

[0088] In this embodiment, the clock synchronization module connects a programmable delay line in series between the transmitting end and the pulse output port of each transmission link. The programmable delay line is composed of cascaded multi-stage numerically controlled delay units, with a single-stage delay step Δt_step less than one-tenth of the preset synchronization error tolerance ε_sync, for example, Δt_step = 500ps and ε_sync = ±10ns. The control input port of the programmable delay line is connected to the delay compensation controller inside the clock synchronization module. The delay compensation controller reads the relative delay difference ΔT_i corresponding to each transmission link from the register. For each transmission link, if ΔT_i > 0, indicating that the propagation delay of the transmission link is greater than the propagation delay of the reference link, the delay compensation controller writes a negative delay compensation amount to the programmable delay line or adjusts the relative transmission timing of the reference synchronization pulse, so that the reference synchronization pulse on the link is emitted ΔT_i time earlier than the reference synchronization pulse of the reference link; if ΔT_i < 0, indicating that the propagation delay of the transmission link is less than the propagation delay of the reference link, the delay compensation controller controls the programmable delay line to apply an additional delay to the reference synchronization pulse, the additional delay amount being equal to |ΔT_i|, so that the reference synchronization pulse on the link is emitted |ΔT_i| time later; if ΔT_i = 0, the programmable delay line applies zero additional delay to the reference synchronization pulse. After the above-mentioned differential pre-delay compensation, the reference synchronization pulses that were originally scattered in time due to the difference in the physical length of each transmission link will arrive at the input of each remote current acquisition node or voltage acquisition node after experiencing different propagation delays on their respective transmission links. The maximum deviation between the arrival times is constrained to within ε_sync.

[0089] A104. Each current acquisition node or voltage acquisition node receives a reference synchronization pulse after pre-delay compensation. The edge of the reference synchronization pulse triggers the local phase-locked loop of the node. The phase-locked loop filters out electromagnetic interference jitter coupled by the transmission link and regenerates a local sampling clock that is fixed with the edge of the reference synchronization pulse.

[0090] In this embodiment, each current or voltage acquisition node includes a local clock regeneration circuit, the core of which is a digital phase-locked loop (PLL). The PLL comprises a digital phase detector, a digital loop filter, a digitally controlled oscillator, and a feedback divider. One input of the digital phase detector receives a pre-delay-compensated reference synchronization pulse after photoelectric conversion, while the other input receives the feedback edge signal of the local sampling clock output by the feedback divider. At each valid edge of the reference synchronization pulse, the digital phase detector measures the phase difference between the reference synchronization pulse edge and the feedback edge signal, and outputs a digital phase error codeword proportional to the phase difference. The bandwidth of the digital loop filter is parameterized to be lower than the starting frequency of the typical electromagnetic interference spectrum in the substation. For example, the cutoff frequency of the loop filter is set to a fixed value between 0.5Hz and 1Hz. This ensures that high-frequency jitter components introduced into the digital phase error codeword through fiber coupling or power conduction due to disconnector operation, corona discharge, etc., are significantly attenuated by the low-pass characteristics of the digital loop filter, with an attenuation exceeding 40dB at the main interference frequency. The filtered digital phase error codeword is sent to the frequency control input of the numerically controlled oscillator (CNC), controlling the CNC to adjust the frequency and phase of its output clock. This causes the edge of the CNC oscillator's output clock to gradually approach and eventually lock onto the edge of the reference synchronization pulse. The output of the CNC oscillator serves as the regenerated local sampling clock, provided to subsequent analog-to-digital conversion circuits. There is only one tiny fixed bias between each valid edge of the local sampling clock and the corresponding reference synchronization pulse edge, which is determined by the steady-state phase error of the phase-locked loop. This tiny fixed bias is basically the same across all nodes in the station due to the high consistency of circuit parameters, and remains stable during long-term operation. It will not introduce random time displacement due to transient electromagnetic interference on the transmission link.

[0091] A105. The analog-to-digital conversion circuit of each current acquisition node or voltage acquisition node performs sampling at the effective edge of the local sampling clock, so that the sampling points of all current acquisition nodes or voltage acquisition nodes in the entire station are aligned on the absolute time axis.

[0092] In this embodiment, the analog-to-digital conversion circuit of each current or voltage acquisition node includes a sample-and-hold amplifier and a quantization encoder. The sampling switch control terminal of the sample-and-hold amplifier is connected to the output terminal of the local sampling clock. The conversion start signal of the quantization encoder is also triggered by the same valid edge of the local sampling clock or a valid edge after fixed frequency division. When the valid edge of the local sampling clock arrives, the sample-and-hold amplifier instantaneously samples the input analog leakage current signal or analog bus voltage signal within a preset aperture time and keeps the sampled value stable. The quantization encoder then performs analog-to-digital conversion on the held value and outputs the corresponding digital codeword. Simultaneously, a timestamp generation module inside each current or voltage acquisition node generates a first timestamp corresponding to this sampling from the edge counter of the local sampling clock and the time information of the reference synchronization pulse, and appends the first timestamp to the digital codeword to form a leakage current digital signal or voltage digital signal carrying the first timestamp. Since the local sampling clock edges of each current or voltage acquisition node have been processed by delay compensation and jitter filtering as described in A101 to A104, and are forcibly aligned to the same moment on the absolute time axis, the sampling actions of all current or voltage acquisition nodes of different electrical intervals and voltage levels in the entire station on their respective analog signals at the effective edge of the same local sampling clock all occur at the same absolute moment. The residual time deviation between sampling points is determined by the preset synchronization error tolerance ε_sync, the steady-state phase error difference of each phase-locked loop, and the aperture time difference of each analog-to-digital conversion circuit. This composite deviation is controlled on the order of nanoseconds, which meets the strict requirements of synchronization accuracy for subsequent cross-interval three-phase leakage current vector synthesis.

[0093] Please see Figure 2 It should be further explained that in this embodiment, the leakage current digital signal and the voltage digital signal within the same time window are subjected to windowed fast Fourier transform, including:

[0094] B101. Extract leakage current data sequence and voltage data sequence with a time length equal to an integer multiple of the power frequency period from the leakage current digital signal and the voltage digital signal carrying the same first timestamp.

[0095] In this embodiment, the centralized monitoring host maintains a data buffer pool indexed by a first timestamp. This buffer pool uses the first timestamp as the key to merge and store the leakage current digital signals uploaded by all current acquisition nodes and the voltage digital signals uploaded by all voltage acquisition nodes corresponding to the same first timestamp. When processing data for a specific first timestamp is required, the centralized monitoring host uses that first timestamp as the retrieval condition to extract all leakage current and voltage digital signals corresponding to that first timestamp from the buffer pool. The centralized monitoring host uses the sampling time represented by the first timestamp as the starting point and extracts all sampling points within a preset time window. The preset time window length is equal to an integer multiple of the nominal power frequency period. The nominal power frequency period is the period value corresponding to the rated frequency of the power grid, and the integer multiple is preset to a fixed value based on the trade-off between frequency resolution and response speed. The extracted leakage current data sequence consists of leakage current sample values ​​arranged in chronological order within the time window, and the voltage data sequence consists of bus voltage sample values ​​arranged in chronological order within the same time window. Both sequences have the same number of sampling points and correspond one-to-one to the same absolute sampling time. If a current or voltage acquisition node has missing sampling points within the time window corresponding to the first timestamp, or if the cyclic redundancy check of the data packet fails, the centralized monitoring host marks all data corresponding to that first timestamp for that node as unavailable and excludes it from subsequent processing.

[0096] B102. Divide the leakage current data sequence into segments according to the power frequency cycle, calculate the root mean square value of each power frequency cycle segment, and determine the power frequency cycle segment whose root mean square value exceeds a preset multiple of the root mean square value of the entire leakage current data sequence as a transient interference pollution segment, and set the data points in the leakage current data sequence and the voltage data sequence corresponding to the transient interference pollution segment to zero.

[0097] In this embodiment, the centralized monitoring host divides the leakage current data sequence into non-overlapping, equal-length segments according to the number of sampling points contained in a single nominal power frequency cycle, with each segment corresponding to a complete nominal power frequency cycle. For each segment of the power frequency cycle, the centralized monitoring host squares the sampled values ​​of all sampling points within the segment, calculates the arithmetic mean, and then takes the square root of this arithmetic mean to obtain the root mean square value of that power frequency cycle segment. Simultaneously, the centralized monitoring host applies the same calculation method to all sampling points of the leakage current data sequence to obtain the root mean square value for the entire segment. The centralized monitoring host sets the preset multiplier to a fixed positive real number. Its value is determined through measured statistics based on the normal fluctuation range of the leakage current of the surge arrester under steady-state operating conditions. This means that during normal substation operation, the leakage current flowing through the metal oxide surge arrester varistor is dominated by a capacitive fundamental component. The root mean square (RMS) value of its waveform within a complete power frequency cycle is mainly affected by the slow modulation of the grid voltage amplitude and the inherent weak nonlinearity of the varistor varistor. The difference in RMS values ​​between adjacent power frequency cycle segments is minimal. Statistical analysis was conducted on multiple well-functioning surge arresters in several substations of different voltage levels during steady-state operation without switching, lightning strikes, or corona discharge. The data collected continuously at the power frequency cycle level from numerous leakage current waveform samples. The results show that the normalized ratio of the RMS value of any power frequency cycle segment to the RMS value of the entire segment under steady-state conditions always fluctuates narrowly around 1.0. This fluctuation mainly originates from small random fluctuations in the grid voltage during the power frequency cycle and the analog-to-digital conversion circuit. The quantization noise has a statistical upper limit of less than 1.5 times the root mean square value of the entire segment. When sudden electromagnetic transient processes such as disconnecting switch operation, circuit breaker opening and closing, corona discharge, or lightning surge occur, the root mean square value of the polluted power frequency cycle segment will surge instantaneously due to the superposition of transient impact current, and its ratio to the root mean square value of the entire segment is usually much greater than 2.0 times. In order to ensure that the judgment threshold can fully cover the statistical upper limit of steady-state normal fluctuations, and has sufficient margin to adapt to the differences in electromagnetic environment of different substations and the differences in individual characteristics of different surge arresters, and at the same time avoid misjudging the small current changes caused by normal switching of grid load as interference, an engineering margin coefficient of about 1.5 to 2.0 times the statistical upper limit of steady state is taken, and the preset multiple is determined to be a fixed positive real number that can reliably separate steady-state fluctuations from transient impacts. In this way, while ensuring sensitive detection of transient interference pollution segment, the effective steady-state data is preserved to the maximum extent, providing a high signal-to-noise ratio time domain data basis for subsequent windowed fast Fourier transform.

[0098] The centralized monitoring host compares the root mean square (RMS) value of each power frequency cycle segment with the product of the RMS value of the entire segment multiplied by a preset multiple. When the RMS value of a certain power frequency cycle segment is greater than this product, that power frequency cycle segment is identified as a transient interference pollution segment affected by disconnecting switch operation, corona discharge, or other sudden electromagnetic transient processes. The centralized monitoring host records the sampling point number intervals covered by each power frequency cycle segment identified as a transient interference pollution segment. The values ​​of all sampling points in the leakage current data sequence falling within this number interval are modified to zero, and the values ​​of all sampling points in the voltage data sequence falling within the same sampling point number interval are also modified to zero. Sampling points not falling into any transient interference pollution segment interval retain their original sampling values. This zero-processing operation eliminates the broadband noise increase effect of transient interference pollution segments on subsequent spectrum analysis, while preserving the time-domain correspondence between the voltage data sequence and the leakage current data sequence.

[0099] B103. Multiply the zeroed leakage current data sequence and the zeroed voltage data sequence point by point by the Hanning window function to obtain the windowed leakage current data sequence and the windowed voltage data sequence.

[0100] In this embodiment, the centralized monitoring host pre-stores a Hanning window function value table. The length of this table is equal to the total number of sampling points within the time window, and each element in the table is the function value of the Hanning window function at the corresponding sampling point number. The centralized monitoring host multiplies each sampling point in the zeroed leakage current data sequence with the window function value at the same number in the Hanning window function value table, according to its sequence number. The result is used as the sampling value at the same number in the windowed leakage current data sequence. The centralized monitoring host performs the same point-by-point multiplication operation on the zeroed voltage data sequence, multiplying each sampling point in the zeroed voltage data sequence with the window function value at the same number in the Hanning window function value table to obtain the sampling value at the same number in the windowed voltage data sequence. The Hanning window function asymptotically approaches zero at both ends of the sequence and reaches a peak in the middle of the sequence. After point-by-point multiplication, the two ends of the leakage current data sequence and voltage data sequence are smoothly attenuated, thereby significantly suppressing the spectral leakage sidelobes introduced by time-domain truncation in the subsequent Fourier transform, concentrating the signal energy near the main lobe of each frequency component, and creating spectral morphology conditions for the accurate extraction of fundamental parameters through interpolation correction.

[0101] B104. Perform radix-2 decimation-fast Fourier transform on the windowed leakage current data sequence and the windowed voltage data sequence to obtain the complex spectrum sequence of leakage current and the complex spectrum sequence of voltage.

[0102] In this embodiment, the centralized monitoring host performs a radix-2 decimation-time fast Fourier transform on the windowed leakage current data sequence. This transform converts the time-domain windowed leakage current data sequence into a frequency-domain complex spectrum sequence of leakage current. Each element in the complex spectrum sequence of leakage current is a complex number, corresponding to a discrete frequency point. The real part of the complex number represents the amplitude and sign of the cosine component of the signal at that frequency point, and the imaginary part represents the amplitude and sign of the sine component of the signal at that frequency point. The centralized monitoring host can calculate the magnitude of the signal at that frequency point based on the real and imaginary parts of the complex number. The magnitude represents the amplitude intensity of the signal component at that frequency point. Simultaneously, the host can calculate the phase angle of the signal at that frequency point based on the real and imaginary parts of the complex number. The phase angle represents the initial phase of the signal component at that frequency point. The frequency interval between adjacent discrete frequency points in the frequency domain is equal to the sampling rate divided by the total number of sampling points. The analog frequency corresponding to each discrete frequency point is equal to the frequency point index multiplied by the frequency interval. The centralized monitoring host performs the exact same radix-2 time-decimation fast Fourier transform on the windowed voltage data sequence to obtain a complex voltage spectrum sequence. The complex properties of each element in the complex voltage spectrum sequence and its correspondence with the analog frequency are exactly the same as those of the complex leakage current spectrum sequence.

[0103] B105. In the complex spectrum sequence of the leakage current, take the three consecutive frequency points with the largest modulus, and substitute the modulus of the three frequency points and the corresponding frequency values ​​into the three-point amplitude interpolation correction formula to calculate the fundamental frequency, fundamental amplitude and fundamental phase of the leakage current.

[0104] In this embodiment, the centralized monitoring host first determines a power frequency search range in the complex spectrum sequence of leakage current. The lower limit of this power frequency search range is set as the rated frequency of the power grid minus a preset frequency search offset, and the upper limit is set as the rated frequency of the power grid plus the preset frequency search offset. The frequency search offset is set as a fixed value based on the historical fluctuation range of the power grid frequency. The basis for this setting is that, in actual operation, the power grid frequency is not constantly locked at the nominal rated frequency, but exhibits continuous small random fluctuations near the rated frequency due to the dynamic balance between power generation output and load. According to my country's power system frequency quality standards and long-term monitoring statistics of the bus frequencies of multiple substations, under normal operating conditions, the fluctuation range of the power grid frequency is usually controlled within ±0.2 Hz of the rated frequency. In extreme cases, the frequency offset caused by the tripping of large-capacity units or sudden load changes rarely exceeds ±0.5 Hz. If the frequency search offset is set too small, when the power grid frequency... When the frequency deviates from the rated frequency due to system disturbances and exceeds the search range, the true spectral peak of the leakage current fundamental wave will fall outside the search window, causing the fundamental frequency point to fail to be located or to be mistakenly identified as the fundamental wave. This leads to errors in the reference frequency point for subsequent three-point amplitude interpolation correction, resulting in unacceptable deviations in the calculated leakage current fundamental frequency, amplitude, and phase, directly compromising the accuracy of the resistive current fundamental component projection calculation. If the frequency search offset is set too large, the search range will cover too many non-fundamental frequency points, increasing not only the overhead of invalid spectrum scanning calculations for the centralized monitoring host but also the risk of misidentifying high-amplitude low-order harmonics or interharmonic components as the leakage current fundamental wave. Therefore, using the statistical upper limit of the historical fluctuation range of the power grid frequency, plus a necessary safety margin, as the fixed frequency search offset can limit the search range to the minimum necessary width while ensuring that the true fundamental frequency point is reliably included within the search window, thus achieving the optimal balance between the robustness of fundamental frequency point location and computational efficiency.

[0105] Within the discrete frequency range corresponding to the power frequency search range, the centralized monitoring host compares the magnitude values ​​of each frequency point one by one, finds the frequency point with the largest magnitude value, and records its index. The centralized monitoring host then takes the preceding and following adjacent frequency points of this maximum magnitude value, forming three consecutive frequency points together with the maximum magnitude value. The centralized monitoring host extracts the magnitude value and corresponding analog frequency value of each of these three frequency points, and substitutes these three magnitude values ​​and three frequency values ​​into the three-point amplitude interpolation correction formula derived for the Hanning window. This correction formula utilizes the relative proportional relationship of the amplitudes of the three sampling points within the main lobe of the Hanning window spectrum to calculate the frequency correction term. The frequency correction term represents the offset of the true fundamental frequency from the frequency of the discrete frequency point with the largest magnitude value. Adding this frequency offset to the frequency corresponding to the discrete frequency point with the largest magnitude value yields the fundamental frequency of the leakage current. Substituting the magnitude value of the discrete frequency point with the largest magnitude value and the frequency correction term into the amplitude correction expression yields the fundamental amplitude of the leakage current. Substituting the complex phase angle at the discrete frequency point with the maximum magnitude, the frequency correction term, and the time window length into the phase correction expression, the fundamental phase of the leakage current is obtained. After three-point interpolation correction, the measurement errors of the fundamental amplitude and phase caused by the non-integer cycle truncation due to real-time fluctuations in the power grid frequency are effectively compensated.

[0106] B106. Using the calculated fundamental frequency of the leakage current as the index frequency, take the frequency point closest to the index frequency in the complex spectrum sequence of the voltage, and perform three-point phase interpolation correction on the complex spectrum values ​​of this frequency point and its two adjacent frequency points to obtain the fundamental amplitude and phase of the bus voltage.

[0107] In this embodiment, the centralized monitoring host uses the fundamental frequency of the leakage current calculated in B105 as the index frequency. The centralized monitoring host calculates the precise position of this index frequency in the frequency domain coordinates of the complex voltage spectrum sequence. Since the discrete frequency points of the complex voltage spectrum sequence are only defined at integer multiples of fixed frequency intervals, the index frequency usually does not fall exactly on a single discrete frequency point. Therefore, the centralized monitoring host takes the discrete frequency point closest to the index frequency as the reference frequency point. The centralized monitoring host takes the reference frequency point and its preceding and following adjacent frequency points, a total of three consecutive frequency points, and extracts the complex spectrum values ​​of each of these three frequency points. The centralized monitoring host calculates a frequency correction term, which is equal to the difference between the index frequency and the corresponding frequency of the reference frequency point divided by the frequency interval. The value of the frequency correction term is between -0.5 and +0.5. The centralized monitoring host substitutes the frequency correction term and the magnitude values ​​of the reference frequency point and its two adjacent frequency points into the three-point amplitude interpolation correction formula derived for the Hanning window to obtain the fundamental amplitude of the bus voltage. Simultaneously, the frequency correction term and the phase angle of the reference frequency are substituted into the three-point phase interpolation correction formula derived for the Hanning window to obtain the fundamental phase of the bus voltage. Since the voltage spectrum is located and interpolated using the same index frequency as the leakage current fundamental frequency, rather than performing an independent frequency search on the complex voltage spectrum sequence, the extracted fundamental frequency of the bus voltage and the fundamental frequency of the leakage current are mathematically forced to maintain strict consistency. This avoids the frequency mismatch that might occur due to independent searches, thus ensuring that when projection calculations are performed using the fundamental phase of the bus voltage as the reference phase, the phase difference between the fundamental vector of the leakage current and the reference phase accurately reflects the orthogonality between the resistive and capacitive components at the same fundamental frequency of the power grid, eliminating the additional phase error introduced during frequency parameter transfer.

[0108] In this embodiment, at the clock synchronization level, GNSS timing signals are used to perform long-term frequency training on high-stability crystal oscillators or atomic clocks, locking the long-term frequency accuracy of the reference synchronization pulse to the ±1×10⁻¹² level. Then, through link-by-link loopback delay measurement and differential pre-delay compensation using programmable delay lines, the arrival time deviation caused by differences in the physical length of the transmission links is constrained within a preset synchronization error tolerance. Simultaneously, the local digital phase-locked loops at each acquisition node filter out high-frequency jitter from transmission link coupling with a loop bandwidth lower than the starting frequency of the electromagnetic interference spectrum, regenerating a local sampling clock that is strictly locked to the edge of the reference synchronization pulse. Ultimately, this ensures that the analog-to-digital conversion circuits of all widely distributed acquisition nodes across the entire station synchronously perform sampling within a residual time deviation on the order of nanoseconds, thus providing an absolute time reference for subsequent cross-interval three-phase leakage current vector synthesis. At the windowed Fourier transform level, by calculating the root mean square value of the leakage current data sequence segmented according to the power frequency cycle and comparing it with a preset multiple of the root mean square value of the entire segment, transient interference pollution segments are automatically identified and zeroed, eliminating the need for disconnector operation. The influence of sudden electromagnetic transient processes such as electrostatic discharge and corona discharge on broadband noise rise in spectrum analysis is mitigated. Then, through point-by-point weighting using the Hanning window function and radix-2 time-decimation fast Fourier transform, the signal energy is concentrated near the main lobe. Finally, three-point amplitude interpolation correction is performed on the three consecutive frequency points with the largest magnitude in the leakage current spectrum to calculate the true frequency, amplitude, and phase of the leakage current fundamental. Using the same leakage current fundamental frequency as an index, three-point phase interpolation correction is performed on the voltage spectrum, ensuring that the extracted bus voltage fundamental frequency and the leakage current fundamental frequency are mathematically strictly consistent. This eliminates the spectrum leakage error caused by non-integer cycle truncation due to real-time fluctuations in the grid frequency, as well as the frequency mismatch problem that may occur due to independent frequency searches for leakage current and voltage. It ensures that the phase difference between the leakage current fundamental vector and the reference phase in the projection calculation accurately reflects the orthogonality between the resistive and capacitive components at the same fundamental frequency of the grid, thus providing a reliable frequency domain parameter basis for the subsequent high-precision extraction of the resistive current fundamental component and three-phase spatial constraint verification.

[0109] Example 3

[0110] It should be further explained that in this embodiment, the leakage current fundamental vector of each surge arrester is projected onto the direction determined by the reference phase, including:

[0111] C101. Read the fundamental amplitude of the leakage current, the fundamental phase of the leakage current, the fundamental amplitude of the bus voltage, and the fundamental phase of the bus voltage.

[0112] In this embodiment, after the centralized monitoring host sequentially executes the windowed fast Fourier transform and three-point interpolation correction process for each surge arrester, it writes the fundamental amplitude and phase of the leakage current corresponding to each surge arrester, as well as the fundamental amplitude and phase of the bus voltage corresponding to each voltage level bus, into a fundamental parameter data table in memory, according to the correspondence between the surge arrester number, voltage level number, and first timestamp. This fundamental parameter data table uses the surge arrester number as the primary key and the first timestamp as the secondary key to establish an index structure. Each record contains seven fields: surge arrester number, voltage level number, first timestamp, fundamental amplitude of leakage current, fundamental phase of leakage current, fundamental amplitude of bus voltage, and fundamental phase of bus voltage. When the centralized monitoring host performs projection calculations, it uses the arrester number of the currently processed surge arrester and the voltage level number corresponding to the voltage level to which the surge arrester belongs as joint search conditions. It then extracts the fundamental amplitude and phase of the leakage current corresponding to the surge arrester at the current sampling moment from the fundamental parameter data table. Simultaneously, it extracts the fundamental amplitude and phase of the bus voltage belonging to the same voltage level as the surge arrester. In this embodiment, all four parameters are stored in double-precision floating-point format in the fundamental parameter data table. The unit of the leakage current fundamental amplitude is milliamperes, the unit of the bus voltage fundamental amplitude is volts, and the units of the leakage current fundamental phase and the bus voltage fundamental phase are radians, with phase values ​​ranging from -π to +π.

[0113] C102. Read the first fixed phase lag amount corresponding to the aperture time of the analog filter circuit at the front end of the current acquisition node and the first analog-to-digital conversion circuit, which are pre-calibrated and stored in the centralized monitoring host, and the second fixed phase lag amount corresponding to the aperture time of the analog filter circuit at the front end of the voltage acquisition node and the second analog-to-digital conversion circuit.

[0114] In this embodiment, the channel phase calibration parameter table for all acquisition nodes in the entire station has been generated and fixed in the non-volatile memory inside the centralized monitoring host through an offline calibration process before the system leaves the factory. The channel phase calibration parameter table has two sub-tables. The first sub-table is the current channel phase calibration sub-table, which records the mapping relationship between the node number of each current acquisition node in the entire station and the first fixed phase hysteresis corresponding to that node. The second sub-table is the voltage channel phase calibration sub-table, which records the mapping relationship between the node number of each voltage acquisition node in the entire station and the second fixed phase hysteresis corresponding to that node. For each current acquisition node in the current channel phase calibration sub-table, the calibration process for its first fixed phase lag is as follows: In the factory calibration environment, a standard AC current source capable of outputting pure capacitive current is connected to the current sensor input terminal of the current acquisition node. The phase difference between the fundamental phase of the pure capacitive reference current signal output by the standard AC current source and the fundamental phase of the standard voltage signal in the same calibration environment is precisely 90°. The current acquisition node performs a complete acquisition, analog-to-digital conversion, and windowed fast Fourier transform processing flow on the pure capacitive reference current signal, and extracts the measured value of the fundamental phase of the leakage current from the transformation result. The difference between the measured value of the fundamental phase of the leakage current and the fundamental phase of the standard voltage signal is reduced by 90 degrees. The resulting difference is the fixed phase lag introduced by the current acquisition node due to the delay of the front-end analog filter circuit group and the aperture time of the first analog-to-digital conversion circuit. This difference is recorded as the first fixed phase lag of the current acquisition node. For each voltage acquisition node in the voltage channel phase calibration sub-table, the calibration process for its second fixed phase lag is as follows: Under the same factory calibration environment, a standard AC voltage source is connected to the input terminal of the voltage acquisition node. The fundamental phase of the standard voltage signal output by the standard AC voltage source is a known reference value. The voltage acquisition node performs a complete acquisition, analog-to-digital conversion, and windowed fast Fourier transform processing flow on the standard voltage signal, and extracts the measured value of the fundamental phase of the bus voltage from the transformation result. The measured value of the fundamental phase of the bus voltage is subtracted from the known reference phase value of the standard voltage signal. The difference is the fixed phase lag introduced by the voltage acquisition node due to the delay of the front-end analog filter circuit group and the aperture time of the second analog-to-digital conversion circuit. This difference is recorded as the second fixed phase lag of the voltage acquisition node. The centralized monitoring host loads both sub-tables from non-volatile memory into memory each time it is powered on and initialized. When the centralized monitoring host performs projection calculations, it retrieves the corresponding first fixed phase lag from the current channel phase calibration sub-table based on the node number of the current acquisition node connected to the surge arrester currently being processed; and retrieves the corresponding second fixed phase lag from the voltage channel phase calibration sub-table based on the node number of the voltage acquisition node corresponding to the voltage level of the surge arrester.Both the first and second fixed phase lag values ​​are stored as constants in radians, and their values ​​remain unchanged throughout the system's lifecycle unless there is a hardware change to the front-end analog filtering circuit or analog-to-digital conversion circuit of the corresponding acquisition node.

[0115] C103. Subtract the first fixed phase lag from the fundamental phase of the leakage current to obtain the corrected fundamental phase of the leakage current.

[0116] In this embodiment, the centralized monitoring host uses the fundamental phase of the leakage current of the surge arrester read from the fundamental parameter data table in C101 as the minuend, and the first fixed phase lag corresponding to the current acquisition node connected to the surge arrester retrieved from the current channel phase calibration sub-table in C102 as the subtrahend. It then calls a double-precision floating-point subtraction instruction to calculate the difference between the minuend and the subtrahend; the resulting difference is the corrected fundamental phase of the leakage current. Essentially, this correction operation removes the fixed phase delay component introduced by the hardware circuit characteristics of the current acquisition node itself from the fundamental phase of the leakage current extracted from actual measurements. Since the front-end analog filter circuit of the current acquisition node is composed of passive devices such as resistors and capacitors and active devices such as operational amplifiers, its group delay characteristic for different frequency signals exhibits a fixed phase lag near the power frequency. Simultaneously, the first analog-to-digital conversion circuit has a fixed aperture time during the sampling and holding phase, which also introduces a fixed phase lag. The combined value of these two fixed phase lag components is the first fixed phase lag. In the corrected fundamental phase of the leakage current, the phase distortion introduced by the above hardware has been subtracted. The corrected fundamental phase of the leakage current only reflects the true fundamental phase of the leakage current signal after being converted by the current sensor at the grounding lead of the surge arrester.

[0117] C104. Subtract the second fixed phase lag from the fundamental phase of the bus voltage to obtain the corrected fundamental phase of the bus voltage.

[0118] In this embodiment, the centralized monitoring host uses the fundamental phase of the bus voltage read from the fundamental parameter data table in C101 as the minuend, and the second fixed phase lag corresponding to the voltage acquisition node at the corresponding voltage level retrieved from the voltage channel phase calibration sub-table in C102 as the subtrahend. It then calls a double-precision floating-point subtraction instruction to calculate the difference between the minuend and the subtrahend; the resulting difference is the corrected fundamental phase of the bus voltage. This correction operation is essentially equivalent to C103, removing the fixed phase delay component introduced by the hardware circuit characteristics of the voltage acquisition node from the fundamental phase of the bus voltage extracted from actual measurements. The group delay of the front-end analog filter circuit near the power frequency and the aperture time of the second analog-to-digital converter circuit also introduce a fixed phase lag; the combined value of these fixed phase lags is the second fixed phase lag. In the corrected fundamental phase of the bus voltage, the phase distortion introduced by the hardware has been subtracted, and the corrected fundamental phase of the bus voltage only reflects the true fundamental phase of the bus voltage signal on the secondary side of the voltage transformer.

[0119] C105. Subtract the corrected fundamental phase of the bus voltage from the corrected fundamental phase of the leakage current to obtain the voltage-current phase difference.

[0120] In this embodiment, the centralized monitoring host uses the corrected leakage current fundamental phase obtained from C103 as the minuend and the corrected bus voltage fundamental phase obtained from C104 as the subtrahend. It then calls a double-precision floating-point subtraction instruction to calculate the difference between the minuend and the subtrahend. This difference is the voltage-current phase difference. This voltage-current phase difference characterizes the difference in fundamental phase angle between the leakage current signal flowing through the arrester's grounding lead and the bus voltage signal applied to the arrester at the synchronous sampling moment. Since the fundamental phase of the corrected leakage current and the fundamental phase of the corrected bus voltage have both had their respective hardware-fixed phase lag of the acquisition channels deducted, and both signals are sampled by their respective analog-to-digital converter circuits at the synchronously aligned sampling edges under the synchronous pulse triggering at the same first timestamp, the voltage-current phase difference only includes the true phase relationship between the leakage current signal and the bus voltage signal determined by the equivalent circuit characteristics of the surge arrester body, and does not include the asymmetric additional phase bias introduced between the current acquisition node and the voltage acquisition node due to the time delay difference of the front-end analog filter circuit group and the time difference of the aperture of the analog-to-digital converter circuit.

[0121] C106. Calculate the cosine value of the phase difference between the voltage and current.

[0122] In this embodiment, the centralized monitoring host calls the cosine function operation instruction from the built-in mathematical function library. The voltage-current phase difference calculated by C105 is used as the input parameter of the cosine function. The cosine function operation instruction performs a Taylor series expansion or lookup table combined with interpolation numerical calculation on the input parameter, returning the cosine function value corresponding to the input parameter. The centralized monitoring host stores this cosine function value in a temporary variable in memory in double-precision floating-point format. Mathematically, this cosine value represents the direction cosine of the angle between the fundamental vector of the leakage current and the fundamental vector of the bus voltage, and its value ranges from -1 to +1. When the fundamental vector of the leakage current and the fundamental vector of the bus voltage are in phase, the voltage-current phase difference is 0, and the cosine value is +1; when the fundamental vector of the leakage current and the fundamental vector of the bus voltage are orthogonal, the voltage-current phase difference is 90°, and the cosine value is 0; when the fundamental vector of the leakage current and the fundamental vector of the bus voltage are out of phase, the voltage-current phase difference is 180°, and the cosine value is -1.

[0123] C107. Multiply the fundamental amplitude of the leakage current by the cosine of the phase difference between the voltage and current, and use the product as the fundamental component of the current resistive current of the surge arrester.

[0124] In this embodiment, the centralized monitoring host uses the fundamental amplitude of the leakage current read from the fundamental parameter data table in C101 as the multiplier and the cosine of the voltage-current phase difference calculated in C106 as the multiplicand. It then calls a double-precision floating-point multiplication instruction to calculate the product of the multiplier and multiplicand. The resulting product is the current resistive current fundamental component of the surge arrester. The centralized monitoring host stores this resistive current fundamental component in double-precision floating-point format, with units of milliamperes (mA). The mathematical essence of this multiplication operation is to project the magnitude of the leakage current fundamental vector onto a direction determined by the corrected fundamental phase of the bus voltage. The real part length in this direction after projection is the amplitude of the resistive current component in phase with the bus voltage. Physically, the resistive current fundamental component characterizes the active component in the leakage current that is in phase with the bus voltage. This active component is mainly generated by the nonlinear resistance characteristics of the surge arrester's metal oxide varistors, and its amplitude directly reflects the aging degree and moisture condition of the varistors. Since the first fixed phase lag of the current acquisition node and the second fixed phase lag of the voltage acquisition node have been compensated and deducted in C103 and C104 respectively, the voltage and current phase difference between the fundamental vector of the leakage current and the fundamental vector of the bus voltage has eliminated the asymmetric phase bias of the two acquisition channels. Therefore, the voltage and current phase difference on which this projection calculation depends can accurately reflect the true voltage and current phase relationship of the arrester body. This avoids the problem that the small phase measurement error in the high phase sensitive area caused by the capacitive component in the leakage current being much larger than the resistive component is amplified by projection, causing the resistive current extraction value to deviate significantly from the true value. This ensures the extraction accuracy of the fundamental component of the resistive current and provides a reliable data basis for the subsequent arrester condition assessment and early warning based on the fundamental component of the resistive current.

[0125] It should be further explained that in this embodiment, the three leakage current fundamental vectors are vector synthesized to obtain a synthesized vector, including:

[0126] D101. Read the electrical bay configuration table from the non-volatile memory of the centralized monitoring host. The electrical bay configuration table stores the correspondence between the surge arrester number of each surge arrester in the entire station and the number of the three-phase surge arrester group to which the surge arrester belongs, as well as the phase identifier of the surge arrester in the three-phase surge arrester group.

[0127] In this embodiment, the non-volatile memory of the centralized monitoring host stores an electrical bay configuration table. During the installation and commissioning phase of the substation surge arrester centralized monitoring system, engineering technicians confirm the electrical bay assignment of each surge arrester in the primary system based on the actual electrical main wiring diagram of the substation and the results of on-site surveys. The table is then entered and stored item by item through the configuration management interface of the centralized monitoring host. The electrical bay configuration table contains complete records of all surge arresters in the entire station. Each record corresponds to a unique surge arrester within the station. The fields of the record include the surge arrester number, the three-phase surge arrester group number to which the surge arrester belongs, the phase identifier of the surge arrester within the three-phase surge arrester group, the voltage level number of the surge arrester, and the name of the electrical bay to which the surge arrester belongs. Each surge arrester is assigned a unique numerical code across the entire station. Similarly, each three-phase surge arrester group is assigned a unique numerical code across the entire station. Three surge arresters belonging to the same three-phase surge arrester group share the same group number. The phase identifier is an enumerated value for phase A, phase B, or phase C. During each power-on initialization, the centralized monitoring host loads the electrical bay configuration table entirely from non-volatile memory into memory and establishes a hash index using the three-phase surge arrester group number as the key. This allows for quick retrieval of surge arrester and phase information within any three-phase surge arrester group during operation.

[0128] D102. According to the electrical bay configuration table, all surge arresters in the station are divided into multiple three-phase surge arrester groups according to the three-phase surge arrester group number. Each three-phase surge arrester group consists of a surge arrester with phase A, a surge arrester with phase B, and a surge arrester with phase C.

[0129] In this embodiment, the centralized monitoring host traverses the loaded electrical bay configuration table in memory, extracts all unique three-phase surge arrester group numbers that have appeared in the table, and arranges these numbers in ascending order to form a three-phase surge arrester group number list. For each three-phase surge arrester group number in the list, the centralized monitoring host uses that number as a filter in the electrical bay configuration table to select all surge arrester records belonging to that group. The selected records are then categorized and statistically analyzed according to their phase identifiers. The centralized monitoring host checks whether the three-phase surge arrester group contains exactly one surge arrester with phase identifier A, one surge arrester with phase identifier B, and one surge arrester with phase identifier C. If any phase arrester is missing from the three-phase surge arrester group, or if any phase arrester has more than one arrester, the centralized monitoring host determines that the configuration of the three-phase surge arrester group is incomplete. It writes the group number and corresponding configuration anomaly type to the anomaly log, generates a configuration anomaly alarm, and sends it to the monitoring backend via the communication network. Simultaneously, the three-phase surge arrester group is marked as unprocessable, and subsequent vector synthesis and zero-sequence deviation verification processes are not performed on the group. For a three-phase surge arrester group with complete configuration and all three phase arresters, the centralized monitoring host constructs an intra-group arrester mapping table in memory. This mapping table contains three entries: Phase A (storage the arrester number of Phase A), Phase B (storage the arrester number of Phase B), and Phase C (storage the arrester number of Phase C). Subsequent vector synthesis operations for this group are based on this intra-group arrester mapping table to obtain the arrester numbers for each phase.

[0130] D103. For any three-phase surge arrester group, using the first timestamp and the corresponding three-phase surge arrester group number as joint search conditions, extract the fundamental amplitude and corrected fundamental phase of the leakage current of phase A surge arrester, the fundamental amplitude and corrected fundamental phase of the leakage current of phase B surge arrester, and the fundamental amplitude and corrected fundamental phase of the leakage current of phase C surge arrester from the stored resistive current data table.

[0131] In this embodiment, before performing vector synthesis on a certain three-phase surge arrester group, the centralized monitoring host uses the currently processed first timestamp as the first timestamp retrieval condition and the three-phase surge arrester group number as the group number retrieval condition, together forming a joint retrieval condition, to search the resistive current data table in memory. This resistive current data table is a data table that the centralized monitoring host writes into the surge arrester's fundamental leakage current amplitude, corrected fundamental leakage current phase, and fundamental resistive current component calculated at the current sampling time after C107 is completed, according to the surge arrester number and the first timestamp. The corrected fundamental leakage current phase is the corrected fundamental leakage current phase obtained after C103 is completed. The centralized monitoring host retrieves records from the resistive current data table based on the arrester numbers stored in the A-phase entry of the three-phase arrester group's intra-group arrester mapping table constructed by D102. Records with arrester numbers equal to the A-phase arrester number and whose first timestamps are equal to the current first timestamp are found in the arrester data table. The fundamental amplitude of the leakage current is extracted from these records as the fundamental amplitude of the leakage current for the A-phase arrester, and the corrected fundamental phase of the leakage current is extracted as the corrected fundamental phase of the leakage current for the A-phase arrester. Similarly, based on the arrester numbers stored in the B-phase entry of the intra-group arrester mapping table, the fundamental amplitude and corrected fundamental phase of the leakage current for the B-phase arrester are retrieved from the resistive current data table; and based on the arrester numbers stored in the C-phase entry of the intra-group arrester mapping table, the fundamental amplitude and corrected fundamental phase of the leakage current for the C-phase arrester are retrieved from the resistive current data table. If, during the retrieval process, it is found that the corresponding record for any phase arrester in the three-phase arrester group does not exist at the current first timestamp, or the data validity in the corresponding record is marked as unavailable, the centralized monitoring host will terminate the vector synthesis processing flow for the three-phase arrester group, mark the fundamental resistive current components calculated by the three arresters of phases A, B, and C in the three-phase arrester group at the current sampling time as invalid data, and record the reason for invalidity as missing corresponding phase data.

[0132] D104. Using the fundamental amplitude of the leakage current of phase A arrester as the modulus and the corrected fundamental phase of the leakage current of phase A arrester as the argument, calculate the real and imaginary parts of the fundamental vector of the leakage current of phase A arrester; using the fundamental amplitude of the leakage current of phase B arrester as the modulus and the corrected fundamental phase of the leakage current of phase B arrester as the argument, calculate the real and imaginary parts of the fundamental vector of the leakage current of phase C arrester; using the fundamental amplitude of the leakage current of phase C arrester as the modulus and the corrected fundamental phase of the leakage current of phase C arrester as the argument, calculate the real and imaginary parts of the fundamental vector of the leakage current of phase C arrester.

[0133] In this embodiment, the centralized monitoring host records the fundamental amplitude of the leakage current of phase A surge arrester extracted from the resistive current data table by D103 as the phase A magnitude, and the corrected phase of the fundamental leakage current of phase A as the phase A angle. The centralized monitoring host calls the cosine function operation instruction in the built-in mathematical function library, using the phase A angle as the input parameter of the cosine function, to calculate the cosine value of the phase A angle; it also calls the sine function operation instruction in the built-in mathematical function library, using the phase A angle as the input parameter of the sine function, to calculate the sine value of the phase A angle. The centralized monitoring host performs a floating-point multiplication operation on the phase A magnitude and the cosine value of the phase A angle, and the product is used as the real part of the fundamental vector of the phase A leakage current, stored in memory as the real part variable of the fundamental vector of the phase A leakage current; it also performs a floating-point multiplication operation on the phase A magnitude and the sine value of the phase A angle, and the product is used as the imaginary part of the fundamental vector of the phase A leakage current, stored in memory as the imaginary part variable of the fundamental vector of the phase A leakage current. The centralized monitoring host processes the data of the B-phase surge arrester using the same method. The fundamental amplitude of the leakage current of the B-phase surge arrester is recorded as the B-phase magnitude, and the corrected fundamental phase of the B-phase leakage current is recorded as the B-phase amplitude. The cosine value of the B-phase amplitude is calculated using a cosine function, and the sine value of the B-phase amplitude is calculated using a sine function. Multiplying the B-phase magnitude by the cosine of the B-phase amplitude yields the real part of the B-phase leakage current fundamental vector, and multiplying the B-phase magnitude by the sine of the B-phase amplitude yields the imaginary part of the B-phase leakage current fundamental vector. The centralized monitoring host processes the data of the C-phase surge arrester using the same method. The fundamental amplitude of the leakage current of the C-phase surge arrester is recorded as the C-phase magnitude, and the corrected fundamental phase of the C-phase leakage current is recorded as the C-phase amplitude. The product of the C-phase magnitude and the cosine of the C-phase amplitude is calculated as the real part of the C-phase leakage current fundamental vector, and the product of the C-phase magnitude and the sine of the C-phase amplitude is calculated as the imaginary part of the C-phase leakage current fundamental vector. The above six floating-point values, namely the real part of phase A, the imaginary part of phase A, the real part of phase B, the imaginary part of phase B, the real part of phase C, and the imaginary part of phase C, are all stored in independent temporary variables in memory in double-precision floating-point format.

[0134] D105. Add the real parts of the fundamental wave vectors of the A-phase leakage current, B-phase leakage current, and C-phase leakage current to obtain the real part of the composite vector; add the imaginary parts of the fundamental wave vectors of the A-phase leakage current, B-phase leakage current, and C-phase leakage current to obtain the imaginary part of the composite vector; the composite vector is formed by the real part and the imaginary part of the composite vector.

[0135] In this embodiment, the centralized monitoring host sequentially reads the real parts of the fundamental wave vectors of phase A, phase B, and phase C leakage currents calculated by D104 and stored in temporary memory variables. It then calls a floating-point addition instruction to add these three real parts, and the sum of the additions is used as the real part of the composite vector, stored in memory as the composite vector real part variable. The centralized monitoring host also sequentially reads the imaginary parts of the fundamental wave vectors of phase A, phase B, and phase C leakage currents calculated by D104 and stored in temporary memory variables. It then calls a floating-point addition instruction to add these three imaginary parts, and the sum of the additions is used as the composite vector imaginary part, stored in memory as the composite vector imaginary part variable. Both the real and imaginary parts of the composite vector are stored together in memory in double-precision floating-point format, forming a complete complex composite vector. The composite vector represents the vector sum of the fundamental leakage current vectors of the three surge arresters (phases A, B, and C) at the sampling time. Under ideal operating conditions where the three-phase power system is completely symmetrical and none of the three surge arresters in the three-phase arrester group are affected by electromagnetic interference, the fundamental leakage current vectors of phases A, B, and C have equal amplitudes and their phases differ by 120° in the complex plane. The vector sum of the three is zero, and both the real and imaginary parts of the composite vector are zero. When there is a certain degree of asymmetry in the three-phase system, or when the leakage current measurement of one or more phases of the surge arrester in the three-phase arrester group is interfered with by electromagnetic transient processes such as disconnecting switch operation or corona discharge, the amplitudes of the three-phase leakage current fundamental vectors are no longer equal, or the phases no longer satisfy the strict 120° phase difference relationship. The vector sum of the three will deviate from zero, and the real or imaginary part of the composite vector will no longer be zero. This synthesized vector will be used to calculate the magnitude and compared with a preset zero-sequence deviation allowable threshold to determine whether the measurement data of the three-phase surge arrester group is valid.

[0136] This embodiment deeply embeds channel phase differential compensation and three-phase spatial constraint verification into the resistive current extraction link. Specifically, at the resistive current fundamental component calculation level, differential compensation is performed on the measured leakage current fundamental phase and bus voltage fundamental phase using the factory-calibrated first fixed phase lag of the current acquisition node and the second fixed phase lag of the voltage acquisition node. This fundamentally eliminates the asymmetric additional phase bias introduced by the time delay difference of the front-end analog filter circuit group and the aperture time difference of the analog-to-digital conversion circuit between the current acquisition node and the voltage acquisition node. This ensures that the voltage and current phase difference only reflects the true phase relationship determined by the equivalent circuit characteristics of the surge arrester itself. Therefore, in the high phase-sensitive region where the capacitive component of the leakage current is much larger than the resistive component, this avoids the problem of small phase measurement errors being amplified by the cosine function of the projection operation, leading to a significant deviation of the extracted resistive current value from the true value, thus ensuring the accuracy of the resistive current extraction. The fundamental component of the current has a true characterization ability for the aging and moisture state of valve plates. At the three-phase spatial constraint verification level, the surge arresters of the entire station are precisely grouped according to the three-phase surge arrester group number by reading the electrical bay configuration table. The leakage current fundamental vector of the A-phase, B-phase and C-phase surge arresters in the group is vector synthesized in complex form. Utilizing the physical constraint that the vector sum is zero under the symmetrical operation state of the three-phase power system, the comparison between the magnitude of the synthesized vector and the preset zero-sequence deviation allowable threshold is used as the data validity criterion. Abnormal measurement data caused by electromagnetic transient processes such as disconnecting switch operation and corona discharge are automatically identified and eliminated. Only the resistive current fundamental component that meets the three-phase circuit topology consistency constraint is marked as valid data. Thus, cross-bay redundancy verification and data purification are achieved without relying on additional sensors and manual intervention, providing a high-confidence data foundation for subsequent long-term trend assessment.

[0137] Example 4

[0138] Please see Figure 3 It should be further noted that this embodiment calculates the average resistive current and the resistive current growth rate within the evaluation period for each surge arrester, including:

[0139] E101. For each surge arrester, using a preset evaluation period as the time window, extract all fundamental components of the resistive current that are marked as valid data within the current evaluation period from the historical resistive current data table of the surge arrester to form an evaluation sample sequence.

[0140] In this embodiment, the centralized monitoring host maintains an independent historical resistive current data table for each surge arrester in the entire station in its memory. This data table adopts a time-series database storage structure, organizing records in chronological order using the first timestamp as the index key. When writing each historical resistive current record, the centralized monitoring host appends four fields to the table: the corresponding surge arrester number, the first timestamp, the fundamental component value of the resistive current obtained through projection calculation and spatial constraint verification, and a data validity flag. This appends the data to the table without overwriting existing records. The data validity flag is a single-byte enumeration value, with zero for valid data and 1 for invalid data. The preset evaluation cycle duration parameter is stored in the parameter configuration area of ​​the centralized monitoring host in hours, with a typical value of 24 hours, meaning one calendar day constitutes one evaluation cycle. When calculating the evaluation cycle, the centralized monitoring host reads the evaluation cycle duration parameter from the parameter configuration area. Combining this with the current system clock's calendar time and timestamp, it calculates the start and end absolute times of the current evaluation cycle. The start absolute time equals the current system absolute time minus the number of seconds corresponding to the evaluation cycle duration parameter, and the end absolute time equals the current system absolute time. The centralized monitoring host locks the corresponding historical resistive current data table based on the surge arrester's arrester number. Using the start and end absolute times as the time range, it performs a time range scan on the data table, reading each record whose first timestamp falls within that time range. For each read record, the centralized monitoring host checks the value of its data validity flag field. If the field value equals the valid data flag, it extracts the fundamental resistive current component value from that record and appends it sequentially to a temporary one-dimensional floating-point array in the order it was read. This array constitutes the evaluation sample sequence. After the scan is complete, if the surge arrester does not generate any fundamental resistive current components marked as valid data within the current evaluation cycle, the evaluation sample sequence is an empty array.

[0141] E102. Count the number of sample points in the evaluation sample sequence. When the number of sample points is less than the preset minimum sample number threshold, abandon the calculation of the average resistive current and the resistive current growth rate for this evaluation period, and generate a data shortage mark.

[0142] In this embodiment, the centralized monitoring host obtains the array length of the evaluation sample sequence constructed by E101, that is, the total number of floating-point elements contained in the array, which is the number of sample points. The parameter configuration area of ​​the centralized monitoring host stores a preset minimum sample number threshold parameter. The value of the minimum sample number threshold parameter is determined by the evaluation period duration and the uniform sampling interval of the entire station. The specific calculation method is as follows: the total evaluation period duration is divided by the station-wide synchronous sampling period to obtain the theoretical maximum number of samplings within the evaluation period. 50% of the theoretical maximum number of samplings is then taken and rounded down as the minimum sample number threshold parameter. In this embodiment, the minimum sample number threshold parameter is taken as 50% of the theoretical maximum sampling number and rounded down. This is because, within a preset evaluation period, the theoretical maximum sampling number is determined by dividing the total evaluation period duration by the unified synchronous sampling interval across the entire station, representing the total number of resistive current fundamental component samples that should be acquired within that period. However, in actual operation, data from some sampling moments may be marked as invalid due to electromagnetic interference as determined by the three-phase spatial constraint verification, or may fail to be successfully uploaded to the centralized monitoring host due to momentary interruptions in the communication link or momentary failures of the acquisition node, resulting in insufficient usable data. The effective sample size is inevitably less than the theoretical maximum. If the minimum sample size threshold is set too high, such as requiring the effective sample size to reach more than 80% of the theoretical maximum, then when occasional operations or short-term electromagnetic environment degradation in the substation cause a slight increase in the proportion of invalid data, it is very easy to trigger the insufficient data flag, causing the evaluation cycle to be frequently judged as invalid, resulting in the interruption of the calculation continuity of the average resistive current and growth rate, which seriously weakens the practicality of long-term trend monitoring and the trust of operation and maintenance personnel in the system. If the minimum sample size threshold is set too low, such as only requiring the effective sample size to reach 10% of the theoretical maximum, then the evaluation... The small amount of remaining valid data in the sample sequence may be concentrated in a specific period of the evaluation cycle, failing to uniformly cover the peak-valley changes of the power grid load and the diurnal cycle of ambient temperature and humidity. The average resistive current calculated based on this will deviate significantly from the true average level within that cycle, losing statistical representativeness. Statistical analysis of long-term operating data from online monitoring systems of surge arresters in multiple substations shows that, under normal operating conditions without continuous strong electromagnetic interference, the proportion of invalid data removed due to spatial constraints typically does not exceed 30% of the theoretical maximum sampling number. Considering factors such as intermittent packet loss in communication, the typical value of the effective sample size is approximately 70% to 90% of the theoretical maximum. Using 50% as the minimum sample size threshold is equivalent to requiring the effective sample size to reach at least half of the theoretical maximum. This proportion is significantly lower than the lower limit of the typical effective sample size under normal operating conditions, reserving sufficient margin for abnormal operating conditions. At the same time, it ensures that when the effective data coverage is less than half, the evaluation cycle must have experienced a long-term communication interruption or continuous strong electromagnetic interference across the entire station. In this case, forcibly calculating the average resistive current will introduce unacceptable deviations. Abandoning the calculation and generating a data insufficiency marker is the only reasonable handling strategy.For example, in the scenario described in Example 1, the station-wide synchronous sampling period is 1 second, the evaluation period is 24 hours, the theoretical maximum number of samplings is 86,400, and the minimum sample size threshold is 50% rounded down to 43,200. On that day, the surge arrester actually acquired 78,200 resistive current fundamental components marked as valid data, with a valid data ratio of approximately 90.5%, far exceeding the threshold requirement of 43,200, thus fully satisfying the statistical reliability. Therefore, using 50% of the theoretical maximum number of samplings as the minimum sample size threshold achieves the optimal balance between the utilization rate of valid data during the evaluation period and the reliability of statistical conclusions.

[0143] The centralized monitoring host compares the number of sample points with the minimum sample number threshold parameter. When the number of sample points is less than the minimum sample number threshold parameter, the centralized monitoring host determines that the accumulated effective resistive current fundamental component sample size in this evaluation period does not meet the minimum requirements for statistical reliability, and therefore does not calculate the average resistive current and resistive current growth rate. The centralized monitoring host immediately constructs a data insufficiency marker record in memory. This record includes the surge arrester number, the timestamp of the absolute end time of this evaluation period, and the marker type value. The marker type value is a preset fixed code indicating insufficient data. This data insufficiency marker record is written to the alarm log buffer of the centralized monitoring host and sent to the substation monitoring backend in the form of an alarm message in the next communication period, prompting the maintenance personnel that the surge arrester has insufficient effective monitoring data in the corresponding evaluation period, which may be due to communication interruption or continuous strong electromagnetic interference. The centralized monitoring host then skips post-processing E103 to E105 and directly ends the processing of this surge arrester in this evaluation period. When the number of sample points is greater than or equal to the minimum sample number threshold parameter, the centralized monitoring host continues to execute E103.

[0144] E103. When the number of sample points is greater than or equal to the minimum sample number threshold, sort the fundamental components of resistive current in the evaluation sample sequence according to their numerical values, and remove the first preset proportion sample points with the largest values ​​and the second preset proportion sample points with the smallest values ​​in the sorted sequence to obtain the extreme value removal sample sequence.

[0145] In this embodiment, when the number of sample points meets the minimum sample size threshold, the centralized monitoring host performs a numerical sorting operation on all resistive current fundamental component values ​​in the evaluation sample sequence. The sorting algorithm is a quicksort algorithm, and the sorting direction is in ascending order of values. After sorting, an ascending sample sequence is obtained. The parameter configuration area of ​​the centralized monitoring host stores a first preset ratio parameter and a second preset ratio parameter. Both the first preset ratio parameter and the second preset ratio parameter are fixed small percentage constants, with the first preset ratio parameter equal to 10% and the second preset ratio parameter equal to 10%. The basis for setting the first and second preset ratio parameters to 10% is as follows: The majority of the effective resistive current fundamental component samples collected within an evaluation period correspond to the actual valve leakage current level of the surge arrester under steady-state operating conditions, and their values ​​exhibit an approximately normal or symmetrical distribution around the actual average value of that period. However, due to the residual effects of sudden electromagnetic transient processes such as occasional disconnecting switch operations, corona discharges, and lightning surges within the substation, as well as instantaneous quantization noise spikes in the analog-to-digital conversion circuit of the current acquisition node and occasional bit errors in the communication link, a small number of "outliers" with abnormally high or low values ​​inevitably appear in the evaluation sample sequence. These outliers are numerically far from the main distribution range of the samples. If they are directly included in the arithmetic mean calculation, they will significantly pull the average value away from the true central trend, leading to a systematic bias in the estimation of the resistive current average value. If the rejection ratio is set too low, such as only rejecting 1% to 2% at the beginning and end, the coverage probability of the aforementioned occasional outliers is insufficient, and a small number of unrejected extreme values ​​will still affect the average value. The significant pull-up or suppression effect of the surge arrester prevents the goal of extreme value removal from being fully achieved. If the removal ratio is set too high, such as removing more than 20% at the beginning and end, a large number of normal sample points reflecting the actual operating state of the surge arrester will be incorrectly excluded. Although the dispersion of the sample sequence after extreme value removal is artificially compressed, it loses its representativeness of the true distribution of resistive current within the evaluation period. The average value calculated based on this will be overly smoothed, masking the true fluctuation characteristics of the valve plate status information. Statistical analysis of the massive effective resistive current data accumulated over a long period by the online monitoring systems of surge arresters in multiple substations shows that, under normal operating conditions, the proportion of outliers that deviate significantly from the main sample due to residual interference usually does not exceed 5% of the total effective sample volume in each evaluation period. Taking 10% as the initial and final removal ratio, which is about twice the actual proportion of outliers, provides sufficient coverage margin for the statistical fluctuation of the outlier ratio, ensuring that extreme values ​​introduced by various occasional interferences are reliably removed, while strictly controlling the removal range to within a small portion of the total sample volume, retaining 80% of the steady-state effective samples for average value calculation.For example, in the scenario described in Example 1, the number of valid sample points within the evaluation period is 78,200. After removing the 7,820 sample points with the largest and 7,820 sample points with the smallest values ​​at a ratio of 10% each, the remaining 62,560 samples constitute the outlier removal sample sequence. This sequence not only eliminates the pulling effect of residual interference peaks on the average value, but also fully retains the complete statistical information of the arrester's steady-state operation within the evaluation period. Therefore, setting both the first and second preset ratios to 10% achieves an optimal balance between the sufficiency of outlier removal and the completeness of steady-state data retention.

[0146] The centralized monitoring host calculates the number of high-order and low-order elements to be removed based on the total number of elements in the ascending sample sequence. The number of high-order elements to be removed is equal to the total number of elements multiplied by a first preset ratio parameter and rounded down. The number of low-order elements to be removed is equal to the total number of elements multiplied by a second preset ratio parameter and rounded down. The centralized monitoring host performs a tail deletion operation on the ascending sample sequence, continuously deleting elements from the last element towards the head of the sequence. The number of elements deleted equals the number of high-order elements removed. The deleted elements are the resistive current fundamental components with the largest values ​​throughout the entire evaluation period. The centralized monitoring host then performs a head deletion operation on the ascending sample sequence after the tail deletion operation, continuously deleting elements from the first element towards the tail of the sequence. The number of elements deleted equals the number of low-order elements removed. The deleted elements are the resistive current fundamental components with the smallest values ​​throughout the entire evaluation period. After the head and tail deletions are completed, the remaining elements in the ascending sample sequence are rearranged according to their original sampling time order to form a de-extreme value sample sequence. Through this extreme value removal process, the centralized monitoring host will exclude individual abnormally high values ​​caused by residual electromagnetic interference and individual abnormally low values ​​caused by instantaneous zero drift of the acquisition node or transient saturation of the sensor from the sample sequence during the evaluation period. The resistive current fundamental component value retained in the extreme value removal sample sequence can better represent the true steady-state operation level of the surge arrester during this evaluation period.

[0147] E104. Calculate the arithmetic mean of the extreme value sample sequence as the average resistive current for this evaluation period, and store the average resistive current in the historical sequence of the average resistive current of the surge arrester.

[0148] In this embodiment, the centralized monitoring host performs an accumulation and summation operation on the extreme value removal sample sequence obtained from E103. A double-precision floating-point accumulator variable is initialized to zero. Then, each fundamental component value of the resistive current in the extreme value removal sample sequence is read sequentially, added to the current value of the accumulator, and the result is written back to the accumulator, until all elements in the sequence have been accumulated. The centralized monitoring host performs a floating-point division operation between the final value of the accumulator and the total number of elements in the extreme value removal sample sequence. The quotient of the division operation is taken as the average resistive current value for this evaluation period. The centralized monitoring host stores this average resistive current value in memory in double-precision floating-point format and simultaneously generates a historical record of the average resistive current value. This record contains three fields: the surge arrester number, the timestamp of the absolute end time of this evaluation period, and the average resistive current value. The centralized monitoring host appends this record to the historical sequence of resistive current average values ​​corresponding to the surge arrester. This historical sequence is implemented in memory as a fixed-length circular queue data structure. The maximum storage depth of the queue is equal to the preset fitting window length parameter plus a fixed expansion margin value, which is fixed at five, to accommodate several additional historical average value records retained outside the fitting window. When the queue is full, the write operation of a new record will automatically overwrite the record with the oldest storage time in the queue, ensuring that the queue always stores the resistive current average values ​​of the most recent evaluation periods.

[0149] E105. When the number of consecutively stored resistive current average values ​​in the historical sequence of resistive current average values ​​reaches the preset fitting window length, the least squares linear fitting is performed on the most recent resistive current average values ​​of the fitting window length, with the storage sequence number in the historical sequence of resistive current average values ​​as the horizontal axis and the resistive current average value as the vertical axis. The slope of the fitted straight line is used as the resistive current growth rate of this evaluation period.

[0150] In this embodiment, after successfully adding a new resistive current average value record to the historical sequence of resistive current average values ​​for a surge arrester, the centralized monitoring host immediately scans and counts all currently stored records in the historical sequence, counting the number of records where the resistive current average value field is not null. When the number of records is less than the preset fitting window length parameter, the centralized monitoring host determines that the accumulated historical resistive current average value data is insufficient for reliable linear trend estimation, and does not perform resistive current growth rate calculation or update the resistive current growth rate value of the surge arrester. When the number of records is greater than or equal to the preset fitting window length parameter, the centralized monitoring host extracts the latest batch of records from the historical sequence of resistive current average values, the number of which is equal to the fitting window length parameter. This batch of records is the sample set participating in this fitting operation. The centralized monitoring host assigns an integer storage sequence number to each record according to the order of the timestamps of the absolute termination time of this batch of records. The storage sequence number starts from zero and increases sequentially, with the earliest record corresponding to a storage sequence number of zero and the latest record corresponding to a storage sequence number equal to the fitting window length parameter minus one. The centralized monitoring host uses the storage sequence number as the horizontal axis data sequence and the average resistive current stored in each record as the vertical axis data sequence. These two sequences correspond one-to-one, forming a two-dimensional data point set for fitting. The centralized monitoring host performs least-squares linear fitting on this two-dimensional data point set. The fitting process includes: calculating the average of all storage sequence numbers; calculating the average of all resistive current averages; calculating the difference between the storage sequence number and the average of the storage sequence numbers for each data point, and the difference between the average resistive current and the average of the average resistive current for each data point; multiplying and summing these two differences for each data point, and summing the squares of the differences between the storage sequence number and the average of the storage sequence numbers for each data point; dividing the sum of multiplications by the sum of squares, the quotient is the slope of the fitted line. The centralized monitoring host uses this slope value as the resistive current growth rate for the current evaluation period, in milliamperes divided by the evaluation period duration, and stores it in memory. This least-squares linear fitting method uses the average resistive current from multiple consecutive evaluation periods to jointly estimate the changing trend. It can effectively suppress the influence of small fluctuations in the average resistive current caused by random statistical fluctuations of the residual zero mean within a single evaluation period on the calculation of the rate of change. This makes the estimation result of the resistive current growth rate robustly reflect the overall aging development direction and development rate of the surge arrester varistor within the time scale of the preset fitting window length.

[0151] In this embodiment, at the single-cycle statistical level, a minimum sample size threshold of 50% of the number of valid sample points within the evaluation cycle compared to the theoretical maximum sampling number is used. This automatically filters out evaluation cycles where insufficient valid data accumulation is caused by communication interruptions or continuous strong electromagnetic interference, generating a data insufficiency alarm. This avoids the damage to the reliability of statistical conclusions caused by an excessively small sample size. After passing the sufficiency test, the evaluation sample sequence is sorted in ascending order, and abnormally high and low values ​​are removed at a ratio of 10% at the beginning and 10% at the end. This effectively eliminates the pulling effect of occasional abnormal data such as residual electromagnetic interference spikes and instantaneous zero drift at acquisition nodes on the arithmetic mean, making the resistive current average more robustly reflect the true value of the surge arrester varistor within the current evaluation cycle. Steady-state level; At the multi-cycle trend estimation level, a time series is constructed using the average resistive current of multiple consecutive evaluation cycles. Least squares linear fitting is used, and the slope of the fitted line is taken as the resistive current growth rate. The estimation of aging trend is extended from the finite difference between two adjacent points to the overall regression of multi-cycle data. This significantly suppresses the disturbance of the sign and amplitude of the rate of change caused by the random fluctuation of the residual zero mean in a single evaluation cycle. This allows the positive and negative direction and magnitude of the resistive current growth rate to robustly reflect the true aging development direction and rate of the surge arrester valve within the preset fitting window time scale. Thus, while reducing the false alarm rate caused by statistical fluctuations, it achieves early and sensitive warning of the slow aging process of the valve valve.

[0152] Example 5

[0153] Another embodiment of the present invention provides: a centralized monitoring method for substation surge arresters based on clock synchronization, comprising:

[0154] S1. Generate a unified time synchronization pulse and distribute the time synchronization pulse in parallel to all current acquisition nodes or voltage acquisition nodes in the entire station to force the sampling edges of each current acquisition node or voltage acquisition node to align.

[0155] S2. Install m current acquisition nodes one by one on the grounding lead of each surge arrester in the substation. Each current acquisition node includes a current sensor and a first analog-to-digital conversion circuit. The first analog-to-digital conversion circuit synchronously samples the leakage current under the trigger of the time synchronization pulse and acquires m leakage current digital signals with a first timestamp; where m is an integer greater than 1.

[0156] S3. Connect the input terminals of n voltage acquisition nodes to the secondary side of the substation bus voltage transformer. Each voltage acquisition node includes a second analog-to-digital converter circuit. The second analog-to-digital converter circuit synchronously samples the bus voltage under the trigger of the time synchronization pulse and acquires n voltage digital signals with the first timestamp attached; where n is an integer greater than or equal to 1.

[0157] S4. Obtain the leakage current digital signal and the voltage digital signal carrying the same first timestamp, perform windowed fast Fourier transform on the leakage current digital signal and the voltage digital signal within the same time window, and extract the leakage current fundamental vector constructed by the leakage current fundamental amplitude and leakage current fundamental phase of each arrester, as well as the bus voltage fundamental amplitude and bus voltage fundamental phase from the transformation result.

[0158] S5. Using the fundamental phase of the bus voltage as a reference phase, project the fundamental vector of the leakage current of each surge arrester into the direction determined by the reference phase, and take the real part of the projection as the fundamental component of the current resistive current of the surge arrester.

[0159] S6. Based on the electrical bay assignment relationship of surge arresters in the substation, all surge arresters in the substation are divided into multiple three-phase surge arrester groups. For any three-phase surge arrester group, the leakage current fundamental vectors of the A-phase surge arrester, B-phase surge arrester and C-phase surge arrester in the group are obtained at the same sampling time, and the three leakage current fundamental vectors are vector synthesized to obtain the synthesized vector.

[0160] S7. Calculate the magnitude of the synthesized vector and compare it with a preset zero-sequence deviation allowable threshold. If the magnitude is greater than the zero-sequence deviation allowable threshold, it is determined that the measurement of this group is subject to electromagnetic interference, and the fundamental component of the resistive current obtained by all surge arresters in this group is marked as invalid data; otherwise, it is marked as valid data.

[0161] S8. Collect the fundamental component of resistive current of all data marked as valid data in the entire station, and calculate the average resistive current and the resistive current growth rate of each surge arrester within the preset evaluation period. When the average resistive current of any surge arrester exceeds the first safety limit or its resistive current growth rate exceeds the second safety limit, generate an early warning signal.

[0162] Example 6

[0163] An electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement a clock-synchronized centralized monitoring method for substation surge arresters.

[0164] A computer-readable storage medium storing computer instructions that, when executed, perform a clock-synchronized centralized monitoring method for substation surge arresters.

[0165] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the claims. All of these variations are within the protection scope of the present invention.

Claims

1. A centralized monitoring system for substation surge arresters based on clock synchronization, characterized in that, include: The clock synchronization module is used to generate a unified time synchronization pulse and distribute the time synchronization pulse in parallel to all current acquisition nodes or voltage acquisition nodes in the entire station, so as to force the sampling edges of each current acquisition node or voltage acquisition node to be aligned. The current acquisition module is configured with m current acquisition nodes to acquire m leakage current digital signals with a first timestamp. The voltage acquisition module is configured with n voltage acquisition nodes to acquire n digital voltage signals with the first timestamp attached. The centralized monitoring host is configured to: acquire the leakage current digital signal and the voltage digital signal carrying the same first timestamp; perform windowed fast Fourier transform on the leakage current digital signal and the voltage digital signal within the same time window; and extract the leakage current fundamental vector constructed by the leakage current fundamental amplitude and leakage current fundamental phase of each surge arrester, as well as the bus voltage fundamental amplitude and bus voltage fundamental phase from the transformation result. Using the fundamental phase of the bus voltage as a reference phase, the fundamental vector of the leakage current of each surge arrester is projected onto the direction determined by the reference phase, and the real part of the projection is taken as the fundamental component of the current resistive current of the corresponding surge arrester. Based on the electrical bay assignment relationship of surge arresters in the substation, all surge arresters in the substation are divided into multiple three-phase surge arrester groups. For any three-phase surge arrester group, the leakage current fundamental vectors of the A-phase surge arrester, B-phase surge arrester and C-phase surge arrester in the corresponding group are obtained at the same sampling time, and the three leakage current fundamental vectors are vector synthesized to obtain the synthesized vector.

2. The centralized monitoring system for substation surge arresters based on clock synchronization as described in claim 1, characterized in that, The centralized monitoring host is also configured as follows: The magnitude of the synthesized vector is calculated and compared with a preset zero-sequence deviation allowable threshold. If the magnitude is greater than the zero-sequence deviation allowable threshold, it is determined that the measurement of the group is subject to electromagnetic interference, and the fundamental component of the resistive current obtained by all surge arresters in the group is marked as invalid data; otherwise, it is marked as valid data. The fundamental component of resistive current, which is marked as valid data from the entire station, is collected. According to the preset evaluation period, the average resistive current and the resistive current growth rate within the corresponding evaluation period are calculated for each surge arrester. When the average resistive current of any surge arrester exceeds the first safety limit or the resistive current growth rate exceeds the second safety limit, an early warning signal is generated.

3. The centralized monitoring system for substation surge arresters based on clock synchronization as described in claim 2, characterized in that, The forced alignment of the sampling edges of each current acquisition node or voltage acquisition node includes: A reference synchronization pulse is generated as the basis for the time synchronization pulse, and the reference synchronization pulse is distributed to all current acquisition nodes or voltage acquisition nodes in the entire station via a transmission link; The propagation delay of the reference synchronization pulse on each transmission link is measured to obtain the relative delay difference between each transmission link and the reference link. For each transmission link, the reference synchronization pulse is pre-delayed based on the relative time delay difference, so that the time deviation of the compensated reference synchronization pulse arriving at each current acquisition node or voltage acquisition node falls within the preset synchronization error tolerance.

4. The centralized monitoring system for substation surge arresters based on clock synchronization as described in claim 3, characterized in that, The forced alignment of the sampling edges of each current or voltage acquisition node further includes: Each current acquisition node or voltage acquisition node receives a reference synchronization pulse after pre-delay compensation. The edge of the reference synchronization pulse triggers the local phase-locked loop of the node. The phase-locked loop filters out electromagnetic interference jitter coupled by the transmission link and regenerates a local sampling clock that is fixed to the edge of the reference synchronization pulse. The analog-to-digital conversion circuit of each current or voltage acquisition node performs sampling at the effective edge of the local sampling clock, so that the sampling points of all current or voltage acquisition nodes in the entire station are aligned on the absolute time axis.

5. The centralized monitoring system for substation surge arresters based on clock synchronization as described in claim 4, characterized in that, The step of performing windowed fast Fourier transform on the digital leakage current signal and the digital voltage signal within the same time window includes: Extract leakage current data sequences and voltage data sequences with time lengths equal to integer multiples of the power frequency period from the leakage current digital signals and the voltage digital signals carrying the same first timestamp; The leakage current data sequence is segmented according to the power frequency cycle, and the root mean square value of each power frequency cycle segment is calculated. The power frequency cycle segment whose root mean square value exceeds a preset multiple of the root mean square value of the entire leakage current data sequence is determined as a transient interference pollution segment, and the data points in the leakage current data sequence and the voltage data sequence corresponding to the transient interference pollution segment are set to zero. The leakage current data sequence and the voltage data sequence after being zeroed are multiplied point by point by the Hanning window function to obtain the windowed leakage current data sequence and the windowed voltage data sequence.

6. The centralized monitoring system for substation surge arresters based on clock synchronization as described in claim 5, characterized in that, The step of performing windowed fast Fourier transform on the leakage current digital signal and the voltage digital signal within the same time window also includes: For the windowed leakage current data sequence and the windowed voltage data sequence, respectively, perform radix-2 time decimation fast Fourier transform to obtain the complex spectrum sequence of leakage current and the complex spectrum sequence of voltage; In the complex spectrum sequence of the leakage current, the three consecutive frequency points with the largest modulus are selected. The modulus values ​​of the three frequency points and the corresponding frequency values ​​are substituted into the three-point amplitude interpolation correction formula to calculate the fundamental frequency, fundamental amplitude and fundamental phase of the leakage current. Using the calculated fundamental frequency of the leakage current as the index frequency, the frequency point closest to the corresponding index frequency is selected in the complex spectrum sequence of the voltage. Three-point phase interpolation correction is performed on the complex spectrum values ​​of the frequency point and its two adjacent frequency points to obtain the fundamental amplitude and phase of the bus voltage.

7. The centralized monitoring system for substation surge arresters based on clock synchronization as described in claim 6, characterized in that, The step of projecting the fundamental vector of the leakage current of each surge arrester into the direction determined by the reference phase includes: Read the fundamental amplitude of the leakage current, the fundamental phase of the leakage current, the fundamental amplitude of the bus voltage, and the fundamental phase of the bus voltage; Read the pre-calibrated first fixed phase hysteresis and the second fixed phase hysteresis; Subtracting the first fixed phase lag from the fundamental phase of the leakage current yields the corrected fundamental phase of the leakage current. Subtracting the second fixed phase lag from the fundamental phase of the bus voltage yields the corrected fundamental phase of the bus voltage. Subtracting the corrected fundamental phase of the bus voltage from the corrected fundamental phase of the leakage current yields the voltage-current phase difference. Calculate the cosine value of the phase difference between the voltage and current; Multiply the fundamental amplitude of the leakage current by the cosine of the phase difference between the voltage and current, and the resulting product is taken as the fundamental component of the current resistive current of the surge arrester.

8. The centralized monitoring system for substation surge arresters based on clock synchronization as described in claim 7, characterized in that, The calculation of the average resistive current and the resistive current growth rate within the corresponding evaluation period for each surge arrester includes: For each surge arrester, with a preset evaluation period as the time window, all fundamental components of resistive current marked as valid data within the current evaluation period are extracted from the historical resistive current data table of the surge arrester to form an evaluation sample sequence. The number of sample points in the evaluation sample sequence is counted. When the number of sample points is less than the preset minimum sample number threshold, the calculation of the average resistive current and the resistive current growth rate for this evaluation period is abandoned, and a data shortage mark is generated. When the number of sample points is greater than or equal to the minimum sample number threshold, the fundamental components of resistive current in the evaluation sample sequence are sorted according to their numerical values, and the first preset proportion of sample points with the largest values ​​and the second preset proportion of sample points with the smallest values ​​are removed from the sorted sequence to obtain the extreme value removal sample sequence.

9. The centralized monitoring system for substation surge arresters based on clock synchronization as described in claim 8, characterized in that, The calculation of the average resistive current and the resistive current growth rate within the corresponding evaluation period for each surge arrester also includes: Calculate the arithmetic mean of the extreme value sample sequence as the average resistive current for this evaluation period, and store the average resistive current in the historical sequence of the average resistive current of the surge arrester. When the number of consecutively stored resistive current average values ​​in the historical sequence of resistive current average values ​​reaches the preset fitting window length, the least squares linear fitting is performed on the most recent resistive current average values ​​within the fitting window length, with the storage sequence number in the historical sequence of resistive current average values ​​as the horizontal axis and the resistive current average value as the vertical axis. The slope of the fitted straight line is then used as the resistive current growth rate for the current evaluation period.

10. A method for centralized monitoring of substation surge arresters based on clock synchronization, implemented based on any one of claims 1-9, characterized in that, include: A unified time synchronization pulse is generated and distributed in parallel to all current acquisition nodes or voltage acquisition nodes in the entire station to force the sampling edges of each current acquisition node or voltage acquisition node to align. Acquire m digital leakage current signals with their first timestamps; Acquire n digital voltage signals with the first timestamp attached; Obtain the leakage current digital signal and the voltage digital signal carrying the same first timestamp, perform windowed fast Fourier transform on the leakage current digital signal and the voltage digital signal within the same time window, and extract the leakage current fundamental vector constructed by the leakage current fundamental amplitude and leakage current fundamental phase of each surge arrester, as well as the bus voltage fundamental amplitude and bus voltage fundamental phase from the transformation result. Using the fundamental phase of the bus voltage as a reference phase, the fundamental vector of the leakage current of each surge arrester is projected onto the direction determined by the reference phase, and the real part of the projection is taken as the fundamental component of the current resistive current of the surge arrester.

11. The centralized monitoring method for substation surge arresters based on clock synchronization as described in claim 10, characterized in that, The centralized monitoring method for surge arresters in substations also includes: Based on the electrical bay assignment relationship of surge arresters in the substation, all surge arresters in the substation are divided into multiple three-phase surge arrester groups. For any three-phase surge arrester group, the leakage current fundamental vectors of the A-phase surge arrester, B-phase surge arrester and C-phase surge arrester in the group are obtained at the same sampling time, and the three leakage current fundamental vectors are vector synthesized to obtain the synthesized vector. Calculate the magnitude of the synthesized vector and compare it with a preset zero-sequence deviation allowable threshold. If the magnitude is greater than the zero-sequence deviation allowable threshold, it is determined that the measurement of this group is subject to electromagnetic interference, and the fundamental component of the resistive current obtained by all surge arresters in this group is marked as invalid data; otherwise, it is marked as valid data. The fundamental component of resistive current, which is marked as valid data from the entire station, is collected. According to the preset evaluation period, the average resistive current and the resistive current growth rate within the evaluation period are calculated for each surge arrester. When the average resistive current of any surge arrester exceeds the first safety limit or its resistive current growth rate exceeds the second safety limit, an early warning signal is generated.

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