Integrated circuits including test circuits

Abstract

An integrated circuit including a test circuit is provided. The integrated circuit includes: a voltage divider circuit including a plurality of resistors connected in series with each other, wherein the voltage divider circuit is configured to generate an internal test signal, at least one first reference signal, and at least one second reference signal based on a test signal; a first low-pass filter configured to receive at least one first reference signal and generate a first reference voltage; a second low-pass filter configured to receive at least one second reference signal and generate a second reference voltage; a first comparator configured to compare the first reference voltage with the internal test signal; and a second comparator configured to compare the second reference voltage with the internal test signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0016974, filed with the Korean Intellectual Property Office on February 10, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to integrated circuits including test circuitry. Background Technology

[0004] As semiconductor processes become increasingly sophisticated and integration within a single die increases, semiconductor device testing methods have become a crucial factor directly impacting yield. Various testing and measurement methods are being developed to maximize yield. Due to the extensive testing and verification required, built-in measurement devices (MMTs) are used to evaluate and test the operation of semiconductor devices. Different manufacturers access and control these MMTs in various ways, necessitating standardization to address interoperability issues. Accordingly, testing standards such as IEEE 1149.1, 1687, and 1500 have been introduced. These standards provide standardized interfaces and data models, thereby improving the efficiency of testing and verification processes. However, there are limitations to meeting testing standards by adjusting the offset of the comparators used for testing, and the comparator hysteresis characteristics vary significantly depending on process, voltage, and temperature (PVT) requirements. Summary of the Invention

[0005] One or more example embodiments provide an integrated circuit including a test circuit with reduced area and stable operation even when process or temperature requirements change.

[0006] According to one aspect of an example embodiment, an integrated circuit is provided, comprising: a voltage divider circuit including a plurality of resistors connected in series with each other, wherein the voltage divider circuit is configured to generate an internal test signal, at least one first reference signal, and at least one second reference signal based on a test signal; a first low-pass filter configured to receive at least one first reference signal and generate a first reference voltage; a second low-pass filter configured to receive at least one second reference signal and generate a second reference voltage; a first comparator configured to compare the first reference voltage with the internal test signal; and a second comparator configured to compare the second reference voltage with the internal test signal.

[0007] According to another aspect of an example embodiment, an integrated circuit is provided, comprising: a high-pass filter configured to receive a test signal and generate an internal test signal, at least one first reference signal, and at least one second reference signal; a first low-pass filter configured to receive at least one first reference signal and generate a first reference voltage; a second low-pass filter configured to receive at least one second reference signal and generate a second reference voltage; a first comparator configured to compare the first reference voltage with the internal test signal; and a second comparator configured to compare the second reference voltage with the internal test signal.

[0008] According to another aspect of the example embodiment, an integrated circuit operating in multiple test modes is provided. The integrated circuit includes: a voltage divider circuit including a plurality of resistors connected in series with each other, wherein the voltage divider circuit is configured to generate an internal test signal, a first reference signal, and a second reference signal; a first low-pass filter configured to receive the first reference signal and generate a first reference voltage; a second low-pass filter configured to receive a second reference signal and generate a second reference voltage; a first comparator configured to compare the first reference voltage with the internal test signal; and a second comparator configured to compare the second reference voltage with the internal test signal. The voltage divider circuit is also configured to operate as a high-pass filter in a first test mode among the multiple test modes. Attached Figure Description

[0009] The above and other objects and features will become clearer from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram showing an integrated circuit including a test circuit according to an example embodiment;

[0011] Figure 2 This is a diagram illustrating a test circuit according to an example embodiment;

[0012] Figure 3 It is a diagram showing the waveform of a signal input to a test circuit and generated by the test circuit according to an example embodiment;

[0013] Figure 4 This is a diagram illustrating a test circuit according to an example embodiment;

[0014] Figure 5 This is a diagram illustrating a test circuit according to an example embodiment;

[0015] Figure 6 This is a diagram showing the reference signal generated by the voltage divider circuit;

[0016] Figure 7 This is a diagram illustrating a test circuit according to an example embodiment;

[0017] Figure 8 This is an example circuit diagram of a comparator (e.g., a first comparator or a second comparator) included in a test circuit according to an example embodiment;

[0018] Figure 9 This is an example circuit diagram of a hysteresis comparator included in a test circuit according to an example embodiment; and

[0019] Figure 10 This is a block diagram illustrating an electronic device according to an example embodiment. Detailed Implementation

[0020] In the following description, exemplary embodiments are illustrated with reference to the accompanying drawings. Each embodiment provided in the following description does not exclude association with one or more features of another example or embodiment also provided herein or not provided herein but consistent with this disclosure. It should be understood that when reference is made to an element being “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element, or there may be an intermediate element. In contrast, when reference is made to an element being “directly connected” or “directly coupled” to another element, there is no intermediate element.

[0021] Figure 1 This is a block diagram showing an integrated circuit 10 including a test circuit 100 according to an example embodiment. Figure 2 This is a diagram illustrating a test circuit 100 according to an example embodiment.

[0022] refer to Figure 1 Integrated circuit 10 can constitute a semiconductor device performing various functions. Integrated circuit 10 may include a chip or die, or may include a semiconductor package having at least one chip or die. For example, a semiconductor device including integrated circuit 10 may include a memory device. Furthermore, the semiconductor device may include, but is not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), mobile DRAM, flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change RAM (PRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). For example, a semiconductor device including integrated circuit 10 may include a system semiconductor device. Furthermore, the semiconductor device may include a central processing unit (CPU), application processor (AP), graphics processing unit (GPU), multimedia semiconductor device, sensor, artificial intelligence (AI) semiconductor device, etc. Additionally, the semiconductor device may include a system-on-a-chip (SoC).

[0023] Integrated circuit 10 may include serializer / deserializer (SerDes) circuitry 200 and test circuitry 100. Test circuitry 100 may include test circuitry for performing boundary scan tests on integrated circuit 10. Test circuitry 100 may be referred to as Joint Test Action Group (JTAG) circuitry.

[0024] The SerDes circuit 200 can form a transmission system in which signals are transmitted from a transmitter of one integrated circuit to a receiver of another integrated circuit via a high-speed connection, reducing the amount of physical wiring. In an example embodiment, the SerDes circuit 200 may include a receiver and a transmitter. The receiver may include analog front-end (AFE) circuitry, decision feedback equalizer (DFE) circuitry, clock and data recovery (CDR) circuitry, or a deserializer. The transmitter may include a serializer, an output driver, or a phase-locked loop (PLL) circuitry.

[0025] Integrated circuit 10 can receive test data from an external source. An external logic module of integrated circuit 10 (e.g., a JTAG interface) can activate the data transmission path used to test integrated circuit 10 and send signals at a target data rate.

[0026] Integrated circuit 10 may include multiple terminals for interfacing with external logic modules. The external logic module may configure the test circuit 100 of integrated circuit 10 via the test access port (TAP) of integrated circuit 10, or may generate test result signals. For example, integrated circuit 10 may include multiple terminals for connecting to an external JTAG interface. Integrated circuit 10 may also include terminals for receiving test mode selection signals, terminals for outputting test data, terminals for inputting test data, or terminals for resetting test data.

[0027] The test circuit 100 generates a test result signal based on a comparison between an internal test signal and a reference voltage. Based on the test result signal, defects in the channel between the integrated circuit 10 and the external logic module can be detected. (Reference) Figure 10 The defects that can be detected from the test result signals are described in detail.

[0028] refer to Figure 2 The test circuit 100 can receive a test signal TS and output a first test result signal TRS1 and a second test result signal TRS2. For example, each of the first test result signal TRS1 and the second test result signal TRS2 can be generated by the test circuit 100 based on the test signal TS. The test circuit 100 may include a high-pass filter 110 for receiving the test signal TS and generating an internal test signal IS. The high-pass filter 110 may include a coupling capacitor CC and multiple resistors (e.g., R1 to R4).

[0029] Multiple resistors R1 to R4 (or referred to as first resistors R1 to fourth resistors R4) can operate as a voltage divider circuit 111. That is, the voltage divider circuit 111 may include multiple resistors R1 to R4 connected in series between the power supply voltage VDD and the ground voltage VSS. In this case, the resistance value of each of the multiple resistors R1 to R4 can be determined based on the characteristics of the high-pass filter 110. Furthermore, the resistance value of each of the multiple resistors R1 to R4 can be determined based on the characteristics of the first reference signal RS1 and the second reference signal RS2 generated in the voltage divider circuit 111.

[0030] The test circuit 100 may include: a first low-pass filter 121, which receives a first reference signal RS1 and generates a first reference voltage RV1 based on the first reference signal RS1; and a second low-pass filter 123, which receives a second reference signal RS2 and generates a second reference voltage RV2 based on the second reference signal RS2. Here, the value of the first reference voltage RV1 may be a specific voltage level higher than the common level of the internal test signal IS, while the value of the second reference voltage RV2 may be a specific voltage level lower than the common level of the internal test signal IS.

[0031] The test circuit 100 may include: a first comparator COMP1, which compares a first reference voltage RV1 with an internal test signal IS; and a second comparator COMP2, which compares a second reference voltage RV2 with the internal test signal IS. The first comparator COMP1 may output a first test result signal TRS1 based on the comparison result, and the second comparator COMP2 may output a second test result signal TRS2 based on the comparison result. In an example embodiment, the first comparator COMP1 and the second comparator COMP2 may include non-hysteresis comparators that do not have (or exclude) hysteresis characteristics.

[0032] In boundary scan test operations, the comparison operations performed by each of the first comparators COMP1 and the second comparator COMP2 in test circuit 100 may require hysteresis characteristics to distinguish noise components contained in the test signal TS. The required hysteresis characteristics for the comparison operations are defined in the IEEE 1149.6 standard and may require a hysteresis of approximately 50% to approximately 90% of the input signal amplitude. Meeting the hysteresis characteristics required by the IEEE 1149.6 standard within the first comparators COMP1 and the second comparators COMP2 themselves may be challenging. Furthermore, when comparing a hysteresis comparator with hysteresis characteristics to one without, the hysteresis characteristics of the hysteresis comparators may vary depending on process or temperature requirements. Specifically, due to the gradual decrease in the supply voltages provided for the operation of semiconductor devices in recent years, the stable operating range of the first comparators COMP1 and the second comparators COMP2 may narrow, and the operating range of the test signal TS may also narrow.

[0033] In the test circuit 100 according to the example embodiment, a first reference voltage RV1 and a second reference voltage RV2 can be generated by using a voltage divider circuit 111 that constitutes a high-pass filter 110 for generating an internal test signal IS. The levels of the first reference voltage RV1 and the second reference voltage RV2 are offset by a specific voltage level from the common level of the internal test signal IS. The first reference voltage RV1 and the second reference voltage RV2 can be used as reference voltages for testing defects by using the internal test signal IS in the first comparator COMP1 and the second comparator COMP2, respectively.

[0034] Therefore, even if each of the first comparators COMP1 and the second comparator COMP2 does not have hysteresis characteristics, the hysteresis characteristics can be adjusted by regulating the amplitudes of the first reference voltage RV1 and the second reference voltage RV2. Thus, the hysteresis characteristics required for the comparison operation are not limited by the characteristics of each of the first comparators COMP1 and the second comparator COMP2, but can be satisfied by generating the first reference voltage RV1 and the second reference voltage RV2. Accordingly, even if the process or temperature requirements of each of the first comparators COMP1 and the second comparator COMP2 change, the hysteresis characteristics can be stably maintained. Therefore, even if the process or temperature requirements change, the test circuit 100 can reliably perform test operations to detect defects.

[0035] In the example embodiment, the first comparator COMP1 and the second comparator COMP2 may include hysteresis comparators with hysteresis characteristics. Even though the hysteresis characteristics of the first comparator COMP1 and the second comparator COMP2 themselves are sensitive to changes in process or temperature requirements, the hysteresis characteristics of the comparison operation in the test circuit 100 can be stably maintained because the first reference voltage RV1 and the second reference voltage RV2 are stably generated in the voltage divider circuit 111.

[0036] Figure 3 This is a waveform diagram showing the signal input to test circuit 100 and generated by the test circuit according to an example embodiment.

[0037] refer to Figure 2 and Figure 3 The test circuit 100 can receive a test signal TS with a specific period of pulse waves in AC test mode. In the test signal TS, pulses with positive values ​​and pulses with negative values ​​can appear repeatedly.

[0038] The value of the first reference voltage RV1 can be higher than the common level of the internal test signal IS by a first voltage level ΔV1. The value of the second reference voltage RV2 can be lower than the common level of the internal test signal IS by a second voltage level ΔV2. In an example embodiment, the amplitude of the first voltage level ΔV1 can be equal to the amplitude of the second voltage level ΔV2. In an example embodiment, in the voltage divider circuit 111, the resistance value of the second resistor R2 can be equal to the resistance value of the third resistor R3.

[0039] The first comparator COMP1 can generate a first test result signal TRS1 based on the comparison result. From the time the internal test signal IS becomes greater than the first reference voltage RV1, the first comparator COMP1 can generate the first test result signal TRS1 with a pulse of a first width W1. In this case, the first width W1 can have a predetermined value.

[0040] The second comparator COMP2 can generate a second test result signal TRS2 based on the comparison result. From the time the internal test signal IS becomes less than the second reference voltage RV2, the second comparator COMP2 can generate the second test result signal TRS2 with a pulse of a second width W2. In this case, the second width W2 can have a predetermined value.

[0041] In the test circuit 100 according to the example embodiment, a first reference voltage RV1 is generated, the level of which is a first voltage level ΔV1 higher than the common level of the internal test signal IS; a second reference voltage RV2 is generated, the level of which is a second voltage level ΔV2 lower than the common level of the internal test signal IS; and the first reference voltage RV1 and the second reference voltage RV2 are compared with the internal test signal IS. Accordingly, noise contained in the internal test signal IS can be distinguished, thereby enabling the comparison operation.

[0042] Figure 4 This is a diagram illustrating a test circuit 100A according to an example embodiment. (Refer to...) Figure 4 The description omits the related terms. Figure 2 Repeated descriptions of the same reference numerals in the figures.

[0043] refer to Figure 4 The test circuit 100A can receive the test signal TS and output a first test result signal TRS1 and a second test result signal TRS2. The test circuit 100A may include a high-pass filter 110A, a first low-pass filter 121, a second low-pass filter 122, a first comparator COMP1, and a second comparator COMP2.

[0044] The test circuit 100A may include a high-pass filter 110A for receiving the test signal TS and generating an internal test signal IS. The high-pass filter 110A may include a coupling capacitor CC, a switching circuit SW, and a voltage divider circuit 111.

[0045] The switching circuit SW can be connected in parallel with the coupling capacitor CC. The switching circuit SW can be switched in response to the enable signal DC_EN. In an example embodiment, the switching circuit SW can be implemented as a transmission gate and can be switched by the enable signal DC_EN and a complementary enable signal. The complementary enable signal can be complementary to the enable signal DC_EN and has a phase opposite to that of the enable signal DC_EN.

[0046] Test circuit 100A can operate in multiple test modes. For example, test circuit 100A can operate in DC test mode or AC test mode. In DC test mode, the test signal TS can be a DC signal. Furthermore, in AC test mode, the test signal TS can be an AC signal with a specific pulse waveform having a certain period.

[0047] In DC test mode, the switching circuit SW is turned on in response to the enable signal DC_EN, and the test signal TS can be provided as the internal test signal IS to the first comparator COMP1 and the second comparator COMP2. In AC test mode, the switching circuit SW is turned off in response to the enable signal DC_EN, and the test circuit 100A can be referenced as above. Figure 2 The operation is performed as described.

[0048] The test circuit of the comparative example generates a reference voltage such that the reference voltage is only used for comparison with the test signal TS in DC test mode, thus including a separate reference voltage generation circuit. On the other hand, the test circuit 100A according to the example embodiment is not equipped with the separate reference voltage generation circuit required for operation in DC test mode, and the first reference voltage RV1 and the second reference voltage RV2 can be generated using the voltage divider circuit 111 constituting the high-pass filter 110A in AC test mode. Therefore, the test circuit 100A can operate in both DC test mode and AC test mode, and the area of ​​the test circuit 100A can be reduced.

[0049] Figure 5 This is a diagram illustrating a test circuit 100B according to an example embodiment. Figure 6 This is a diagram showing the reference signal generated by the voltage divider circuit 111B. In the reference... Figure 5 The description omits the related terms. Figure 2 Repeated descriptions of the same reference numerals in the figures.

[0050] refer to Figure 5 The test circuit 100B can receive the test signal TS and output a first test result signal TRS1 and a second test result signal TRS2. For example, each of the first test result signal TRS1 and the second test result signal TRS2 can be generated by the test circuit 100B based on the test signal TS. The test circuit 100B may include a high-pass filter 110B, a first selection circuit 131, a second selection circuit 132, a first low-pass filter 121, a second low-pass filter 122, a first comparator COMP1, and a second comparator COMP2.

[0051] The high-pass filter 110B may include a coupling capacitor CC, a switching circuit SW, and a voltage divider circuit 111B. The voltage divider circuit 111B can generate an internal test signal IS, multiple first reference signals RS11 to RS1n, and multiple second reference signals RS21 to RS2n (where n is a natural number of 2 or greater). The voltage divider circuit 111B may include multiple resistors (e.g., R1 to R4) connected in series between the power supply voltage VDD and the ground voltage VSS. The resistance value of each of the multiple resistors (e.g., R1 to R4) can be determined based on the characteristics of the high-pass filter 110B. Furthermore, the resistance value of each of the multiple resistors R1 to R4 can be determined based on the characteristics of the multiple first reference signals RS11 to RS1n and the multiple second reference signals RS21 to RS2n generated in the voltage divider circuit 111B.

[0052] The first selection circuit 131 can select one of a plurality of first reference signals RS11 to RS1n and output the selected first reference signal RS1 to the first low-pass filter 121. The first selection circuit 131 can perform a selection operation in response to a first selection signal SS1 provided externally to the test circuit 100B. In an example embodiment, the first selection circuit 131 can be implemented as a multiplexer.

[0053] The hysteresis characteristic of the comparison operation performed by the first comparator COMP1 varies depending on which of the multiple first reference signals RS11 to RS1n is selected as the first reference signal RS1. For example, when the first reference signal RS11 with the highest voltage level among the multiple first reference signals RS11 to RS1n is selected, a larger hysteresis characteristic can be obtained compared with the first reference signal RS1n with the lowest voltage level among the multiple first reference signals RS11 to RS1n.

[0054] The second selection circuit 132 can select one of a plurality of second reference signals RS21 to RS2n and output the selected second reference signal RS2 to the second low-pass filter 122. The second selection circuit 132 can perform a selection operation in response to a second selection signal SS2 provided externally from the test circuit 100B. In an example embodiment, the second selection circuit 132 can be implemented as a multiplexer.

[0055] The hysteresis characteristic of the comparison operation performed by the second comparator COMP2 varies depending on which of the multiple second reference signals RS21 to RS2n is selected as the chosen second reference signal RS2. For example, a larger hysteresis characteristic can be obtained when the second reference signal RS21 with the lowest voltage level is selected compared to selecting the second reference signal RS2n with the highest voltage level among the multiple second reference signals RS21 to RS2n.

[0056] Therefore, in order to test an integrated circuit including the test circuit 100B according to the example embodiment, the user can select a desired first reference signal from a plurality of first reference signals RS11 to RS1n, and a desired second reference signal from a plurality of second reference signals RS21 to RS2n. Thus, the user's required test requirements can be met, satisfying the hysteresis level defined in the IEEE 1149.6 standard.

[0057] refer to Figure 5 and Figure 6 The number of first reference signals RS11 to RS1n generated by voltage divider circuit 111B and received by first selection circuit 131 can be equal to the number of second reference signals RS21 to RS2n received by second selection circuit 132. Furthermore, the first reference signal RS1 among the multiple first reference signals RS11 to RS1n and the second reference signal RS2 among the multiple second reference signals RS21 to RS2n can form a pair of signals, and the first selection circuit 131 and the second selection circuit 132 can each select and output a pair of first reference signals RS1 and second reference signals RS2.

[0058] In an example embodiment, signal pairs can be sequentially formed from a plurality of first reference signals RS11 to RS1n and a plurality of second reference signals RS21 to RS2n at a node close to node X that generates the internal test signal IS. For example, one pair of signals can be formed by (RS11, RS21), and another pair of signals can be formed by (RS1n, RS2n). In an example embodiment, the first reference voltage RV1 and the second reference voltage RV2 generated according to the selected first reference signal RS1 and the selected second reference signal RS2, respectively, can have a voltage level offset from the common level of the internal test signal IS. However, the example embodiment is not limited to this. Considering the characteristics of noise, the first reference voltage RV1 and the second reference voltage RV2 generated according to the selected first reference signal RS1 and the selected second reference signal RS2, respectively, can have a voltage level offset from the common level of the internal test signal IS.

[0059] Figure 7 This is a diagram illustrating a test circuit 100C according to an example embodiment. (Refer to...) Figure 7 The description omits the related terms. Figure 2 Repeated descriptions of the same reference numerals in the figures.

[0060] refer to Figure 7The test circuit 100C can receive the test signal TS and output a first test result signal TRS1 and a second test result signal TRS2. For example, each of the first test result signal TRS1 and the second test result signal TRS2 can be generated by the test circuit 100C based on the test signal TS. The test circuit 100C includes a high-pass filter 110C, a first selection circuit 131C, a second selection circuit 132C, a first low-pass filter 121C, a second low-pass filter 122C, a first comparator COMP1, and a second comparator COMP2.

[0061] The high-pass filter 110C may include a coupling capacitor CC, a switching circuit SW, and a voltage divider circuit 111C. The voltage divider circuit 111C may generate an internal test signal IS, multiple first reference signals (e.g., RS11 to RS13), and multiple second reference signals (e.g., RS21 to RS23). Figure 7 The example shows a voltage divider circuit 111C generating three first reference signals RS11 to RS13 and three second reference signals RS21 to RS23, but the example embodiment is not limited thereto. The number of first reference signals and second reference signals generated by the voltage divider circuit 111C can vary.

[0062] Voltage divider circuit 111C may include multiple resistors (e.g., R1C to R8C) connected in series between the power supply voltage VDD and the ground voltage VSS. The resistance of each resistor (e.g., R1C to R8C) may be determined based on the characteristics of high-pass filter 110C, or based on the characteristics of multiple first reference signals RS11 to RS13 and multiple second reference signals RS21 to RS23 generated in voltage divider circuit 111C.

[0063] The first selection circuit 131C can select one of a plurality of first reference signals RS11 to RS13 and output the selected first reference signal RS1 to the first low-pass filter 121C. In an example embodiment, the first selection circuit 131C may include a plurality of switch circuits SW11 to SW13, control the plurality of switch circuits SW11 to SW13, and perform a selection operation in response to a switch signal provided from outside the test circuit 100C. The selected first reference signal RS1 can be determined based on the switch circuits that are turned on among the plurality of switch circuits SW11 to SW13. For example, a single switch among the plurality of switch circuits SW11 to SW13 can be turned on.

[0064] The second selection circuit 132C can select one of a plurality of second reference signals RS21 to RS23 and output the selected second reference signal RS2 to the second low-pass filter 122C. The second selection circuit 132C may include a plurality of switch circuits SW21 to SW23, control the plurality of switch circuits SW21 to SW23, and perform a selection operation in response to a switch signal provided externally to the test circuit 100C. The selected second reference signal RS2 can be determined based on which switch circuit among the plurality of switch circuits SW21 to SW23 is turned on. For example, a single switch among the plurality of switch circuits SW21 to SW23 can be turned on.

[0065] The hysteresis characteristic of the comparison operation performed by the first comparator COMP1 varies depending on which of the multiple second reference signals RS21 to RS23 is selected as the chosen second reference signal RS2. Similarly, the hysteresis characteristic of the comparison operation performed by the second comparator COMP2 varies depending on which of the multiple second reference signals RS21 to RS23 is selected as the chosen second reference signal RS2.

[0066] The first reference signal RS1 among the multiple first reference signals RS11 to RS13 and the second reference signal RS2 among the multiple second reference signals RS21 to RS23 can form a pair of signals, and the first selection circuit 131C and the second selection circuit 132C can each select and output a pair of first reference signals RS1 and second reference signals RS2.

[0067] In an example embodiment, the signal pair can be formed sequentially from a plurality of first reference signals RS11 to RS13 and a plurality of second reference signals RS21 to RS23 at a node close to node X that generates the internal test signal IS. For example, a pair of signals can be formed from each of (RS11, RS21), (RS12, RS22), and (RS13, RS23).

[0068] In the example embodiment, the first reference voltage RV1 and the second reference voltage RV2 generated according to the selected first reference signal RS1 and the selected second reference signal RS2, respectively, can have a voltage level offset from the common level of the internal test signal IS. In this case, some of the resistors (e.g., R1C to R8C) can have the same resistance symmetrical about node X. For example, resistor R4C can have the same resistance as resistor R5C, resistor R3C can have the same resistance as resistor R6C, and resistor R2C can have the same resistance as resistor R7C. However, the example embodiment is not limited to this, and the multiple resistors R1C to R8C can be modified to have various resistances.

[0069] Figure 8 This is an example circuit diagram of a comparator COMP according to an example embodiment. For example, according to the example embodiment, the comparator COMP may be included in a test circuit. For example, the comparator COMP may be implemented as a first comparator COMP1 and / or a second comparator COMP2. Figure 8 The comparator COMP in the example is an example of a comparator without hysteresis characteristics, but the example embodiment is not limited to this.

[0070] refer to Figure 8 The comparator COMP may include multiple transistors (e.g., MP11, MP12, MN11, and MN12) and a current source CSS. The multiple transistors may include a first P-type transistor MP11, a second P-type transistor MP12, a first N-type transistor MN11, and a second N-type transistor MN12. For example, the current source CSS may be implemented as an N-type transistor, i.e., an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), one end of which may be connected to ground to generate a bias current.

[0071] The gates of the first N-type transistor MN11 and the second N-type transistor MN12 can each receive differential inputs, such as a first input signal INP and a second input signal INN. Furthermore, the first N-type transistor MN11 and the second N-type transistor MN12 can generate a differential current corresponding to the level difference between the first input signal INP and the second input signal INN. For example, when comparator COMP indicates... Figure 2 When the first comparator COMP1 is shown, the internal test signal TS can be received as the first input signal INP, and the first reference voltage RV1 can be received as the second input signal INN. Furthermore, for example, when comparator COMP indicates... Figure 2 When the second comparator COMP2 is shown, the second reference voltage RV2 can be received as the first input signal INP, and the internal test signal TS can be received as the second input signal INN.

[0072] One end (source) of the first N-type transistor MN11 can be connected to the current source CSS, and the other end (drain) of the first N-type transistor MN11 can be connected to the second output node OPN. One end (source) of the second N-type transistor MN12 can be connected to the current source CSS, and the other end (drain) of the second N-type transistor MN12 can be connected to the first output node OP. The first N-type transistor MN11 and the second N-type transistor MN12 can be referred to as the first input transistor and the second input transistor, respectively.

[0073] When the first input signal INP and the second input signal INN are the same, the same current can flow through the first N-type transistor MN11 and the second N-type transistor MN12. Furthermore, when the first input signal INP and the second input signal INN are different, different currents can flow through the first N-type transistor MN11 and the second N-type transistor MN12. The sum of the currents flowing through the first N-type transistor MN11 and the second N-type transistor MN12 can be equal to the bias current of the current source CSS.

[0074] One end (source) of the first P-type transistor MP11 can be powered by the power supply voltage VDD, and the other end (drain) of the first P-type transistor MP11 can be connected to the output node that outputs the second output signal OS1N. One end (source) of the second P-type transistor MP12 can be powered by the power supply voltage VDD, and the other end (drain) of the second P-type transistor MP12 can be connected to the output node OP that outputs the first output signal OS1P. The first P-type transistor MP11 and the second P-type transistor MP12 can be referred to as the first load transistor and the second load transistor, respectively.

[0075] The first output signal OS1P and the second output signal OS1N can be determined based on the current mirrors of the first P-type transistor MP11 and the second P-type transistor MP12. The first output signal OS1P and the second output signal OS1N can also be determined based on the amount of current flowing through the first N-type transistor MN11 and the second N-type transistor MN12. When the level of the first input signal INP is higher than the level of the second input signal INN, a relatively larger current can flow through the first N-type transistor MN11 compared to the second N-type transistor MN12. Accordingly, the level of the first output signal OS1P may increase, while the level of the second output signal OS1N may decrease.

[0076] The comparator COMP may also include a buffer BUF. The buffer BUF receives the first output signal OS1P and generates the output signal VOUT. The output signal VOUT can be represented as shown in the reference. Figure 2 The first test result signal TRS1 or the second test result signal TRS2 are described.

[0077] In the integrated circuit including the test circuit according to the example embodiment, the reference voltage for testing the internal test signal is generated by using a voltage divider circuit, which includes a plurality of resistors connected in series with each other and forming a high-pass filter. Therefore, even if a comparator COMP without hysteresis characteristics is used, the hysteresis characteristics of the comparison operation can be formed by using the reference voltage.

[0078] Figure 9This is an example circuit diagram of a hysteresis comparator COMP_H according to an example embodiment. For example, the hysteresis comparator COMP_H may be included in a test circuit according to an example embodiment. For example, the hysteresis comparator COMP_H may be implemented as a first comparator COMP1 and / or a second comparator COMP2. Figure 9 The hysteresis comparator COMP_H in the example is a hysteresis comparator with hysteresis characteristics, but the example embodiment is not limited thereto.

[0079] refer to Figure 9 The hysteresis comparator COMP_H may include multiple transistors MP21, MP22, MP23, MP24, MN21, MN22, MN23, MN24, MN25, and MN26 (or referred to as the first P-type transistors MP21 to the fourth P-type transistor MP24 and the first N-type transistors MN21 to the sixth N-type transistor MN26) and a current source CSS'. For example, the current source CSS can be implemented as a P-type transistor, i.e., a P-type MOSFET, one end of which can be connected to the power supply voltage VDD to generate a bias current.

[0080] The gates of the third P-type transistor MP23 and the fourth P-type transistor MP24 can each receive differential inputs, such as the second input signal INN and the first input signal INP, respectively. Furthermore, the third P-type transistor MP23 and the fourth P-type transistor MP24 can generate a differential current corresponding to the level difference between the second input signal INN and the first input signal INP. For example, when the hysteresis comparator COMP_H represents... Figure 2 When the first comparator COMP1 is shown, the internal test signal TS can be received as the first input signal INP, and the first reference voltage RV1 can be received as the second input signal INN. Furthermore, for example, when the hysteresis comparator COMP_H indicates... Figure 2 When the second comparator COMP2 is shown, the second reference voltage RV2 can be received as the first input signal INP, and the internal test signal TS can be received as the second input signal INN.

[0081] When the first input signal INP is greater than the value obtained by adding the first hysteresis voltage (rising hysteresis voltage) to the second input signal INN, the output signal OSP output through the output node OP' may have a logic high level ("1"). On the other hand, when the first input signal INP is less than the value obtained by subtracting the second hysteresis voltage (falling hysteresis voltage) from the second input signal INN, the output signal OSP output through the output node OP may have a logic low level ("0").

[0082] When the value of the first input signal INP is much greater than the second input signal INN and the output signal OSP is at a logic high level, the fifth N-type transistor MN25 and the sixth N-type transistor MN26 are blocked, and the current from the current source CSS' can flow to the ground voltage through the third N-type transistor MN23 and the fourth N-type transistor MN24.

[0083] As the first input signal INP gradually decreases to a level lower than the second input signal INN, and as the current from the current source CSS flows through the fifth N-type transistor MN25 and the sixth N-type transistor MN26, the output signal OSP changes from a logic high level to a logic low level. Furthermore, this change continues until the first input signal INP becomes equal to the second input signal INN minus the second hysteresis voltage. When the first input signal INP becomes equal to the second input signal INN minus the second hysteresis voltage, the fifth N-type transistor MN25 and the sixth N-type transistor MN26 can be turned on, and the third N-type transistor MN23 and the fourth N-type transistor MN24 can be turned off.

[0084] The width ratio of the third N-type transistor MN23 and the fourth N-type transistor MN24 can be 1:a, while the width ratio of the fifth N-type transistor MN25 and the sixth N-type transistor MN26 can be b:1. The first hysteresis voltage and the second hysteresis voltage can be determined by the fourth N-type transistor MN24 and the fifth N-type transistor MN25. The first hysteresis voltage can vary depending on the value of a, the amplitude of the current from the current source CSS', or the characteristics of the third P-type transistor MP23 or the fourth P-type transistor MP24. Furthermore, the second hysteresis voltage can vary depending on the value of b, the amplitude of the current from the current source CSS', or the characteristics of the third P-type transistor MP23 or the fourth P-type transistor MP24. Therefore, the hysteresis comparator COMP_H can change the amplitudes of the first and second hysteresis voltages according to changes in process conditions or temperature requirements.

[0085] In the integrated circuit including the test circuit according to the example embodiment, the reference voltage for testing the internal test signal is generated by using a voltage divider circuit, which includes multiple resistors connected in series with each other and forming a high-pass filter. Therefore, even if the hysteresis characteristics of the hysteresis comparator COMP_H change due to variations in process requirements or temperature requirements, the test operation can be performed stably while meeting the hysteresis characteristics required by the standard.

[0086] The hysteresis comparator COMP_H may also include a buffer BUF'. Buffer BUF' receives the output signal OSP and generates the output signal VOUT'. The output signal VOUT' can represent either the first test result signal TRS1 or the second test result signal TRS2, as shown in the reference. Figure 2 As mentioned above.

[0087] Figure 10 This is a block diagram illustrating an electronic device 20 according to an example embodiment.

[0088] refer to Figure 10 The electronic device 20 may include a first device 11 and a second device 12. In an example embodiment, the first device 11 and the second device 12 may each represent a device including the one described above. Figures 1 to 9 The integrated circuit of the test circuit described herein. Furthermore, the first device 11 and the second device 12 may each represent various hardware components included in a single user equipment, such as processors, storage devices, memory devices, or control devices.

[0089] The first device 11 and the second device 12 can exchange a first signal SIG1 and a second signal SIG2 with each other via a communication channel CH. For example, the first device 11 may include a first transmission circuit 11_1. The first transmission circuit 11_1 can transmit the information generated by the first device 11 as the first signal SIG1 to the second device 12 via the channel CH. The second device 12 may include a first receiving circuit 12_1. The first receiving circuit 12_1 can receive the first signal SIG1 sent from the first transmission circuit 11_1 via the channel CH.

[0090] Furthermore, the second device 12 may include a second transmission circuit 12_2, and the first device 11 may include a second receiving circuit 11_2. The second transmission circuit 12_2 may transmit the second signal SIG2 to the first device 11 via channel CH, and the second receiving circuit 11_2 may receive the second signal SIG2 via channel CH.

[0091] In example embodiments, such as Figure 10 As shown, the first transmission circuit 11_1 and the second receiving circuit 11_2 can be respectively disposed in the first device 11, and the first receiving circuit 12_1 and the second transmission circuit 12_2 can be respectively disposed in the second device 12. However, the example embodiment is not limited thereto. The first transmission circuit 11_1 and the second receiving circuit 11_2 can be implemented as a single circuit, and the first receiving circuit 12_1 and the second transmission circuit 12_2 can be implemented as a single circuit.

[0092] In the example embodiment, the first signal SIG1 may be distorted due to the response characteristics of the channel CH or noise caused by external factors when passing through the channel CH. In this case, the information sent from the first transmission circuit 11_1 may differ from the information received by the first receiving circuit 12_1, and therefore the second device 12 may malfunction or fail.

[0093] Furthermore, the first signal SIG1 may be distorted due to defects during the channel CH process connecting the first device 11 to the second device 12. The test circuit according to the example embodiment can be used in boundary scan testing to detect such defects. For example, defects detectable by test operations in the test circuit according to the example embodiment include: an open circuit or connection to power / ground voltage at the output pin of the first transmission circuit 11_1, an interconnection of the output pins of the first transmission circuit 11_1, or an connection of the output pin of the first transmission circuit 11_1 to the output pin of another transmission circuit of the first device 11. Furthermore, defects detectable by test operations in the test circuit according to the example embodiment include: an open circuit or connection to power / ground voltage at the input pin of the first receiving circuit 12_1, an interconnection of the input pins of the first receiving circuit 12_1, or an connection of the input pin of the first receiving circuit 12_1 to the input pin of another receiving circuit of the second device 12. Furthermore, defects detectable by test operations in the test circuit according to the example embodiment include: defects occurring in resistors or capacitors within the channel CH.

[0094] The electronic device according to the example embodiment includes a test circuit that is insensitive to changes in operating voltage or operating temperature (VT), thereby improving test accuracy and meeting the requirements of boundary scan test standards.

[0095] According to one aspect of an example embodiment, a method for controlling test operations of an integrated circuit is provided, the method comprising: controlling a voltage divider circuit comprising a plurality of resistors connected in series with each other, based on a test signal, to generate an internal test signal, a first reference signal, and a second reference signal; generating a first reference voltage based on the first reference signal through a first low-pass filter; generating a second reference voltage based on the second reference signal through a second low-pass filter; comparing the first reference voltage with the internal test signal; and comparing the second reference voltage with the internal test signal.

[0096] The method may further include: controlling a first selection circuit to select a first reference signal from a plurality of first reference signals generated by a voltage divider circuit.

[0097] The method may further include: controlling a second selection circuit to select a second reference signal from a plurality of second reference signals generated by a voltage divider circuit.

[0098] The first selection circuit may include a first multiplexer, while the second selection circuit may include a second multiplexer.

[0099] The method may further include: controlling a switch connected between an input node configured to receive a test signal and a voltage divider circuit, based on a DC mode signal.

[0100] The switch can be connected in parallel with a capacitor between the input node and the voltage divider circuit.

[0101] The method may also include: closing the switch based on the activation of a DC mode signal.

[0102] The method may also include: disconnecting the switch based on the DC mode signal being disabled.

[0103] Although various aspects of the exemplary embodiments have been specifically shown and described above, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. An integrated circuit, comprising: A voltage divider circuit includes a plurality of resistors connected in series with each other, wherein the voltage divider circuit is configured to generate an internal test signal, at least one first reference signal and at least one second reference signal based on a test signal; A first low-pass filter is configured to receive the at least one first reference signal and generate a first reference voltage; A second low-pass filter is configured to receive the at least one second reference signal and generate a second reference voltage; A first comparator is configured to compare the first reference voltage with the internal test signal; and A second comparator is configured to compare the second reference voltage with the internal test signal.

2. The integrated circuit according to claim 1, further comprising: A coupling capacitor is configured to receive the test signal and is connected to the voltage divider circuit.

3. The integrated circuit of claim 2, further comprising: A switching circuit, connected in parallel with the coupling capacitor, is configured to switch according to an enable signal.

4. The integrated circuit of claim 1, wherein, The voltage divider circuit generates multiple first reference signals and multiple second reference signals. The first low-pass filter is further configured to generate the first reference voltage based on a first reference signal selected from the plurality of first reference signals, and The second low-pass filter is further configured to generate the second reference voltage based on a second reference signal selected from the plurality of second reference signals.

5. The integrated circuit according to claim 4, further comprising: A first multiplexer is configured to select one of the plurality of first reference signals; as well as The second multiplexer is configured to select one of the plurality of second reference signals.

6. The integrated circuit of claim 4, wherein, The selected first reference signal and the selected second reference signal are offset by the same voltage level relative to the internal test signal.

7. The integrated circuit of claim 1, wherein, Each of the first comparator and the second comparator includes a comparator that does not have hysteresis characteristics.

8. The integrated circuit of claim 1, wherein, Each of the first comparator and the second comparator includes a hysteresis comparator with hysteresis characteristics.

9. An integrated circuit, comprising: A high-pass filter is configured to receive a test signal and generate an internal test signal, at least one first reference signal, and at least one second reference signal; A first low-pass filter is configured to receive the at least one first reference signal and generate a first reference voltage; A second low-pass filter is configured to receive the at least one second reference signal and generate a second reference voltage; A first comparator is configured to compare the first reference voltage with the internal test signal; as well as A second comparator is configured to compare the second reference voltage with the internal test signal.

10. The integrated circuit of claim 9, wherein, The high-pass filter includes: A coupling capacitor is configured to receive the test signal; and A voltage divider circuit consists of multiple resistors connected in series with each other.

11. The integrated circuit of claim 10, further comprising: A switching circuit, connected in parallel with the coupling capacitor, is configured to switch according to an enable signal. The integrated circuit is also configured to operate in either a DC test mode or an AC test mode according to the enable signal.

12. The integrated circuit of claim 10, wherein, The voltage divider circuit is further configured to generate at least one first reference signal that is upwardly offset by a specific voltage level relative to the common level of the internal test signal, and to generate at least one second reference signal that is downwardly offset by the specific voltage level relative to the common level of the internal test signal.

13. The integrated circuit of claim 9, wherein, The high-pass filter is also configured to generate a plurality of first reference signals and a plurality of second reference signals. The first low-pass filter is further configured to generate the first reference voltage based on a first reference signal selected from the plurality of first reference signals, and The second low-pass filter is further configured to generate the second reference voltage based on a second reference signal selected from the plurality of second reference signals.

14. The integrated circuit according to claim 13, further comprising: A plurality of first switching circuits, each first switching circuit being configured to receive a corresponding first reference signal among the plurality of first reference signals; as well as A plurality of second switching circuits, each configured to receive a corresponding second reference signal among the plurality of second reference signals.

15. The integrated circuit of claim 9, wherein, Each of the first comparator and the second comparator includes a comparator that does not have hysteresis characteristics.

16. The integrated circuit of claim 9, wherein, Each of the first low-pass filter and the second low-pass filter includes a resistor and a capacitor.

17. An integrated circuit operating in multiple test modes, the integrated circuit comprising: A voltage divider circuit includes multiple resistors connected in series with each other, wherein the voltage divider circuit is configured to generate an internal test signal, a first reference signal, and a second reference signal; A first low-pass filter is configured to receive the first reference signal and generate a first reference voltage. The second low-pass filter is configured to receive the second reference signal and generate a second reference voltage. A first comparator is configured to compare the first reference voltage with the internal test signal; and A second comparator is configured to compare the second reference voltage with the internal test signal. The voltage divider circuit is also configured to operate as a high-pass filter in the first test mode of the plurality of test modes.

18. The integrated circuit according to claim 17, further comprising: The coupling capacitor is configured to operate as the high-pass filter in cooperation with the voltage divider circuit in the first test mode; as well as A switching circuit is connected in parallel with the coupling capacitor, wherein the switching circuit is configured to be turned on in a second test mode among the plurality of test modes.

19. The integrated circuit of claim 17, wherein, The voltage divider circuit is further configured to generate a first reference signal that is upwardly offset by a specific voltage level relative to the common level of the internal test signal, and a second reference signal that is downwardly offset by the specific voltage level relative to the common level of the internal test signal.

20. The integrated circuit according to claim 17, wherein, Each of the first comparator and the second comparator includes a comparator that does not have hysteresis characteristics.

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