A dynamic gate stress aging test method and system for a power semiconductor device

Abstract

This invention discloses a dynamic gate stress aging test method and system for power semiconductor devices, relating to the field of semiconductor testing technology. It includes: a host computer control module for managing device-under-test parameters, editing aging test conditions, sending control commands, and storing test data; a main control unit for receiving control commands from the host computer control module, controlling the aging power supply output, and monitoring the test temperature; and a multi-station drive module communicatively connected to the main control unit. The dynamic gate stress aging test system of this invention uses a high-speed switching transistor half-bridge circuit to generate dynamic gate stress signals, with dv / dt reaching over 1V / ns and a frequency range of 0Hz to 500kHz, meeting the high-frequency application testing requirements of third-generation semiconductor devices such as SiC / GaN.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, specifically to a dynamic gate stress aging test method and system for power semiconductor devices. Background Technology

[0002] Third-generation semiconductor materials, represented by silicon carbide (SiC / GaN), are a driving force and crucial guarantee for the transformation and upgrading of my country's manufacturing industry. Industry experts believe that silicon carbide (SiC) power devices are expected to drive the upgrading of new energy vehicles, wind, solar, and energy storage systems, as well as aerospace power systems, providing a new generation of power devices. However, issues such as reliability verification and failure modes of silicon carbide (SiC) power devices share similarities with silicon (Si)-based power devices and urgently need to be addressed; otherwise, they cannot be used in high-reliability applications such as new energy vehicles and aerospace. During the manufacturing process of SiC MOSFET power devices, SiC / GaN... The interface contains numerous interface states and near-interface traps. Under specific temperature and electric field conditions, these defects can trap or release charge carriers, leading to a threshold voltage ( Threshold voltage drift occurs. The stability of the threshold voltage directly affects the on-resistance, switching losses, and system control accuracy of the device, and in severe cases, may lead to system failure. Therefore, threshold voltage drift is a core indicator for evaluating the reliability of SiC power devices.

[0003] Currently, the industry commonly uses bias temperature instability (BTI) testing to evaluate the impact of gate bias and temperature on threshold voltage stability. Traditional BTI testing employs DC gate stress (DC-BTI), which involves applying a constant gate voltage to the device under test (DUT), maintaining it at a specified temperature for a certain period, and then measuring the change in threshold voltage. However, research shows that under AC gate stress (AC-BTI) conditions, the parameter drift of SiC power devices may exceed the typical values ​​after applying standard DC gate stress. With changes in switching frequency, turn-off voltage, turn-on voltage, and temperature, the threshold voltage will drift to varying degrees, and the drift effect will saturate under long-term experimental conditions. To address the reliability verification requirements of third-generation semiconductor devices, the European Centre for Power Electronics' (ECE) AQG324 standard added a Dynamic Gate Stress (DGS) test item, requiring 100% DGS testing for SiC power devices. DGS testing applies a rectangular wave stress signal to the gate of the device under test (DUT), cycles it under set temperature and voltage conditions, and measures the threshold voltage at time intervals to obtain the threshold voltage drift curve, thus comprehensively evaluating the reliability of the gate oxide layer. However, existing dynamic gate stress testing equipment has the following shortcomings: First, the frequency, duty cycle, and voltage change rate (dv / dt) adjustment range of the dynamic stress signal are limited, making it difficult to cover high-frequency application scenarios; second, there is a measurement blind zone when the leakage current detection range is fixed or switched, making it impossible to achieve accurate detection over a wide range from nanoamperes to microamperes; third, the switching efficiency between the threshold voltage measurement process and the stress application process is low, and the measurement timing is difficult to control precisely; fourth, the parameter settings for each station are not independent during multi-station testing, which cannot meet the needs of simultaneous testing of different device models.

[0004] Therefore, there is an urgent need to develop a dynamic gate stress aging test method and system for power semiconductor devices that can accurately control dynamic gate bias stress parameters, realize wide-range leakage current detection, efficiently perform alternating stress application and threshold voltage measurement operations, and support multi-station independent control. Summary of the Invention

[0005] To address the aforementioned technical problems, a dynamic gate stress aging test method and system for power semiconductor devices is provided. This technical solution solves the problems mentioned above.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A dynamic gate stress aging test method and system for power semiconductor devices includes a host computer control module for managing device parameters, editing aging test conditions, sending control commands, and storing test data. The main control unit is used to receive control commands from the host computer control module, control the aging power supply output, and monitor the test temperature. The multi-station drive module is communicatively connected to the main control unit. It is used to generate a dynamic gate stress signal based on the received aging test parameters and apply it to the corresponding device under test leakage current detection module. It is used to detect the gate-source leakage current threshold voltage measurement module of the device under test during stress application and to measure the threshold voltage of the device under test after the stress application is paused. The dynamic gate stress signal is a rectangular wave signal, and its frequency, duty cycle, turn-on voltage, and turn-off voltage can be set independently.

[0007] Preferably, the multi-station drive module includes a high-speed dv / dt generation unit; The high-speed dv / dt generation unit adopts a switching transistor half-bridge circuit structure, and controls the voltage change rate and overshoot amplitude of the dynamic gate stress signal by adjusting the resistance value of the series gate resistor. The voltage change rate is not less than 0.3V / ns, and the overshoot amplitude is controlled within ±0.5V of the specified values ​​of the turn-on voltage and turn-off voltage.

[0008] Preferably, the leakage current detection module includes: The sampling resistor is used to convert the gate-source leakage current into a sampling voltage; The multi-stage amplification unit uses a zero-drift rail-to-rail operational amplifier to amplify the sampled voltage step by step, forming multiple amplification levels; A range switching unit is used to automatically select the amplification range based on the amplitude of the current sampled voltage. The measurement ranges of adjacent magnification levels overlap, preventing repeated back-and-forth switching when changing levels.

[0009] Preferably, the multi-level amplification unit includes three amplification levels, with amplification factors of 10 for the first level, 100 for the second level, and 1000 for the third level. The gear switching unit preferentially selects the highest amplification level for measurement, and when the output is at full deflection, it switches to the next highest amplification level in sequence.

[0010] Preferably, the threshold voltage measurement module performs the following measurement process: After pausing the application of the dynamic gate stress signal, a pre-pulse is applied to the device under test; After the pre-pulse ends, a preset threshold current is injected into the drain and source of the device under test; Within a preset reading time after threshold current injection, the gate-source voltage of the device under test is read as the threshold voltage. The duration of the pre-pulse is from 1ms to 100ms.

[0011] Preferably, the pre-emitter pulse includes a positive pre-emitter pulse and a negative pre-emitter pulse; Within a complete threshold voltage measurement cycle, the threshold voltage measurement module sequentially performs a first threshold voltage measurement under a positive forward pulse condition and a second threshold voltage measurement under a negative forward pulse condition to obtain a bipolar threshold voltage measurement result.

[0012] Preferably, it also includes a stress application and measurement alternation control module for controlling the alternation of the dynamic gate stress application stage and the threshold voltage measurement stage; During the dynamic gate stress application phase, it continuously applies a dynamic gate stress signal to the device under test for a specified number of cycles or for a specified time. During the threshold voltage measurement phase, the application of the dynamic gate stress signal is paused, the threshold voltage measurement is performed, and the measurement results are recorded. A threshold voltage drift curve is generated based on the threshold voltage measurement results obtained from multiple measurement stages.

[0013] Preferably, the multi-station drive module corresponds to several independent test stations, and each test station is equipped with an independent heating aging seat and temperature control unit; The temperature control unit is used to independently control the test temperature of the corresponding test station. The temperature control range is from room temperature to 200℃, and the temperature control accuracy does not exceed ±2℃. The host computer control module can individually set the aging test time, test device model, and aging test parameters for each test station.

[0014] Preferably, the host computer control module, the main control unit, and the multi-station drive module adopt a hierarchical control architecture: The host computer control module communicates with the main control unit via an Ethernet interface; The main control unit is connected to the corresponding drive board of each test station via a communication bus. After receiving the aging test parameters, the driver board performs waveform generation, power output, and status monitoring.

[0015] A gate stress aging test system for power semiconductor devices, Step 1. Parameter configuration: Configure the aging test parameters of the power semiconductor device under test in the host computer. The aging test parameters include the frequency, duty cycle, turn-on voltage, turn-off voltage, test temperature and test duration of the dynamic gate stress signal. Step 2. Stress Application: A dynamic gate stress signal is generated according to the aging test parameters. The dynamic gate stress signal is applied to the gate of the power semiconductor device under test through a high-speed dv / dt generation circuit, while the power semiconductor device under test is controlled to be at the set test temperature. Step 3. Leakage current monitoring: During the application of dynamic gate stress signal, the gate-source leakage current of the power semiconductor device under test is detected in real time through a multi-level adaptive amplifier circuit; Step 4. Threshold voltage measurement: Pause the application of dynamic gate stress signal at preset time intervals, apply a pre-pulse to the power semiconductor device under test and inject threshold current, and read the threshold voltage within a specified time. Step 5. Drift curve generation: Based on the results of multiple threshold voltage measurements, generate a drift curve of the threshold voltage as a function of stress application time or period to evaluate the reliability of the gate oxide layer of the power semiconductor device under test.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: The dynamic gate stress aging test system of the present invention uses a high-speed switching transistor half-bridge circuit to generate dynamic gate stress signal, with dv / dt reaching more than 1V / ns and a frequency range of 0Hz ~ 500kHz, which meets the high-frequency application test requirements of third-generation semiconductor devices such as SiC / GaN. The system of the present invention achieves a wide range detection of 1nA to 99.9 μA through a three-level adaptive amplifier circuit, and sets an overlap area between the levels to avoid repeated switching, with a measurement accuracy of ±1% ± 2LSB; The system of this invention is designed according to the JEDEC JEP183A standard, supports positive / negative bipolar pre-pulse, and completes within 100ms. The readings and measurement results are accurate and reliable. The system of the present invention can automatically control the alternating execution of dynamic stress application and threshold voltage measurement, generate a complete threshold voltage drift curve, and comprehensively evaluate the reliability of the gate oxide layer. The system of this invention features 24 independent temperature control stations and independent parameter settings, supporting simultaneous testing of different device models and significantly improving testing efficiency. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the dynamic grid stress aging test system of the present invention; Figure 2 This is a flowchart of the software aging test process of the system of the present invention; Figure 3 This is a block diagram illustrating the principle of leakage current detection in this invention. Figure 4 A half-bridge circuit diagram for generating high-speed dv / dt in this invention; Figure 5 The system of the present invention Output waveform of voltage detection; Figure 6 The system of the present invention The rising waveform of voltage detection; Figure 7 The system of the present invention The voltage drop waveform; Figure 8 The waveform diagram is an actual test waveform diagram of the dynamic DGS to VTH test of the system of the present invention. Detailed Implementation

[0018] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0019] Reference Figure 1 As shown, a dynamic gate stress aging test method and system for power semiconductor devices includes: a host computer control module for managing device-under-test parameters, editing aging test conditions, sending control commands, and storing test data; a main control unit for receiving control commands from the host computer control module, controlling the aging power supply output, and monitoring the test temperature; a multi-station drive module, communicatively connected to the main control unit, for generating dynamic gate stress signals based on the received aging test parameters and applying them to the corresponding device-under-test leakage current detection module, for detecting the gate-source leakage current threshold voltage of the device-under-test during stress application, and for measuring the threshold voltage of the device-under-test after pausing stress application; The dynamic grid stress signal is a rectangular wave signal, and its frequency, duty cycle, turn-on voltage, and turn-off voltage can be set independently.

[0020] This application provides a dynamic gate stress aging test system for power semiconductor devices. The system employs a hierarchical control mode with upper and lower computers, and mainly includes an upper computer control module, a main control unit, a multi-station drive module, an aging power supply module, a leakage current detection module, a threshold voltage measurement module, and a heating and temperature control module. The upper computer control module is implemented using an industrial computer and is equipped with dedicated control software for managing the parameter library of the device under test, editing aging test conditions, sending control commands, performing status and data queries, storing test data, and generating test reports.

[0021] The host computer communicates with the main control unit via a gigabit Ethernet interface, with the communication address set to the 192.168.123.XXX network segment. The main control unit is implemented using a microcontroller and is responsible for receiving control commands from the host computer control module, controlling the output of the primary aging power supply, monitoring the test chamber temperature, and forwarding control parameters to the driver boards at each workstation. The entire machine is configured with two main control microcontroller units, each corresponding to one of the two test chambers. The multi-workstation driver module contains multiple graphic driver detection boards (hereinafter referred to as driver boards), each driver board corresponding to 12 test workstations, for a total of 24 test workstations. After receiving the aging test parameters forwarded by the main control unit, the driver boards perform waveform generation, power output, and status monitoring functions.

[0022] like Figure 4 As shown, the multi-station drive module includes a high-speed dv / dt generation unit; The high-speed dv / dt generation unit adopts a switching transistor half-bridge circuit structure, and controls the voltage change rate and overshoot amplitude of the dynamic gate stress signal by adjusting the resistance value of the series gate resistor. The voltage change rate is not less than 0.3V / ns, and the overshoot amplitude is controlled within ±0.5V of the specified values ​​of the turn-on and turn-off voltages.

[0023] The high-speed dv / dt generation unit employs a high-speed switching transistor half-bridge circuit structure, including upper and lower bridge arm switching transistors. The switching transistors are selected from low on-resistance, low switching loss power MOSFETs or GaN devices to achieve nanosecond-level switching speeds. The output of the half-bridge circuit is connected to the gate of the device under test (DUT) via a series gate resistor Rg. The gate resistor Rg is adjustable or replaceable; adjusting its value controls the voltage change rate (dv / dt) and overshoot amplitude of the dynamic gate stress signal. Specifically, a smaller Rg results in faster dv / dt but a larger overshoot; a larger Rg results in slower dv / dt and a smaller overshoot. By selecting an appropriate Rg value, dv / dt can be controlled at ≥0.3V / ns, while the overshoot amplitude is controlled within ±0.5V of the specified turn-on and turn-off voltage values.

[0024] In an actual test of an embodiment of this application, the device under test was an Infineon 1200V 14mΩ SiC MOSFET IMZA120R014M1H (input capacitance Ciss = 4580pF), with a drive pulse frequency of 50kHz. The drive pulse parameters were set as follows: frequency 50kHz, turn-on voltage +18V, turn-off voltage -4V, and duty cycle 50%. The measured results were: rise time 16.80ns, fall time 17.60ns, and calculated dv / dt approximately 1.0V / ns~1.05V / ns, with a positive overshoot of 1.82% and a negative overshoot of 1.82%, meeting the ±0.5V overshoot control requirement.

[0025] like Figure 3 As shown, the leakage current detection module includes: The sampling resistor is used to convert the gate-source leakage current into a sampling voltage; The multi-stage amplification unit uses a zero-drift rail-to-rail operational amplifier to amplify the sampled voltage step by step, forming multiple amplification levels; A range switching unit is used to automatically select the amplification range based on the amplitude of the current sampled voltage. The measurement ranges of adjacent magnification levels overlap, preventing repeated back-and-forth switching when changing levels.

[0026] The multi-level amplification unit includes three amplification levels, with amplification factors of sin×10, sin×100, and sin×1000 respectively. The gear switching unit prioritizes the highest amplification level for measurement, and switches to the next highest amplification level when the output is at full deflection.

[0027] The leakage current detection module includes a sampling resistor, a multi-stage amplification unit, and a range switching unit. Connected between the source and ground of the device under test, it is used to transmit the gate-source leakage current. Converted to sampling voltage The sampling resistor value should be selected to balance sensitivity and measurement range; a typical value is 1kΩ to 100kΩ. The multi-stage amplification unit uses a zero-drift, ultra-low-noise rail-to-rail operational amplifier to achieve step-by-step amplification, forming three amplification levels: Level 1: Amplification factor ×10, measurement range 1nA to 99.9 μA, resolution 0.1 μA, measurement error ±1% ±2LSB; Level 2: Amplification factor ×100, measurement range 100nA to 999.9nA, resolution 10nA, measurement error ±1% ±2LSB; Level 3: Amplification factor ×1000, measurement range 1nA to 99.9nA, resolution 1nA, measurement error ±1% ±2LSB. The range switching unit is controlled by an MCU, and its workflow is as follows: The MCU first reads the output value of the third range (sin×1000) through an AD analog-to-digital converter; if the output is not fully biased, the leakage current is calculated using this value; if the output is fully biased, it switches to the second range (sin×100) for reading; if the second range is still fully biased, it switches to the first range (sin×10) for reading. Crucially, there is an overlap between the measurement ranges of the three ranges; for example, the upper limit of the second range (999.9 nA) overlaps with the lower limit of the first range (1 μA). This overlapping design prevents repeated range switching near critical values, ensuring measurement stability and continuity. The entire leakage current detection range is 1 nA to 99.9 μA, covering a wide range requirement from nanoamperes to microamperes.

[0028] like Figures 5 to 8 The threshold voltage measurement module shown performs the following measurement procedure: After pausing the application of the dynamic gate stress signal, a pre-pulse is applied to the device under test; After the pre-pulse ends, a preset threshold current is injected into the drain and source of the device under test. Within a preset reading time after threshold current injection, the gate-source voltage of the device under test is read as the threshold voltage. The duration of the pre-pulse is 1 to 100 ms.

[0029] The pre-pulse includes positive pre-pulse and negative pre-pulse; Within a complete threshold voltage measurement cycle, the threshold voltage measurement module sequentially performs the first threshold voltage measurement under the positive forward pulse condition and the second threshold voltage measurement under the negative forward pulse condition to obtain the bipolar threshold voltage measurement result.

[0030] The threshold voltage measurement module is designed according to the JEDEC JEP183A standard. Its measurement principle is as follows: a preset threshold current is injected into the drain and source of the device under test. When the drain-source current achieve At this time, read the gate-source voltage. as threshold voltage .

[0031] The measurement process includes the following steps: When measuring the threshold voltage, the output of the dynamic gate stress signal must be stopped first to allow the device under test to enter a stable state.

[0032] A pre-pulse is applied to the gate of the device under test, and the pulse duration is [duration missing]. The range is 1 to 100 ms. The purpose of the pre-pulse is to bring the interface state of the device under test to a stable state, thereby reducing measurement errors.

[0033] After the pre-pulse ends, set the idle time. The requirement is less than 50ms to keep the gate in a high-resistivity state.

[0034] Injecting threshold current into the drain and source of the device under test The current range is 100 μA to 50mA, and the steps can be set according to the device specifications.

[0035] After threshold current injection, it needs to be completed within 100ms. Threshold voltage completed in <100ms) This reading avoids the problems caused by long-term bias. Drift affects measurement results.

[0036] In this embodiment, the pre-pulse includes both positive and negative pre-pulse. Within a complete threshold voltage measurement cycle, a positive pre-pulse is applied first, followed by the first threshold voltage measurement, and then a negative pre-pulse is applied, followed by the second threshold voltage measurement, thus obtaining a bipolar threshold voltage measurement result. This bipolar measurement method can more comprehensively evaluate the threshold voltage drift characteristics of the device under test under positive and negative bias conditions.

[0037] Threshold voltage measurement module / The voltage measurement and control range is 1~10V, with a resolution of 0.01V.

[0038] In this embodiment, a stress application and measurement alternation control module is also included to control the alternation of the dynamic gate stress application stage and the threshold voltage measurement stage; During the dynamic gate stress application phase, it continuously applies a dynamic gate stress signal to the device under test for a specified number of cycles or for a specified time. During the threshold voltage measurement phase, the application of the dynamic gate stress signal is paused, the threshold voltage measurement is performed, and the measurement results are recorded. A threshold voltage drift curve is generated based on the threshold voltage measurement results obtained from multiple measurement stages.

[0039] The alternating control process for stress application and measurement includes: Configure aging test parameters in the host computer control module, including the frequency of the dynamic grid stress signal, duty cycle, turn-on voltage, turn-off voltage, test temperature, total test duration or total number of cycles, threshold voltage measurement interval, etc.

[0040] The multi-station drive module generates a dynamic gate stress signal based on the configuration parameters and applies it to the gate of the device under test. At the same time, the heating and temperature control module heats the device under test to the set test temperature.

[0041] A dynamic gate stress signal is continuously applied according to a set number of cycles or time. According to the AQG324 standard, the stress cycle number must be at least [number missing]. This is equivalent to running at a frequency of 100kHz for approximately 278 hours.

[0042] Determine whether the threshold voltage measurement time has been reached according to the preset time interval (such as every 1 hour, 10 hours, or 100 hours).

[0043] If the measurement time is reached, the stress application is paused, the threshold voltage measurement is performed according to the measurement procedure of the fourth embodiment, and the measurement results are recorded.

[0044] Determine whether the test duration or number of cycles has reached the set value. If not, return to the stress application stage; if it has, proceed to the next stage.

[0045] Generate drift curves and test reports. Based on the threshold voltage measurement results obtained at multiple measurement times, generate a drift curve of the threshold voltage as a function of stress application time or period to evaluate the reliability of the gate oxide layer of the device under test and automatically generate a test report.

[0046] like Figure 1 As shown, the multi-station drive module corresponds to several independent test stations, and each test station is equipped with an independent heating aging seat and temperature control unit; The temperature control unit is used to independently control the test temperature of the corresponding test station. The temperature control range is from room temperature to 200 ℃, and the temperature control accuracy does not exceed ±2 ℃. The host computer control module can individually set the aging test time, test device model, and aging test parameters for each test station.

[0047] The entire machine is equipped with 24 test stations, divided into 2 test chambers, each containing 12 test stations. Each test station is equipped with an independent heating aging seat and temperature control unit.

[0048] The heating aging chamber uses resistance heating, and the test temperature of each station is independently controlled by a PID algorithm. The temperature control range is: room temperature to 200℃, with an accuracy of ≤±1%±2℃.

[0049] The test parameters for each test station can be set independently, including: Aging test time: 0~9999 hours can be set arbitrarily; Test device models: Different models can be selected from the device library; Dynamic gate stress signal parameters: frequency, duty cycle, turn-on voltage, and turn-off voltage can be set independently; Test temperature: Different test temperatures can be set for each workstation.

[0050] The testing processes at each testing station are independent of each other, and each station can independently perform operations such as aging start, aging pause, aging continuation, and termination. When the aging test at a certain station is completed, the system will automatically alarm and terminate the test at that station, while other stations will not be affected.

[0051] The host computer control module provides a component library management function, which can pre-compile test parameter templates for different component models. When the test starts, the corresponding component library parameters can be called, which facilitates the query and archiving of test data.

[0052] In this embodiment, the host computer control module, the main control unit, and the multi-station drive module adopt a hierarchical control architecture: The host computer control module communicates with the main control unit via an Ethernet interface; The main control unit communicates with the corresponding drive board of each test station via a communication bus; After receiving the aging test parameters, the driver board performs waveform generation, power output, and status monitoring.

[0053] The dynamic grid stress aging test system adopts a modular structure, with external dimensions of 800mm (width) × 1400mm (depth) × 1950mm (height), and a weight not exceeding 500kg. The complete unit includes a main cabinet, monitor, keyboard and mouse set, industrial computer, equipment status indicator lights, zone status indicator lights, a high-voltage control panel, aging test chamber, and casters. Each test chamber is equipped with two independent test power supplies (60V / 5A, output voltage 0 ~ 60V, output current 0 ~ 5.0A, ripple (rms) ≤ 0.2% + 20mV, load regulation ≤ 20mV), a control system, a system power supply, a heating power supply, and a communication interface.

[0054] Equipment operating environment requirements: Ambient temperature: 5 ~ 35℃; Relative humidity: not greater than 75%RH; Atmospheric pressure: 750±30 mmHg; Mains voltage: three-phase five-wire AC380V±38V (30A), frequency 50Hz±1Hz; The surrounding environment is free from strong magnetic field interference and harmful gas corrosion; Maximum power consumption: less than 10kW.

[0055] Installation requirements: All units of the machine are air-cooled, requiring sufficient installation space and good ventilation. The rear door should be at least one meter away from the wall. The machine casing must be properly grounded to ensure normal operation of the equipment and personal safety. An insulating mat should be placed in the operator's work area to ensure the operator's personal safety.

[0056] A dynamic gate stress aging test method for power semiconductor devices: Step 1. Parameter Configuration: Configure the aging test parameters of the power semiconductor device under test in the host computer. The aging test parameters include the frequency, duty cycle, turn-on voltage, turn-off voltage, test temperature and test duration of the dynamic gate stress signal. Step 2. Stress Application: A dynamic gate stress signal is generated based on the aging test parameters. The dynamic gate stress signal is applied to the gate of the power semiconductor device under test through a high-speed dv / dt generation circuit, while the power semiconductor device under test is controlled to be at the set test temperature. Step 3. Leakage current monitoring: During the application of dynamic gate stress signal, the gate-source leakage current of the power semiconductor device under test is detected in real time through a multi-level adaptive amplifier circuit; Step 4. Threshold voltage measurement: Pause the application of dynamic gate stress signal at preset time intervals, apply a pre-pulse to the power semiconductor device under test and inject threshold current, and read the threshold voltage within a specified time. Step 5. Drift curve generation: Based on the results of multiple threshold voltage measurements, generate a drift curve of the threshold voltage as a function of stress application time or period to evaluate the reliability of the gate oxide layer of the power semiconductor device under test.

[0057] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.

Claims

1. A dynamic gate stress burn-in test system for power semiconductor devices, characterized by, include: The host computer control module is used to manage the parameters of the device under test, edit aging test conditions, send control commands, and store test data. The main control unit is used to receive control commands from the host computer control module, control the aging power supply output, and monitor the test temperature. The multi-station drive module is communicatively connected to the main control unit. It is used to generate a dynamic gate stress signal based on the received aging test parameters and apply it to the corresponding device under test leakage current detection module. It is used to detect the gate-source leakage current threshold voltage measurement module of the device under test during stress application and to measure the threshold voltage of the device under test after the stress application is paused. The dynamic gate stress signal is a rectangular wave signal, and its frequency, duty cycle, turn-on voltage, and turn-off voltage can be set independently.

2. The dynamic gate stress burn-in test system for power semiconductor devices of claim 1, wherein: The multi-station drive module includes a high-speed dv / dt generation unit; The high-speed dv / dt generation unit adopts a switching transistor half-bridge circuit structure, and controls the voltage change rate and overshoot amplitude of the dynamic gate stress signal by adjusting the resistance value of the series gate resistor. The voltage change rate is not less than 0.3V / ns, and the overshoot amplitude is controlled within ±0.5V of the specified values ​​of the turn-on voltage and turn-off voltage.

3. The dynamic gate stress burn-in system for power semiconductor devices of claim 1, wherein: The leakage current detection module includes: The sampling resistor is used to convert the gate-source leakage current into a sampling voltage; The multi-stage amplification unit uses a zero-drift rail-to-rail operational amplifier to amplify the sampled voltage step by step, forming multiple amplification levels; A range switching unit is used to automatically select the amplification range based on the amplitude of the current sampled voltage. The measurement ranges of adjacent magnification levels overlap, preventing repeated back-and-forth switching when changing levels.

4. The dynamic gate stress burn-in system for power semiconductor devices of claim 3, wherein: The multi-level amplification unit includes three amplification levels, with amplification factors of sin×10, sin×100, and sin×1000 respectively. The gear switching unit preferentially selects the highest amplification level for measurement, and when the output is at full deflection, it switches to the next highest amplification level in sequence.

5. The dynamic gate stress burn-in system for power semiconductor devices of claim 1, wherein: The threshold voltage measurement module performs the following measurement process: After pausing the application of the dynamic gate stress signal, a pre-pulse is applied to the device under test; After the pre-pulse ends, a preset threshold current is injected into the drain and source of the device under test; Within a preset reading time after threshold current injection, the gate-source voltage of the device under test is read as the threshold voltage. The duration of the pre-pulse is from 1ms to 100ms.

6. The dynamic gate stress burn-in test system for power semiconductor devices of claim 5, wherein: The pre-pulse includes positive pre-pulse and negative pre-pulse; Within a complete threshold voltage measurement cycle, the threshold voltage measurement module sequentially performs a first threshold voltage measurement under a positive forward pulse condition and a second threshold voltage measurement under a negative forward pulse condition to obtain a bipolar threshold voltage measurement result.

7. The dynamic gate stress burn-in system for power semiconductor devices of claim 1, wherein: It also includes a stress application and measurement alternation control module, which controls the alternation of the dynamic gate stress application stage and the threshold voltage measurement stage; During the dynamic gate stress application phase, it continuously applies a dynamic gate stress signal to the device under test for a specified number of cycles or for a specified time. During the threshold voltage measurement phase, the application of the dynamic gate stress signal is paused, the threshold voltage measurement is performed, and the measurement results are recorded. A threshold voltage drift curve is generated based on the threshold voltage measurement results obtained from multiple measurement stages.

8. The dynamic gate stress burn-in system for power semiconductor devices of claim 1, wherein: The multi-station drive module corresponds to several independent test stations, and each test station is equipped with an independent heating aging seat and temperature control unit. The temperature control unit is used to independently control the test temperature of the corresponding test station. The temperature control range is from room temperature to 200℃, and the temperature control accuracy does not exceed ±2℃. The host computer control module can individually set the aging test time, test device model, and aging test parameters for each test station.

9. The dynamic gate stress burn-in system for power semiconductor devices of claim 1, wherein: The host computer control module, main control unit, and multi-station drive module adopt a hierarchical control architecture: The host computer control module communicates with the main control unit via an Ethernet interface; The main control unit is connected to the corresponding drive board of each test station via a communication bus. After receiving the aging test parameters, the driver board performs waveform generation, power output, and status monitoring.

10. The dynamic gate stress aging test method for a power semiconductor device according to claim 1, characterized in that: Step 1. Parameter Configuration: Configure the aging test parameters of the power semiconductor device under test in the host computer. The aging test parameters include the frequency, duty cycle, turn-on voltage, turn-off voltage, test temperature and test duration of the dynamic gate stress signal. Step 2. Stress Application: A dynamic gate stress signal is generated according to the aging test parameters. The dynamic gate stress signal is applied to the gate of the power semiconductor device under test through a high-speed dv / dt generation circuit, while the power semiconductor device under test is controlled to be at the set test temperature. Step 3. Leakage current monitoring: During the application of dynamic gate stress signal, the gate-source leakage current of the power semiconductor device under test is detected in real time through a multi-level adaptive amplifier circuit; Step 4. Threshold voltage measurement: Pause the application of dynamic gate stress signal at preset time intervals, apply a pre-pulse to the power semiconductor device under test and inject threshold current, and read the threshold voltage within a specified time. Step 5. Drift curve generation: Based on the results of multiple threshold voltage measurements, generate a drift curve of the threshold voltage as a function of stress application time or period to evaluate the reliability of the gate oxide layer of the power semiconductor device under test.

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