A device and method for comprehensive characterization of dynamic characteristics of a power semiconductor device

Abstract

This invention proposes a comprehensive characterization device and method for the dynamic characteristics of power semiconductor devices, belonging to the field of comprehensive characterization technology. The device includes a multi-stress control and implementation circuit module and a multi-parameter data acquisition module. The multi-stress control and implementation circuit module is connected to the multi-parameter data acquisition module. The multi-stress control and implementation circuit module includes a signal and logic control unit, a multi-mode stress generation main circuit, and an online measurement circuit matrix. The signal and logic control unit is connected to both the multi-mode stress generation main circuit and the online measurement circuit matrix, and the multi-mode stress generation main circuit is connected to the online measurement circuit matrix. This invention enables flexible application of multiple stresses and synchronous measurement of multiple parameters, simplifies the testing process, improves characterization accuracy, accurately characterizes device degradation, and reduces testing costs.

Description

Technical Field

[0001] This invention proposes a device and method for comprehensive characterization of the dynamic characteristics of power semiconductor devices, which relates to the field of comprehensive characterization technology, specifically to the field of comprehensive characterization of the dynamic characteristics of power semiconductor devices. Background Technology

[0002] Wide-bandgap power semiconductor devices, represented by silicon carbide (SiC) and gallium nitride (GaN), have been widely used in electric vehicles, renewable energy power generation, and industrial drives due to their excellent characteristics such as high voltage resistance, high temperature resistance, and high switching speed. However, power devices face complex electrical and thermal stress conditions in actual operation, such as short-circuit impacts, high voltage interruption, and semi-conducting states. These stresses can lead to internal degradation of the devices, manifested as changes in parameters such as increased on-resistance, threshold voltage drift, and increased turn-off leakage current.

[0003] Currently, dynamic characterization techniques for power devices have several shortcomings. First, existing testing schemes typically separate high-power stress application equipment (such as dual-pulse test benches and short-circuit test benches) from high-precision parameter analyzers (such as source meters, signal transducers, and micrometers). During reliability assessments, it is often necessary to first apply electrical stress to the device under test on a stress platform, and then manually or mechanically transfer the device to the parameter analyzer for measurement. Because power device parameter degradation (especially threshold voltage drift) has significant transient recovery characteristics, the time delay during the transfer process (typically on the order of seconds or even minutes) can alter the internal thermal state and carrier trapping state of the device, resulting in the loss of crucial transient degradation information and making it impossible to accurately assess the device's true health status. Second, traditional dynamic testing devices can usually only simulate a single type of stress (e.g., only hard-switching tests or only load short-circuit tests), making it difficult to flexibly reproduce multiple actual operating conditions such as hard-switching short circuits, load short circuits, off-state high voltage, and half-open states on the same platform. This leads to low testing efficiency and makes it difficult to assess the impact of combined stresses on the device. Furthermore, implementing online measurement of nanoampere-level leakage current and millivolt-level threshold voltage under dynamic high-voltage and high-current environments is extremely challenging. Traditional relay switching methods have slow response speeds and are difficult to achieve effective isolation and switching between the main power circuit and the precision measurement circuit without introducing parasitic parameter interference. Summary of the Invention

[0004] This invention provides a device and method for comprehensive characterization of the dynamic characteristics of power semiconductor devices, in order to solve the above-mentioned problems: This invention proposes a device and method for comprehensive characterization of dynamic characteristics of power semiconductor devices. The device includes a multi-stress control and implementation circuit module and a multi-parameter data acquisition module. The multi-stress control and implementation circuit module is connected to the multi-parameter data acquisition module; The multi-stress control and implementation circuit module includes a signal and logic control unit, a multi-mode stress generation main circuit, and an online measurement circuit matrix. The signal and logic control unit is connected to the multi-mode stress generation main circuit and the online measurement circuit matrix, respectively, and the multi-mode stress generation main circuit is connected to the online measurement circuit matrix.

[0005] Furthermore, the signal and logic control unit includes a host computer, an FPGA controller, and a drive interface circuit; The host computer is connected to the FPGA controller, and the FPGA controller is connected to the drive interface circuit; The drive interface circuit is provided with seven independent signal output ports, namely the first output port A1 to the seventh output port A7. Port A1 is connected to the short-circuit switch. The control terminal, port A2, is connected to the upper tube switch. The control terminal, port A3, is connected to the auxiliary switch. The control terminal, port A4 is connected to the gate drive circuit input terminal of the power switching device under test (DUT), and port A5 is connected to the threshold voltage measurement access switch. The control terminal, port A6, is connected to the auxiliary capacitor reset switch. The control terminal, port A7, is connected to the weak current monitoring switch. The control terminal.

[0006] Furthermore, the multi-mode stress generation main circuit includes a DC high-voltage source. Bus capacitor Load inductance Upper pipe switch Short circuit switch and auxiliary switch ; The DC high voltage source The positive terminal is connected to the bus capacitor. The positive terminal of the bus capacitor The negative terminal is connected to the main power circuit ground; The short-circuit switch Connected in parallel to the load inductor The two ends; The load inductor With the short-circuit switch A parallel network is formed, and the input terminal of the parallel network is connected to the bus capacitor. The positive terminal of the parallel network is connected to the upper tube switch. The drain electrode; The upper tube switch The source is connected to the drain of the power switching device under test (DUT); The auxiliary switch The drain of the auxiliary switch is connected to the drain of the power switching device under test (DUT). The source is connected to the main power circuit ground, forming a parallel structure with the power switch device under test (DUT); The source of the power device under test (DUT) is connected to the input terminal of the online measurement circuit matrix.

[0007] Furthermore, the online measurement circuit matrix includes a threshold voltage measurement access switch. Auxiliary capacitor reset switch Weak current monitoring switch Auxiliary capacitor And clamping circuit and microcurrent measurement unit; The clamping circuit is connected in parallel between the drain and source of the power switching device under test (DUT); the clamping circuit samples and obtains the on-state voltage drop V1 across the source and drain terminals of the power switching device under test (DUT). The weak current monitoring switch One end is connected to the source of the power switching device under test (DUT), and the other end is connected to the microcurrent measurement unit. The threshold voltage measurement access switch One end is connected to the source of the power switch device under test (DUT), and the other end is connected to the auxiliary capacitor. One end and the auxiliary capacitor reset switch One end; The auxiliary capacitor The other end and the auxiliary capacitor reset switch The other end is connected to analog ground or main power loop ground; The auxiliary capacitor reset switch Configured as a dual-function switch, it closes during the on-resistance measurement and stress application phases, and works in conjunction with the threshold voltage measurement connection switch. Construct the main current path from the source of the power switching device under test (DUT) to ground; Disconnect during the threshold voltage measurement phase, in conjunction with the threshold voltage measurement access switch. Construct a capacitor charging circuit.

[0008] Furthermore, the multi-parameter data acquisition module includes a current probe, a high-precision oscilloscope, and a data processing terminal; The current probe is sleeved on the main circuit connection line of the power switching device under test (DUT). The analog input channels of the high-precision oscilloscope are respectively connected to the output terminal of the current probe, the output terminal of the clamping circuit, and the auxiliary capacitor. The voltage measurement terminal and the output terminal of the microcurrent measurement unit; The high-precision oscilloscope is connected to the data processing terminal.

[0009] Furthermore, the method includes: S1. Test parameters are set through the host computer, the signal and logic control unit generates initialization control signals, configures the online measurement circuit matrix, and controls the power switch device under test (DUT) to be in the test state. S2. According to the set stress mode, the signal and logic control unit generates a timing drive signal to control the operation of the multi-mode stress generation main circuit and apply preset electrical or thermal stress to the power switching device DUT under test. S3. During a specific conduction window after stress application, the drain-source voltage of the power switching device under test (DUT) is acquired through a clamping circuit. Combined with the drain current acquired by the current probe, the dynamic on-resistance is calculated via a data processing terminal. ; S4. Control the power device under test (DUT) to enter the off state, configure the online measurement circuit matrix to construct a capacitor charging loop, and use a specific current to charge the auxiliary capacitor. During charging, the source voltage variation curve of the power switching device under test (DUT) is acquired, and the dynamic threshold voltage is extracted. ; S5. After the threshold voltage measurement is completed, configure the online measurement circuit matrix to connect the source of the power switch device under test (DUT) to the micro-current measurement unit and collect the turn-off leakage current flowing through the DUT. .

[0010] Further, S2 includes: When hard switching stress is applied, the short-circuit switch is controlled. Disconnect and maintain threshold voltage measurement connection switch Auxiliary capacitor reset switch closure; via auxiliary switch Matching the upper tube switch Establish inductor current to control the power under test (DUT) to perform hard switching conduction under rated voltage and current; When a hard switch short-circuit stress is applied, the short-circuit switch is controlled. Close, maintain threshold voltage measurement access switch Auxiliary capacitor reset switch closure; Control upper pipe switch Close, so that the DC high voltage source It directly acts on the power device under test (DUT) and quickly turns off the DUT after detecting that the short-circuit current has reached the threshold. When a high-voltage off-state stress is applied, the power under test (DUT) is turned off, and the auxiliary switch... Turn off and maintain threshold voltage measurement connection switch Auxiliary capacitor reset switch Close, so that the DC high voltage source A continuous pressure is applied across the drain and source terminals of the power switching device under test (DUT). When a half-open stress is applied, the threshold voltage measurement is maintained at the switch. Auxiliary capacitor reset switch Close, control the upper tube switch Turn on and adjust the gate-source voltage of the power switching device under test (DUT). This allows it to operate in the saturation region, generating constant power loss.

[0011] Furthermore, before the stress application ends, the signal and logic control unit confirms that the stress application is complete and the power switch device under test (DUT) has entered the measurement conduction state. Control auxiliary capacitor reset switch When in the closed state, control the bypass auxiliary capacitor. ; The data acquisition channel of the trigger clamping circuit records the waveform data of V_{ds_on}.

[0012] Further, S5 includes: confirm Measurement complete; the power switch device under test (DUT) is in the off state. Control threshold voltage measurement access switch Disconnect, disconnect the source of the power switching device under test (DUT) from the power source. Network connectivity; Delay Then, control the weak current monitoring switch. Close the circuit and connect the source of the power switching device under test (DUT) to the microcurrent measurement unit; Acquire the leakage current signal output by the microcurrent measurement unit; After the measurement is completed, control the weak current monitoring switch. Disconnect and close the threshold voltage measurement connection switch. and auxiliary capacitor reset switch Reset system.

[0013] Furthermore, it also includes: Collected within the same period Data is presented as a set of state vectors; The trend of state vector change under different stress cycles was statistically analyzed, and the degradation of the package bond line was characterized by the change in on-resistance. Gate oxide layer damage was characterized by threshold voltage drift. Increased leakage current characterizes junction temperature rise or lattice defects.

[0014] Beneficial effects of the present invention: The present invention aims to solve the technical problems of transient information loss, incomplete stress mode coverage and low online measurement accuracy caused by the separation of dynamic and static parameter testing equipment in the prior art, and provides a multi-parameter online characterization device and method for power switching devices under multiple stress conditions. It enables comprehensive and accurate characterization of the dynamic characteristics of power switching devices, especially wide-bandgap field-effect transistors, under various complex stress conditions. For the first time, it integrates a multi-stress control and implementation circuit module and a multi-parameter data acquisition module on a single device. Without moving the device under test, it can continuously complete online measurements of three key parameters—stress application and on-resistance, threshold voltage, and turn-off leakage current—within milliseconds, effectively capturing transient degradation characteristics after stress and solving the problem of separation between traditional dynamic and static testing. A single platform can flexibly cover various typical stress conditions, such as hard-switching short circuits, load short circuits, off-state high voltage, and half-open states, significantly reducing the cost of testing equipment and improving the comprehensiveness and accuracy of evaluation results. Furthermore, through a unique dual-function switch design combined with an online measurement matrix, it cleverly solves the problem of coexistence and isolation between high-current main circuits and micro-signal measurement circuits, ensuring both the safety of stress application and the accurate extraction of weak parameters. Attached Figure Description

[0015] Figure 1 A schematic diagram of a comprehensive characterization method for the dynamic characteristics of power semiconductor devices; Figure 2 This is a schematic diagram of the structure of a power semiconductor device dynamic characteristic comprehensive characterization device provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the internal connections of a method for comprehensively characterizing the dynamic characteristics of a power semiconductor device according to an embodiment of the present invention; Figure 4 A schematic diagram of the control waveform for applying hard switching stress to the power semiconductor device under test (DUT); Figure 5 A schematic diagram of the control waveform for applying hard-switching short-circuit stress to the power semiconductor device under test (DUT); Figure 6 A schematic diagram of the control waveform for applying off-state high voltage stress to the power semiconductor device under test (DUT); Figure 7 A schematic diagram of the control waveform for applying half-open state stress to the power semiconductor device under test (DUT); Figure 8 This is a schematic diagram of the control waveforms for measuring Ron, Vth, and Ioff after stress has been applied to the power semiconductor device under test (DUT). Detailed Implementation

[0016] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0017] One embodiment of the present invention, such as Figure 2 and 3 As shown, the present invention proposes a device and method for comprehensive characterization of dynamic characteristics of power semiconductor devices. The device includes a multi-stress control and implementation circuit module and a multi-parameter data acquisition module. The multi-stress control and implementation circuit module is connected to the multi-parameter data acquisition module; The multi-stress control and implementation circuit module includes a signal and logic control unit, a multi-mode stress generation main circuit, and an online measurement circuit matrix. The signal and logic control unit is connected to the multi-mode stress generation main circuit and the online measurement circuit matrix, respectively, and the multi-mode stress generation main circuit is connected to the online measurement circuit matrix.

[0018] The signal and logic control unit is used to generate timing control signals to drive the operation of each switching device. The multi-mode stress generation main circuit is used to generate different types of electrical stress and thermal stress. The online measurement circuit matrix is ​​used to cooperate with the multi-parameter data acquisition module to complete the measurement of on-resistance, threshold voltage and turn-off leakage current within the same test cycle.

[0019] Within the same test cycle, obtain the stress application end time and parameter measurement start time; Obtain the corresponding measurement data based on the stress application end time and parameter measurement start time; The time period reduction adjustment was performed on the stress application end time and parameter measurement start time to obtain time reduction adjustment data; Updated measurement data is obtained based on time-reduction adjustment data; Calculate the difference between the corresponding measurement data and the updated measurement data to obtain the measurement error data; The measurement error data is compared with a preset error threshold to obtain the measurement comparison result; Based on the measurement comparison results, a time period adjustment command is generated to adjust the parameter measurement start time until the measurement error data is less than the preset error threshold.

[0020] This solution addresses the issue of large measurement errors caused by stress and timing discrepancies within the same testing cycle. It enables automatic timing calibration, significantly reducing measurement errors without manual intervention, thereby improving characterization accuracy and efficiency.

[0021] The working principle and technical effects of the above-mentioned technical solution are as follows: The device integrates stress generation and measurement switching functions through a multi-stress control and implementation circuit module. The signal and logic control unit, acting as the "brain," issues commands to control the multi-mode stress generation main circuit to generate a specified high-voltage, high-current, or thermal stress environment for the device under test (DUT). Simultaneously, the online measurement circuit matrix acts as a "bridge," rapidly switching the circuit topology within milliseconds to smoothly transition the DUT from a stress state to a measurement state. The multi-parameter data acquisition module acts as the "eyes," capturing the voltage and current waveforms in real time during this process. Using the solution provided by this invention, a comprehensive and accurate characterization of the dynamic characteristics of power switching devices under various complex stress conditions can be achieved; it solves the problem of the separation between dynamic and static parameter measurement equipment in traditional testing.

[0022] The multi-stress control and implementation circuit module is responsible for generating and applying various electrical and thermal stresses required for testing, while also coordinating the switching of parameter measurement loops. The multi-parameter data acquisition module is responsible for capturing various electrical signals during the testing process and performing parameter calculations and analysis. Specifically, the signal and logic control unit, the multi-mode stress generation main circuit, and the online measurement circuit matrix within the multi-stress control and implementation circuit module work in synergy: the signal and logic control unit generates precise timing control signals to drive the multi-mode stress generation main circuit to generate different types of stress, while simultaneously controlling the online measurement circuit matrix to switch to the corresponding measurement loop; under the control of the timing signals, the online measurement circuit matrix, in conjunction with the multi-parameter data acquisition module, completes the synchronous measurement of three key dynamic parameters—on-resistance, threshold voltage, and turn-off leakage current—within the same test cycle.

[0023] This device addresses the technical problems of "single stress application, scattered parameter measurements, and low testing efficiency" in the dynamic characteristic testing of power semiconductor devices. Existing technologies often require multiple independent devices for stress application and parameter measurement, necessitating frequent device switching and device re-clamping during testing. This is not only cumbersome but also increases testing errors and fails to achieve synchronous capture of multiple parameters under the same stress. This device integrates stress application and multi-parameter measurement into a single module, enabling flexible application of various stress types and synchronous measurement of multiple parameters without the need for additional equipment, significantly simplifying the testing process and reducing operational difficulty. Simultaneously, synchronous measurement within the same testing cycle avoids testing errors caused by multiple clamping and device switching, improving the accuracy and consistency of dynamic characteristic characterization. Furthermore, the clear module division and rigorous connection logic ensure the stability and reliability of the device, enabling it to adapt to the dynamic characteristic testing needs of different types of power semiconductor devices and expanding its applicability.

[0024] In one embodiment of the present invention, the signal and logic control unit includes a host computer, an FPGA controller, and a driver interface circuit; The host computer is connected to the FPGA controller and is used to send test commands and monitor the status; the FPGA controller is connected to the driver interface circuit. The drive interface circuit is provided with seven independent signal output ports, namely the first output port A1 to the seventh output port A7. Port A1 is connected to the short-circuit switch. The control terminal, port A2, is connected to the upper tube switch. The control terminal, port A3, is connected to the auxiliary switch. The control terminal, port A4 is connected to the gate drive circuit input terminal of the power switching device under test (DUT), and port A5 is connected to the threshold voltage measurement access switch. The control terminal, port A6, is connected to the auxiliary capacitor reset switch. The control terminal, port A7, is connected to the weak current monitoring switch. The control terminal.

[0025] The host computer serves as the user interface, setting test parameters (such as stress type, duration, sampling frequency, etc.) and sending them to the FPGA controller. The FPGA controller utilizes its parallel processing capabilities to generate seven independent timing signals with nanosecond-level precision. The drive interface circuit converts these logic level signals into drive signals sufficient to drive power switches (such as IGBTs or MOSFETs). Through the precise coordination of ports A1-A7, tight timing control is achieved for the high-power switches in the stress generation circuit and the signal switches in the measurement matrix, ensuring seamless connection between stress application and parameter measurement.

[0026] The solution provided by the invention enables complex timing control of up to seven switching devices, ensuring the safety and accuracy of the system during mode switching; in particular, the independent signal output port design decouples the control of each part of the circuit, facilitating debugging and timing optimization.

[0027] The working principle and technical effects of the above technical solution are as follows: The signal and logic control unit, as the "control center" of the entire device, undertakes the core functions of issuing test commands, generating timing signals, monitoring equipment status, and outputting drive signals. Internally, through the collaborative work of the host computer, FPGA controller, and drive interface circuit, it achieves precise control of the entire device. Specifically, the host computer serves as the human-machine interface, allowing testers to set test parameters (such as stress type, test cycle, parameter thresholds, etc.) and receive test status information from the FPGA controller, enabling real-time monitoring and command adjustment of the test process. The FPGA controller, as the core control chip, receives test commands from the host computer, parses them into specific timing control logic, generates precise timing drive signals, and simultaneously collects the working status of each module in real time, feeding it back to the host computer. The drive interface circuit, as a bridge for signal amplification and transmission, amplifies and isolates the timing drive signals generated by the FPGA controller, and drives the corresponding switching devices through seven independent signal output ports (A1-A7). Each port corresponds to a specific controlled object, ensuring precise synchronization of the action timing of each switching device and avoiding test failures or errors caused by signal interference or timing deviations. Specific port functions: A1 controls the short-circuit switch to switch between short-circuiting and opening the load inductor; A2 controls the upper transistor switch to adjust the on / off state of the main power circuit; A3 controls the auxiliary switch to construct different stress application circuits; A4 connects to the DUT gate drive circuit to control the DUT's on / off state; A5 controls the threshold voltage measurement access switch to switch the on / off state of the threshold voltage measurement circuit; A6 controls the auxiliary capacitor reset switch to reset the auxiliary capacitor and switch the circuit; A7 controls the weak current monitoring switch to switch the on / off state of the leakage current measurement circuit.

[0028] This invention solves the technical problems of low timing accuracy, chaotic control logic, large signal interference, and poor scalability in existing technologies. In existing technologies, some test devices use a single controller to realize the control function, resulting in low timing control accuracy, inability to meet the synchronous operation requirements of multiple switching devices, weak signal driving capability, and susceptibility to external interference, leading to instability in the test process; at the same time, the control interface is singular, unable to adapt to the driving requirements of multiple types of switching devices, and has poor scalability. This device utilizes the collaborative control of a host computer and an FPGA controller. On one hand, the host computer enables convenient parameter setting and status monitoring, enhancing the operability and intuitiveness of the test. On the other hand, the high-speed timing control capability of the FPGA controller ensures the accuracy of the timing drive signals, achieving synchronous operation of each switching device with timing errors controlled at the microsecond level, meeting the high timing accuracy requirements of dynamic characteristic testing. The design of seven independent drive ports enables independent control of different switching devices, avoiding mutual interference between signals and improving the stability and reliability of control. The signal amplification and isolation processing of the drive interface circuit further enhances the anti-interference capability of the drive signals, avoiding the influence of external electromagnetic interference on the control signals and ensuring the stable operation of the test process. In addition, the structural design of this control unit has good scalability, allowing for flexible adjustment of the port control logic according to different test requirements, adapting to the test needs of different types of power semiconductor devices.

[0029] In one embodiment of the present invention, the multi-mode stress generation main circuit includes a DC high-voltage source. Bus capacitor Load inductance Upper pipe switch Short circuit switch and auxiliary switch ; The DC high voltage source The positive terminal is connected to the bus capacitor. The positive terminal of the bus capacitor The negative terminal is connected to the main power circuit ground; The short-circuit switch Connected in parallel to the load inductor The two ends are used to short-circuit the load inductor when closed; The load inductor With the short-circuit switch A parallel network is formed, and the input terminal of the parallel network is connected to the bus capacitor. The positive terminal of the parallel network is connected to the upper tube switch. The drain electrode; The upper tube switch The source is connected to the drain of the power switching device under test (DUT); The auxiliary switch The drain of the auxiliary switch is connected to the drain of the power switching device under test (DUT). The source is connected to the main power circuit ground, forming a parallel structure with the power switch device under test (DUT); The source of the power device under test (DUT) is connected to the input terminal of the online measurement circuit matrix.

[0030] DC high voltage source and bus capacitor Provides a stable DC bus voltage; by controlling the short-circuit switch The circuit can switch on and off in inductive load mode (…). disconnect, Access) and resistive / short circuit mode ( closure, Switching between bypassed and connected circuits; upper-side switch To implement a half-bridge or single-transistor test structure in conjunction with the device under test (DUT); auxiliary switches It provides additional freewheeling channels or auxiliary commutation paths, enabling the circuit to be flexibly constructed into various topologies such as hard switching and load short circuit.

[0031] By adopting the solution provided by the invention, circuit reconstruction for various typical stress conditions can be achieved using a limited combination of devices. A single platform can flexibly cover various typical stress conditions such as hard switch short circuit, load short circuit, off-state high voltage and half-open state, which greatly reduces the cost of test equipment.

[0032] The working principle and technical effect of the above technical solution are as follows: The multi-mode stress generation main circuit is the core execution unit for applying various electrical and thermal stresses. Through the reasonable connection of various components and the precise control of switching actions, it generates various types of stresses such as hard switching, hard switching short circuit, off-state high voltage, and half-open state, providing a stress environment that meets the test requirements for the power switching device under test (DUT). Specific circuit connection logic: The DC high-voltage source serves as the main power supply unit, providing a stable high-voltage DC power supply for the entire main circuit; the bus capacitor is connected in parallel across the DC high-voltage source to stabilize the bus voltage, absorb voltage fluctuations in the circuit, and prevent voltage spikes from damaging the DUT and circuit components; the load inductor and short-circuit switch are connected in parallel to form a parallel network. The input of this parallel network is connected to the positive terminal of the bus capacitor, and the output is connected to the drain of the upper-side switch. By closing and opening the short-circuit switch, the connection and short-circuit switching of the load inductor are realized. When the short-circuit switch is closed, the load inductor is... A short circuit reduces the circuit load; when the short-circuit switch is open, the load inductance is connected to the circuit, increasing the circuit load. The source of the upper-side switch is connected to the drain of the DUT, used to control the on / off state of the main power circuit and adjust the voltage and current applied to the drain of the DUT. The auxiliary switch is connected in parallel with the DUT (drain connected to the drain of the DUT, source connected to the ground of the main power circuit), used to cooperate with the upper-side switch to construct different stress application circuits and assist in adjusting the working state of the DUT. The source of the DUT is connected to the online measurement circuit matrix to ensure that the electrical signal of the DUT can be acquired in real time during stress application. Through the precise control of each switching device (upper-side switch, short-circuit switch, auxiliary switch) by the signal and logic control unit, different stress application modes can be flexibly switched to achieve on-demand application of various stresses.

[0033] This invention addresses the technical problems of existing stress generation circuits, such as limited functionality, limited stress modes, low stress application accuracy, and insufficient protection for the device under test (DUT). In existing technologies, most stress generation circuits can only apply a single type of stress, failing to meet the demands of dynamic characteristic testing of power semiconductor devices for diverse stress environments. Furthermore, the stress application process suffers from large voltage and current fluctuations, low accuracy, and a lack of effective voltage buffering and protection mechanisms, easily leading to DUT damage. This technical solution integrates multiple stress generation functions through a reasonable circuit topology design, enabling flexible application of various stresses such as hard switching, hard switching short circuit, off-state high voltage, and half-open state. It covers the most critical and commonly used stress types in the dynamic characteristic testing of power semiconductor devices, meeting the testing needs of different test scenarios and devices. The bus capacitor effectively stabilizes the bus voltage, absorbs voltage spikes and current fluctuations in the circuit, reduces the impact of voltage fluctuations on the DUT test accuracy, and protects the DUT and other components in the circuit from damage caused by voltage surges. The parallel design of the load inductor and short-circuit switch enables flexible load switching, allowing for rapid adjustment of the loop load according to different stress modes, improving the flexibility and accuracy of stress application. The parallel design of the auxiliary switch and DUT further optimizes the stress application loop, assisting in adjusting the DUT's operating state and ensuring the stability and accuracy of stress application. The entire circuit topology is simple, logically clear, and rationally selected components, reducing circuit complexity and manufacturing costs while improving circuit reliability and lifespan, enabling long-term stable operation.

[0034] In one embodiment of the present invention, the online measurement circuit matrix includes a threshold voltage measurement access switch. Auxiliary capacitor reset switch Weak current monitoring switch Auxiliary capacitor And clamping circuit and microcurrent measurement unit; The clamping circuit is connected in parallel between the drain and source of the power switching device under test (DUT); the clamping circuit samples and obtains the on-state voltage drop V1 across the source and drain terminals of the power switching device under test (DUT). The weak current monitoring switch One end is connected to the source of the power switching device under test (DUT), and the other end is connected to the microcurrent measurement unit. The threshold voltage measurement access switch One end is connected to the source of the power switch device under test (DUT), and the other end is connected to the auxiliary capacitor. One end and the auxiliary capacitor reset switch One end; The auxiliary capacitor The other end and the auxiliary capacitor reset switch The other end is connected to analog ground or main power loop ground; The auxiliary capacitor reset switch Configured as a dual-function switch, it closes during the on-resistance measurement and stress application phases, and works in conjunction with the threshold voltage measurement connection switch. Construct the main current path from the source of the power switching device under test (DUT) to ground; Disconnect during the threshold voltage measurement phase, in conjunction with the threshold voltage measurement access switch. Construct a capacitor charging circuit.

[0035] The online measurement circuit matrix is ​​located between the source and ground of the device under test (DUT) and on the parallel branches. Clamping circuitry is used to extract the small on-state voltage drop when the DUT is on, and to provide isolation protection when the DUT is off and subjected to high voltage. The ingenious design solves the problem of the high-current circuit and the precision measurement circuit sharing a common ground: when a large current needs to be passed (stress application or...) During measurement, A closed path provides a low-impedance path; when measurement is required. hour, Disconnect, using auxiliary capacitor The integral characteristic measures the source potential change; when it is necessary to measure hour, Disconnect the isolation capacitor network. The closing mechanism introduces a weak leakage current into the measurement unit.

[0036] By adopting the solution provided by the invention, and through a unique dual-function switch design combined with an online measurement matrix, the problem of coexistence and isolation between the high-current main circuit and the micro-signal measurement circuit is cleverly solved, which not only ensures the safety of stress application, but also achieves the accurate extraction of weak parameters.

[0037] The working principle and technical effect of the above technical solution are as follows: The online measurement circuit matrix is ​​the core unit for realizing synchronous measurement of multiple parameters. Through the coordinated work of various switching devices and measuring elements, and in conjunction with the multi-parameter data acquisition module, it completes the measurement of three key parameters, namely on-resistance, threshold voltage, and turn-off leakage current, within the same test cycle. Furthermore, through the time-division multiplexing of switches, seamless switching of different measurement circuits is achieved, avoiding mutual interference between measurements. Specific operating logic: The clamping circuit is connected in parallel between the drain and source of the DUT. Its core function is to stabilize the voltage across the drain and source of the DUT, and simultaneously sample the on-state voltage drop V1 across the source and drain of the DUT in real time, providing voltage data for calculating the on-resistance. One end of the weak current monitoring switch is connected to the source of the DUT, and the other end is connected to the micro-current measurement unit. It is used to control the on / off state of the leakage current measurement circuit. When it is necessary to measure the off-state leakage current, the switch is closed, connecting the source of the DUT to the micro-current measurement unit to realize the acquisition of leakage current. One end of the threshold voltage measurement access switch is connected to the source of the DUT, and the other end is connected to the auxiliary capacitor and the auxiliary capacitor reset switch. The other ends of the auxiliary capacitor and the auxiliary capacitor reset switch are both grounded (analog ground). (Or the main power circuit ground), where the auxiliary capacitor reset switch is a dual-function switch to switch the measurement circuit: During the on-resistance measurement and stress application stages, the auxiliary capacitor reset switch is closed, forming a main current path from the source of the DUT to ground in conjunction with the threshold voltage measurement access switch, ensuring the normal operation of stress application and on-resistance measurement, while simultaneously short-circuiting and resetting the auxiliary capacitor to prevent residual capacitor voltage from affecting measurement accuracy; During the threshold voltage measurement stage, the auxiliary capacitor reset switch is open, forming a capacitor charging circuit in conjunction with the threshold voltage measurement access switch, charging the auxiliary capacitor with a specific current, and indirectly obtaining the source voltage change curve of the DUT by collecting the voltage change of the auxiliary capacitor, thereby extracting the dynamic threshold voltage. Throughout the measurement process, the online measurement circuit matrix, under the control of the signal and logic control unit, precisely switches the measurement circuit to ensure that the measurements of the three main parameters do not interfere with each other and are completed synchronously.

[0038] This solution addresses the technical problems of complex parameter measurement circuits, mutual interference among multiple parameter measurements, low measurement accuracy, and low measurement efficiency in existing technologies. In existing technologies, multi-parameter measurements often require separate measurement circuits, resulting in complex circuit structures, cumbersome switching, and easy cross-interference between different measurement circuits, leading to decreased measurement accuracy. Furthermore, the measurement of parameters such as threshold voltage and turn-off leakage current requires additional reset and isolation mechanisms, and existing solutions lack effective designs, resulting in large measurement errors and low efficiency. This technical solution integrates the measurement circuits of the three major parameters into a single unit through the integrated design of an online measurement circuit matrix. Through time-division multiplexing of switches and the design of dual-function switches, seamless switching between different measurement circuits is achieved without the need for additional independent measurement circuits, simplifying the circuit structure and reducing circuit complexity and manufacturing costs. The dual-function design of the auxiliary capacitor reset switch not only constructs the main current path but also completes the reset of the auxiliary capacitor and the switching of the measurement circuit, achieving two goals at once, simplifying the control logic, and avoiding the influence of residual voltage of the auxiliary capacitor on measurement accuracy, thus improving measurement accuracy. The clamping circuit stabilizes the measurement circuit. The voltage across the drain and source terminals of the DUT ensures the stability and accuracy of the on-state voltage drop sampling, providing a guarantee for the accurate calculation of the on-resistance. The cooperation between the micro-current measurement unit and the weak current monitoring switch enables the accurate acquisition of the turn-off leakage current. Furthermore, the opening and closing of the switch isolates the leakage current measurement circuit from other circuits, avoiding cross-interference. The design of the entire measurement circuit matrix enables the synchronous measurement of multiple parameters within the same test cycle, significantly improving test efficiency while reducing measurement errors and enhancing the accuracy of dynamic parameter characterization. This meets the high requirements for measurement accuracy and efficiency in the dynamic characteristic testing of power semiconductor devices.

[0039] In one embodiment of the present invention, the multi-parameter data acquisition module includes a current probe, a high-precision oscilloscope, and a data processing terminal; The current probe is connected to the main circuit connection line of the power switching device under test (DUT) and is used to collect the drain current signal flowing through the DUT. The analog input channels of the high-precision oscilloscope are respectively connected to the output terminal of the current probe, the output terminal of the clamping circuit, and the auxiliary capacitor. The voltage measurement terminal and the output terminal of the microcurrent measurement unit; The high-precision oscilloscope is connected to the data processing terminal, which is used to calculate the on-resistance based on the acquired voltage and current waveforms. Threshold voltage and shut off leakage current .

[0040] The current probe, clamping circuit output, auxiliary capacitor voltage, and micro-current measurement unit output correspond to four key physical quantities in the system: high current, on-state voltage drop, source potential change, and turn-off leakage current, respectively. A high-precision oscilloscope synchronously acquires these analog quantities and transmits the data to the data processing terminal. The data processing terminal utilizes built-in algorithms, such as... , Algorithms and other methods are used to extract key parameters characterizing the transient properties of a device under stress from the original waveform.

[0041] The solution provided by the invention can capture the device state at the moment of stress termination with extremely high time resolution, avoiding time delays and information loss caused by device switching, and ensuring the authenticity and integrity of the data.

[0042] The working principle and technical effect of the above technical solution are as follows: The multi-parameter data acquisition module is the core unit for realizing test data acquisition, processing and analysis. Through the collaborative work of the current probe, high-precision oscilloscope and data processing terminal, it completes the capture, transmission, calculation and analysis of various electrical signals during the test process, and finally outputs the three key parameters of the DUT: dynamic on-resistance, dynamic threshold voltage and turn-off leakage current. The specific working logic is as follows: The current probe is connected to the main circuit connection line of the DUT, using a non-contact acquisition method to capture the drain current signal flowing through the DUT in real time. This avoids interference from contact acquisition to the main circuit and ensures the authenticity and accuracy of the current signal. A high-precision oscilloscope, as the core device for signal acquisition, has multiple analog input channels connected to the output terminals of the current probe, clamping circuit, auxiliary capacitor voltage measurement unit, and micro-current measurement unit, simultaneously acquiring the drain current signal, DUT drain-source on-state voltage drop signal, auxiliary capacitor voltage signal, and turn-off drain current signal. These analog signals are converted into digital signals and transmitted to the data processing terminal. The data processing terminal receives the digital signals transmitted from the high-precision oscilloscope and analyzes and calculates the acquired voltage and current waveforms according to a preset algorithm: it calculates the dynamic on-resistance using the drain current and drain-source on-state voltage drop, extracts the dynamic threshold voltage using the auxiliary capacitor voltage change curve, and determines the turn-off drain current using the micro-current measurement signal. Simultaneously, the acquired data is organized and stored to form a test report for analysis and reference by test personnel.

[0043] This invention solves the technical problems of low data acquisition accuracy, high signal interference, low data processing efficiency, and inaccurate parameter calculation in existing technologies. In existing technologies, some data acquisition modules use contact-type acquisition methods, which are prone to interference with the main circuit, leading to signal distortion. Simultaneously, insufficient oscilloscope accuracy and imperfect data processing algorithms result in large parameter calculation errors and low data processing efficiency, making real-time analysis impossible. This technical solution employs a non-contact current probe to acquire drain current, effectively avoiding interference from contact acquisition to the main circuit and ensuring the authenticity and accuracy of the current signal. The use of a high-precision oscilloscope enhances the accuracy and sensitivity of signal acquisition, enabling the capture of weak voltage and current changes, meeting the high accuracy requirements of dynamic parameter measurements. The multi-channel synchronous acquisition design achieves simultaneous acquisition of various signals, ensuring the correlation and accuracy of parameter calculations and avoiding calculation errors caused by asynchronous signal acquisition. The integrated design of the data processing terminal enables real-time data processing, calculation, and storage, significantly improving data processing efficiency. Simultaneously, the preset precise algorithm ensures the accuracy of the three major parameter calculations, avoiding errors caused by manual calculations. Furthermore, the data processing terminal can organize and analyze test data to generate test reports, providing testers with intuitive and comprehensive test results, reducing the difficulty of data analysis, and improving the overall efficiency of the testing work.

[0044] In one embodiment of the present invention, the method includes: S1. Test parameters are set through the host computer, the signal and logic control unit generates initialization control signals, configures the online measurement circuit matrix, and controls the power switch device under test (DUT) to be in the test state. S2. According to the set stress mode, the signal and logic control unit generates a timing drive signal to control the operation of the multi-mode stress generation main circuit and apply preset electrical or thermal stress to the power switching device DUT under test. S3. During a specific conduction window after stress application, the drain-source voltage of the power switching device under test (DUT) is acquired through a clamping circuit. Combined with the drain current acquired by the current probe, the dynamic on-resistance is calculated via a data processing terminal. ; S4. Control the power device under test (DUT) to enter the off state, configure the online measurement circuit matrix to construct a capacitor charging loop, and use a specific current to charge the auxiliary capacitor. During charging, the source voltage variation curve of the power switching device under test (DUT) is acquired, and the dynamic threshold voltage is extracted. ; S5, such as Figure 8 As shown, after the threshold voltage measurement is completed, the online measurement circuit matrix is ​​configured to connect the source of the power device under test (DUT) to the micro-current measurement unit to collect the turn-off leakage current flowing through the DUT. ,like Figure 1 As shown.

[0045] Within the same test cycle, obtain the stress application end time and parameter measurement start time; Obtain the corresponding measurement data based on the stress application end time and parameter measurement start time; The time period reduction adjustment was performed on the stress application end time and parameter measurement start time to obtain time reduction adjustment data; Updated measurement data is obtained based on time-reduction adjustment data; Calculate the difference between the corresponding measurement data and the updated measurement data to obtain the measurement error data; The measurement error data is compared with a preset error threshold to obtain the measurement comparison result; Based on the measurement comparison results, a time period adjustment command is generated to adjust the parameter measurement start time until the measurement error data is less than the preset error threshold.

[0046] This solution addresses the issue of large measurement errors caused by stress and timing discrepancies within the same testing cycle. It enables automatic timing calibration, significantly reducing measurement errors without manual intervention, thereby improving characterization accuracy and efficiency.

[0047] This method integrates traditionally fragmented stress testing and parameter measurement into a continuous process according to a specific timing logic. First, the system is initialized to ensure safety; then, in step two, real-world conditions are simulated to cause device degradation; subsequently, steps three through five are performed immediately (typically within microseconds or milliseconds of delay) to sequentially acquire the on-state and semi-on-state (estimated). The key parameters of the device in the current aging state are used to construct a complete picture of the device.

[0048] Using the solution provided by the invention, the online measurement of three key parameters—stress application, on-resistance, threshold voltage, and turn-off leakage current—can be completed continuously within milliseconds without moving the device under test, effectively capturing the transient degradation characteristics after stress.

[0049] The working principle and technical effects of the above technical solution are as follows: S1 is the initialization stage. The tester sets the test parameters (such as stress type, test cycle, parameter threshold, etc.) through the host computer. After receiving the test command, the signal and logic control unit generates an initialization control signal, configures the online measurement circuit matrix, switches to the initial test loop, and controls the DUT to be in the test state, ensuring that the DUT and each circuit module are in normal working condition, preparing for subsequent tests; S2 is the stress application stage. The signal and logic control unit generates the corresponding timing drive signal according to the set stress mode, controls the operation of each switching device in the multi-mode stress generation main circuit, constructs the corresponding stress application loop, and applies the preset electrical stress or thermal stress to the DUT to ensure that the DUT is in the set stress environment; S3 is the dynamic on-resistance measurement stage. Within a specific conduction window (transient window) after the stress application ends, the clamping circuit is used to collect data. The drain-source voltage of the DUT, combined with the drain current acquired by the current probe, is used by the data processing terminal to calculate the dynamic on-resistance of the DUT according to the algorithm of "on-resistance = drain-source voltage / drain current". The selection of this on-resistance window can avoid measurement errors caused by stress effect attenuation. S4 is the dynamic threshold voltage measurement stage. The DUT is controlled to enter the off state. The signal and logic control unit configures the online measurement circuit matrix and switches to the capacitor charging circuit. The auxiliary capacitor is charged with a specific current. The voltage change curve of the auxiliary capacitor is acquired by a high-precision oscilloscope, thereby indirectly obtaining the source voltage change curve of the DUT. The data processing terminal extracts the dynamic threshold voltage from the curve. S5 is the turn-off leakage current measurement stage. After the threshold voltage measurement is completed, the signal and logic control unit configures the online measurement circuit matrix again, connects the source of the DUT to the micro-current measurement unit, and acquires the turn-off leakage current flowing through the DUT, completing the multi-parameter measurement of the entire test cycle.

[0050] This invention addresses the technical problems of existing characterization methods, such as cumbersome procedures, long testing cycles, asynchronous multi-parameter measurements, large measurement errors, and the inability to accurately characterize dynamic parameters. In existing technologies, dynamic characteristic testing of power semiconductor devices often employs a step-by-step testing approach, first applying stress and then measuring each parameter individually. This process is cumbersome, has a long testing cycle, and time intervals exist between measurements of different parameters, leading to stress effect attenuation and measurement results that fail to reflect the true dynamic characteristics of the device under stress. Furthermore, inaccurate measurement timing control results in large measurement errors. This technical solution integrates initialization, stress application, and multi-parameter measurement into a complete test cycle through standardized process design. The process is coherent and easy to operate, significantly shortening the test cycle and improving test efficiency. Parameter measurement is performed within the transient window after stress application, avoiding measurement errors caused by stress effect decay and device state changes, ensuring that the measurement results accurately reflect the dynamic characteristics of the DUT under stress. Multi-parameter measurements are completed synchronously within the same test cycle, eliminating the need for step-by-step operations and avoiding errors caused by multiple clamping and equipment switching, thus improving measurement consistency and accuracy. The entire method is highly compatible with the device structure, with precise timing control, ensuring the stability and repeatability of the test process, and enabling comprehensive and accurate characterization of the dynamic characteristics of power semiconductor devices.

[0051] In one embodiment of the present invention, S2 includes: like Figure 4 As shown, when hard switching stress is applied, the short-circuit switch is controlled. Disconnect (load connection), maintain threshold voltage measurement connection switch Auxiliary capacitor reset switch closure; via auxiliary switch Matching the upper tube switch Establish inductor current to control the power under test (DUT) to perform hard switching conduction under rated voltage and current; like Figure 5 As shown, when a hard switch short-circuit stress is applied, the short-circuit switch is controlled. Close (load short circuit), maintain threshold voltage measurement connection switch Auxiliary capacitor reset switch closure; Control upper pipe switch Close, so that the DC high voltage source It directly acts on the power device under test (DUT) and quickly turns off the DUT after detecting that the short-circuit current has reached the threshold. like Figure 6 As shown, when a high-voltage stress is applied in the off-state, the power device under test (DUT) is turned off, and the auxiliary switch... Turn off (or close the auxiliary switch) to maintain the threshold voltage measurement connection. Auxiliary capacitor reset switch Close, so that the DC high voltage source A continuous pressure is applied across the drain and source terminals of the power switching device under test (DUT). like Figure 7 As shown, when a half-open stress is applied, the threshold voltage measurement is maintained by the connected switch. Auxiliary capacitor reset switch Close, control the upper tube switch Turn on and adjust the gate-source voltage of the power switching device under test (DUT). This allows it to operate in the saturation region, generating constant power loss.

[0052] For different failure mechanisms (such as electrothermal fatigue, gate oxide damage, avalanche breakdown, etc.), through , , Different combinations of DUT operations are used to construct corresponding circuit topologies and voltage / current conditions. Hard switching mode is used to examine the temperature rise caused by switching losses; short-circuit mode is used to examine extreme current surges; high-voltage mode is used to examine ion migration caused by electric fields; and half-on mode is used to examine thermal degradation under high power density.

[0053] The solution provided by the invention can flexibly simulate various working conditions and fault conditions that may occur in actual applications, making the test results more valuable and comprehensive.

[0054] The working principle and technical effect of the above technical solution are as follows: The short-circuit switch is opened, allowing the load inductor to connect to the main circuit, while maintaining the threshold voltage measurement connection switch and the auxiliary capacitor reset switch closed, thus constructing a complete main current path; a stable inductor current is established through the action of the auxiliary switch in conjunction with the upper-side switch, thereby controlling the DUT to perform hard switching conduction under rated voltage and current, achieving the application of hard switching stress; the short-circuit switch is closed, short-circuiting the load inductor and reducing the circuit load, while maintaining the threshold voltage measurement connection switch and the auxiliary capacitor reset switch closed; the upper-side switch is closed, allowing the DC high-voltage source to directly act on the drain and source terminals of the DUT. After the DUT conducts, a short-circuit current is generated. When the detected short-circuit current reaches a preset value... At the threshold, the DUT is quickly shut off to prevent damage from prolonged short circuits, thus applying hard-switching short-circuit stress. The DUT is controlled to be in the off state, and the auxiliary switch is selected to be off or closed according to the test requirements (when closed, it can help share the voltage and protect the DUT). At the same time, the threshold voltage measurement connection switch and the auxiliary capacitor reset switch are kept closed, so that the DC high voltage source is continuously applied to the drain and source terminals of the DUT, thus applying off-state high voltage stress. The threshold voltage measurement connection switch and the auxiliary capacitor reset switch are kept closed to ensure that the main current path is unobstructed. The upper transistor switch is controlled to open, and the gate-source voltage of the DUT is adjusted to make the DUT operate in the saturation region. At this time, the DUT generates constant power loss, thus achieving the application of half-open stress.

[0055] This invention addresses the technical problems of existing technologies, such as limited stress application modes, low stress application accuracy, inconvenient switching, and insufficient protection for the device under test (DUT). In existing technologies, most characterization methods can only apply a single type of stress, failing to meet the needs of different testing scenarios. Furthermore, during stress application, inaccurate timing of switching actions leads to large fluctuations in stress parameters, resulting in low application accuracy and a lack of effective protection mechanisms, which can easily damage the DUT. This method defines in detail the specific application methods for four core stress modes, covering the most commonly used stress types in the dynamic characteristic testing of power semiconductor devices, and meeting the requirements of different devices and different testing needs. Through precise timing control of each switching device by the signal and logic control unit, it ensures that the switching actions are synchronized and precise during the application of each stress mode, and that stress parameters (voltage, current, power) are stable, improving the accuracy and consistency of stress application. During the hard-switching short-circuit stress application process, a short-circuit current threshold detection and fast turn-off mechanism are added, effectively protecting the DUT and preventing damage due to prolonged short circuits, thus improving the safety and reliability of the testing process. Switching between different stress modes can be achieved simply by adjusting the switching actions, without the need for additional circuit structure adjustments, making switching convenient and efficient, and significantly improving the flexibility and efficiency of the test. Simultaneously, the application of each stress mode is coordinated with the state of the online measurement circuit matrix, ensuring seamless connection between stress application and subsequent parameter measurements.

[0056] In one embodiment of the present invention, before the stress application ends, the signal and logic control unit confirms that the stress application is complete and the power switch device under test (DUT) has entered the measurement conduction state. Control auxiliary capacitor reset switch When in the closed state, control the bypass auxiliary capacitor. Avoid the impact of voltage rise Measurement; The data acquisition channel of the trigger clamping circuit records the waveform data of V_{ds_on}.

[0057] In measurement hour, The closure of the circuit is crucial, ensuring strong grounding of the DUT source and preventing current shunting or voltage fluctuations in the measurement branch from affecting accuracy. When switching to microcurrent measurement, to prevent high voltage or large signal interference with the microammeter, the main circuit connection is first disconnected. Disconnect and then reconnect the measuring meter. The "Break-Before-Make" strategy (closed).

[0058] By employing the solution provided by the invention, and through precise timing control, smooth switching between different measurement modes is ensured, circuit damage is avoided, and the purity of weak signal measurements is guaranteed.

[0059] The working principle and technical effect of the above technical solution are as follows: Before the stress application ends, the signal and logic control unit first confirms the test status to ensure that the stress application has been completed according to the preset parameters and that the DUT has entered the measurement conduction state (i.e., the DUT is in a stable conduction state without abnormal conduction or turn-off phenomena); then, the auxiliary capacitor reset switch is controlled to be in the closed state, at which time the auxiliary capacitor is short-circuited to achieve reset, and at the same time, in conjunction with the threshold voltage measurement access switch, the main current path from the source of the DUT to ground is constructed to ensure the stable transmission of conduction current; at the same time, the bypass auxiliary capacitor is controlled to avoid voltage rise in the auxiliary capacitor during conduction, thereby avoiding interference of voltage rise on the measurement of the drain-source conduction voltage drop of the DUT; finally, the data acquisition channel of the clamping circuit is triggered, so that the clamping circuit starts to sample the conduction voltage drop Vds_on across the drain and source of the DUT in real time and records its waveform data.

[0060] This solution addresses the technical problems of insufficient preparation, significant measurement interference, and low accuracy in existing on-resistance measurement technologies. Existing technologies often perform on-resistance measurement directly after stress application without confirming and optimizing the DUT state and measurement circuit. This leads to DUT instability, residual voltage in the auxiliary capacitor, and voltage rise, interfering with the measurement results and increasing measurement errors. This solution ensures the DUT is in a stable on-state before stress application ends, avoiding measurement errors caused by DUT anomalies. The closed auxiliary capacitor reset switch and bypass design effectively eliminate interference from residual voltage and voltage rise in the auxiliary capacitor, ensuring accurate sampling of the DUT drain-source on-state voltage drop. Pre-triggered clamping circuit data acquisition channels ensure the capture of the on-state voltage drop waveform within the transient window after stress application, avoiding measurement errors caused by acquisition delays and further improving the accuracy of dynamic on-resistance measurement. The entire preparation process is automatically completed under the control of the signal and logic control unit, requiring no manual intervention, simplifying the operation process while ensuring consistency and reliability of the preparation work.

[0061] In one embodiment of the present invention, S5 includes: confirm Measurement complete; the power switch device under test (DUT) is in the off state. Control threshold voltage measurement access switch Disconnect, disconnect the source of the power switching device under test (DUT) from the power source. Network connectivity; Delay Then, control the weak current monitoring switch. Close the circuit and connect the source of the power switching device under test (DUT) to the microcurrent measurement unit; Acquire the leakage current signal output by the microcurrent measurement unit; After the measurement is completed, control the weak current monitoring switch. Disconnect and close the threshold voltage measurement connection switch. and auxiliary capacitor reset switch Reset system.

[0062] The working principle and technical effect of the above technical solution are as follows: First, confirm that the threshold voltage measurement has been completed and the DUT is in a stable off-state (no conduction), avoiding interference from DUT conduction on leakage current measurement. Then, control the threshold voltage measurement access switch to open, disconnecting the DUT source from the auxiliary capacitor and the auxiliary capacitor reset switch, thus isolating the leakage current measurement circuit from the threshold voltage measurement circuit, preventing interference from residual voltage in the auxiliary capacitor and other factors. Next, perform a short delay to ensure the circuit switching is complete and the DUT state is stable, avoiding interference from transient signals generated during the switching process. After the delay, control the weak current monitoring switch to close, connecting the DUT source to the micro-current measurement unit. The micro-current measurement unit begins to acquire the off-state leakage current signal flowing through the DUT and transmits the signal to a high-precision oscilloscope. After leakage current acquisition is complete, control the weak current monitoring switch to open, disconnecting the leakage current measurement circuit. Simultaneously, close the threshold voltage measurement access switch and the auxiliary capacitor reset switch, resetting the online measurement circuit matrix to its initial state, preparing for the next test.

[0063] This invention solves the technical problems of high interference, low measurement accuracy, cumbersome circuit switching, and inability to reset after testing in existing technologies for shutdown leakage current measurement. In existing technologies, shutdown leakage current measurement is often not effectively isolated from other measurement circuits, resulting in interference from residual voltage of auxiliary capacitors, main current circuit signals, etc., which can cause leakage current measurement. Moreover, leakage current is a weak current (nA level), and interference factors can easily lead to distorted measurement results. At the same time, the circuit cannot be reset in time after the measurement, affecting the accuracy of the next test. This technical solution effectively isolates the leakage current measurement circuit from other circuits by disconnecting the threshold voltage measurement access switch, avoiding cross-interference and ensuring the purity of leakage current measurement. The short delay design ensures the stability of circuit switching, avoiding instantaneous signal interference during switching and further improving measurement accuracy. Precise control of the weak current monitoring switch enables flexible on / off switching of the leakage current measurement circuit, ensuring the timeliness and accuracy of leakage current acquisition. The circuit reset design after measurement restores the online measurement circuit matrix to its initial state, avoiding the influence of residual signals on the next test and ensuring test repeatability. The entire measurement process is logically rigorous and timing-precise, effectively improving the accuracy and reliability of turn-off leakage current measurement and meeting the high-precision measurement requirements of power semiconductor device turn-off leakage current.

[0064] One embodiment of the present invention further includes: Collected within the same period Data is presented as a set of state vectors; The trend of state vector change under different stress cycles was statistically analyzed, and the degradation of the package bond line was characterized by the change in on-resistance. Gate oxide layer damage was characterized by threshold voltage drift. Increased leakage current characterizes junction temperature rise or lattice defects.

[0065] By statistically analyzing a large amount of periodic test data, a mathematical relationship between the number of stresses and parameter degradation was established. Since damage to different physical structures has different effects on parameters (for example, bond wire breakage mainly increases resistance, while interface state increases mainly affect the threshold), the root cause of device failure can be deduced through joint analysis of multiple parameters.

[0066] The solution provided by the invention not only gives a conclusion on whether the device is "broken", but also provides a basis for device improvement by deeply analyzing "where it is broken" and "why it is broken" through multi-dimensional state vectors.

[0067] The working principle and technical effect of the above technical solution are as follows: Data on three main parameters—dynamic on-resistance, dynamic threshold voltage, and turn-off leakage current—collected within the same test cycle are integrated into a set of state vectors. This state vector comprehensively reflects the dynamic characteristics of the DUT under the current stress cycle number. Through repeated testing, multiple sets of state vectors are obtained under different stress cycle numbers, and the changing trends of these state vectors are statistically analyzed. Based on the correspondence between parameter changing trends and device degradation mechanisms, accurate characterization of device degradation is achieved: Changes in dynamic on-resistance characterize the degree of degradation of the DUT's package bonding wires (increased on-resistance indicates increased bonding wire contact resistance and accelerated degradation); drift in dynamic threshold voltage characterizes the degree of damage to the DUT's gate oxide layer (a larger threshold voltage drift indicates more severe gate oxide layer damage); and an increase in turn-off leakage current characterizes the degree of junction temperature rise or lattice defects in the DUT (increased leakage current indicates increased junction temperature or more lattice defects).

[0068] This invention addresses the technical problems of existing technologies, which can only measure parameters but cannot characterize device degradation, resulting in low utilization of test data. In existing technologies, most characterization methods can only collect and output measured values ​​of various parameters, but cannot analyze parameter change trends or correlate parameter changes with device degradation mechanisms, leading to low utilization of test data. This technical solution integrates multi-parameter data through the construction of state vectors, enabling multi-parameter linkage analysis and providing a more comprehensive and intuitive reflection of the dynamic characteristics of the device under test (DUT). By analyzing parameter change trends under different stress cycles, real-time monitoring of the DUT performance degradation process is achieved, allowing for timely detection of device degradation signs. Establishing a correspondence between parameter changes and device degradation mechanisms (bond line degradation, gate oxide damage, junction temperature rise, and lattice defects) enables precise characterization of device degradation. Without additional testing equipment, the internal damage state of the device can be determined through test data, significantly improving the utilization rate of test data. Simultaneously, this analysis method can improve the reliability design of power semiconductor devices, reduce the cost and difficulty of device reliability assessment, and expand the application scenarios of the entire characterization device and method, enabling not only dynamic parameter measurement but also precise assessment of device degradation.

[0069] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A device for comprehensive characterization of dynamic properties of power semiconductor devices, characterized in that, The device includes a multi-stress control and implementation circuit module and a multi-parameter data acquisition module; The multi-stress control and implementation circuit module is connected to the multi-parameter data acquisition module; The multi-stress control and implementation circuit module includes a signal and logic control unit, a multi-mode stress generation main circuit, and an online measurement circuit matrix. The signal and logic control unit is connected to the multi-mode stress generation main circuit and the online measurement circuit matrix, respectively, and the multi-mode stress generation main circuit is connected to the online measurement circuit matrix.

2. The device of claim 6, wherein The signal and logic control unit includes a host computer, an FPGA controller, and a driver interface circuit. The host computer is connected to the FPGA controller, and the FPGA controller is connected to the drive interface circuit; The drive interface circuit is provided with seven independent signal output ports, namely the first output port A1 to the seventh output port A7. Port A1 is connected to the short-circuit switch. The control terminal, port A2, is connected to the upper tube switch. The control terminal, port A3, is connected to the auxiliary switch. The control terminal, port A4 is connected to the gate drive circuit input terminal of the power switching device under test (DUT), and port A5 is connected to the threshold voltage measurement access switch. The control terminal, port A6, is connected to the auxiliary capacitor reset switch. The control terminal, port A7, is connected to the weak current monitoring switch. The control terminal.

3. The device of claim 6, wherein: The multi-mode stress generation main circuit includes a DC high-voltage source. Bus capacitor Load inductance Upper pipe switch Short circuit switch and auxiliary switch ; The DC high voltage source The positive terminal is connected to the bus capacitor. The positive terminal of the bus capacitor The negative terminal is connected to the main power circuit ground; The shorting switch is connected in parallel across the load inductance ​ The load inductor With the short-circuit switch A parallel network is formed, and the input terminal of the parallel network is connected to the bus capacitor. The positive terminal of the parallel network is connected to the upper tube switch. The drain electrode; The upper tube switch The source of the upper tube switch is connected to the drain of the power switch device under test (DUT). The auxiliary switch The drain of the auxiliary switch is connected to the drain of the power switch device under test DUT. The source of the auxiliary switch is connected to the main power loop ground, forming a parallel structure with the power switch device under test DUT. The source of the power device under test (DUT) is connected to the input terminal of the online measurement circuit matrix.

4. The device of claim 6, wherein, The on-line measurement circuit matrix comprises threshold voltage measurement access switches , auxiliary capacitor reset switches , weak current monitoring switches , auxiliary capacitors and clamping circuits and micro-current measurement units; The clamping circuit is connected in parallel between the drain and source of the power switching device under test (DUT); the clamping circuit samples and obtains the on-state voltage drop V1 across the source and drain terminals of the power switching device under test (DUT). The weak current monitoring switch One end is connected to the source of the power switching device under test (DUT), and the other end is connected to the microcurrent measurement unit. The threshold voltage measurement access switch One end is connected to the source of the power switch device under test (DUT), and the other end is connected to the auxiliary capacitor. One end and the auxiliary capacitor reset switch One end; The auxiliary capacitor The other end and the auxiliary capacitor reset switch The other end is connected to analog ground or main power loop ground; The auxiliary capacitor reset switch The threshold voltage measurement access switch is configured to be a dual-function switch that is closed during the on-resistance measurement and stress application phase A main current path from a source of the power switch device under test (DUT) to ground is constructed disconnected during the threshold voltage measurement phase, in cooperation with the threshold voltage measurement access switch A capacitance charging loop is constructed.

5. The device of claim 6, wherein the device is a power semiconductor device. The multi-parameter data acquisition module includes a current probe, a high-precision oscilloscope, and a data processing terminal. The current probe is sleeved on the main circuit connection line of the power switching device under test (DUT). The analog input channels of the high-precision oscilloscope are respectively connected to the output end of the current probe, the output end of the clamping circuit, the voltage measuring end of the auxiliary capacitor and the output end of the micro-current measuring unit. of the auxiliary capacitor and the output end of the micro-current measuring unit. The high-precision oscilloscope is connected to the data processing terminal.

6. A method for comprehensive characterization of dynamic characteristics of a power semiconductor device, characterized in that, The method includes: S1. Test parameters are set through the host computer, the signal and logic control unit generates initialization control signals, configures the online measurement circuit matrix, and controls the power switch device under test (DUT) to be in the test state. S2. According to the set stress mode, the signal and logic control unit generates a timing drive signal to control the operation of the multi-mode stress generation main circuit and apply preset electrical or thermal stress to the power switching device DUT under test. S3, in a certain conduction window after the stress application ends, the drain-source voltage of the power switch device DUT under test is collected by a clamping circuit, the drain current is collected by a current probe, and the dynamic on-resistance is calculated by a data processing terminal ; S4. Control the power device under test (DUT) to enter the off state, configure the online measurement circuit matrix to construct a capacitor charging loop, and use a specific current to charge the auxiliary capacitor. During charging, the source voltage variation curve of the power switching device under test (DUT) is acquired, and the dynamic threshold voltage is extracted. ; S5. After the threshold voltage measurement is completed, configure the online measurement circuit matrix to connect the source of the power switch device under test (DUT) to the micro-current measurement unit and collect the turn-off leakage current flowing through the DUT. .

7. The method of claim 6, wherein the dynamic characteristics of the power semiconductor device are comprehensively characterized by: S2 includes: control shorting switch open, maintaining threshold voltage measurement access switch auxiliary capacitance reset switch closed; By auxiliary switch Cooperating with the tube switch Establishes inductance current, controls the hard switch conduction of the power switch device DUT under the rated voltage and current; When a hard switch short-circuit stress is applied, the short-circuit switch is controlled. Close, maintain threshold voltage measurement access switch Auxiliary capacitor reset switch closure; Controlling the on-pipe switch closing, a direct current high voltage source directly acting on the power switch device under test (DUT) and quickly turning off the power switch device under test (DUT) after detecting that the short-circuit current reaches a threshold value; When a high-voltage off-state stress is applied, the power under test (DUT) is turned off, and the auxiliary switch... Turn off and maintain threshold voltage measurement connection switch Auxiliary capacitor reset switch Close, so that the DC high voltage source A continuous pressure is applied across the drain and source terminals of the power switching device under test (DUT). When a half-open stress is applied, the threshold voltage measurement is maintained at the switch. Auxiliary capacitor reset switch Close, control the upper pipe switch Turn on and adjust the gate-source voltage of the power switching device under test (DUT). This allows it to operate in the saturation region, generating constant power loss.

8. The method of claim 6, wherein the dynamic characteristics of the power semiconductor device are comprehensively characterized by: Before the stress application ends, the signal and logic control unit confirms that the stress application is complete and the power switch device under test (DUT) has entered the measurement conduction state. Control auxiliary capacitor reset switch In the closed state, control bypass auxiliary capacitor ; The data acquisition channel of the trigger clamping circuit records the waveform data of V_{ds_on}.

9. The method of claim 6, wherein the method further comprises: S5 includes: acknowledgement The measurement has been completed and the power switching device under test (DUT) is in an off state. Controlling threshold voltage measurement access switch turning off, disconnecting the source of the power switch device under test (DUT) from the network connection; time delay After the time delay is closed, the source of the power switch device under test (DUT) is connected to the micro-current measurement unit. Acquire the leakage current signal output by the microcurrent measurement unit; After the measurement is complete, the weak current monitoring switch is opened, the threshold voltage measurement access switch is closed and the auxiliary capacitor reset switch resets the system.

10. The method of claim 6, wherein the method further comprises: Also includes: Collected within the same period Data is presented as a set of state vectors; The trend of state vector change under different stress cycles was statistically analyzed, and the degradation of the package bond line was characterized by the change in on-resistance. Gate oxide layer damage was characterized by threshold voltage drift. Increased leakage current characterizes junction temperature rise or lattice defects.

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