PCBA carrier board test system and method for embodied intelligence controller

Abstract

This specification provides a PCBA carrier board testing system and method for embodied intelligent controllers. The PCBA carrier board testing system for embodied intelligent controllers uses an independent module signal conversion module to bridge the physical connection between high-value NVIDIA modules and the PCBA carrier board under test via a low-cost conversion board. This transfers the wear risk caused by repeated plugging and unplugging to the conversion board interface, significantly reducing consumable costs in mass production testing. Simultaneously, the one-to-one lossless conversion ensures signal integrity and test accuracy. Through the collaborative work of the host computer test control module, high-precision data acquisition module, and dedicated tooling positioning and clamping module, a fully automated closed-loop test is achieved from command issuance and data acquisition to result determination. This avoids the inefficiency and errors of manual item-by-item verification, effectively improving test efficiency.

Description

Technical Field

[0001] This specification relates to the field of device hardware testing, and in particular to a PCBA carrier board testing system for a smart controller. Background Technology

[0002] Traditional PCBA carrier board functional testing fixtures are structured around a dedicated carrier board, a fixed bed of pins, custom wiring harnesses, and a host computer with fixed test scripts. They verify the presence of cold solder joints, open circuits, short circuits, or functional abnormalities in the PCBA through mechanical positioning and clamping, and point-to-point electrical connections. However, for highly dense, small-sized, and multifunctional PCBA carrier boards such as embodied intelligent controllers, existing technologies have the following drawbacks: Under the testing requirements of high-density, high-frequency, high-speed, and multi-interface dynamic loads, traditional bed-of-pin ICT fixtures are costly, have long lead times, and lack flexibility, making them unsuitable for rapid iteration across multiple models. Furthermore, the inability to insert probes under BGA / LGA and high-speed differential lines results in low test coverage, and uncontrollable contact force can easily damage components. While flying probe testing eliminates the need for fixtures, it is slow and lacks parallelism, failing to meet mass production cycle requirements. Traditional FCT functional testing involves long development cycles for customized fixtures, difficulties in switching between multiple models, and can only perform static or quasi-dynamic verification, making it difficult to simulate the dynamic load in real robot motion. Moreover, the data is discrete and lacks traceability, failing to meet the requirements of Industry 4.0 and reliability closed-loop systems. AOI / AXI optical or X-ray inspection cannot test electrical performance, timing, and signal integrity. In addition, in existing testing solutions, core high-value modules such as NVIDIA modules need to be repeatedly plugged and unplugged directly to the PCBA carrier board under test, which can easily lead to wear and tear on the module interface, significantly increasing testing costs. At the same time, the testing process lacks real-time anomaly monitoring and protection, and the test board or testing equipment can easily burn out in the event of short circuits, overcurrent, or other faults. Test data only stores the final results, lacking full-link traceability capabilities for raw data and process data, failing to meet the quality inspection requirements of embodied intelligent devices for high reliability, high consistency, and traceability.

[0003] Therefore, a better solution is urgently needed. Summary of the Invention

[0004] In view of this, embodiments of this specification provide a PCBA carrier board testing system for embodied intelligent controllers to address the technical deficiencies existing in the prior art.

[0005] According to a first aspect of the embodiments of this specification, a PCBA carrier board testing system for an embodied intelligent controller is provided, comprising: The host computer test management module is used to receive user configuration instructions and store standard parameters, generate standardized test instruction data packets and send them out; The module signal conversion module communicates with the host computer test and control module and is used for electrical connection with the PCBA carrier board under test. The module signal conversion module receives standardized test command data packets and outputs test commands to the PCBA carrier board under test, simulating the working state of the intelligent device. The high-precision data acquisition module has a data acquisition end that is directly connected to the functional interface of the PCBA carrier board under test, and a data output end that is connected to the host computer test and control module. It is used to synchronously acquire the raw running data generated by the PCBA carrier board under test after responding to the test command in real time, and after preprocessing, generate a valid acquisition data packet and upload it to the host computer test and control module. The dedicated tooling positioning and clamping module is used to physically position and clamp the PCBA carrier board under test, and to achieve physical connection and electrical conduction between the PCBA carrier board under test and the module signal conversion module and the high-precision data acquisition module. The real-time anomaly monitoring and protection module is connected in parallel to the test circuit of the PCBA carrier board under test. It is used to monitor the circuit status in real time, trigger protection when an anomaly is detected, and generate a status monitoring data packet to be uploaded to the host computer test management module. The results output and storage module is connected to the host computer test management module. It is used to receive and store the final test result data packet generated by the host computer test management module and to visualize the test results. The host computer test management module is also used to receive valid data acquisition data packets and status monitoring data packets, compare and analyze them with built-in standard parameters, and generate the final test result data packet.

[0006] In one possible implementation, the host computer test management module has a built-in embodied intelligent dedicated test algorithm model, which includes a dynamic difference judgment algorithm, a timing response judgment algorithm, and a multiple fluctuation stability judgment algorithm, used to judge the signal delay, dynamic response consistency, and multiple interaction stability of the PCBA carrier board under test.

[0007] In one possible implementation, the module signal conversion module is an independent conversion board. The upper layer of the conversion board has a first interface for connecting to the NVIDIA module, and the lower layer has a second interface for connecting to the PCBA carrier board under test. The conversion board converts all signals from the first interface and the second interface one-to-one, realizing signal bridging between the NVIDIA module and the PCBA carrier board under test.

[0008] In one possible implementation, the raw operating data acquired by the high-precision data acquisition module includes network port data, USB interface data, M.2 interface data, CAN bus data, UART serial port data, SPI interface data, I2C interface data, GPIO interface data, SD card data, fan data, and camera data; preprocessing includes removing invalid data caused by environmental interference and contact errors.

[0009] In one possible implementation, the loop status monitored by the real-time anomaly monitoring and protection module includes overvoltage, overcurrent, short circuit, signal anomaly, and data interruption; the trigger protection includes immediate triggering of hardware power-off protection and synchronously uploading anomaly alarm data and fault location information to the host computer test and control module.

[0010] In one possible implementation, the results output and storage module stores data including all raw test data, process data, analysis results, and fault logs, supporting full-process traceability of a single test data item; and visualizes the test progress, real-time parameters, and pass / fail judgment results on a display screen.

[0011] According to a first aspect of the embodiments of this specification, a PCBA carrier board testing method for an embodied intelligent controller applied to the above-described system is provided, comprising: The host computer test and control module initializes the system, generates standardized test instruction data packets based on the parameters of the PCBA carrier board under test entered by the user and the built-in standard database, and sends them to the module signal conversion module. The module signal conversion module receives and parses standardized test instruction data packets, simulates the dynamic working state of the embodied intelligent device, and outputs test instructions for each interface to the PCBA carrier board under test that is clamped and fixed on the special tooling positioning clamping module. The high-precision data acquisition module synchronously acquires all raw operating data generated by the PCBA carrier board under test after responding to the test command in real time, and generates a valid acquisition data packet after preprocessing; at the same time, the real-time anomaly monitoring and protection module synchronously acquires the status data of the test circuit and generates a status monitoring data packet. The host computer test management module receives valid data acquisition data and status monitoring data, retrieves built-in standard parameters for comparison and analysis, and generates a final test result data package containing test items, real-time parameters, standard parameters, differences, and pass / fail status. The host computer test management module transmits the final test result data packet to the result output and storage module for data solidification, storage, and visualization.

[0012] In one possible implementation, when the module signal adapter outputs test commands to the PCBA carrier board under test, it transmits all 699 pins of the NVIDIA module one-to-one without loss through the module signal adapter, thereby achieving signal bridging between the NVIDIA module and the PCBA carrier board under test.

[0013] In one possible implementation, after the high-precision data acquisition module synchronously acquires the raw operating data in real time, it also includes time-series binding and data alignment preprocessing of the acquired multi-channel data, binding the equipment operating data and the loop status data in a one-to-one time sequence correspondence.

[0014] In one possible implementation, when the host computer test management module performs comparative analysis, it calls the built-in intelligent dedicated test algorithm model to perform dynamic difference judgment, timing response judgment, and multiple fluctuation stability judgment on the PCBA carrier board under test. When the result output and storage module performs data solidification storage, it archives the original data, process data, operating parameters, and fault logs of a single test in the entire chain, supporting full-process traceability of test data.

[0015] This application bridges the physical connection between high-value NVIDIA modules and the PCBA carrier board under test by setting up an independent module signal conversion module. This low-cost conversion board transfers the wear risk caused by repeated plugging and unplugging to the conversion board interface, significantly reducing consumable costs in mass production testing. Simultaneously, the one-to-one lossless conversion ensures signal integrity and test accuracy. Through the collaborative work of the host computer test management module, high-precision data acquisition module, and dedicated tooling positioning and clamping module, a fully automated closed-loop test is achieved from command issuance and data acquisition to result judgment. This avoids the inefficiency and errors of manual item-by-item verification, effectively... It improves testing efficiency; through the hardware-level rapid power-off protection of the real-time anomaly monitoring and protection module, it can immediately cut off the power supply and report the fault location when anomalies such as overvoltage, overcurrent, and short circuit are detected, which not only protects the board under test and the test equipment, but also provides a basis for rapid fault location; through the result output and storage module, it realizes the complete traceability of single test data by storing and visualizing the entire chain of test raw data, process data, and analysis results, which provides reliable data support for quality improvement and process optimization, and fully meets the testing needs of the PCBA carrier board of the intelligent controller for high density, high dynamics, high reliability, and rapid iteration of multiple models. Attached Figure Description

[0016] Figure 1 This is a system schematic diagram of a PCBA carrier board testing system for an embodied intelligent controller, provided in one embodiment of this specification. Figure 2 This is a flowchart of a PCBA carrier board testing method for an embodied intelligent controller, provided in one embodiment of this specification. Detailed Implementation

[0017] Many specific details are set forth in the following description to provide a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this specification. Therefore, this specification is not limited to the specific implementations disclosed below.

[0018] The terminology used in one or more embodiments of this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this specification. The singular forms “a” and “the” as used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0019] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this specification, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0020] This specification provides a PCBA carrier board testing system for embodied intelligent controllers, which will be described in detail in the following embodiments.

[0021] See Figure 1 , Figure 1This diagram illustrates a system schematic of a PCBA carrier board testing system for an embodied intelligent controller according to an embodiment of this specification. Specifically, it includes a host computer test management module for receiving user configuration commands and storing standard parameters, generating standardized test command data packets and issuing them; a module signal conversion module, communicatively connected to the host computer test management module and electrically connected to the PCBA carrier board under test (DUT), receiving standardized test command data packets, simulating the working state of an embodied intelligent device, and outputting test commands to the DUT; and a high-precision data acquisition module, with its acquisition end directly connected to the functional interface of the DUT and its data output end connected to the host computer test management module, for real-time synchronous acquisition of the raw operating data generated by the DUT after responding to test commands, preprocessing it to generate valid acquisition data packets, and... The test module uploads data to the host computer's test and control module. A dedicated tooling positioning and clamping module is used for the physical positioning and clamping of the PCBA carrier board under test, and for physical connection and electrical conduction between the PCBA carrier board under test, the module signal conversion module, and the high-precision data acquisition module. A real-time anomaly monitoring and protection module is connected in parallel to the test circuit of the PCBA carrier board under test. It monitors the circuit status in real time, triggers protection when an anomaly is detected, and generates a status monitoring data packet, which is then uploaded to the host computer's test and control module. A result output and storage module is connected to the host computer's test and control module. It receives and stores the final test result data packet generated by the host computer's test and control module and visualizes the test results. The host computer's test and control module also receives valid acquisition data packets and status monitoring data packets, compares and analyzes them with built-in standard parameters, and generates the final test result data packet.

[0022] The host computer test management module refers to the central control center and human-machine interface unit of the entire test system. It typically runs on a general-purpose Windows operating system computer, which communicates bidirectionally with other modules in the system via Gigabit Ethernet. This module is responsible for receiving configuration information input by the operator, such as the model of the PCBA carrier under test, test item selection, and standard thresholds. It internally stores a pre-established standard test parameter library and can generate standardized test instruction data packets based on the configuration. User configuration instructions refer to the test requirements set by the operator through a graphical interface or configuration file, such as selecting to test the Gigabit Ethernet port function or setting the acceptable range of signal amplitude. Standard parameters refer to the benchmark data pre-stored in the system that characterizes the electrical performance, signal timing, and response characteristics that the various functional interfaces of the PCBA carrier under test should achieve when working normally. Standardized test instruction data packets refer to a set of instructions that have been formatted uniformly, have a verification mechanism, and can be correctly parsed by downstream modules. These instructions include information such as test type, test stimulus parameters, and expected response values.

[0023] The module signal conversion module is an independent printed circuit board assembly that acts as a signal bridge between the actual NVIDIA high-performance computing module and the PCBA carrier board under test. The module has a high-density male connector on the upper layer for connecting to the NVIDIA module and a corresponding female connector on the lower layer for connecting to the PCBA carrier board. Internal wiring between the two interfaces enables a one-to-one physical conversion of all 699 signals. Simulating the working state of the embodied intelligent device refers to the module's response to test commands from the host computer. It drives the fixed NVIDIA module to generate corresponding test stimulus signals based on the actual operating parameters of the embodied intelligent device (such as processor load, interface communication rate, and task switching frequency), and outputs these signals to the PCBA carrier board.

[0024] A high-precision data acquisition module refers to one or more sets of data acquisition hardware with synchronous triggering and anti-interference capabilities. Its acquisition end is directly connected to each functional interface of the PCBA carrier board under test via a dedicated wiring harness or probe array. Real-time synchronous acquisition means that the module can simultaneously capture signals from all interfaces of the PCBA carrier board under test under a unified clock reference, ensuring that the time correspondence between data from different interfaces is preserved. Raw operating data includes unprocessed signals such as voltage waveforms, data packet content, communication handshake status, and interrupt response timings from each interface. Preprocessing refers to operations such as filtering and denoising, removing invalid data, and unit conversion on the acquired raw data to make it a valid data packet that is easy for the host computer to analyze.

[0025] The dedicated fixture positioning and clamping module is a mechanical structural unit. Internally, it features positioning pins, a clamping mechanism, and an insulating base that precisely match the contour of the PCBA carrier board under test. Physical positioning and clamping refers to the operator placing the PCBA carrier board under test in the predetermined position on the fixture and then manually or pneumatically activating the clamping device to firmly fix the carrier board in place. The repeatability of each placement is accurate to the micrometer level. Physical connection and electrical continuity refer to the spring probes or conductive strips integrated within the fixture establishing a reliable electrical connection with the test contacts on the carrier board under the clamping force. Simultaneously, the other ends of these probes are connected via wiring harnesses to the corresponding terminals of the module signal conversion module and data acquisition module.

[0026] The real-time anomaly monitoring and protection module is an independent hardware circuit unit, typically composed of a current / voltage monitoring chip, a fast comparator, and a solid-state relay. Parallel connection to the test circuit means that the module's monitoring terminal is connected across the power supply and signal lines of the PCBA under test, without affecting the main circuit operation but continuously sensing voltage and current values. Triggered protection includes cutting off the power supply path and sending an interrupt signal to the system within microseconds when anomalies such as overvoltage, overcurrent, or short circuit are detected. Simultaneously, the circuit number where the anomaly occurred and the fault parameters are packaged into a status monitoring data packet.

[0027] The results output and storage module includes a local solid-state drive and a touch screen. Receiving and storing the final test result data packet means that this module saves each test record from the host computer in a structured file format in the built-in storage, supporting subsequent querying and export. Visualizing the test results means that the display screen shows, in real-time, information such as the name of the current test item, measured value, judgment conclusion, and overall pass rate through tables, graphs, or red / green indicator lights.

[0028] The present invention will be further described below through a detailed embodiment: In this embodiment, a batch of 100 PCBA carrier boards for embodied intelligent robot controllers needs to undergo full-function testing before leaving the factory. The PCBA carrier board integrates Gigabit Ethernet, USB 3.2, M.2 solid-state drive interface, MIPI CSI camera interface, two CAN buses, four UART serial ports, and multiple GPIO ports.

[0029] The testing system operates as follows: First, the operator places the PCBA carrier board under test into the positioning slot of the dedicated fixture positioning and clamping module, and activates the pneumatic clamping mechanism to firmly press the carrier board. At this time, the spring probe array inside the fixture simultaneously contacts all functional test points on the carrier board and completes electrical connection with the lower socket of the module signal conversion module and each acquisition channel of the high-precision data acquisition module. The operator selects the "Full Function Test" scheme on the interface of the host computer test management module, enters the serial number range for this batch, and clicks "Start Test." The host computer test management module (a Windows workstation with customized test software installed) reads the threshold values ​​matching the model from the internally stored standard parameter library (such as gigabit network packet loss rate less than 0.001%, CAN bus baud rate error less than ±0.5%, GPIO response time less than 10 microseconds, etc.), generates a standardized test command data packet containing 28 test instructions, and simultaneously sends it to the module signal conversion module and the dedicated fixture positioning and clamping module (the latter is only used to confirm the fixture status) via gigabit Ethernet.

[0030] Upon receiving the command, the module signal adapter runs a dedicated test firmware program via its fixed NVIDIA module. This program simulates the typical operating conditions of an embodied intelligent robot simultaneously processing visual data and motor control commands during its movement: generating GPIO toggle signals at a frequency of 1000Hz, sending periodic data frames to the CAN bus at a rate of 500kbps, and injecting simulated point cloud data streams into the network port at gigabit bandwidth. These test stimuli are transmitted losslessly to the PCBA carrier board under test through the 699 signal channels of the module signal adapter board, triggering various interface circuits on the carrier board to generate response signals.

[0031] Simultaneously, the high-precision data acquisition module initiates synchronous acquisition across all channels. Internally, this module shares a high-precision crystal oscillator and trigger controller, ensuring that all acquisition channels begin recording data at the same moment the test starts. For example, when testing a gigabit Ethernet port, the acquisition module not only records the content of the Ethernet frames emitted by the port but also synchronously records the timestamps of the corresponding GPIO interrupt signals for analyzing interrupt response latency. The acquired raw data undergoes moving average filtering and outlier removal via the module's internal field-programmable gate array (FPGA), is packaged into valid acquisition data packets, and rapidly uploaded to the host computer via the PCIe bus.

[0032] Throughout the testing process, the real-time anomaly monitoring and protection module continuously monitors the power supply current of the PCBA carrier board under test. When a capacitor breakdown on the carrier board causes the current to suddenly exceed a preset threshold, the module cuts off the power supply within 5 microseconds, records the voltage drop waveform and loop identification at the time of the fault, and generates a status monitoring data packet containing "Overcurrent Alarm, Fault Location: VDD_5V" which is then sent to the host computer. The host computer immediately stops the testing process and issues an alarm on the interface.

[0033] For normal testing procedures without any anomalies, the host computer test management module receives all valid data acquisition packets and status monitoring packets, and then compares them one by one with the standard parameters: whether the actual network port throughput meets the standard, whether the CRC check of each frame of the CAN bus passes, and whether the GPIO edge transition time is within the tolerance range. Finally, a test result data packet containing all 28 test sub-items is generated, and each sub-item records the measured value, standard value, deviation, and pass / fail judgment.

[0034] The result data packet is sent to the result output and storage module. This module writes the original waveform file, intermediate data, final judgment result, operator information, timestamp, etc., to the built-in solid-state drive, forming a traceable record. Simultaneously, the overall conclusion is displayed on the touchscreen with a green "pass" or red "fail" icon, and users can click to view detailed waveforms for each item. After the test, the operator can export the test reports for all 100 chips via the USB port.

[0035] The beneficial effects of this embodiment include at least the following: by designing an independent module signal adapter, the high-value NVIDIA module is physically isolated from the test board, so that insertion and removal wear only occurs on the low-cost adapter board, significantly reducing the cost of consumable replacement in batch testing; through centralized scheduling by the host computer and a fully automated testing process, the operational errors and inefficiencies of manual item-by-item verification are eliminated, and the full-function testing time of the entire board is shortened; through real-time anomaly monitoring and protection module hardware-level rapid power-off, the test equipment is prevented from burning out due to short circuit failure of a single board or damaging other boards under test, significantly improving the safety of production line testing; through the full data retention of the result output and storage module, the traceability of test data is realized, providing a complete basis for quality analysis and process improvement.

[0036] In one possible implementation, the host computer test management module has a built-in embodied intelligent dedicated test algorithm model, which includes a dynamic difference judgment algorithm, a timing response judgment algorithm, and a multiple fluctuation stability judgment algorithm, used to judge the signal delay, dynamic response consistency, and multiple interaction stability of the PCBA carrier board under test.

[0037] The host computer test management module has been described in detail in the corresponding embodiments and will not be repeated here. The embodied intelligence-specific test algorithm model refers to a set of judgment logic specifically designed for the dynamic, real-time, and interactive characteristics unique to embodied intelligent controllers in actual operation, differing from the simple model in traditional PCBA testing that only compares static parameters at fixed thresholds. This model is embedded in the software of the host computer test management module, serving as the core computational unit for the comparison and analysis steps.

[0038] Dynamic difference judgment algorithm refers to a method that dynamically evaluates the difference between the measured signal and the standard signal according to the time series. Traditional static difference judgment only compares whether the numerical difference at a single time point is within a fixed window, while dynamic difference algorithm calculates the integral, rate of change, and overshoot of the difference over a period of time to determine whether the performance of the test board in the transient response process meets the requirements of the embodied intelligent device for fast tracking.

[0039] Timing response determination algorithms refer to methods for accurately measuring the time relationship between excitation and response signals. Embodied intelligent controllers need to process large amounts of real-time data from sensors and rapidly output control commands; therefore, the signal synchronization and response delay between interfaces directly affect the closed-loop performance of the system. This algorithm calculates the end-to-end delay by comparing the transmission timestamp of the input command with the arrival timestamp of the corresponding output signal, and compares it with the maximum allowable delay specified in the standard model.

[0040] The multiple fluctuation stability determination algorithm refers to evaluating the consistency degree of the response signal of the test carrier board under the condition of repeatedly applying the same excitation. Embodied intelligent devices often need to maintain stable performance during long-term operation, and any intermittent jitter or drift may lead to unstable motion control. This algorithm judges whether there is a hidden instability fault by statistically analyzing the variance, range, and drift trend of the same parameter in multiple consecutive tests.

[0041] Signal delay, dynamic response consistency, and multiple interaction stability refer to the three core indicators for evaluating the performance of an embodied intelligent controller. Signal delay refers to the time interval from the excitation being sent to the response appearing; dynamic response consistency refers to the ability of the carrier board to maintain the same shape and amplitude of the output signal under different loads, different temperatures, or different voltages; multiple interaction stability refers to the degree of difference between the responses of the carrier board in repeatedly executing the same operation sequence.

[0042] The following further introduces the present invention through a detailed embodiment, and this embodiment can be mutually referred to with the system embodiment described previously.

[0043] Continuing with the system architecture described above, when testing a batch of PCBA carrier boards for humanoid robot joint controllers, the carrier board needs to process analog signals from torque sensors in real time and output PWM control signals to the motor driver at a rate of 1 kHz. The upper computer test control and management module of this system incorporates an exclusive test algorithm model for embodied intelligence.

[0044] During the test, the module signal transfer module drives the NVIDIA module to send a set of continuously changing digital control instruction sequences to the SPI interface of the test carrier board, and this sequence simulates the complete motion curve of the robot joint accelerating from rest to the maximum speed and then decelerating to a stop. At the same time, the high-precision data acquisition module synchronously acquires the waveform of the PWM output pin of the test carrier board and the feedback data of the SPI interface at a sampling rate of 10 kHz. The acquired raw data is uploaded to the upper computer.

[0045] The upper computer first calls the dynamic difference determination algorithm. This algorithm reads the standard motion curve parameters (including the reference sequence of the expected PWM duty cycle changing with time), subtracts the measured PWM duty cycle sequence from the reference sequence point by point to obtain a difference sequence. The algorithm further calculates the root mean square error, maximum absolute error, and the rise time and settling time of the error of this difference sequence. If the root mean square error is less than a preset threshold (such as 2% of the full scale) and the settling time is less than a specified number of cycles (such as 5 control cycles), then this dynamic difference test is determined to be qualified. This ensures that the test carrier board can accurately follow under rapidly changing instructions without obvious lag or overshoot.

[0046] Next, the timing response judgment algorithm is invoked. This algorithm analyzes the time difference between the falling edge of the chip select signal of the SPI interface sending command and the edge of the PWM output signal of the board under test. The test system embeds a timestamp accurate to the nanosecond level in the excitation data packet, and the acquisition module also records the local timestamp when capturing the PWM edge. The host computer subtracts the two timestamps to obtain the actual response delay. The algorithm statistically analyzes the delay data of 1000 consecutive command-response pairs, calculating the average delay and the maximum delay. If the average delay is lower than the standard specified value (e.g., 2 microseconds) and the maximum delay does not exceed 1.5 times the average value, the timing response is deemed qualified. This verifies the real-time response capability of the board when handling high-frequency periodic tasks.

[0047] Finally, the stability assessment algorithm for multiple fluctuations is invoked. The entire dynamic testing process described above is repeated 50 times, with the same time interval between each execution. The algorithm extracts the root mean square error and average delay, two core indicators calculated in each execution, forming two time series of length 50. The algorithm calculates the coefficient of variation (standard deviation divided by mean) for each series and uses a sliding window method to detect the presence of trend drift (e.g., the error value monotonically increases with the number of tests). If the coefficient of variation is less than a preset value (e.g., 5%) and there is no obvious monotonic trend, and the difference between two adjacent test results does not exceed a threshold, then the stability of the multiple interactions is deemed satisfactory.

[0048] Based on the above three criteria, the host computer generates a final "qualified" result only when the dynamic difference, timing response, and stability under multiple fluctuations are all satisfactory; otherwise, specific unqualified items are marked. For example, a test board may pass all static parameter tests, but the dynamic difference algorithm may find that its PWM duty cycle rising edge has excessive overshoot (exceeding the standard value of 8%). Although the static duty cycle accuracy of the board is satisfactory, it is deemed unqualified because its dynamic characteristics do not meet the requirements of intelligent control.

[0049] The beneficial effects of this embodiment include at least the following: by introducing dynamic difference, timing response, and multiple fluctuation stability judgment algorithms specifically designed for embodied intelligent controllers, it overcomes the shortcomings of traditional static threshold testing in failing to identify dynamic latent faults; it can accurately capture key issues affecting robot motion control performance such as signal delay fluctuations, transient response overshoot, and long-term operation drift, significantly reducing the false negative rate; at the same time, the built-in algorithm model realizes the unification and automation of judgment standards, avoiding inconsistencies caused by differences in experience in manual judgment, and providing test assurance for the quality control of embodied intelligent controllers that directly corresponds to the end application scenario.

[0050] In one possible implementation, the module signal conversion module is an independent conversion board. The upper layer of the conversion board has a first interface for connecting to the NVIDIA module, and the lower layer has a second interface for connecting to the PCBA carrier board under test. The conversion board converts all signals from the first interface and the second interface one-to-one, realizing signal bridging between the NVIDIA module and the PCBA carrier board under test.

[0051] The module signal conversion module has been preliminarily introduced in the corresponding embodiment. This embodiment further defines its physical structure and signal connection method. The independent conversion board refers to a printed circuit board assembly that has no fixed dependence on the NVIDIA module and the PCBA carrier board under test. Its size, number of layers, impedance control and other parameters are specially designed according to signal integrity requirements.

[0052] The first interface is typically a high-density board-to-board male connector whose pin arrangement, spacing, and contact type are perfectly matched to the female connector on the NVIDIA module. The second interface is a female connector corresponding to the first interface, whose pin definitions are completely consistent with the female connector of the module mounting interface reserved on the PCBA carrier. A one-to-one adapter refers to a direct electrical connection between each signal pin of the first interface and the corresponding pin of the second interface through the internal traces of the adapter board, without adding any active devices (such as buffers, level shifters) or logic processing units, and without changing the signal transmission direction or signal type. Signal bridging refers to physically forming a continuous conductive path from the pin of the NVIDIA module, through the adapter board, and finally to the corresponding pin of the PCBA carrier under test, allowing signal interaction between the NVIDIA module and the carrier under test as if directly plugged in.

[0053] The present invention will be further described below through a detailed embodiment, which can be referred to in conjunction with the system embodiment described above.

[0054] In this test system, a real NVIDIA Jetson Orin module serves as the test stimulus source and control core, with a female connector with 699 pins at its bottom. Traditional direct testing involves inserting the module directly into the corresponding male connector on the PCBA substrate under test, requiring a plug-in / plug-out operation for each substrate tested. Based on the connector's design lifespan, its reliable plug-in / plug-out cycles are typically around 50. However, mass production testing often requires testing hundreds or even thousands of substrates, meaning the module's connector will quickly wear out and become unusable, while the module itself is worth thousands of RMB.

[0055] To address this issue, this system employs a modular signal adapter module. This module is an eight-layer printed circuit board, approximately 2.5 mm thick, with impedance-matched copper traces. A male connector (i.e., the first interface) matching the NVIDIA module's female connector is soldered to the top surface of the adapter board. Each pin of this male connector mates with a corresponding pin on the NVIDIA module. A female connector (i.e., the second interface) matching the male connector on the PCBA under test is soldered to the bottom surface of the adapter board. The internal traces of each layer of the adapter board connect a pin of the first interface on the top surface vertically or via a short trace to the same signal pin of the second interface on the bottom surface.

[0056] For example, for differential high-speed signal pairs (such as PCIe TX differential pairs), the adapter board uses equal-length differential traces with calculated trace widths and spacing to match the 100-ohm differential impedance. Meanwhile, vias between the upper and lower layers utilize back-drilling technology to reduce signal reflections introduced by residual pins. For power pins, the adapter board uses widened traces or multiple parallel layers to reduce DC resistance and ensure no significant voltage drop during high-current transmission. For ground pins, multiple vias connect to the internal ground plane, forming a low-impedance loop.

[0057] During testing, the NVIDIA module is permanently inserted and secured to the first interface of the module signal adapter board, and the connection between the two remains intact. When testing a new PCBA carrier board, the operator simply places the module signal adapter board (with the pre-secured NVIDIA module) as a single unit, aligns the second interface on its lower surface with the corresponding slot on the PCBA carrier board under test, and presses it in place. After testing, the module signal adapter board is removed from the carrier board under test. At this point, the frictional contact surfaces during the insertion and removal action are the second interface (a low-cost connector) on the adapter board and the interface on the PCBA carrier board under test. Even after thousands of insertions and removals, if the second interface on the adapter board wears out and becomes unusable, only a module signal adapter board costing only tens of yuan needs to be replaced, while the expensive NVIDIA module and its first interface remain intact.

[0058] The test signal transmission path is as follows: the test signal emitted by the NVIDIA module is output from the module pin, enters the first interface of the adapter board, passes through the one-to-one adapter traces inside the adapter board, reaches the same pin of the second interface, and then enters the PCBA carrier board under test. The electrical length of this path is designed to be extremely short (typically less than 50 mm), and signal attenuation and timing offset are controlled within acceptable ranges. Actual measurements show that before and after using the module signal adapter board, the change in eye diagram opening of key high-speed signals is less than 5%, and the increase in delay is less than 100 picoseconds, which does not affect the accuracy of the test results.

[0059] The beneficial effects of this embodiment include at least the following: by adding an independent, low-cost adapter board between the NVIDIA module and the PCBA carrier board under test, the risk of mechanical wear caused by repeated plugging and unplugging is transferred from the expensive module body to the interface of the adapter board, extending the module's lifespan by tens of times and significantly reducing the consumable costs in mass production testing; the one-to-one adapter method ensures signal integrity, does not introduce additional timing deviations or signal distortion, and ensures that the test results are equivalent to those when directly connected; in addition, this structure makes module replacement and adapter board replacement simple and quick, has good maintenance convenience, and is suitable for high-intensity use environments on production lines.

[0060] In one possible implementation, the raw operating data acquired by the high-precision data acquisition module includes network port data, USB interface data, M.2 interface data, CAN bus data, UART serial port data, SPI interface data, I2C interface data, GPIO interface data, SD card data, fan data, and camera data; preprocessing includes removing invalid data caused by environmental interference and contact errors.

[0061] The high-precision data acquisition module has been described in the corresponding embodiment. This embodiment specifies the specific data types that the module can acquire and the specific content of preprocessing.

[0062] Ethernet data refers to data packets transmitted through the Ethernet physical layer, including the content of TCP / IP protocol frames, timestamps, frame intervals, and error counts. USB interface data includes handshake packets during enumeration, data payloads for bulk transfers, interrupt transmission status information, and voltage bus levels. M.2 interface data mainly refers to data packets transmitted through the PCIe channel and solid-state drive read / write performance parameters. CAN bus data includes data frame identifiers, data fields, cyclic redundancy check codes, and bit timing information. UART serial port data includes start bits, data bits, stop bits, and parity bits. SPI interface data includes clock signals, chip select signals, and master-to-slave / master-to-slave data sequences. I2C interface data includes start conditions, address bytes, acknowledge bits, and the data byte stream. GPIO interface data refers to the level states of input / output pins and edge transition events. SD card data refers to command and response sequences and data blocks transmitted through the SDIO interface. Fan data includes the frequency of the fan speed pulse signal and the duty cycle control signal. Camera data refers to the image pixel clock, line sync, field sync signals, and pixel values ​​transmitted through the MIPI CSI interface.

[0063] Environmental interference refers to noise components superimposed on the acquired signal due to factors such as electromagnetic radiation, power supply ripple, vibration, or temperature changes present at the test site. This noise may cause glitches or amplitude distortion in otherwise normal signals. Contact error refers to signal attenuation, reflection, or intermittent open circuits caused by unstable contact resistance between the probe and the test point, loose connectors, or poor cable shielding. Eliminating invalid data involves using algorithms to identify and discard abnormal samples that clearly exceed reasonable ranges due to the above reasons, or filtering the data and replacing unreliable measurements with estimated values ​​to prevent these erroneous data from participating in subsequent judgments and causing misjudgments.

[0064] The present invention will be further described below through a detailed embodiment, which can be referred to in conjunction with the system embodiment described above.

[0065] Following the system described above, when testing an embodied intelligent controller PCBA carrier board, this carrier board integrates all the interface types listed in the previous embodiments. The high-precision data acquisition module adopts a modular design, with each interface type corresponding to an independent acquisition daughter card. All daughter cards are connected to a common controller and clock source through a backplane.

[0066] At the start of the test, the host computer issued a command to perform a full interface function test. The module signal conversion module drove the NVIDIA module to activate each interface in sequence and send predefined test data patterns.

[0067] For Ethernet data acquisition, the high-precision data acquisition module's Ethernet daughter card mirrors and captures all Ethernet frames emitted by the network port of the tested board at line speed (1000Mbps). The acquired data includes the destination Media Access Control (MAC) address, source MAC address, Ethernet type field, payload, and frame check sequence for each frame. Simultaneously, the daughter card hardware generates a precise timestamp (1 nanosecond resolution) for the arrival of each frame and records the interval between frames. This raw data is temporarily stored in the daughter card's buffer memory.

[0068] For CAN bus data acquisition, the daughter card listens to the differential signals on the bus and decodes each data frame according to the CAN protocol. The acquired data includes the start-of-frame flag, arbitration segment identifier, control segment data length code, 8 bytes of data in the data segment, cyclic redundancy check segment, and acknowledge segment. The daughter card also records the bit timing sampling point deviation values ​​to evaluate bus signal quality.

[0069] During data acquisition, the simultaneous operation of multiple switching power supplies at the test site may introduce common-mode interference onto the CAN bus, potentially leading to misinterpretation of certain bits. Furthermore, the contact between the tooling probes and the test points on the carrier board may momentarily break due to minor vibrations, causing brief abnormal spikes in the acquired signal. The high-precision data acquisition module's preprocessing stage processes this raw data in real time.

[0070] Specifically, the module first applies a median filter to each signal, with a window size set to 3 or 5 sampling points. Taking CAN bus data as an example, if a sampled dominant bit is preceded and followed by recessive bits, and the duration is less than the minimum bit width allowed by the protocol (e.g., 100 nanoseconds), the pulse is determined to be a glitch caused by contact jitter, and the median filter replaces it with the surrounding recessive bit values. For Ethernet data, the module checks the frame check sequence. If a check error is found and the error position changes in multiple consecutive samplings of the same data frame, it is determined to be caused by electromagnetic interference, the frame is discarded, and a resampling request is triggered.

[0071] After removing invalid data, the module repackages the cleaned-up valid data. For example, if the CAN bus originally acquired 1000 data frames, 15 frames would be discarded due to CRC check errors and abnormal spikes, and the remaining 985 frames would be retained and have their frame sequence numbers and synchronization timestamps added to form a valid acquisition data packet. The data fields, identifiers, and checksums of each frame in this data packet have been verified to be correct.

[0072] Simultaneously, the module records statistical information on invalid data rejection, such as "CAN bus: 15 frames dropped, frame drop rate 1.5%", and appends this information to the data packet, uploading it to the host computer for quality analysts to assess the stability of the test contact. If the frame drop rate of a batch remains consistently high, it indicates that the probes need to be cleaned or the tooling needs to be inspected.

[0073] The beneficial effects of this embodiment include at least the following: by comprehensively covering all commonly used interface types on the PCBA carrier of the embodied intelligent controller through a high-precision data acquisition module, full-function parallel acquisition in a single test is achieved, avoiding the inefficiency of multiple wiring and repeated testing; through interference and contact error elimination algorithms in preprocessing, false abnormal signals caused by test environment rather than carrier board faults are effectively filtered out, significantly reducing the false alarm rate and improving the reliability of test results; at the same time, the statistical information of invalid data can also indirectly reflect the health status of the test fixture, playing an auxiliary diagnostic role.

[0074] In one possible implementation, the loop status monitored by the real-time anomaly monitoring and protection module includes overvoltage, overcurrent, short circuit, signal anomaly, and data interruption; the trigger protection includes immediate triggering of hardware power-off protection and synchronously uploading anomaly alarm data and fault location information to the host computer test and control module.

[0075] The real-time anomaly monitoring and protection module has been described in the corresponding embodiments. This embodiment further defines the specific anomaly types monitored by this module and the specific content of the protection actions.

[0076] The circuit status refers to the current operating parameters of the power supply and signal circuits of the PCBA under test. Overvoltage indicates that the power supply voltage of the PCBA under test exceeds the preset safety limit; for example, a nominal 5V power line may actually have a voltage exceeding 5.8V. Overcurrent indicates that the current flowing through a power supply circuit of the PCBA under test exceeds the maximum allowable value; for example, the normal operating current of the core 1.8V power supply is 1A, but a short circuit may cause the current to surge to over 5A. Short circuit indicates the presence of a low-impedance path in the power supply circuit, typically manifested as a sudden voltage drop and a sharp increase in current. Signal anomaly indicates that the data acquisition module detects that the signal level, frequency, or timing of a certain interface does not conform to the standard protocol specifications; for example, the CAN bus may remain at a recessive level for an extended period. Data interruption indicates that the communication link between the host computer and the module signal conversion module, or between the data acquisition module and the host computer, is broken for more than the preset heartbeat timeout period.

[0077] Hardware power-off protection refers to power-off actions executed directly by independent hardware circuits without relying on host computer software responses. It typically employs solid-state relays or power metal-oxide-semiconductor field-effect transistors connected in series in the power supply path, controlled by a threshold detection circuit consisting of a comparator and a flip-flop. When overvoltage or overcurrent is detected, the comparator output flips, the flip-flop latches, and drives the switching device to turn off; the entire process can be completed in microseconds. The abnormal alarm data packet includes the abnormality type (e.g., overcurrent), the actual measured value at the time of the abnormality (e.g., 5.2A), the duration of the abnormality, and the identifier of the loop where the abnormality occurred (e.g., VDD_5V power channel). Fault location information refers to codes or descriptions that uniquely identify the location of the fault, such as "5V power network near U3 chip" or "Pin 8 of J2 connector".

[0078] The present invention will be further described below through a detailed embodiment, which can be referred to in conjunction with the system embodiment described above.

[0079] On the actual testing production line, a PCBA carrier board with manufacturing defects was placed into the fixture for testing. One of the decoupling capacitors on the carrier board developed an internal crack during reflow soldering, which caused leakage current to gradually increase as the temperature rose after power was applied.

[0080] At the start of the test, the real-time anomaly monitoring and protection module is activated. Internally, this module has an independent monitoring channel for each power supply of the board under test. Taking a 3.3V power supply as an example, the module uses a precision resistor divider network to sample the voltage onto a window comparator, with an upper threshold set to 3.6V and a lower threshold set to 3.0V. Simultaneously, a Hall effect current sensor converts the current signal into a voltage signal, which is then fed into another comparator with a threshold set to 1.5 times the rated current (e.g., 1.5A).

[0081] During the first 30 seconds of basic function testing, the 3.3V power supply voltage stabilized at 3.32V, the current stabilized at 0.9A, all comparator outputs were low, and the module was in a ready-to-trigger state.

[0082] When the test reached the M.2 interface stress test, the board under test needed to drive a high-speed solid-state drive to perform a large amount of data read and write, which increased power consumption. The leakage current of the cracked capacitor increased sharply, causing the total current of the 3.3V power supply to gradually rise from 0.9A to 1.6A, exceeding the comparator threshold of 1.5A. The current comparator output a high level instantaneously, and this high-level signal was sent to the set terminal of an SR latch. The output of the latch immediately became high, and the signal split into two paths: one path was connected to the gate drive circuit of a P-channel metal-oxide-semiconductor field-effect transistor connected in series on the 3.3V power supply bus, and the field-effect transistor was completely turned off within a few microseconds, cutting off the power supply; the other path was connected to the interrupt pin of a microcontroller on the module (which runs independently of the host computer), triggering the microcontroller to record this abnormal event.

[0083] Upon hardware power failure, the PCBA under test immediately shuts down, preventing leakage from further damaging PCB traces or affecting other healthy components. Simultaneously, the microcontroller reads the current comparator output status, voltage sample value, the counter at the time of the fault, and the channel number where the anomaly occurred (channel 2 for the 3.3V power supply), packaging this information into an anomaly alarm data packet. This packet contains: anomaly type (overcurrent), measured current value (1.62A), threshold (1.5A), anomaly duration (recorded by the microcontroller as approximately 2 milliseconds based on the comparator high-level duration), and fault location information (matrix-coded based on the tooling bed to "3.3V network near the M.2 interface"). This data packet is synchronously uploaded to the host computer test management module via a standby communication interface (e.g., CAN bus or RS485) independent of the main test Ethernet.

[0084] Upon receiving the abnormal alarm data packet, the host computer immediately stopped the current test process and displayed a red alarm window on the monitoring interface, showing "Channel 2 overcurrent protection, possible fault location: M.2 socket area, please check PCBA." Simultaneously, the host computer logged the fault and prohibited any further testing of the board. The operator then removed the board for repair and analysis, quickly locating the cracked capacitor based on the fault location information. After replacement, the test passed.

[0085] The beneficial effects of this embodiment include at least the following: comprehensive safety protection for the testing process is achieved by real-time monitoring of various circuit states such as overvoltage, overcurrent, short circuit, signal abnormality, and data interruption; the hardware-level power failure protection response speed is much faster than software processing, and the power supply can be cut off before the fault causes permanent damage, effectively protecting expensive testing equipment and the board under test; the synchronously uploaded abnormal alarms and fault location information provide maintenance personnel with accurate fault location guidance, greatly shortening the fault investigation time and improving the overall test yield and maintenance efficiency of the production line.

[0086] In one possible implementation, the results output and storage module stores data including all raw test data, process data, analysis results, and fault logs, supporting full-process traceability of a single test data item; and visualizes the test progress, real-time parameters, and pass / fail judgment results on a display screen.

[0087] The result output and storage module has been described in the corresponding embodiments above. This embodiment further defines its storage content and display functions.

[0088] Raw test data refers to the raw waveforms, data frames, timestamps, etc., uploaded by the high-precision data acquisition module without any statistical processing or filtering, such as the complete binary content of each frame captured by the CAN bus in a test. Process data refers to intermediate state information generated during test execution, including the start time, end time, executed instruction sequence, number of timeout retries, and data discard statistics during data preprocessing for each test item. Analysis results refer to the conclusions output by the host computer test control module after comparison and evaluation using a dedicated algorithm model, including the measured value, standard value, deviation, single-item pass / fail flag, and overall judgment result for each sub-item. Fault logs refer to the abnormal alarm records reported by the real-time anomaly monitoring and protection module during the test, as well as communication errors or timeout events detected by the host computer's self-diagnosis. Each log entry includes a timestamp, fault type, severity level, and relevant module identifier.

[0089] Full-process traceability of single test data refers to the ability, for any test (corresponding to a unique serial number of a PCBA carrier), to trace back from the final comprehensive judgment result to the analysis result data that triggered that judgment, and further back to the process data and raw data used to generate that analysis result. It also allows for association with the test environment parameters at the time (such as test time, operator, tooling number, software version, etc.). This feature requires the storage module to store data at all levels in a structured manner and establish indexed associations.

[0090] Visualized displays refer to the use of a graphical interface to present test progress, real-time parameters, and judgment results to operators in an intuitive way. Test progress is displayed as a progress bar or percentage, showing the ratio of completed test items to the total number of items. Real-time parameters are dynamically updated with the currently acquired key signal values ​​in the form of a digital dashboard, trend chart, or waveform graph. Pass or fail judgment results are usually displayed with a large green "PASS" or red "FAIL" icon, accompanied by an audio prompt.

[0091] The present invention will be further described below through a detailed embodiment, which can be referred to in conjunction with the system embodiment described above.

[0092] During a full day of mass production testing, the system tested a total of 500 PCBA carrier boards, of which 480 passed and 20 were deemed unqualified. The results output and storage module continued to run in the background.

[0093] For each completed carrier board, the result output and storage module receives data packets from the host computer. These data packets form a hierarchical data structure. The top layer is a test summary, including the carrier board serial number, test start and end times, and the overall judgment result (PASS / FAIL). The second layer is a list of test items, such as "Gigabit Ethernet," "USB 3.0," "CAN0," "CAN1," and "GPIO," totaling 28 items, each with its own judgment result. The third layer contains detailed analysis results for each item. For example, under the Gigabit Ethernet item, it includes the measured throughput (985Mbps), standard requirement (≥950Mbps), packet loss rate (0.0005%), standard requirement (≤0.001%), and the pass / fail indicator for each item. The fourth layer contains process data, such as the number of data packets sent and received during the Gigabit Ethernet test, the number of retransmissions, and the specific time point of each measurement. The bottom layer contains raw data, such as the actual content (hexadecimal) of a specific test packet and the nanosecond-level timestamp when the packet was acquired.

[0094] The module stores this data hierarchically in the built-in solid-state drive, using an indexed database file system. The root key of each test record is the unique serial number of the carrier board, which allows for quick retrieval of all test data.

[0095] When a quality engineer needs to perform failure analysis on a carrier board (e.g., serial number "R202605270015") that failed at the user's site, he enters the serial number into the system's query interface. The results output and storage module immediately reads the corresponding record from the database and reconstructs the complete test data. The engineer discovers that the carrier board was deemed PASS during factory testing, but intermittent CAN communication errors occurred at the user's site.

[0096] The engineer first reviewed the analysis results layer, confirming that both CAN0 and CAN1 interfaces passed factory testing. However, he noticed that the measured signal amplitude of CAN0 was 2.1V (standard range 1.8V-2.2V), which was on the edge of the range. Next, he checked the process data layer and found that during the CAN0 test, the system recorded three "CRC check error counts were non-zero," but all were within the allowable range (less than 5 times). Furthermore, the high-precision data acquisition module discarded two data frames during preprocessing and labeled them as "caused by interference." The engineer then retrieved the original data layer and examined the original waveforms of the two discarded data frames. He found that the dominant bit amplitude of these two frames was significantly lower and accompanied by oscillations, showing a clear difference from normal frames.

[0097] Through end-to-end tracing, engineers concluded that the CAN0 bus driver on the carrier board had a weak load capacity. While it passed factory testing, its edge performance caused actual failures in the noisier environment at the user's site. Based on this finding, the design department tightened CAN driver testing standards and improved material selection.

[0098] During testing, the display screen in front of the operator updates the visual content in real time. A large circular indicator in the center of the screen displays a yellow rotating animation during testing and a green checkmark or red cross upon completion. On the left is a progress list of test items, highlighting ongoing items and displaying completed items with green checkmarks. On the right is a real-time parameter area; for example, when testing gigabit networks, it displays the current throughput value and dynamic curve in real time in a simulated dashboard format. When the throughput approaches the lower threshold, the dashboard border turns orange as a warning. The bottom of the screen displays the current carrier board serial number and the overall test progress bar.

[0099] After testing a carrier board is completed, a large pop-up window displaying the overall judgment result appears on the screen, along with a voice announcement of "pass" or "fail". Operators can quickly place the carrier board into the next process (qualified product) or rework box (unqualified product) without having to view detailed data.

[0100] The beneficial effects of this embodiment include at least the following: by storing data across the entire chain (from raw data to analysis results), complete traceability of test data is achieved, providing a solid data foundation for quality improvement, failure analysis, and batch statistics; the real-time visualization function of the display screen enables operators to intuitively grasp the test progress and results, reducing the risk of misjudgment and misplacement, and improving the efficiency of the production line operation; the indexed design of the storage module supports fast single data retrieval, making subsequent data analysis and problem review efficient and convenient.

[0101] See Figure 2 This application also discloses a PCBA carrier board testing method for an embodied intelligent controller applied to the aforementioned system, comprising: Step 201: The host computer test management module initializes the system, generates a standardized test instruction data packet based on the parameters of the PCBA carrier board under test entered by the user and the built-in standard database, and sends it to the module signal conversion module. Step 202: The module signal conversion module receives and parses the standardized test instruction data packet, simulates the dynamic working state of the intelligent device, and outputs the test instructions of each interface to the PCBA carrier board under test that is clamped and fixed on the special tooling positioning clamping module. Step 203: The high-precision data acquisition module synchronously acquires all raw operating data generated by the PCBA carrier board under test after responding to the test command in real time, and generates a valid acquisition data packet after preprocessing; at the same time, the real-time anomaly monitoring and protection module synchronously acquires the status data of the test circuit and generates a status monitoring data packet. Step 204: The host computer test management module receives valid data acquisition data and status monitoring data, retrieves built-in standard parameters for comparison and analysis, and generates a final test result data package containing test items, real-time parameters, standard parameters, differences, and pass / fail status. Step 205: The host computer test management module transmits the final test result data packet to the result output and storage module for data solidification, storage, and visualization.

[0102] This embodiment describes a complete testing method flow, which is applied to the aforementioned system. The key steps are explained below.

[0103] System initialization refers to the self-check and preparation operations performed by the host computer test control module before power-on or before each new round of testing. This includes checking the communication links with downstream modules, loading the built-in standard database, initializing log files, and clearing temporary caches. User-entered parameters of the PCBA carrier board under test refer to information related to this batch of boards entered by the operator through the interface, such as model code, version number, test serial number range, and whether certain specific tests need to be performed. The built-in standard database refers to a set of verified thresholds and reference models stored on the host computer's hard drive; different PCBA carrier board models correspond to different standard databases. The standardized test instruction data package has been explained previously.

[0104] Parsing standardized test instruction data packets refers to the process where the microcontroller or driver software within the module's signal transfer module reads the instruction fields from the data packets and converts them into a sequence of low-level operations that the NVIDIA module can execute. The dynamic operating state of the simulated embodied intelligent device has been explained in the corresponding embodiments.

[0105] Real-time synchronous acquisition refers to all channels of the high-precision data acquisition module starting data acquisition under the same clock reference. Preprocessing includes filtering, noise reduction, and removal of invalid data. Loop status data refers to physical quantities such as voltage, current, temperature, and communication link status.

[0106] Comparative analysis involves comparing measured data with standard parameters item by item, calculating the differences, and determining whether they are within the allowable range. The final test result data packet is a structured data object, in which the test items list all the functions executed in this test (e.g., "Gigabit Ethernet_TX"), the real-time parameters are the actual measured values ​​of the items, the standard parameters are the reference values ​​in the database, the difference is the difference between the two (which can be an absolute or relative value), and the pass / fail status is marked as "pass" or "fail".

[0107] Data persistence storage refers to saving the result data packets persistently to non-volatile memory, ensuring they are not lost after power failure. Visual display refers to presenting the results to the operator through a screen, indicator lights, or sound.

[0108] The present invention will be further described below through a detailed embodiment, which is referenced in conjunction with the foregoing system embodiments.

[0109] Before initiating a complete test procedure, the operator places a PCBA carrier board of the intelligent controller to be tested into the dedicated tooling positioning and clamping module and starts clamping. Then, on the software interface of the host computer test control module, the operator selects the model of the carrier board, "ECU-2026", enters the starting serial number "001" and the ending serial number "100", checks the "Full Function Test" checkbox, and clicks the "Start" button.

[0110] Step 1: The host computer test and control module performs system initialization. The software checks whether the Ethernet connection with the module signal conversion module is successful (sends a Ping command and waits for a response), whether the PCIe link with the high-precision data acquisition module is enumerated normally, and whether the heartbeat signal with the real-time anomaly monitoring and protection module is received. After all checks pass, the module loads the standard parameter file of model "ECU-2026" from the local database. This file contains a list of standard values ​​for 28 test items. The software generates a test task queue based on the serial number range entered by the user and generates the first standardized test instruction data packet for the board under test (serial number 001). This data packet is in JSON format and includes a list of test items, the excitation parameters for each test item (such as the specific data mode to be sent for gigabit network testing, the frame interval required for CAN bus testing, etc.), the expected response range, and the timeout period. The data packet is sent to the module signal conversion module via Ethernet.

[0111] Step Two: After receiving the data packet, the module signal converter receives the JSON content. Its internal embedded processor parses the JSON content and converts the excitation parameters into input parameters for the test program running on the NVIDIA module. Once the test program starts, it simulates a scenario where an embodied intelligent robot walks on a flat surface while recognizing obstacles ahead. Specifically, the module drives the NVIDIA module to send simulated gyroscope data to the PCBA under test (DUT) via the SPI interface at a 1MHz clock rate, and simultaneously sends a continuous stream of image data to the DUT's network coprocessor via the gigabit Ethernet port. These test commands are transmitted through the module signal converter's 699 signal channels to the securely clamped DUT, triggering the various functional modules on the board to begin operating.

[0112] Step 3: Simultaneously with the response from the board under test, all daughter cards of the high-precision data acquisition module begin acquisition. For example, the SPI daughter card records the waveforms of the clock line, data input line, and data output line at a 10MHz sampling rate; the Gigabit Ethernet daughter card mirrors and timestamps all data packets on the network port. Acquisition lasts for 30 seconds. The acquired raw data stream is sent to the module's field-programmable gate array for preprocessing: a low-pass filter is applied to the SPI waveform to eliminate high-frequency glitches, and CRC error frames caused by interference in the network port data are discarded. After preprocessing, the module generates a valid acquisition data packet, which includes the sensor data sequence read back from the SPI, the count of successfully received data packets from the network port, and other information. At the same time, the real-time anomaly monitoring and protection module samples the current and voltage values ​​of the 3.3V and 5V power supplies of the board under test at a period of 1 millisecond, continuously recording whether any thresholds are exceeded within 30 seconds, generating a status monitoring data packet, which includes the maximum, minimum, and average values ​​of the voltage / current time series curves, as well as any record of exceeding limits. These two data packets are uploaded to the host computer through their respective data channels.

[0113] Step 4: After receiving two data packets, the host computer's test control module initiates the comparison and analysis process. Taking the gigabit network test as an example, the host computer compares the actual number of received data packets in the collected data packets (e.g., 1 million data packets were sent, and 999,950 were actually received) with the standard parameter (packet loss rate ≤ 0.01%), calculates the packet loss rate to be 0.005%, which is less than the standard, and determines that this item is qualified. For the SPI test, the host computer compares the collected sensor data sequence with the expected ramp sequence point by point, calculates the root mean square error to be 0.02 (the standard requires ≤ 0.05), and determines that it is qualified. Finally, the host computer summarizes the judgment results of all 28 items and generates a final test result data packet, which includes each item name, measured value, standard value, difference, individual judgment, and overall judgment (all items are qualified if they are, otherwise it is unqualified).

[0114] Step 5: The host computer sends the data packet to the result output and storage module. This module appends the data packet to the test log file for the day in CSV format, with each line representing the test record of one carrier board. Simultaneously, the module displays "Serial Number 001 Test Pass Rate 100%" on the touchscreen, accompanied by a green background and voice prompt "Passed." The operator removes the tested carrier board and places it in the qualified product tray, then places the next carrier board, and the system automatically begins the next test cycle.

[0115] The beneficial effects of this embodiment include at least the following: by dividing the testing method into five clear steps—initialization, instruction issuance and stimulation, data acquisition and monitoring, comparison and analysis, and result output—a fully automated closed-loop process from user input to final judgment is achieved, significantly reducing manual intervention; the data flow and module interaction relationships between each step are clear, ensuring the repeatability and reliability of the method; and the method can be adapted to different system configurations of the aforementioned embodiments, exhibiting good versatility and scalability.

[0116] In one possible implementation, when the module signal adapter outputs test commands to the PCBA carrier board under test, it transmits all 699 pins of the NVIDIA module one-to-one without loss through the module signal adapter, thereby achieving signal bridging between the NVIDIA module and the PCBA carrier board under test.

[0117] This embodiment further defines the specific operation of the module signal conversion module in the aforementioned test method. One-to-one lossless transmission has been explained in detail in the corresponding embodiments above. At the methodological level, this step emphasizes that throughout the entire process of the test command output, no active transformation or protocol conversion occurs on the signal path; it is merely a physical connection.

[0118] The present invention will be further described below through a detailed embodiment, which can be referred to in conjunction with the method embodiments described above.

[0119] When performing tests as described above, the module signal conversion module plays a crucial role as a bridge. Taking the PCIe Gen3 high-speed interface test on the PCBA under test as an example, the specific implementation of one-to-one lossless transmission is explained.

[0120] When the standardized test command data packet issued by the host computer contains the "PCIe link test" item, the embedded processor in the module's signal transfer module instructs the NVIDIA module to run a PCIe link training and throughput test program. This program requires the NVIDIA module to send a specific set of training sequences (ordered sets of TS1 and TS2) to the PCBA carrier board under test through the connector pins on its bottom, and to detect the acknowledgment signal returned from the carrier board.

[0121] The signal transmission path is as follows: The differential transmit pins (e.g., TX_P and TX_N) of the PCIe controller inside the NVIDIA module are directly connected to the corresponding pins of the first interface of the module adapter board. Inside the adapter board, these two differential signal lines are routed from the upper layer to the lower layer in the form of tightly coupled microstrip lines. The line width, spacing, and dielectric thickness are precisely calculated to ensure that the differential impedance is stable within the range of 100 ohms ± 5%. To ensure signal integrity, no capacitors, resistors, or buffers are placed on the adapter board, and no level shifters are introduced. The signal starts from the TX_P pin of the first interface, passes through the serpentine equal-length winding inside the adapter board (used to match the propagation delay of the other set of signals), reaches the TX_P pin of the second interface, and finally enters the corresponding receive pin of the PCBA carrier board under test. The insertion loss along the entire path is less than 1dB at 5GHz, and the return loss is less than -15dB.

[0122] During testing, the NVIDIA module transmitted PCIe data streams at a rate of 8GT / s, with a signal rise time of approximately 30 picoseconds. One-to-one lossless transmission ensured that the signal edge steepness and eye diagram opening remained virtually unchanged. To verify this, an oscilloscope was used to capture the signal eye diagram at the pins of the second interface and compared with the eye diagram at the first interface. The measured results showed that after using the module signal adapter board, the eye height decreased by only about 2%, the eye width decreased by about 1%, and the jitter increased by less than 1 picosecond. These minute changes are entirely within the tolerances allowed by the PCIe standard; therefore, the test system was able to correctly complete link training and rate negotiation as if connected directly, and accurately measure throughput.

[0123] At the methodological level, operators do not need to be aware of the adapter board's existence; the entire one-to-one lossless transmission is transparent. The step in the testing method where "the module signal adapter receives and parses standardized test command data packets and outputs test commands for each interface to the PCBA carrier board under test" is actually completed automatically through the adapter board's physical pass-through characteristic, requiring no additional software configuration or manual intervention. This demonstrates the simplicity and robustness of the method's design.

[0124] The beneficial effects of this embodiment include at least the following: the test method explicitly adopts a one-to-one lossless transmission method, which ensures that the introduction of the module signal conversion module does not change the electrical characteristics of the test signal, thus guaranteeing the consistency of the test results with those obtained through direct connection; at the same time, since there is no need for signal regeneration or protocol conversion, this method avoids introducing additional delays and fault points, and simplifies system debugging and maintenance.

[0125] In one possible implementation, after the high-precision data acquisition module synchronously acquires the raw operating data in real time, it also includes time-series binding and data alignment preprocessing of the acquired multi-channel data, binding the equipment operating data and the loop status data in a one-to-one time sequence correspondence.

[0126] This embodiment, based on the previously described testing method, adds further limitations to the preprocessing steps after data acquisition. Multi-channel data timing binding refers to associating data samples from different acquisition cards (such as Ethernet cards, CAN cards, and GPIO cards) according to a unified time base, ensuring that signals belonging to the same moment can be analyzed together. Data alignment preprocessing corrects time offsets caused by hardware delay differences between different acquisition channels (e.g., different signal line lengths, different analog-to-digital conversion times), aligning the data sequences of each channel on the time axis.

[0127] Equipment operation data refers to the signal data collected by the high-precision data acquisition module from various functional interfaces of the PCBA under test, such as CAN bus frames, Ethernet packets, and GPIO edges. Loop status data refers to parameters such as voltage, current, and temperature collected by the real-time anomaly monitoring and protection module. One-to-one timing correspondence means that for any given time point t, it is possible to find both the equipment operation data sample and the loop status data sample collected at that moment, and to confirm that these two samples were indeed acquired at the same physical time point.

[0128] The present invention will be further described below through a detailed embodiment, which can be referred to in conjunction with the method embodiments described above.

[0129] During a test, the PCBA carrier board under test exhibited intermittent overcurrent protection when executing motor control commands. To pinpoint the cause of the fault, it is necessary to precisely analyze the relationship between the control signal and the power supply current on the carrier board within a microsecond-level time window before and after the overcurrent occurred.

[0130] According to this method, before the high-precision data acquisition module begins testing, all acquisition daughter cards receive synchronization pulses from the same high-precision clock source. The 10MHz reference frequency output by this clock source and the pulse synchronization signal once per second are distributed to each daughter card through the backplane. Each daughter card has an independent counter based on this reference frequency. When the synchronization pulse arrives, the counters of all daughter cards simultaneously reset to zero and begin to increment.

[0131] During the data acquisition process, when the network interface card captures each Ethernet frame, it reads the current value of the local counter as the timestamp of that frame, with an accuracy of 100 nanoseconds. When the GPIO interface card captures the rising edge of a GPIO line, it also reads the current counter value as the timestamp. Simultaneously, the real-time anomaly monitoring and protection module collects current values ​​at a fixed 1-microsecond sampling interval, and each current value also includes its corresponding timestamp (based on the same counter).

[0132] After the test, all timestamped data streams were transmitted to the host computer. The host computer performed timing binding and data alignment preprocessing. First, due to the different hardware delays of different channels (e.g., the response time of the current sensor is 2 microseconds, while the GPIO rising edge detection circuit has a delay of 0.5 microseconds), the host computer needs to perform alignment calibration. This calibration parameter is measured during the system initialization phase by injecting a test signal with a known timing relationship. Assuming that the GPIO channel is 1 microsecond ahead of the actual physical time and the current channel is 0.5 microseconds behind the actual physical time, the host computer subtracts 1 microsecond from all timestamps of the GPIO data sequence and adds 0.5 microseconds to all timestamps of the current data sequence, calibrating them to a unified "physical timeline".

[0133] Then, the host computer performs timing binding. It sorts all calibrated data streams according to their timestamps, forming a unified time series table. The first column of this table is the timestamp (in microseconds), the second column is the current value at that moment, the third column is the GPIO level at that moment, and the fourth column is the CAN bus frame content at that moment (if any). For channels where no events were collected at certain time points, null values ​​are used to fill in the blanks.

[0134] Taking overcurrent fault analysis as an example, the real-time anomaly monitoring and protection module recorded that the current value jumped to 5.2A (threshold 1.5A) at 12,345,678 microseconds after the test started. By querying the unified time series table, the host computer found that at 12,345,675 microseconds (3 microseconds before the overcurrent), GPIO_5 (this pin controls the enable of the motor drive) switched from high to low; at 12,345,676 microseconds, an "emergency stop" command frame was received on the CAN bus. Timing binding clearly revealed the causal relationship: after the CAN bus received the emergency stop command, the controller shut down the motor drive through GPIO_5, but the drive circuit generated back electromotive force during the shutdown process, causing a current spike. This is not a board fault, but normal motor braking behavior. Without timing binding, the overcurrent event would appear as an isolated anomaly and might be misjudged as a hardware short circuit.

[0135] In this way, the system completes the complex time alignment and binding work in the preprocessing stage, so that subsequent comparison and analysis can directly use data with correct time correlation to make accurate judgments.

[0136] The beneficial effects of this embodiment include at least the following: by performing time-series binding and data alignment preprocessing on multi-channel data, isolated data originally scattered in different acquisition daughter cards can be mapped onto a unified time axis, thereby enabling accurate analysis of the temporal causal relationship between events; this is crucial for locating common time-related latent faults in embodied intelligent controllers (such as the correlation between signal competition, power disturbance and logic error); this method significantly improves the depth of test data analysis and the accuracy of fault diagnosis, and reduces false alarms and missed alarms.

[0137] In one possible implementation, when the host computer test management module performs comparative analysis, it calls the built-in intelligent dedicated test algorithm model to perform dynamic difference judgment, timing response judgment, and multiple fluctuation stability judgment on the PCBA carrier board under test. When the result output and storage module performs data solidification storage, it archives the original data, process data, operating parameters, and fault logs of a single test in the entire chain, supporting full-process traceability of test data.

[0138] In this embodiment, two key steps are further defined: first, the comparison and analysis step calls the embodied intelligence-specific test algorithm model; second, the result storage step adds full-link archiving and traceability functions.

[0139] The explanations of the proprietary intelligent test algorithm model, dynamic difference judgment, timing response judgment, and multiple fluctuation stability judgment can be found in the corresponding implementation examples. The explanations of raw data, process data, analysis results, and fault logs can also be found in the corresponding implementation examples. Operating parameters refer to the environmental and working conditions information during test execution, such as the power supply voltage setpoint, ambient temperature (if the system is equipped with a temperature sensor), test software version, module firmware version, and test fixture number. Full-link archiving refers to organizing all levels of data (from operating parameters to raw data) according to the dimensions of the test task, forming an immutable record. Full-process traceability means being able to trace back from the final judgment result along the path of data generation to the original collected data and be able to associate it with the operating conditions at that time.

[0140] The present invention will be further described below through a detailed embodiment, which can be referred to in conjunction with the method embodiments described above.

[0141] The tests were run as described above. However, for some high-performance PCBA carrier boards with embodied intelligent controllers, the quality control standards require dynamic performance evaluation. Therefore, when configuring the test task, the operator selected the "Enable Dedicated Algorithm Model" option.

[0142] When the host computer's test management module reaches the comparison and analysis step, after the ordinary parameter comparison is completed, it additionally calls the built-in embodied intelligence-specific test algorithm model. This model contains three sub-modules, which respectively perform dynamic difference determination, timing response determination, and multiple fluctuation stability determination.

[0143] Taking dynamic difference determination as an example: This algorithm module extracts a measured duty cycle sequence and a standard reference sequence for 1000 consecutive cycles from the PWM output interface of the tested board. The algorithm calculates the root mean square error of the difference sequence to be 0.8% (standard ≤ 1%), the maximum instantaneous difference to be 1.2% (standard ≤ 1.5%), and the error settling time (the time from the start of the step change to entering the ±0.5% steady-state band) to be 120 microseconds (standard ≤ 150 microseconds). All indicators are qualified, and the dynamic difference determination result is passed.

[0144] Timing response judgment: For the SPI slave interface, the algorithm module analyzed the time from the falling edge of the chip select signal to the valid data output. The average delay across 1000 measurements was 85 nanoseconds (standard ≤ 100 nanoseconds), the maximum delay was 98 nanoseconds, and the jitter (standard deviation) of the delay was 4.5 nanoseconds (standard ≤ 10 nanoseconds). Judgment passed.

[0145] Stability assessment after multiple fluctuations: The above dynamic test was repeated 30 times. The algorithm module calculated the coefficient of variation of the root mean square error for 30 iterations to be 2.1% (standard ≤5%), and no monotonically increasing or decreasing trend was observed. The assessment passed.

[0146] Based on the above three dynamic judgment results, even if all static parameter tests are qualified, the host computer will still generate a final test result data packet containing the dynamic judgment sub-results. For carrier boards that fail the dynamic judgment, they will be judged as overall unqualified even if the static parameters are qualified.

[0147] In the data storage stage, the result output and storage module not only saves the routine test conclusions but also performs end-to-end archiving. For this test (serial number "DYN-2026-088"), the module creates a folder named after the serial number. This folder contains: a "raw" subfolder containing all raw waveform files uploaded by the high-precision data acquisition module (one binary file per interface); a "process" subfolder containing preprocessed valid acquisition data packets, a unified timeline table after time-series binding, and intermediate calculation results; a "report" subfolder containing analysis result data packets (including dynamic judgment details) and the final judgment PDF report; and a "log" subfolder containing status monitoring data packets uploaded by the real-time anomaly monitoring and protection module, fault logs, and the operating parameters of this test (including test software version number, operator ID, tooling temperature, etc.).

[0148] All files are linked to a single master record via hard links in the file system or foreign keys in the database. When tracing the source is needed later, users can enter the serial number through the query interface of the host computer software to view the complete test reconstruction interface. This interface not only allows replaying any original waveform but also overlays and displays the voltage and current curves at that time. If a carrier board fails at the user's site, the quality engineer can precisely trace back to every detail of the carrier board's factory testing to determine whether the problem existed at the time of manufacture (but might have been missed during testing due to unreasonable threshold settings) or occurred later.

[0149] The beneficial effects of this embodiment include at least the following: by introducing dynamic difference, timing response and multiple fluctuation stability judgment in the comparative analysis, the test method can evaluate the real performance of PCBA carrier under dynamic working conditions, making up for the shortcomings of traditional static testing and better matching the high real-time and high reliability operation requirements of the intelligent controller; through full-link archiving and traceability support, it provides a complete data foundation for product quality traceability and continuous improvement, which meets the Industry 4.0 quality control standards of high-end intelligent equipment.

[0150] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments in this specification are not limited to the described order of actions, because according to the embodiments in this specification, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments in this specification.

[0151] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0152] The preferred embodiments disclosed above are merely illustrative of this specification. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments described herein. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the embodiments, thereby enabling those skilled in the art to better understand and utilize this specification. This specification is limited only by the claims and their full scope and equivalents.

Claims

1. A PCBA carrier board testing system for an embedded intelligent controller, characterized in that, include: The host computer test management module is used to receive user configuration instructions and store standard parameters, generate standardized test instruction data packets and send them out; The module signal conversion module is communicatively connected to the host computer test and control module and is used for electrical connection with the PCBA carrier board under test. The module signal conversion module receives the standardized test instruction data packet and outputs test instructions to the PCBA carrier board under test in a simulated working state of the intelligent device. The high-precision data acquisition module has an acquisition end that is directly connected to the functional interface of the PCBA carrier board under test, and a data output end that is connected to the host computer test and control module. It is used to synchronously acquire the raw operating data generated by the PCBA carrier board under test after responding to the test command in real time, and after preprocessing, generate a valid acquisition data packet and upload it to the host computer test and control module. A dedicated tooling positioning and clamping module is used to physically position and clamp the PCBA carrier board under test, and to achieve physical connection and electrical conduction between the PCBA carrier board under test, the module signal conversion module, and the high-precision data acquisition module. The real-time anomaly monitoring and protection module is connected in parallel to the test circuit of the PCBA carrier board under test. It is used to monitor the circuit status in real time and trigger protection when an anomaly is detected, and generate a status monitoring data packet to be uploaded to the host computer test control module. The result output and storage module is connected to the host computer test management module and is used to receive and store the final test result data packet generated by the host computer test management module and to visualize the test results. The host computer test management module is also used to receive the valid data acquisition data and the status monitoring data, compare and analyze them with the built-in standard parameters, and generate the final test result data package.

2. The PCBA carrier board test system for body- smart controller of claim 1, wherein, The host computer test management module has a built-in intelligent dedicated test algorithm model, which includes a dynamic difference judgment algorithm, a timing response judgment algorithm, and a multiple fluctuation stability judgment algorithm, used to judge the signal delay, dynamic response consistency, and multiple interaction stability of the PCBA carrier board under test.

3. The PCBA carrier board test system for body- smart controller of claim 1, wherein, The module signal conversion module is an independent conversion board. The upper layer of the conversion board has a first interface for connecting to the NVIDIA module, and the lower layer has a second interface for connecting to the PCBA carrier board under test. The conversion board converts all signals of the first interface and the second interface one-to-one, realizing signal bridging between the NVIDIA module and the PCBA carrier board under test.

4. The PCBA carrier board test system for body- smart controller of claim 1, wherein, The raw operating data acquired by the high-precision data acquisition module includes network port data, USB interface data, M.2 interface data, CAN bus data, UART serial port data, SPI interface data, I2C interface data, GPIO interface data, SD card data, fan data, and camera data; the preprocessing includes removing invalid data caused by environmental interference and contact errors.

5. The PCBA carrier board test system for body- smart controller of claim 1, wherein, The real-time anomaly monitoring and protection module monitors circuit states including overvoltage, overcurrent, short circuit, signal anomalies, and data interruptions; the trigger protection includes immediate triggering of hardware power-off protection and synchronously uploading anomaly alarm data and fault location information to the host computer test and control module.

6. The PCBA carrier board test system for body- smart controller of claim 1, wherein, The result output and storage module stores data including all raw test data, process data, analysis results and fault logs, and supports full-process traceability of a single test data item; The test progress, real-time parameters, and pass / fail results are displayed visually on the screen.

7. A PCBA carrier board testing method for embodied intelligence controller applied to the system of any one of claims 1 to 6, characterized in that, include: The host computer test management module initializes the system, generates the standardized test instruction data packet based on the PCBA carrier board parameters entered by the user and the built-in standard database, and sends it to the module signal conversion module. The module signal conversion module receives and parses the standardized test instruction data packet, simulates the dynamic working state of the embodied intelligent device, and outputs test instructions for each interface to the PCBA carrier board under test that is clamped and fixed on the special tooling positioning clamping module. The high-precision data acquisition module synchronously acquires all raw operating data generated by the PCBA carrier board under test after responding to the test command in real time, and generates the effective acquisition data packet after preprocessing; at the same time, the real-time anomaly monitoring and protection module synchronously acquires the status data of the test circuit and generates the status monitoring data packet. The host computer test control module receives the valid data acquisition data and the status monitoring data, retrieves the built-in standard parameters for comparison and analysis, and generates the final test result data package containing test items, real-time parameters, standard parameters, differences, and pass / fail status. The host computer test management module transmits the final test result data packet to the result output and storage module for data solidification, storage, and visualization.

8. The PCBA carrier board testing method for body- smart controller according to claim 7, wherein, When the module signal conversion module outputs test commands to the PCBA carrier board under test, it transmits all 699 pin signals of the NVIDIA module one-to-one without loss through the module signal conversion module, thereby realizing signal bridging between the NVIDIA module and the PCBA carrier board under test.

9. The PCBA carrier board testing method for a personal intelligent controller according to claim 7, characterized in that, After the high-precision data acquisition module synchronously acquires the original operating data in real time, it also includes time-series binding and data alignment preprocessing of the acquired multi-channel data, binding the device operating data and loop status data in a one-to-one time sequence correspondence.

10. The PCBA carrier board testing method for a personal intelligent controller according to claim 7, characterized in that, When the host computer test management module performs comparison and analysis, it calls the built-in intelligent dedicated test algorithm model to perform dynamic difference determination, timing response determination and multiple fluctuation stability determination on the PCBA carrier board under test. When the result output and storage module performs data solidification and storage, it archives the original data, process data, operating parameters and fault logs of a single test in the entire chain, supporting full-process traceability of test data.

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