Method and apparatus for determining lifetime of diode chip, and electronic device

Abstract

This invention discloses a method, apparatus, and electronic device for determining the lifetime of a diode chip. The method includes: controlling a predetermined number of heating power cycles on a transistor chip in a power module, causing the diode chip in the power module to withstand a first junction temperature fluctuation amplitude due to thermal coupling; controlling a predetermined number of heating power cycles on a diode chip in a pre-damage state due to junction temperature fluctuation to obtain a first failure lifetime; and controlling a predetermined number of heating power cycles on a diode chip not in a pre-damage state due to junction temperature fluctuation to obtain a second failure lifetime; and determining a target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on a linear cumulative damage function, a predetermined number of cycles, the first failure lifetime, and the second failure lifetime. This invention solves the technical problem of low device lifetime acquisition efficiency caused by long power cycle testing cycles and high testing costs under low junction temperature fluctuations.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a method, apparatus, and electronic device for determining the lifetime of a diode chip. Background Technology

[0002] In the context of new power systems, new energy sources such as wind power and photovoltaics are being integrated into the power system at an explosive growth rate, leading to the widespread use of power electronic equipment such as converters. Power semiconductor devices are key components of power electronic equipment, but also the most prone to failure. Statistics show that failures caused by power semiconductor devices account for 31% of all failures in the power system. Therefore, to ensure the reliability of new energy grid connection and the safe and stable operation of the power grid, it is urgent to conduct reliability assessments and lifetime predictions for power semiconductor devices. In lifetime prediction methods based on lifetime models, establishing a lifetime model for the device based on power cycle test lifetime data is the most crucial step, directly affecting the accuracy of the lifetime prediction results.

[0003] Currently widely used lifetime models typically involve power cycling tests under high junction temperature fluctuations, and the lifetime model is built based on the relevant test data. However, using lifetime models built from test data under high junction temperature fluctuations to evaluate the lifetime of devices under low junction temperature fluctuations is inaccurate. Furthermore, since device lifetime is inversely proportional to the amplitude of junction temperature fluctuations, and device lifetime under low junction temperature fluctuations exhibits a power function growth trend, directly conducting power cycling tests under low junction temperature fluctuations requires extremely long testing times. This results in the technical problem of low efficiency in obtaining device lifetime data due to the long testing cycle and high testing cost of power cycling tests under low junction temperature fluctuations.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This invention provides a method, apparatus, and electronic device for determining the lifetime of a diode chip, in order to at least solve the technical problem of low efficiency in obtaining device lifetime due to long power cycle testing cycles and high testing costs under low junction temperature fluctuations.

[0006] According to one aspect of the present invention, a method for determining the lifetime of a diode chip is provided, comprising: controlling a predetermined number of heating power cycles on a transistor chip in a power module, causing the diode chip in the power module to experience a first junction temperature fluctuation amplitude due to thermal coupling effect, thereby obtaining a diode chip in a junction temperature fluctuation pre-damage state; controlling a predetermined heating power cycle on the diode chip in the junction temperature fluctuation pre-damage state to obtain a first failure lifetime when the diode chip reaches a preset aging failure condition; and controlling a predetermined heating power cycle on a diode chip not in the junction temperature fluctuation pre-damage state to obtain a second failure lifetime. The second failure lifetime of the diode chip when it reaches the preset aging failure condition, wherein the preset condition is that the junction temperature fluctuation of the diode chip is the second junction temperature fluctuation amplitude, and the first junction temperature fluctuation amplitude is less than the second junction temperature fluctuation amplitude; based on the linear cumulative damage function, the predetermined number of times, the first failure lifetime and the second failure lifetime, the target lifetime of the diode chip under the first junction temperature fluctuation amplitude is determined, wherein the linear cumulative damage function includes a function in which the sum of the first term and the second term is one, the first term is the ratio of the predetermined number of times term to the target lifetime term, and the second term is the ratio of the first failure lifetime term to the second failure lifetime term.

[0007] Optionally, controlling the diode chip in the pre-damage state of junction temperature fluctuation to perform heating power cycling under predetermined conditions to obtain the first failure lifetime when the diode chip reaches the preset aging failure condition includes: during the process of controlling the diode chip in the pre-damage state of junction temperature fluctuation to perform heating power cycling under predetermined conditions, collecting the forward voltage drop and junction temperature data of the diode chip in real time; based on the real-time collected forward voltage drop and junction temperature data, using a sequential particle filter algorithm to track the degradation state of the diode chip online; when the degradation state indicates that the cumulative damage of the diode chip reaches a preset threshold, terminating the heating power cycling, and taking the current number of cycles as the first failure lifetime.

[0008] Optionally, before controlling the heating power cycle of the transistor chip in the power module to be performed a predetermined number of times, so that the diode chip in the power module is subjected to a first junction temperature fluctuation amplitude due to thermal coupling effect, and the diode chip is obtained in a pre-damage state due to junction temperature fluctuation, the method further includes: constructing a digital twin model of the power module, wherein the digital twin model includes thermal coupling path parameters between the transistor chip and the diode chip; simulating the junction temperature fluctuation amplitude and cumulative damage degree of the diode chip under different heating power cycle numbers using the digital twin model, and determining the target predetermined number of times required for the diode chip to reach the target pre-damage degree; and executing the heating power cycle using the target predetermined number of times as the predetermined number of times.

[0009] Optionally, determining the target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on the linear cumulative damage function, the predetermined number of times, the first failure lifetime, and the second failure lifetime includes: acquiring a physical information neural network model, wherein the physical information neural network takes the material properties, packaging geometry parameters, and the first and second junction temperature fluctuation amplitudes of the transistor chip and the diode chip as inputs, the weight coefficients of the first and second terms in the linear cumulative damage function as outputs, and the historical failure data of the power cycle test of the power module model as constraints; determining the target weight coefficients corresponding to the first and second terms in the linear cumulative damage function based on the physical information neural network model; and determining the target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on the linear cumulative damage function with corresponding target weight coefficients, the predetermined number of times, the first failure lifetime, and the second failure lifetime.

[0010] Optionally, determining the target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on the linear cumulative damage function, the predetermined number of failures, the first failure lifetime, and the second failure lifetime includes: when the preset aging failure conditions include a first failure condition and a second failure condition, obtaining the on-state voltage drop and thermal resistance of the diode chip at the first failure lifetime and the second failure lifetime, wherein the first failure condition is that the increase in the on-state voltage drop of the diode chip reaches a first preset threshold, used to characterize bond wire failure; the second failure condition is that the increase in the thermal resistance of the diode chip reaches a second preset threshold, used to characterize solder aging; comparing the order in which the first remaining space and the second remaining space reach zero based on the first remaining space between the on-state voltage drop and the first preset threshold corresponding to the first failure condition, and the second remaining space between the thermal resistance and the second preset threshold corresponding to the second failure condition, to determine the target failure mode characterized by the parameter that first reaches the corresponding failure condition; and retrieving the damage accumulation function parameter corresponding to the target failure mode.

[0011] Optionally, determining the target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on the linear cumulative damage function, the predetermined number of times, the first failure lifetime, and the second failure lifetime includes: obtaining the thermal coupling coefficient between the transistor chip and the diode chip; correcting the first junction temperature fluctuation amplitude based on the thermal coupling coefficient to obtain a corrected junction temperature fluctuation amplitude; and determining the target lifetime of the diode chip under the corrected junction temperature fluctuation amplitude based on the linear cumulative damage function, the predetermined number of times, the first failure lifetime, and the second failure lifetime.

[0012] Optionally, controlling the heating power cycle of the transistor chip in the power module to be performed a predetermined number of times, so that the diode chip in the power module is subjected to a first junction temperature fluctuation amplitude due to thermal coupling effect, and the diode chip is in a pre-damage state of junction temperature fluctuation, includes: obtaining the highest and lowest junction temperature values ​​of the diode chip within the heating power cycle of the transistor chip; and using the difference between the highest and lowest junction temperature values ​​as the first junction temperature fluctuation amplitude.

[0013] According to one aspect of the present invention, a device for determining the lifetime of a diode chip is provided, comprising: a first control module, configured to control heating power cycling of a transistor chip in a power module for a predetermined number of times, causing the diode chip in the power module to withstand a first junction temperature fluctuation amplitude due to thermal coupling effect, thereby obtaining a diode chip in a junction temperature fluctuation pre-damage state; and a second control module, configured to control heating power cycling of the diode chip in the junction temperature fluctuation pre-damage state under predetermined conditions, thereby obtaining a first failure lifetime when the diode chip reaches a preset aging failure condition, and to control heating power cycling of the diode chip not in the junction temperature fluctuation pre-damage state under the predetermined conditions. A ring is formed to obtain the second failure lifetime of the diode chip when it reaches the preset aging failure condition, wherein the preset condition is that the junction temperature fluctuation of the diode chip is the second junction temperature fluctuation amplitude, and the first junction temperature fluctuation amplitude is less than the second junction temperature fluctuation amplitude; a determining module is used to determine the target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on a linear cumulative damage function, the predetermined number of times, the first failure lifetime and the second failure lifetime, wherein the linear cumulative damage function includes a function in which the sum of a first term and a second term is one, the first term is the ratio of the predetermined number of times term to the target lifetime term, and the second term is the ratio of the first failure lifetime term to the second failure lifetime term.

[0014] According to one aspect of the present invention, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the diode chip lifetime determination method described in any of the preceding claims.

[0015] According to one aspect of the present invention, a computer-readable storage medium is provided, wherein when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the diode chip lifetime determination method described in any of the preceding claims.

[0016] In this embodiment of the invention, the transistor chip in the power module is subjected to a predetermined number of heating power cycles, causing the diode chip in the power module to experience a first junction temperature fluctuation amplitude due to thermal coupling effect, resulting in a diode chip in a junction temperature fluctuation pre-damage state. The diode chip in the junction temperature fluctuation pre-damage state is then subjected to heating power cycles under predetermined conditions to obtain a first failure lifetime when the diode chip reaches a preset aging failure condition. Furthermore, the diode chip not in the junction temperature fluctuation pre-damage state is subjected to heating power cycles under predetermined conditions to obtain a second failure lifetime when the diode chip reaches a preset aging failure condition. The predetermined condition is that the junction temperature fluctuation of the diode chip is the second junction temperature fluctuation amplitude, and the first junction temperature fluctuation amplitude is less than the second junction temperature fluctuation amplitude. Based on a linear cumulative damage function, a predetermined number of cycles, the first failure lifetime, and the second failure lifetime, a target lifetime for the diode chip under the first junction temperature fluctuation amplitude is determined. The linear cumulative damage function includes a function whose sum is one of a first term and a second term. The first term is the ratio of the predetermined number of cycles to the target lifetime term, and the second term is the ratio of the first failure lifetime term to the second failure lifetime term. By employing a thermally coupled pre-damage combined with two-stage testing, the target lifetime is determined by using a linear cumulative damage function and a predetermined number of failures, along with the first and second failure lifetimes. This achieves the goal of determining the target lifetime of the diode chip under the first junction temperature fluctuation amplitude. In other words, the target lifetime is obtained by using the damage ratio between pre-damage under the first junction temperature fluctuation amplitude and accelerated failure under the second junction temperature fluctuation amplitude, without the need for long-term testing under low junction temperature fluctuations. This solves the technical problem of low device lifetime acquisition efficiency caused by long power cycle testing cycles and high testing costs under low junction temperature fluctuations. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0018] Figure 1 This is a flowchart of a method for determining the lifetime of a diode chip according to an embodiment of the present invention.

[0019] Figure 2 This is an infrared temperature measurement image of one phase bridge arm in a three-phase full-bridge module provided by an optional embodiment of the present invention.

[0020] Figure 3 This is a flowchart of obtaining the power cycle lifetime of an FRD chip under low junction temperature fluctuations, provided by an optional embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the FRD chip damage process provided by an optional embodiment of the present invention.

[0022] Figure 5 This is a SAM diagram of the device for testing provided by an optional embodiment of the present invention.

[0023] Figure 6 This is a structural block diagram of a diode chip lifetime determination device according to an embodiment of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] Example 1

[0027] According to an embodiment of the present invention, an embodiment of a method for determining the lifetime of a diode chip is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0028] Figure 1 This is a flowchart of a method for determining the lifetime of a diode chip according to an embodiment of the present invention, such as... Figure 1 As shown, the method includes the following steps:

[0029] Step S102: Control the heating power cycle of the transistor chip in the power module to be performed a predetermined number of times, so that the diode chip in the power module can withstand the first junction temperature fluctuation amplitude due to the thermal coupling effect, and obtain the diode chip in the junction temperature fluctuation pre-damage state.

[0030] Among them, power modules refer to semiconductor devices that encapsulate multiple chips in parallel within a single housing, enabling them to carry large currents. For example, in a three-phase full-bridge module, multiple IGBT chips and FRD chips are encapsulated in parallel on the same copper plate.

[0031] Among them, transistor chips and IGBT chips refer to active switching devices in power modules that act as heat sources and can generate heat by being energized, such as insulated gate bipolar transistor chips.

[0032] Among them, diode chips and FRD chips refer to passive semiconductor devices in power modules that have a thermal coupling effect with transistor chips. They can withstand the heat from transistor chips and generate junction temperature fluctuations, such as fast recovery diode chips.

[0033] Among them, thermal coupling effect refers to the phenomenon in power modules where multiple chips are connected in parallel on the same conductive substrate, and the heat generated by the heat-generating chip is conducted to the adjacent chips through thermal diffusion. This can cause passive junction temperature fluctuations in diode chips that do not actively generate heat. For example, FRD chips can withstand thermal coupling temperatures of up to 95°C due to the heat generated by IGBT chips.

[0034] The first junction temperature fluctuation amplitude refers to the passive junction temperature change amplitude that the diode chip passively experiences through thermal coupling due to the heating power cycle of the transistor chip. This can be called low junction temperature fluctuation, and its amplitude is lower than the high-amplitude junction temperature change amplitude used in subsequent active testing. For example, the 30K junction temperature fluctuation amplitude experienced by the FRD chip due to thermal coupling of the IGBT chip. It should be noted that high junction temperature fluctuation can refer to test conditions where ΔTvj ≥ 60℃, and low junction temperature fluctuation can refer to test conditions where ΔTvj < 60℃.

[0035] Among them, the junction temperature fluctuation pre-damage state refers to the state of the diode chip after it has accumulated damage due to the first junction temperature fluctuation amplitude.

[0036] In this step, the transistor chip in the power module is subjected to a predetermined number of heating power cycles. Utilizing the thermal coupling effect, the diode chip passively withstands the first junction temperature fluctuation amplitude without active heating, resulting in a diode chip in a pre-damage state due to junction temperature fluctuation. This step eliminates the need for direct low junction temperature fluctuation testing of the diode chip. Instead, it utilizes the thermal coupling effect during transistor chip heating to passively subject the diode chip to low junction temperature fluctuation pre-damage, providing necessary pre-damage samples for subsequent inference of the target lifetime through linear cumulative damage.

[0037] Step S104: Control the diode chip in the pre-damage state of junction temperature fluctuation to cycle the heating power under predetermined conditions to obtain the first failure lifetime when the diode chip reaches the preset aging failure condition, and control the diode chip not in the pre-damage state of junction temperature fluctuation to cycle the heating power under predetermined conditions to obtain the second failure lifetime when the diode chip reaches the preset aging failure condition, wherein the predetermined condition is that the junction temperature fluctuation of the diode chip is the second junction temperature fluctuation amplitude, and the first junction temperature fluctuation amplitude is less than the second junction temperature fluctuation amplitude.

[0038] The predetermined conditions refer to the junction temperature fluctuation conditions that must be met when the diode chip is subjected to heating power cycling, specifically the junction temperature fluctuation of the diode chip being the second junction temperature fluctuation amplitude.

[0039] The second junction temperature fluctuation amplitude refers to the junction temperature change amplitude generated when the diode chip actively heats up by the current flowing through it. This amplitude is greater than the first junction temperature fluctuation amplitude and can be called high junction temperature fluctuation, such as the 90K junction temperature fluctuation amplitude generated by the FRD chip itself when it is powered on and heated.

[0040] Among them, the preset aging failure condition refers to the pre-set criteria used to determine whether the diode chip has reached the aging failure state.

[0041] The first failure lifetime refers to the number of cycles a diode chip that has already suffered pre-damage from junction temperature fluctuations undergoes when heated under the second junction temperature fluctuation amplitude until it reaches the preset aging failure condition. For example, the average lifetime of 14,324 cycles obtained by testing an FRD chip that has already suffered 50,000 cycles of 30K thermal coupling pre-damage under a 90K junction temperature fluctuation.

[0042] Among them, "not in a state of pre-damage due to junction temperature fluctuations" means that the diode chip has not suffered any pre-damage due to junction temperature fluctuations caused by thermal coupling effects.

[0043] The second failure lifetime refers to the number of cycles a diode chip that has not been subjected to pre-damage from junction temperature fluctuations undergoes when heated under the second junction temperature fluctuation amplitude until it reaches the preset aging failure condition. For example, the average lifetime of 23,595 cycles obtained by testing an FRD chip that is not affected by thermal coupling under a junction temperature fluctuation of 90K.

[0044] In this step, both the diode chip that has undergone pre-damage and the diode chip that has not undergone pre-damage are subjected to heating power cycling tests under the same second junction temperature fluctuation amplitude, resulting in two sets of failure lifetime data. This step utilizes the short failure cycle characteristic under high junction temperature fluctuations to obtain two sets of key data for calculating the linear cumulative damage function in a relatively short time, avoiding the need for prolonged testing directly under low junction temperature fluctuations.

[0045] Step S106: Based on the linear cumulative damage function, the predetermined number of failures, the first failure lifetime, and the second failure lifetime, determine the target lifetime of the diode chip under the first junction temperature fluctuation amplitude. The linear cumulative damage function includes a function in which the sum of the first term and the second term is one. The first term is the ratio of the predetermined number of failures to the target lifetime term, and the second term is the ratio of the first failure lifetime term to the second failure lifetime term.

[0046] The linear cumulative damage function refers to the functional relationship used to characterize the damage generated by a diode chip under different junction temperature fluctuation amplitudes, which can be linearly accumulated according to the number of cycles, and the chip fails when the total accumulated damage reaches one.

[0047] The target lifetime refers to the desired power cycle life of the diode chip under the first junction temperature fluctuation amplitude.

[0048] In this step, the target lifetime of the diode chip under the first junction temperature fluctuation amplitude is calculated and determined based on the linear cumulative damage function, the predetermined number of tests obtained in step S102, and the first and second failure lifetimes obtained in step S104. This step eliminates the need for prolonged testing under the first junction temperature fluctuation amplitude until failure; the target lifetime can be calculated by using the linear cumulative damage law, effectively shortening the lifetime acquisition time and reducing testing costs.

[0049] Through the above steps S102-S106, the power module controls the transistor chip to undergo a predetermined number of heating power cycles, causing the diode chip in the power module to withstand the first junction temperature fluctuation amplitude due to thermal coupling effect, resulting in a diode chip in a junction temperature fluctuation pre-damage state; the power module controls the diode chip in the junction temperature fluctuation pre-damage state to undergo a predetermined condition of heating power cycles, resulting in a first failure lifetime when the diode chip reaches a preset aging failure condition; and the power module controls the diode chip not in the junction temperature fluctuation pre-damage state to undergo a predetermined condition of heating power cycles, resulting in a second failure lifetime when the diode chip reaches a preset aging failure condition. The predetermined condition is that the junction temperature fluctuation of the diode chip is the second junction temperature fluctuation amplitude, and the first junction temperature fluctuation amplitude is less than the second junction temperature fluctuation amplitude. Based on the linear cumulative damage function, the predetermined number of cycles, the first failure lifetime, and the second failure lifetime, the target lifetime of the diode chip under the first junction temperature fluctuation amplitude is determined. The linear cumulative damage function includes a function whose first term and second term sum to one, where the first term is the ratio of the predetermined number of cycles to the target lifetime term, and the second term is the ratio of the first failure lifetime term to the second failure lifetime term. By employing a thermally coupled pre-damage combined with two-stage testing, the target lifetime is determined by using a linear cumulative damage function and a predetermined number of failures, along with the first and second failure lifetimes. This achieves the goal of determining the target lifetime of the diode chip under the first junction temperature fluctuation amplitude. In other words, the target lifetime is obtained by using the damage ratio between pre-damage under the first junction temperature fluctuation amplitude and accelerated failure under the second junction temperature fluctuation amplitude, without the need for long-term testing under low junction temperature fluctuations. This solves the technical problem of low device lifetime acquisition efficiency caused by long power cycle testing cycles and high testing costs under low junction temperature fluctuations.

[0050] As an optional embodiment, controlling the heating power cycle of a diode chip in a pre-damage state with junction temperature fluctuations under predetermined conditions to obtain the first failure lifetime when the diode chip reaches the preset aging failure condition includes: during the process of controlling the heating power cycle of the diode chip in a pre-damage state with predetermined conditions, collecting the forward voltage drop and junction temperature data of the diode chip in real time; based on the real-time collected forward voltage drop and junction temperature data, using a sequential particle filter algorithm to track the degradation state of the diode chip online; when the degradation state indicates that the cumulative damage of the diode chip reaches a preset threshold, terminating the heating power cycle, and taking the current number of cycles as the first failure lifetime.

[0051] Among them, forward voltage drop refers to the voltage drop between the anode and cathode of a diode chip when it is in the conducting state. It can reflect the degree of degradation of the bonding wires and solder layers inside the chip. For example, when the bonding wires crack due to thermal cycling fatigue, the forward voltage drop will gradually increase.

[0052] Junction temperature data refers to the temperature value of the PN junction region inside the diode chip, which can reflect the thermal state of the chip during power cycling. For example, the chip junction temperature can be obtained through thermistor method or infrared thermometry.

[0053] Among them, the sequential particle filter algorithm refers to a nonlinear non-Gaussian state tracking algorithm based on Bayesian estimation and Monte Carlo simulation. It can process real-time acquired observation data online and dynamically update the system state estimate. For example, the particle filter algorithm can be used to recursively estimate the device degradation state.

[0054] Among them, the degradation state refers to the degree to which the performance of a diode chip gradually deteriorates due to cumulative damage, such as the trend of the on-state voltage drop gradually increasing with the number of cycles.

[0055] The preset threshold refers to a pre-set critical value used to determine that the cumulative damage of the diode chip has reached the threshold at which the test needs to be terminated. For example, when the cumulative damage value reaches 0.9, it is determined that the preset threshold has been reached.

[0056] The current number of cycles refers to the total number of power cycles that the diode chip has experienced at the moment the heating power cycle is terminated. This number is the value of the first failure lifetime.

[0057] In this embodiment, during the high junction temperature fluctuation heating power cycle of a diode chip in a pre-damage state, the on-state voltage drop and junction temperature data are collected in real time. A sequential particle filter algorithm is used to track the degradation state online. When the accumulated damage reaches a preset threshold, the test is terminated early, and the current number of cycles is taken as the first failure lifetime. This method utilizes the real-time filtering capability of the sequential particle filter algorithm to recursively process the observed data and dynamically update the state estimate. This allows for earlier identification of whether the device has reached the effective failure threshold compared to traditional methods that rely on empirical thresholds or simple statistical inference. By terminating the test earlier while ensuring the accuracy of the test results, the test time is further shortened and the test efficiency is improved.

[0058] As an optional embodiment, before controlling the heating power cycle of the transistor chip in the power module to be performed a predetermined number of times, so that the diode chip in the power module is subjected to a first junction temperature fluctuation amplitude due to thermal coupling effect, and the diode chip is obtained in a pre-damage state due to junction temperature fluctuation, the method further includes: constructing a digital twin model of the power module, wherein the digital twin model includes thermal coupling path parameters between the transistor chip and the diode chip; simulating the junction temperature fluctuation amplitude and cumulative damage degree of the diode chip under different heating power cycle numbers through the digital twin model, determining the target predetermined number of times required for the diode chip to reach the target pre-damage degree; and performing the heating power cycle with the target predetermined number of times as the predetermined number of times.

[0059] Among them, the digital twin model refers to a virtual simulation model that is constructed based on physical information and measured data and is mapped one-to-one with the real power module. It can reflect the physical state change process inside the power module, such as a multiphysics simulation model that includes electrothermal coupling path and thermal stress distribution parameters.

[0060] Among them, thermal coupling path parameters refer to the physical parameters that describe the transmission path of heat inside the power module from the heat-generating chip through the conductive substrate and other media to the adjacent chips, such as thermal conductivity, thermal resistance, thermal capacity and chip spacing.

[0061] The target pre-damage level refers to the pre-set cumulative damage level that the diode chip is expected to reach by withstanding the first junction temperature fluctuation amplitude, and is used to determine when the pre-damage stage should be terminated.

[0062] The target predetermined number of cycles refers to the optimal number of heating power cycles required to bring the diode chip to the target pre-damage level, as determined by simulation using a digital twin model. This number is then used as the predetermined number of cycles in subsequent steps.

[0063] In this embodiment, before performing the transistor chip heating power cycle, a digital twin model of the power module is first constructed. By simulating the junction temperature fluctuation amplitude and cumulative damage degree of the diode chip under different cycle numbers, the optimal predetermined number of cycles required for the diode chip to reach the target pre-damage degree is determined. This method utilizes a digital twin model to pre-simulate and optimize the pre-damage process, avoiding problems such as insufficient pre-damage (failing to effectively reflect low-fluctuation damage characteristics) or excessive pre-damage (leading to excessively short lifespans in subsequent high-fluctuation tests and increased testing errors), which can occur when setting a predetermined number of cycles based solely on experience. This makes the pre-damage degree in the first step more controllable and accurate, thereby improving the reliability of the final target lifespan estimation result.

[0064] As an optional embodiment, determining the target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on the linear cumulative damage function, a predetermined number of times, a first failure lifetime, and a second failure lifetime includes: acquiring a physical information neural network model, wherein the physical information neural network takes the material properties, packaging geometry parameters, and the first and second junction temperature fluctuation amplitudes of the transistor chip and the diode chip as inputs, the weight coefficients of the first and second terms in the linear cumulative damage function as outputs, and the historical failure data of the power cycle test of the power module model as constraints; determining the target weight coefficients corresponding to the first and second terms in the linear cumulative damage function based on the physical information neural network model; and determining the target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on the linear cumulative damage function with corresponding target weight coefficients, a predetermined number of times, the first failure lifetime, and the second failure lifetime.

[0065] Among them, physical information neural networks refer to deep learning models that embed physical laws or prior physical knowledge as constraints into the neural network architecture. They can use physical information to constrain the network output to conform to physical laws. For example, a linear cumulative damage function can be embedded into the neural network as a physical constraint.

[0066] Material properties refer to the physical characteristics of the semiconductor materials and packaging materials used in transistor chips and diode chips, such as the coefficient of thermal expansion, elastic modulus, and thermal conductivity.

[0067] Among them, the packaging geometry parameters refer to the packaging structure and size parameters of the power module, such as chip thickness, solder layer thickness, bonding wire arc height and length, chip spacing, etc.

[0068] The weighting coefficient, in the linear cumulative damage function, is a multiplier factor used to adjust the contribution ratio of the first and second terms to the total damage, and can reflect the difference in the actual damage accumulation rate under different junction temperature fluctuation amplitudes.

[0069] Historical failure data refers to the failure lifetime data accumulated from existing power cycle tests on the same type of power module. It is used to constrain the training process of the neural network to ensure the physical rationality of the output results.

[0070] In this embodiment, a physical information neural network model is obtained, trained with material properties, packaging geometry parameters, and junction temperature fluctuation amplitude as inputs, and the weight coefficients of the first and second terms as outputs, constrained by historical failure data. This model is used to determine the target weight coefficients for the first and second terms, and then the target lifetime is calculated based on a linear cumulative damage function with set target weight coefficients. This approach introduces a physical information neural network to perform data-driven optimization of the weight coefficients of the two terms in the linear cumulative damage function. This allows the damage contribution under different junction temperature fluctuation amplitudes to be adaptively allocated according to the actual physical characteristics of the device, rather than using a simple form where the sum of the two ratios equals one. This improves the accuracy of lifetime estimation across amplitude ranges and its universality for different power module models.

[0071] As an optional embodiment, the target lifetime of the diode chip under a first junction temperature fluctuation amplitude is determined based on a linear cumulative damage function, a predetermined number of failures, a first failure lifetime, and a second failure lifetime. This includes: when preset aging failure conditions include a first failure condition and a second failure condition, obtaining the on-state voltage drop and thermal resistance of the diode chip at the first failure lifetime and the second failure lifetime, wherein the first failure condition is that the increase in the on-state voltage drop of the diode chip reaches a first preset threshold, used to characterize bond wire failure; the second failure condition is that the increase in the thermal resistance of the diode chip reaches a second preset threshold, used to characterize solder aging; based on a first remaining space between the on-state voltage drop and the first preset threshold corresponding to the first failure condition, and a second remaining space between the thermal resistance and the second preset threshold corresponding to the second failure condition, comparing the order in which the first remaining space and the second remaining space reach zero, determining the target failure mode characterized by the parameter that first reaches the corresponding failure condition; and retrieving the damage accumulation function parameter corresponding to the target failure mode.

[0072] The first failure condition refers to the preset aging failure condition in which the increase in on-state voltage drop reaches a first preset threshold as the condition for determining that the bonding wire of the diode chip has failed.

[0073] The second failure condition refers to the preset aging failure condition in which the increase in thermal resistance reaches a second preset threshold as the condition for determining that the diode chip has undergone solder aging.

[0074] Among them, bonding wire failure refers to the failure mode in which the aluminum or copper bonding wires connecting the chip and the external terminal in the power module crack or even break due to the accumulation of thermal cycling stress. This failure mode is mainly affected by the junction temperature fluctuation amplitude and is characterized by the increase of the on-state voltage drop.

[0075] Solder aging refers to the failure mode in which fatigue cracks occur in the solder layer between the chip and the substrate in the power module due to the accumulation of thermal cycling stress. This failure mode is mainly affected by the junction temperature fluctuation amplitude and the maximum junction temperature, and is characterized by the increase of thermal resistance.

[0076] The increase in on-state voltage drop refers to the difference or relative percentage change between the current value and the initial value of the on-state voltage drop, which is used to quantify the degree of bond line degradation.

[0077] The increase in thermal resistance refers to the difference or relative percentage change between the current value and the initial value of thermal resistance, which is used to quantify the degree of solder layer degradation.

[0078] The first preset threshold and the second preset threshold refer to the pre-set critical values ​​for the increase in conduction voltage drop and the increase in thermal resistance. When the monitored value reaches the corresponding critical value, it is determined that the failure mode has occurred, for example, the increase in conduction voltage drop reaches 5% of the initial value or the increase in thermal resistance reaches 20% of the initial value.

[0079] The first remaining space refers to the difference between the current increase in the forward voltage drop and the first preset threshold, reflecting how much margin the bonding wire of the diode chip still has before reaching the bonding wire failure critical point in the current state.

[0080] The second remaining space refers to the difference between the current increase in thermal resistance and the second preset threshold, reflecting how much margin the solder layer of the diode chip still has before reaching the solder aging critical point in its current state.

[0081] Among them, the damage accumulation function parameter refers to the parameter value in the linear cumulative damage function corresponding to a specific failure mode. The damage accumulation rate is different under different failure modes, and the corresponding function parameters are also different.

[0082] In this embodiment, when the preset aging failure conditions simultaneously include a first failure condition corresponding to the on-state voltage drop and a second failure condition corresponding to the thermal resistance, the on-state voltage drop and thermal resistance corresponding to the diode chip at the first and second failure lifetimes are obtained. The order in which the first remaining space corresponding to the on-state voltage drop and the second remaining space corresponding to the thermal resistance reach zero is compared to determine the target failure mode represented by the parameter that first reaches the corresponding failure condition. Then, the damage accumulation function parameter corresponding to the target failure mode is retrieved. By introducing a competitive judgment mechanism that simultaneously monitors both on-state voltage drop and thermal resistance, it is possible to distinguish whether the actual failure mode is bond wire failure or solder aging. Because the order in which the two failure modes occur is not fixed under different test conditions or device structures, for example, bond wire failure may be insignificant and solder aging may dominate under low junction temperature fluctuations, while the opposite may be true under high junction temperature fluctuations. Therefore, the damage accumulation function parameter that matches the target failure mode is selected to calculate the target lifetime, avoiding the lifetime estimation deviation caused by applying a single failure model to all situations, and improving the actual accuracy of the target lifetime estimation results under low junction temperature fluctuations.

[0083] As an optional embodiment, determining the target lifetime of the diode chip under a first junction temperature fluctuation amplitude based on a linear cumulative damage function, a predetermined number of times, a first failure lifetime, and a second failure lifetime includes: obtaining the thermal coupling coefficient between the transistor chip and the diode chip; correcting the first junction temperature fluctuation amplitude based on the thermal coupling coefficient to obtain a corrected junction temperature fluctuation amplitude; and determining the target lifetime of the diode chip under the corrected junction temperature fluctuation amplitude based on the linear cumulative damage function, a predetermined number of times, the first failure lifetime, and the second failure lifetime.

[0084] The thermal coupling coefficient is a physical quantity that quantifies the thermal coupling strength between a transistor chip and a diode chip. It is determined by measuring the ratio of the junction temperature change of the diode chip to the junction temperature change of the transistor chip during the heating power cycle of the transistor chip. For example, when the junction temperature of the IGBT chip changes by 80K and the junction temperature of the FRD chip changes by 30K, the thermal coupling coefficient is 0.375.

[0085] In this embodiment, the thermal coupling coefficient between the transistor chip and the diode chip is obtained. The first junction temperature fluctuation amplitude is corrected based on the thermal coupling coefficient to obtain the corrected junction temperature fluctuation amplitude. Then, the target lifetime is determined based on the linear cumulative damage function and the corrected junction temperature fluctuation amplitude. This method uses the thermal coupling coefficient to correct the directly measured first junction temperature fluctuation amplitude, eliminating measurement deviations caused by differences in different power module packaging structures, such as chip spacing, substrate materials, and heat dissipation conditions. This ensures that the final determined target lifetime accurately corresponds to the actual lifetime of the diode chip under the first junction temperature fluctuation amplitude, rather than the nominal value before correction. This improves the applicability of the method to power modules with different packaging structures and the accuracy of the target lifetime estimation results.

[0086] As an optional embodiment, controlling the heating power cycle of the transistor chip in the power module to be performed a predetermined number of times, so that the diode chip in the power module is subjected to a first junction temperature fluctuation amplitude due to thermal coupling effect, and the diode chip is obtained in a pre-damage state of junction temperature fluctuation, including: obtaining the highest and lowest junction temperature values ​​of the diode chip within the heating power cycle of the transistor chip; and using the difference between the highest and lowest junction temperature values ​​as the first junction temperature fluctuation amplitude.

[0087] Among them, the highest junction temperature refers to the maximum junction temperature reached by the diode chip due to thermal coupling effect within one heating power cycle of the transistor chip.

[0088] The lowest junction temperature refers to the minimum junction temperature reached by the diode chip due to thermal coupling effect within one heating power cycle of the transistor chip, which usually occurs at the end of the cooling phase.

[0089] In this embodiment, within the heating power cycle of the transistor chip, the highest and lowest junction temperatures of the diode chip are obtained, and the difference between them is used as the first junction temperature fluctuation amplitude. This method clarifies the specific way to obtain the first junction temperature fluctuation amplitude: it is directly determined by the difference between the measured highest and lowest junction temperatures within each heating power cycle, rather than through thermal simulation estimation or empirical formula deduction. This ensures the accuracy and repeatability of the measured first junction temperature fluctuation amplitude, providing an accurate input data foundation for subsequent linear cumulative damage function calculations.

[0090] Based on the above embodiments and optional embodiments, an optional implementation method is provided, which is described in detail below.

[0091] In related technologies, test lifetimes are typically long under low junction temperature fluctuation conditions, leading to longer testing times and higher testing costs. For example... Figure 1 As shown, when the junction temperature fluctuation decreases from 80K to 60K, the test lifetime increases to 3.6 times that under the 80K condition. Based on the test cycle, the increased test time is approximately 6... (250000 3.6-250000) / (24 60 60)≈45 (days).

[0092] In view of this, an optional embodiment of the present invention provides a method for obtaining the power cycle test lifetime of a power semiconductor device under low junction temperature fluctuations, which can effectively shorten the test time of the device under low junction temperature fluctuations and reduce the test cost. Figure 2 This is an infrared temperature measurement image of one phase bridge arm in a three-phase full-bridge module provided by an optional embodiment of the present invention. Figure 3 This is a flowchart of obtaining the power cycle lifetime of an FRD chip under low junction temperature fluctuations, provided by an optional embodiment of the present invention. Figure 4 This is a schematic diagram of the FRD chip damage process provided by an optional embodiment of the present invention. Figure 5 This is a SAM diagram of the tested device provided by an optional embodiment of the present invention. It is described in detail below:

[0093] An optional embodiment of this invention proposes a method for obtaining the power cycle lifetime of a device under low junction temperature fluctuations based on thermal coupling. To achieve high current carrying capacity of the device, it is currently widely adopted to package multiple chips in parallel into a single module, such as... Figure 2 As shown in the figure, the infrared thermogram of one phase arm in a three-phase full-bridge module is displayed. The figure shows that each upper and lower arm of the same phase has three IGBT chips and three FRD chips. During actual operation, when the three IGBT chips generate heat, because the IGBTs and FRD chips are connected in parallel on the same copper plate, heat diffusion causes the FRD chips to be affected by the coupling temperature of the IGBTs. The figure shows that the three FRD chips closest to the IGBTs are all affected by the thermal coupling temperature, with the highest coupling temperature on the chips reaching over 95℃.

[0094] Therefore, during IGBT power cycling testing, the adjacent FRD chip, affected by thermal coupling temperature, also undergoes power cycling under low junction temperature fluctuations, generating thermal stress, leading to device aging and a decrease in overall lifespan. In this case, performing high junction temperature fluctuation power cycling testing on the FRD will result in a shorter lifespan compared to the FRD under the same test conditions without thermal coupling. According to the linear damage accumulation law, we can inversely deduce the FRD chip's test lifespan under thermal coupling temperature (i.e., low junction temperature fluctuation power cycling test lifespan) from its power cycling test lifespan under high junction temperature fluctuations. Figure 3 A flowchart illustrating the power cycle lifetime acquisition process for FRD chips under low junction temperature fluctuations is presented.

[0095] Assuming FRD experiences low junction temperature fluctuations Δ T vj_low The test lifespan is as follows: N f-FRD-low .

[0096] 1) Conduct IGBT heating power cycling, with the number of cycles being NIGBT. At this time, the junction temperature fluctuation coupled to the FRD chip is Δ. T vj_low ;

[0097] 2) Conduct FRD heating power cycling under the influence of thermal coupling, with test conditions including high junction temperature fluctuation Δ T vj_high Until the FRD reaches aging failure, the cycle test life is... N FRD-high ;

[0098] 3) Conduct heating power cycling tests on the FRD (new device) without thermal coupling effects, under test conditions of high junction temperature fluctuation Δ T vj_high Until the FRD reaches aging failure, the cycle test life is... N f-FRD-high ;

[0099] 4) According to the linear damage accumulation law, the damage process of the FRD chip can be described by formula (1). The schematic diagram of the FRD damage process is shown below. Figure 4 As shown.

[0100] (1)

[0101] because N IGBT , N FRD-high , N f-FRD-highAll of these are obtained through power cycle tests. Therefore, the power cycle life of the FRD chip under low junction temperature fluctuations can be calculated using formula (1).

[0102] Through the above optional implementation methods, at least the following beneficial effects can be achieved: The method proposed in this invention effectively solves the problems of long power cycle test time and high cost of devices under low junction temperature fluctuations in existing methods. By utilizing the damage of devices under thermal coupling temperature (low junction temperature) and active heating (high junction temperature), a damage accumulation formula is established to calculate the lifetime of devices under low junction temperature fluctuations.

[0103] The invention has been experimentally tested, and the feasibility of the solution has been verified. Figure 5 The ultrasonic scanning images of the devices actually tested are shown. The chip on the left is an IGBT, and the chip on the right is an FRD. During the actual test, only the IGBT was heated first, and the temperature coupled to the FRD at this time was Δ. T vj =30K, T jmax =102℃, after 50,000 cycles, then Δ is applied to the FRD. T vj =90K, T jmax Active heating power cycling test at 150℃. Table 1 is a schematic table of the test device lifetime results provided by the optional method of the present invention. The test lifetime is shown in Table 1.

[0104] Table 1

[0105]

[0106] The heating and cooling times for the above tests were ton=2s and tof=4s. Table 1 also shows the test lifetime of the FRD directly subjected to power cycling tests without the influence of thermal coupling. Six devices were tested in each group of tests, so the mean of the Weibull distribution of each group of devices can be obtained to represent the device lifetime under that condition.

[0107] The mean lifetime of the Weibull distribution for group 1 is 14324, and the mean lifetime of the Weibull distribution for group 2 is 23595. Therefore, formula (1) can be expressed as follows:

[0108] (2)

[0109] FRD in Δ T vj =30K, T jmax =102℃, t on =2s, toff The lifespan under the 4s test condition can be calculated as follows: =127258. At this point, the power cycle life test time of the FRD under low junction temperature fluctuation is only 50.55% of the traditional test time, which significantly shortens the test time.

[0110] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0111] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of the present invention.

[0112] Example 2

[0113] According to an embodiment of the present invention, an apparatus for implementing the above-described method for determining the lifetime of a diode chip is also provided. Figure 6 This is a structural block diagram of a diode chip lifetime determination device according to an embodiment of the present invention, as shown below. Figure 6 As shown, the device includes a first control module 602, a second control module 604, and a determination module 606. The device will be described in detail below.

[0114] The first control module 602 is used to control the heating power cycle of the transistor chip in the power module for a predetermined number of times, so that the diode chip in the power module is subjected to a first junction temperature fluctuation amplitude due to thermal coupling effect, resulting in a diode chip in a junction temperature fluctuation pre-damage state; the second control module 604 is connected to the first control module 602, and is used to control the heating power cycle of the diode chip in the junction temperature fluctuation pre-damage state for a predetermined condition, to obtain the first failure lifetime of the diode chip when it reaches the preset aging failure condition, and to control the heating power cycle of the diode chip not in the junction temperature fluctuation pre-damage state for a predetermined condition, to obtain a diode chip in a junction temperature fluctuation pre-damage state. The second failure lifetime of the chip when it reaches the preset aging failure condition, wherein the preset condition is that the junction temperature fluctuation of the diode chip is the second junction temperature fluctuation amplitude, and the first junction temperature fluctuation amplitude is less than the second junction temperature fluctuation amplitude; the determining module 606, connected to the second control module 604, is used to determine the target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on the linear cumulative damage function, a predetermined number of times, the first failure lifetime and the second failure lifetime, wherein the linear cumulative damage function includes a function in which the sum of the first term and the second term is one, the first term is the ratio of the predetermined number of times term to the target lifetime term, and the second term is the ratio of the first failure lifetime term to the second failure lifetime term.

[0115] It should be noted that the first control module 602, the second control module 604 and the determination module 606 mentioned above correspond to steps S102 to S106 in the method for determining the lifetime of a diode chip. The multiple modules and the corresponding steps are the same in terms of implementation examples and application scenarios, but are not limited to the content disclosed in the above embodiment 1.

[0116] Example 3

[0117] According to another aspect of the present invention, an electronic device is also provided, comprising: a processor; and a memory for storing processor-executable instructions, wherein the processor is configured to execute instructions to implement the diode chip lifetime determination method of any of the above embodiments.

[0118] Example 4

[0119] According to another aspect of the present invention, a computer-readable storage medium is also provided, which, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the diode chip lifetime determination method described above.

[0120] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0121] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0122] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0123] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0124] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0125] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0126] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for determining the lifetime of a diode chip, characterized in that, include: The power module controls the transistor chip to undergo a predetermined number of heating power cycles, so that the diode chip in the power module is subjected to the first junction temperature fluctuation amplitude due to the thermal coupling effect, resulting in a diode chip in a pre-damage state due to junction temperature fluctuation. The heating power cycle under predetermined conditions is controlled on the diode chip in the pre-damage state of junction temperature fluctuation to obtain a first failure lifetime when the diode chip reaches a preset aging failure condition. The heating power cycle under the predetermined conditions is also controlled on the diode chip not in the pre-damage state of junction temperature fluctuation to obtain a second failure lifetime when the diode chip reaches the preset aging failure condition. The predetermined condition is that the junction temperature fluctuation of the diode chip is the second junction temperature fluctuation amplitude, and the first junction temperature fluctuation amplitude is less than the second junction temperature fluctuation amplitude. Based on the linear cumulative damage function, the predetermined number of failures, the first failure lifetime, and the second failure lifetime, the target lifetime of the diode chip under the first junction temperature fluctuation amplitude is determined. The linear cumulative damage function includes a function in which the sum of the first term and the second term is one. The first term is the ratio of the predetermined number of failures to the target lifetime term, and the second term is the ratio of the first failure lifetime term to the second failure lifetime term.

2. The method according to claim 1, characterized in that, Controlling the heating power cycle of the diode chip in the pre-damage state of junction temperature fluctuation under predetermined conditions to obtain the first failure lifetime of the diode chip when it reaches the preset aging failure condition includes: During the process of controlling the heating power cycle of the diode chip in the pre-damage state of junction temperature fluctuation under the predetermined conditions, the forward voltage drop and junction temperature data of the diode chip are collected in real time. Based on the real-time collected on-state voltage drop and junction temperature data, a sequential particle filter algorithm is used to track the degradation state of the diode chip online. When the degradation state indicates that the cumulative damage to the diode chip has reached a preset threshold, the heating power cycle is terminated, and the current number of cycles is taken as the first failure lifetime.

3. The method according to claim 1, characterized in that, Before controlling the heating power cycle of the transistor chip in the power module to be performed a predetermined number of times, causing the diode chip in the power module to withstand the first junction temperature fluctuation amplitude due to thermal coupling effect, and obtaining the diode chip in a pre-damage state due to junction temperature fluctuation, the method further includes: Construct a digital twin model of the power module, wherein the digital twin model includes thermal coupling path parameters between the transistor chip and the diode chip; The junction temperature fluctuation amplitude and cumulative damage degree of the diode chip under different heating power cycles are simulated using the digital twin model to determine the target predetermined number of cycles required for the diode chip to reach the target pre-damage degree. The heating power cycle is executed the predetermined number of times as the predetermined number of times.

4. The method according to claim 1, characterized in that, Based on the linear cumulative damage function, the predetermined number of failures, the first failure lifetime, and the second failure lifetime, the target lifetime of the diode chip under the first junction temperature fluctuation amplitude is determined, including: A physical information neural network model is obtained, wherein the physical information neural network takes the material properties, packaging geometry parameters, and the first and second junction temperature fluctuation amplitudes of the transistor chip and the diode chip as inputs, the weight coefficients of the first and second terms in the linear cumulative damage function as outputs, and the historical failure data of the power cycle test of the model of the power module as constraints. Based on the physical information neural network model, determine the target weight coefficients corresponding to the first and second terms in the linear cumulative damage function, respectively; Based on a linear cumulative damage function with corresponding target weight coefficients, the predetermined number of failures, the first failure lifetime, and the second failure lifetime, the target lifetime of the diode chip under the first junction temperature fluctuation amplitude is determined.

5. The method according to claim 1, characterized in that, Based on the linear cumulative damage function, the predetermined number of failures, the first failure lifetime, and the second failure lifetime, the target lifetime of the diode chip under the first junction temperature fluctuation amplitude is determined, including: When the preset aging failure conditions include a first failure condition and a second failure condition, the on-state voltage drop and thermal resistance of the diode chip are obtained at the first failure lifetime and the second failure lifetime. The first failure condition is that the on-state voltage drop of the diode chip increases by a first preset threshold, which is used to characterize the bonding wire failure. The second failure condition is that the thermal resistance of the diode chip increases by a second preset threshold, which is used to characterize the solder aging. Based on the first remaining space between the on-state voltage drop and the first preset threshold corresponding to the first failure condition, and the second remaining space between the thermal resistance and the second preset threshold corresponding to the second failure condition, the order in which the first remaining space and the second remaining space reach zero is compared to determine the target failure mode represented by the parameter that first reaches the corresponding failure condition. Retrieve the damage accumulation function parameters corresponding to the target failure mode.

6. The method according to claim 1, characterized in that, Based on the linear cumulative damage function, the predetermined number of failures, the first failure lifetime, and the second failure lifetime, the target lifetime of the diode chip under the first junction temperature fluctuation amplitude is determined, including: Obtain the thermal coupling coefficient between the transistor chip and the diode chip; The first junction temperature fluctuation amplitude is corrected based on the thermal coupling coefficient to obtain the corrected junction temperature fluctuation amplitude. Based on the linear cumulative damage function, the predetermined number of failures, the first failure lifetime, and the second failure lifetime, the target lifetime of the diode chip under the corrected junction temperature fluctuation amplitude is determined.

7. The method according to any one of claims 1 to 6, characterized in that, Controlling the heating power cycle of the transistor chip in the power module a predetermined number of times, causing the diode chip in the power module to withstand a first junction temperature fluctuation amplitude due to thermal coupling effect, resulting in a diode chip in a pre-damage state due to junction temperature fluctuation, including: Within the heating power cycle of the transistor chip, the highest and lowest junction temperatures of the diode chip are obtained. The difference between the highest junction temperature and the lowest junction temperature is taken as the first junction temperature fluctuation amplitude.

8. A device for determining the lifetime of a diode chip, characterized in that, include: The first control module is used to control the heating power cycle of the transistor chip in the power module a predetermined number of times, so that the diode chip in the power module is subjected to the first junction temperature fluctuation amplitude due to the thermal coupling effect, and the diode chip is in the pre-damage state of junction temperature fluctuation. The second control module is used to control the diode chip in the pre-damage state of junction temperature fluctuation to perform heating power cycling under predetermined conditions to obtain a first failure lifetime when the diode chip reaches a preset aging failure condition, and to control the diode chip not in the pre-damage state of junction temperature fluctuation to perform heating power cycling under the predetermined conditions to obtain a second failure lifetime when the diode chip reaches the preset aging failure condition, wherein the predetermined condition is that the junction temperature fluctuation of the diode chip is a second junction temperature fluctuation amplitude, and the first junction temperature fluctuation amplitude is less than the second junction temperature fluctuation amplitude. The determining module is used to determine the target lifetime of the diode chip under the first junction temperature fluctuation amplitude based on the linear cumulative damage function, the predetermined number of times, the first failure lifetime and the second failure lifetime, wherein the linear cumulative damage function includes a function in which the sum of the first term and the second term is one, the first term is the ratio of the predetermined number of times term to the target lifetime term, and the second term is the ratio of the first failure lifetime term to the second failure lifetime term.

9. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the method for determining the lifetime of a diode chip as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the method for determining the lifetime of a diode chip as described in any one of claims 1 to 7.

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