A channel inspection and calibration method applied in dimm test

Abstract

This invention relates to the field of wafer testing technology, specifically disclosing a channel inspection and calibration method applied to DIMM testing, comprising: Step 1: preparing inspection boards and calibration boards adapted to DIMM sockets; Step 2: feeding the trays loaded with inspection boards into a sorting machine; Step 3: completing integrity testing through the inspection boards; Step 4: the sorting machine automatically replaces the calibration boards with the corresponding DIMM sockets and calculates the transmission path length; Step 5: based on the difference in transmission path lengths of each channel, timing compensation is used to synchronize the timing of all digital signals, completing channel calibration; Step 6: after calibration, the sorting machine replaces the DIMM trays under test and directly conducts DIMM mass production testing. This invention, without leaving the sorting machine, only requires replacing the trays of the DIMMs under test with inspection and calibration trays, significantly improving work efficiency and reducing workload.

Description

Technical Field

[0001] This invention relates to the field of wafer testing technology, and more specifically to a channel inspection and calibration method applied to DIMM testing. Background Technology

[0002] In the field of chip testing, testing at the wafer stage is called wafer testing, and after the wafer is diced and packaged, it is called packaging testing, also known as final testing. However, for memory chip testing, the large demand for DIMMs from users means that even after chip packaging testing is completed, it is still necessary to design DIMM (Dual In-line Memory Module) modules, and the testing of DIMM modules is called DIMM testing.

[0003] Regardless of the type of chip being tested, checking and calibrating the internal channels of the test equipment is indispensable. Most chip testing equipment, from bottom to top, consists of instrumentation cards (configurations vary depending on the test equipment), a motherboard, and interface boards. Some interface boards are further divided into an interface board for connecting to the channels and a socket board for connecting to the chip under test. After the equipment is installed or during routine maintenance, the channels within the equipment need to be checked and calibrated. Hardware engineers need to design check and calibration boards corresponding to their equipment. Typically, these check and calibration boards are placed at the top of the motherboard for inspection and calibration. In other words, the topmost interface board needs to be removed, and the check or calibration board replaced with the interface board to check or calibrate the internal channels of the test equipment. Summary of the Invention

[0004] The purpose of this invention is to provide a channel inspection and calibration method for DIMM testing, solving the following technical problems: 1. Whether using inspection or calibration boards, the testing machine must be disconnected from the sorting machine and other equipment before the top socket interface board can be replaced for corresponding inspection and calibration work. Sometimes, after high and low temperature testing, the testing machine needs to be placed at room temperature before further operation can be performed, which often wastes a lot of usable machine time. A more efficient method is urgently needed to solve this problem. 2. Traditional methods for channel inspection and calibration often require checking all channels in the machine. This necessitates bringing out all signals from the inspection and calibration boards, with a single digital board often requiring the calibration of hundreds of channels. Even with proper PCB layout, this necessitates a large number of layers. Reducing the number of layers would allow for better cost control.

[0005] 3. Typically, during inspection and calibration, the top interface board is removed, necessitating signal length matching on the interface board itself to ensure signal consistency. Furthermore, an additional continuity check of the interface board is required. If a method were available to inspect and calibrate the interface board simultaneously, it would save considerable time.

[0006] The objective of this invention can be achieved through the following technical solutions: A channel inspection and calibration method applied in DIMM testing includes the following steps: Step 1: Prepare inspection and calibration boards that are compatible with DIMM sockets; the inspection and calibration boards are completely consistent with the standard DIMM strips in terms of shape, number of gold fingers, spacing, and size, and can be directly plugged into the DIMM socket of the test machine's socket interface board without disassembling or replacing the socket interface board. Step 2: Feed the tray containing the inspection boards into the sorting machine. The sorting machine will automatically insert the inspection boards into the DIMM sockets of the socket interface board in sequence. The host computer will read the board ID information to identify the board type. Step 3: Complete the full-path channel continuity test, wiring harness sequence test, and power signal integrity test by inspecting the board. The test scope includes the complete link of the test machine instrument card, motherboard, wiring harness, and socket interface board. Step 4: The sorting machine automatically replaces the calibration board with the corresponding DIMM socket, collects the signal reflection curves of each digital channel based on the time domain reflectometry, and calculates the transmission path length of each digital channel from the source end of the test machine to the terminal of the DIMM socket. Step 5: Based on the difference in transmission path length for each channel, timing compensation is used to synchronize the timing of all digital signals, thus completing channel calibration; Step 6: After calibration, the sorter replaces the DIMM tray to be tested and directly carries out mass production testing of DIMMs.

[0007] As a further aspect of the present invention: the inspection board has a built-in ID recognition circuit; the ID recognition circuit is connected to the 16-bit GPIO signal output by the machine system control board, and controls the high and low levels of the corresponding GPIO pins by connecting 0-ohm resistors in series at different positions on the board to generate an 8-bit binary ID code, and the host computer distinguishes the board type and adapts to the DIMM specification according to the binary code.

[0008] As a further aspect of the present invention: the 8-bit binary ID code is generated by the combination of the 0~7 pin levels of GPIO; when the corresponding pin is connected to ground with a 0-ohm resistor, a low level is output, and when the pin is left floating, a high level is output. Different DIMM specifications and inspection / calibration functions correspond to unique binary codes.

[0009] As a further aspect of the present invention: the channel detection method in step three specifically includes: The digital channels are divided into two categories: IO and DR. The digital signals from different connectors are connected in series with precision resistors of different resistance values ​​and grounded. A high-level signal is applied to each digital channel in sequence, and the loop current value is collected. The measured current is then compared with the theoretical current threshold. If the current deviation exceeds the threshold, the corresponding channel is considered abnormal. If the signal output voltage of connector A matches the theoretical current value of connector B, then the wiring sequence of the wire harness connectors is determined to be incorrect, and the host computer will output the corresponding error message synchronously. The power signal uses the same pressure-measuring logic to complete the integrity detection.

[0010] As a further aspect of the present invention: the specific implementation logic of the time-domain reflectometry calibration in step four is as follows: The test machine resource board outputs a step signal. After the signal is transmitted to the convergence point of the calibration board through the complete hardware link of the test machine, an impedance change occurs. The reflected voltage is collected to generate a time-domain reflection curve. The impedance change location is calculated based on the reflection coefficient formula Vr / Vi=(Z1-Z0) / (Z1+Z0), and the length of the complete transmission path of a single channel is calculated in combination with the signal transmission speed. Where Vi is the incident voltage, Vr is the reflected voltage, Z0 is the standard line impedance, and Z1 is the impedance at the abrupt change point.

[0011] As a further aspect of the present invention: the calibration board eliminates the FPGA and peripheral SPI communication circuits, and all the digital signals to be tested are shorted to the same convergence point inside the board, retaining only the time domain reflection signal acquisition circuit, thereby reducing the number of board components and PCB stack-up layers.

[0012] As a further aspect of the present invention: channel inspection and calibration are only for the channels actually used in the current DIMM testing; different specifications of DIMM correspond to a set of independent inspection boards and calibration boards, and unused channels are not included in the current board testing and calibration scope.

[0013] As a further aspect of the present invention: the calibration process incorporates the socket interface board into the complete signal link synchronous calibration, eliminating the need for the socket interface board to perform signal line length matching design in advance, and unifying the signal delay consistency of the entire link through time domain reflection timing compensation.

[0014] As a further aspect of the present invention: the DIMM includes five types of standard memory modules: UDIMM, RDIMM, LRDIMM, FB-DIMM, and SO-DIMM.

[0015] The beneficial effects of the present invention are as follows: In the prior art, when the machine is first put on or during subsequent maintenance, the 64 DIMM interface boards of 128 chips under test need to be checked. Each check and calibration board requires maintenance personnel to manually check the board insertion and removal → check → replace the calibration board → calibrate → replace the interface board → perform the test. Such a process often requires at least three maintenance personnel to perform maintenance for one to two days. When using the inspection and calibration scheme of this invention, without leaving the sorting machine, simply replace the tray of the DIMM to be tested with the inspection and calibration tray. The sorting machine automatically replaces the inspection and calibration boards sequentially. All maintenance can be performed fully automatically, and maintenance personnel can operate the system from outside the cleanroom, solely through a host computer. This allows maintenance personnel to complete the maintenance of one machine in as little as one hour, significantly improving work efficiency and reducing workload. Attached Figure Description

[0016] The invention will now be further described with reference to the accompanying drawings.

[0017] Figure 1 This is a simplified diagram of the DIMM structure in this invention; Figure 2 This is a comparative schematic diagram of the channel inspection and calibration method in this invention and the prior art; Figure 3 This is a schematic diagram of the appearance of the DIMM in this invention; Figure 4 This is a schematic diagram illustrating an example of ID determination in this invention; Figure 5 This is a simplified diagram of the DIMM test structure in this invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1 As shown in the diagram, this is a simplified representation of DIMM bars used in the DIMM testing process. Common DIMM classifications include the following: 1. UDIMM (Unbuffered DIMM) unbuffered dual in-line memory modules: This is the most common type of memory used in desktop and laptop computers. Its key feature is the absence of a buffer chip; the CPU's memory controller can directly access the memory chips, resulting in low latency and high performance. However, due to faster signal attenuation, the capacity and number of memory modules that can be stably supported within a single channel are limited.

[0020] 2. RDIMM (Registered DIMM) dual in-line memory modules: Designed specifically for servers and workstations, it incorporates registers and phase-locked loop (PLL) chips into the memory module. Control signals are first purified and buffered by the registers before reaching the memory chip, which greatly enhances the stability and integrity of the signal, thereby supporting larger memory capacities and denser slots, at the cost of an additional clock cycle latency.

[0021] 3. LRDIMM (Load Reduced DIMM) dual in-line memory modules: It can be seen as an advanced version of RDIMM. It not only buffers control signals but also data signals, thereby further reducing the electrical load on the memory bus. This allows more and larger memory modules to be inserted into the same system, which is key to achieving ultra-large memory capacity, but the latency is slightly higher than that of RDIMM.

[0022] 4. FB-DIMM (Full Buffered DIMM) Fully Buffered Dual In-line Memory Module: This was a transitional technology that emerged in the DDR2 era to address the issues of memory capacity and speed. It used an advanced memory buffer chip on the memory module, changing the parallel memory channels to serial ones. While improving capacity and reliability, it also introduced problems of high heat generation and high latency, and has now been largely replaced by RDIMM / LRDIMM.

[0023] 5. SO-DIMM (Small Outline DIMM) Small Dual In-line Memory Module: This is the standard memory for laptops and mini PCs. It is about half the size of a standard DIMM, and the number of pins varies between generations (e.g., DDR4 SO-DIMM has 260 pins) to fit into compact internal spaces.

[0024] The process of channel inspection and calibration often involves frequent replacement of different types of boards, which is complex and often requires long periods of production downtime during maintenance. For example... Figure 2The diagram shows a comparison between existing technologies and the technical solutions of this invention (solid arrows indicate signal connections, and dashed arrows indicate replaceable boards). This invention changes the position of the inspection and calibration board. Previously, it was inserted above the motherboard as a replacement for the socket interface board for inspection and calibration. In this invention, the inspection and calibration board is not used to replace the socket interface board, but is directly inserted into the socket interface board. This eliminates the need for frequent replacement of different types of boards.

[0025] The design of circuit boards inevitably involves adding layers, increasing the cost of non-sales components, and full-channel inspection and calibration are not conducive to efficiency improvement. For example... Figure 2 As shown, this invention eliminates redundant channels, checking and calibrating only the channels used during testing. Furthermore, it modifies the calibration method, changing the original multi-FPGA SPI communication approach to a time-domain reflection-based calibration method. This significantly reduces the number of signal layers and the number of FPGAs used, thereby reducing costs and improving efficiency. The specific calibration scheme will be explained in detail later.

[0026] In existing technologies, the top interface board is typically removed during inspection and calibration. This necessitates performing signal length matching on the interface board to ensure signal consistency, and also requires additional continuity checks on the interface board. Similarly, ... Figure 2 As shown, this invention does not remove the top interface board during inspection and calibration; instead, it includes the interface board for inspection and calibration. Therefore, in the design of the DIMM interface board, there are no requirements for the equal length of signal lines, because the consistency of signal delay throughout the entire path can be guaranteed by the calibration board.

[0027] The descriptions of the five different types of DIMM strips above show that their differences are minor, and all are products that have undergone a series of standardization processes before being put into the market. Based on the characteristics of DIMMs and the improvements made to existing problems mentioned above, this invention makes the following design improvements to the actual inspection and calibration board: 1. The inspection and calibration board is designed to be exactly the same size and shape as the DIMM, so that it can be directly plugged into the DIMM socket in the socket interface board; 2. Only the channels leading out of the DIMM sockets are checked and calibrated. Channels not leading out are not subject to additional checks on this check and calibration board. When the testing machine uses other channels to test other DIMMs, separate check and calibration boards will be designed. Since the types and standards of DIMM strips are fixed, all different types of boards can be prepared in advance.

[0028] 3. Since the board is designed to be identical to the DIMM strip, the size of the board will be smaller than before. If the previous FPGA SPI communication is still used for calibration, the device will not be able to be placed. Therefore, the FPGA and its peripheral circuits were removed, and the calibration method was changed to a calibration method based on time domain reflection.

[0029] The appearance of the inspection and calibration board should be consistent with that of the DIMM, such as... Figure 3 As shown, the external dimensions, the number, spacing and size of the gold fingers (a row of gold-plated conductive metal contacts on the edge of the board, which look like fingers and are gold-plated to a golden color, hence the name gold fingers) are exactly the same as those of the DIMMs, ensuring that the DIMMs can be completely replaced by a sorting machine during inspection and calibration.

[0030] Hardware design of the inspection and calibration board: 1. Check the circuit board: The hardware design of the inspection board mainly consists of the following parts: 1) ID recognition: Since there are many types of DIMMs, when the sorting machine uses different types of DIMM inspection boards for inspection, the host computer needs to determine which type of inspection board the sorting machine is currently using.

[0031] Additionally, when checking and calibrating boards are inserted into the same type of DIMM socket, it is also necessary to determine whether the board being inserted is a check board or a calibration board.

[0032] Therefore, an identifiable ID circuit is needed to ensure that the host computer can read the relevant information for judgment and subsequent operations.

[0033] The 16-bit GPIO signals received from the system control board in the machine's power cabinet, which communicates with the host computer, determine the high or low level of the current GPIO based on the 0-ohm resistor connected in series on different boards. These signals are then processed in a fixed sequence to obtain an 8-bit binary combination used to identify different types of boards. For example, checking an RDIMM board using 3C, which translates to 00111100 in binary, involves grounding GPIO signals 0, 1, 6, and 7 through a 0-ohm resistor, while the remaining GPIO signals are left floating. Specifically... Figure 4 As shown.

[0034] 2) Check the background: Reference Figure 5 As shown, each DIMM test socket board consists of two sets of eight connectors, which are connected to the signals in the tester below using a wiring harness. Each DIMM test socket board typically tests two DIMM strips, with each DIMM strip corresponding to the signals in the four connectors below.

[0035] 3) Inspection method: The digital channels are divided into two types: IO and DR. However, both types of digital signals are connected to the DIMM test socket board via four connectors through a wiring harness, such as... Figure 5 As shown. Therefore, in addition to checking the continuity of each digital channel, it is also necessary to check whether the wiring harness connection sequence is correct.

[0036] In the inspection board, digital signals from different connectors are connected in series with precision resistors of different values ​​and grounded. Using a pressure-based current measurement method, high-level signals are sequentially applied according to their different order, and the current value at the current level is measured.

[0037] When a digital signal outputs voltage, but the current deviates significantly from the theoretical value, the digital signal path is abnormal, and the host computer will display an error message for this channel.

[0038] If the signal in connector A outputs a voltage, and the measured current value is the same as the current value that the signal in connector B should return, it indicates that the connectors below are connected in the wrong order, and the host computer will display a wiring harness connection error message.

[0039] The power signal is checked in the same way.

[0040] 2. Calibration board: 1) ID recognition: Same as the inspection board.

[0041] 2) Why is calibration necessary? Digital signals travel from the digital board through multiple connectors and intermediate boards to the pins of the chip under test in the DIMM interface board. Since the length of all digital boards in this path cannot be guaranteed to be consistent, time-domain calibration is required to ensure that these digital signals are transmitted and received simultaneously from the source to the terminal.

[0042] 3) The principle of time-domain reflection: The resource board inside the machine generates a step signal. After passing through the connector and intermediate board path, the reflected voltage is collected. The impedance value at the impedance discontinuity is calculated based on the reflected voltage. After integration, the final time-domain reflection curve is obtained.

[0043] Assume the incident voltage and reflected voltage at the intersection of Z0 and Z1 are Vi and Vr, respectively: The formula for the reflection coefficient is: Vr / Vi=(Z1-Z0) / (Z1+Z0); We get Z1 = Z0 * (Vi + Vr) / (Vi - Vr).

[0044] When the measured reflected signal voltages are different, the location of the reflection can be determined based on the speed at which the signal propagates in the board or wiring harness.

[0045] For example, with an impedance line of 48 ohms at one end, and a propagation speed of 6 mil / ps, the time for the reflected voltage change is measured to be 1.66 ns. Therefore, this invention can easily calculate the location X of the change by having the signal propagate twice at the point of impedance change.

[0046] X = (1.66ns * 6mil / ps) / 2 = 5 inches.

[0047] 4) Time-domain reflection is used for timing calibration: Time-domain reflection is used to check the continuity of a signal; here, the above-mentioned time-domain reflection principle is used to calibrate the signal: Based on the aforementioned time-domain reflection principle, this invention connects all digital signals to the same point in the calibration board. When a digital signal generates a step signal and the reflected voltage is acquired, a significant impedance change occurs when the signal passes through the same impedance line to the convergence point. This invention can calculate the length from the source to the terminal based on the time of this impedance change. After obtaining the lengths of all digital signals, timing compensation is performed using an FPGA, thus ensuring the timing consistency of all digital signals.

[0048] Check the condition of the circuit boards and calibration boards: The inspection and calibration methods used in the existing technology involve replacing the interface board with an inspection and calibration board. This requires not only additional inspection and length matching of the interface board, but also detaching the test equipment from the sorting machine for operation.

[0049] Based on the typical configuration of 128 chips under test, in the previous inspection and calibration scheme, whether it is the first time the machine is put on or during subsequent maintenance, the 64 DIMM interface boards of the 128 chips under test need to be inspected. Each inspection and calibration board requires maintenance personnel to manually check the board insertion and removal → inspection → replacement of calibration board → calibration → replacement of interface board → test. This process usually requires at least three maintenance personnel to perform maintenance for one to two days.

[0050] When using the inspection and calibration scheme of this invention, without leaving the sorting machine, simply replace the tray of the DIMM to be tested with the inspection and calibration tray. The sorting machine automatically replaces the inspection and calibration boards sequentially. All maintenance can be performed fully automatically, and maintenance personnel can operate the system from outside the cleanroom, solely through a host computer. This allows maintenance personnel to complete the maintenance of one machine in as little as one hour, significantly improving work efficiency and reducing workload.

[0051] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A method for lane check and calibration applied in DIMM testing, characterized in that, Includes the following steps: Step 1: Prepare inspection and calibration boards that are compatible with DIMM sockets; the inspection and calibration boards are completely consistent with the standard DIMM strips in terms of shape, number of gold fingers, spacing, and size, and can be directly plugged into the DIMM socket of the test machine's socket interface board without disassembling or replacing the socket interface board. Step 2: Feed the tray containing the inspection boards into the sorting machine. The sorting machine will automatically insert the inspection boards into the DIMM sockets of the socket interface board in sequence. The host computer will read the board ID information to identify the board type. Step 3: Complete the full-path channel continuity test, wiring harness sequence test, and power signal integrity test by inspecting the board. The test scope includes the complete link of the test machine instrument card, motherboard, wiring harness, and socket interface board. Step 4: The sorting machine automatically replaces the calibration board with the corresponding DIMM socket, collects the signal reflection curves of each digital channel based on the time domain reflectometry, and calculates the transmission path length of each digital channel from the source end of the test machine to the terminal of the DIMM socket. Step 5: Based on the difference in transmission path length for each channel, timing compensation is used to synchronize the timing of all digital signals, thus completing channel calibration; Step 6: After calibration, the sorter replaces the DIMM tray to be tested and directly carries out mass production testing of DIMMs.

2. The lane check and calibration method for use in DIMM testing of claim 1, wherein, The inspection board has a built-in ID recognition circuit. The ID recognition circuit is connected to the 16-bit GPIO signal output by the machine system control board. The high and low levels of the corresponding GPIO pins are controlled by a 0-ohm resistor connected in series at different positions on the board, generating an 8-bit binary ID code. The host computer distinguishes the board type and adapts to the DIMM specification based on the binary code.

3. The channel inspection and calibration method applied to DIMM testing according to claim 2, characterized in that, The 8-bit binary ID code is generated by the combination of the 0~7 pin levels of GPIO; when the corresponding pin is connected to ground with a 0-ohm resistor in series, a low level is output, and when the pin is left floating, a high level is output. Different DIMM specifications and inspection / calibration functions correspond to unique binary codes.

4. The channel inspection and calibration method applied to DIMM testing according to claim 1, characterized in that, The channel detection method described in step three specifically includes: The digital channels are divided into two categories: IO and DR. The digital signals from different connectors are connected in series with precision resistors of different resistance values ​​and grounded. A high-level signal is applied to each digital channel in sequence, and the loop current value is collected. The measured current is then compared with the theoretical current threshold. If the current deviation exceeds the threshold, the corresponding channel is considered abnormal. If the signal output voltage of connector A matches the theoretical current value of connector B, then the wiring sequence of the wire harness connectors is determined to be incorrect, and the host computer will output the corresponding error message synchronously. The power signal uses the same pressure-measuring logic to complete the integrity detection.

5. The channel inspection and calibration method applied to DIMM testing according to claim 1, characterized in that, The specific implementation logic of the time-domain reflectometry calibration described in step four is as follows: The test machine resource board outputs a step signal. After the signal is transmitted to the convergence point of the calibration board through the complete hardware link of the test machine, an impedance change occurs. The reflected voltage is collected to generate a time-domain reflection curve. The impedance change location is calculated based on the reflection coefficient formula Vr / Vi=(Z1-Z0) / (Z1+Z0), and the length of the complete transmission path of a single channel is calculated in combination with the signal transmission speed. Where Vi is the incident voltage, Vr is the reflected voltage, Z0 is the standard line impedance, and Z1 is the impedance at the abrupt change point.

6. The channel inspection and calibration method applied to DIMM testing according to claim 1, characterized in that, The calibration board eliminates the FPGA and peripheral SPI communication circuits. All digital signals under test are shorted to the same convergence point inside the board, and only the time domain reflection signal acquisition circuit is retained, reducing the number of board components and PCB stack-up layers.

7. The channel inspection and calibration method applied to DIMM testing according to claim 1, characterized in that, Channel inspection and calibration only applies to the channels actually used in the current DIMM testing; different DIMM specifications correspond to a separate inspection board and calibration board, and unused channels are not included in the current board's testing and calibration scope.

8. The channel inspection and calibration method applied to DIMM testing according to claim 1, characterized in that, The calibration process incorporates the socket interface board into the complete signal link synchronous calibration. The socket interface board does not need to be designed for signal line length matching in advance. The consistency of signal delay across the entire link is unified through time domain reflection timing compensation.

9. A channel inspection and calibration method for DIMM testing according to claim 1, characterized in that, The DIMM includes five types of standard memory modules: UDIMM, RDIMM, LRDIMM, FB-DIMM, and SO-DIMM.

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