Chip testing method and testing system

Abstract

This disclosure provides a chip testing method and system, relating to the field of chip testing technology. The method includes: obtaining a chip testing work order corresponding to the current chip testing equipment, and matching the corresponding test configuration information in the production execution system based on the work order identification information of the chip testing work order; verifying whether the test equipment identifier in the test configuration information matches the current chip testing equipment; if so, determining the test station corresponding to the test station identifier as the target test station; obtaining at least one corresponding target test program based on the test program information, and sending at least one target test program to each target test station so that each target test station can run the test program to perform the chip testing task and obtain the test results. This disclosure automatically completes work order identification, test configuration information matching and verification, and test program distribution, improving testing efficiency and operational accuracy.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, and in particular to chip testing methods and testing systems. Background Technology

[0002] During chip manufacturing and testing, system-level testing is typically performed on the chip under test using chip testing equipment to verify its functionality, performance, and stability under preset operating conditions. As the number of chip testing tasks increases, multiple chip testing work orders and multiple chip testing devices usually exist simultaneously on the production floor. Different chip testing work orders may correspond to different product models, batch information, test programs, test stations, test boards, test sockets, loading and unloading devices, and configuration requirements such as test temperatures.

[0003] In existing technologies, operators typically use portable terminals to view chip test work orders and manually enter the work order information on the test equipment side, further configuring the test program and test stations. Since the same portable terminal may hold electronic work orders from multiple chip test equipment simultaneously, if the operator mistakenly selects a work order that does not belong to the current chip test equipment, the current chip test equipment may load an incorrect configuration, leading to the chip under test executing an incorrect test program. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this disclosure is to provide a chip testing method and testing system to solve the problems in the related art.

[0005] This disclosure provides a chip testing method, comprising: reading a work order identifier pattern displayed on a portable terminal to obtain a work order identifier for the current chip test work order; wherein the chip test work order corresponds to the establishment of a chip test task; the current chip test work order is determined by matching chip test work orders on an external terminal based on work order information displayed on the external terminal; obtaining a chip test work order corresponding to a current chip test device, and matching corresponding test configuration information in a production execution system based on the work order identifier information of the chip test work order; wherein the chip test device includes at least one test station; the test configuration information includes: a test device identifier, a test station identifier, and test program information; verifying whether the test device identifier in the test configuration information matches the current chip test device; if so, determining the test station corresponding to the test station identifier as a target test station; obtaining at least one corresponding target test program based on the test program information, and sending the at least one target test program to each target test station so that each target test station runs the test program to execute the chip test task and obtains test results.

[0006] In an embodiment of the first aspect, the chip testing equipment further includes a loading / unloading device for transporting the chip under test to a testing station. The method further includes: when the chip under test is at the loading / unloading device, reading first model identification information of the chip under test through the loading / unloading device; when the chip under test is at the target testing station, reading second model identification information of the chip under test through the target testing station; and in response to a mismatch between the first model identification information or the second model identification information of the chip under test and the target chip model corresponding to the chip testing work order, outputting a chip model error message and pausing the running of the testing program at the target testing station.

[0007] In an embodiment of the first aspect, the chip testing equipment includes a loading / unloading device and a site host corresponding to at least one test site. The chip testing equipment is configured with a host computer for communication connection. The method further includes: detecting the loading / unloading communication connection status between the host computer and the loading / unloading device; detecting the site communication connection status between the host computer and the site host corresponding to the target test site; and, in response to the loading / unloading communication connection status and / or the site communication connection status indicating a communication abnormality, outputting a communication abnormality prompt and pausing the test program running at the target test site.

[0008] In an embodiment of the first aspect, a test interaction software is run on a host computer. The test interaction software includes a test preparation display interface, a test process monitoring interface, and a test result display interface. The test preparation display interface is used to display test configuration information matched from the production execution system based on the work order identification information. The test process monitoring interface is used to display the test logs of each of the target test sites. The test result display interface is used to display the test results of each of the target test sites.

[0009] In an embodiment of the first aspect, the step of running the test program by each of the target test sites to perform a chip test task includes: during the execution of the chip test task, acquiring temperature monitoring information corresponding to each of the target test sites; the temperature monitoring information includes a preset test temperature of the target test site and an actual test temperature acquired by a temperature acquisition device; and in response to a temperature deviation between the preset test temperature and the actual test temperature satisfying a preset temperature anomaly condition, performing an interruption test process on the corresponding target test site.

[0010] In an embodiment of the first aspect, the step of each of the target test stations running the test program to perform chip testing tasks includes: the target test station applying preset excitation signals to multiple input pins of the chip under test through a corresponding test board, and acquiring pin output signals fed back by the chip under test through multiple output pins; generating pin output feature information corresponding to the chip under test based on the pin output signals of the multiple output pins; verifying whether the pin output feature information matches the preset chip feature information corresponding to the chip test work order; if not, issuing a chip matching error message and pausing the target test station from running the test program.

[0011] In a first aspect embodiment, the chip testing task includes multiple chip testing items, and the step of each target testing station running the test program to execute the chip testing task includes: during the execution of the chip testing task at each target testing station, traversing each target testing station and determining the currently traversed target testing station as the evaluation station, and determining the target testing stations other than the evaluation station as a set of test reference stations; obtaining the project measurement statistics values ​​corresponding to the evaluation station for each of the multiple chip testing items within a preset statistical window, and obtaining the project reference statistics values ​​corresponding to each of the chip testing items for each test reference station within the preset statistical window; for any chip testing item, performing tests on each of the test reference stations... The reference statistical values ​​of the test sites are fused to obtain the fused reference statistical values ​​of the chip test items. Based on the differences between the measured statistical values ​​of the test sites under each chip test item and the fused reference statistical values, the project offset evaluation values ​​of the test sites under each chip test item are determined. Based on the project offset evaluation values ​​of the test sites under each chip test item, the site offset evaluation value of the test sites is determined. In response to the site offset evaluation value of the test sites meeting the preset offset conditions, it is determined that the test sites have a test anomaly risk. The test is interrupted for the test sites, and each risk factor item is checked one by one according to the preset risk check order.

[0012] In the first aspect of the embodiment, the test program includes a test sequence and test cases corresponding to multiple chip test items. The test cases include at least one of test input information, test item configuration parameters, expected response data, and test judgment rules. The step of each target test station running the test program to perform chip test tasks and obtain test results includes: each target test station sequentially executing the multiple chip test items according to the test sequence, and when executing any chip test item, configuring at least one of the power supply module, signal excitation module, data acquisition module, interface communication module, and test board in the target test station based on the test item configuration parameters of the test program; applying the test input information in the test case to the chip under test through the configured power supply module, signal excitation module, interface communication module, and test board; acquiring the test response data returned by the chip under test through the test board via the data acquisition module and / or the interface communication module; comparing the test response data with the expected response data based on the test judgment rules in the test cases corresponding to the chip test items to determine the test result corresponding to the chip test items; and generating the test result corresponding to the chip under test based on the test results corresponding to the multiple chip test items.

[0013] In a first aspect embodiment, the chip testing task includes at least one of power-on current testing, communication handshake testing, read / write access testing, abnormal access testing, execution function operation testing, and power consumption testing. The method further includes: in response to performing the power-on current test, the target test site is configured with the power module and the data acquisition module; the power module is controlled to apply a supply voltage to the target power pin of the chip under test through the test board according to a preset power-on sequence; and the data acquisition module is controlled to acquire the current value corresponding to the target power pin during power-on; based on a comparison between the current value and a preset current determination range, the test status of the power-on current test is determined. Results: In response to the execution of the communication handshake test, the target test site configures the interface communication module and the test board. Based on the communication protocol parameters corresponding to the interface communication module, it sends a handshake request instruction to the chip under test through the test board and receives the handshake response information returned by the chip under test. Based on the response code in the handshake response information, the test result of the communication handshake test is determined. In response to the execution of the read / write access test, the target test site configures the interface communication module, the data acquisition module, and the test board. Based on the test cases corresponding to the test program, it determines the address to be read / written and the access test data. The test results are obtained through the interface communication module and the test board. The test board sends a write access command to the chip under test (DUT) to write the access test data into the target functional module corresponding to the read / write access address, and sends a read access command to read the readback data returned by the target functional module. Based on the consistency between the readback data and the access test data, the test result of the read / write access test is determined. In response to executing the abnormal access test, the target test site configures the interface communication module, the data acquisition module, and the test board. Based on the test cases corresponding to the test program, it determines the invalid address of the DUT, sends an access test command for the invalid address to the DUT, and uses the data acquisition... The module collects the abnormal response code returned by the chip under test (DUT), and determines the test result of the abnormal access test based on the comparison between the abnormal response code and the expected response data. In response to executing the functional operation test, the target test site is configured with the signal excitation module, the data acquisition module, and the test board. The signal excitation module is controlled to apply a functional test excitation signal to the DUT through the test board to trigger the DUT to execute the corresponding functional operation process, and the data acquisition module is controlled to collect the functional response data output by the DUT. Based on the comparison between the functional response data and the expected response data, the test result of the functional operation test is determined.In response to performing the power consumption test, the target test site is configured with the power module, the signal excitation module, the data acquisition module, and the test board. The system controls the chip under test (DUT) to enter a preset operating mode. In this preset operating mode, the data acquisition module collects voltage and current sampling values ​​corresponding to the DUT. Based on the voltage and current sampling values, the power consumption test value of the DUT is determined. Finally, based on a comparison between the power consumption test value and a preset power consumption judgment range, the test result of the power consumption test is determined.

[0014] The second aspect of this disclosure provides a chip testing system, comprising: a reading device for reading a work order identifier pattern of a current chip testing work order displayed on a portable terminal to obtain a work order identifier of the current chip testing work order; chip testing equipment, each of the chip testing equipment having at least one test station; and a control system communicatively connected to a production execution system, the reading device, and the chip testing equipment, for executing the chip testing method described in any one of the first aspects.

[0015] As described above, this disclosure provides a chip testing method, which includes: reading the work order identifier pattern of a current chip test work order displayed on a portable terminal to obtain the work order identifier of the current chip test work order; wherein, the chip test work order corresponds to the establishment of a chip test task; the current chip test work order is determined by matching chip test work orders on an external terminal based on work order information displayed on the external terminal; obtaining the chip test work order corresponding to the current chip test equipment, and matching the corresponding test configuration information in the production execution system based on the work order identifier information of the chip test work order; wherein, the chip test equipment includes at least one test station; the test configuration information includes: test equipment identifier, test station identifier, and test program information; verifying whether the test equipment identifier in the test configuration information matches the current chip test equipment; if so, determining the test station corresponding to the test station identifier as a target test station; obtaining at least one corresponding target test program based on the test program information, and sending the at least one target test program to each target test station so that each target test station runs the test program to execute the chip test task and obtain test results. This disclosure enables automatic completion of work order identification, test configuration information matching and verification, equipment and site verification, and test program distribution in a production test environment where multiple chip test work orders and multiple chip test devices coexist and are easily confused. This avoids the chip under test from executing incorrect test configurations due to manual selection or incorrect entry of work orders. Attached Figure Description

[0016] Figure 1 A schematic diagram illustrating a scenario application of the chip testing method in one embodiment of this disclosure is shown.

[0017] Figure 2 A schematic flowchart of a chip testing method according to one embodiment of this disclosure is shown.

[0018] Figure 3 A schematic diagram showing the test preparation display interface of the test interactive software in another embodiment of this disclosure is provided.

[0019] Figure 4 A structural block diagram of a chip testing device according to one embodiment of this disclosure is shown.

[0020] Figure 5 This illustration shows a flowchart of a chip test project executed based on test cases in one embodiment of the present disclosure.

[0021] Figure 6 A flowchart illustrating a test site anomaly detection method in one embodiment of this disclosure is shown.

[0022] Figure 7 A schematic diagram of the structure of a computer device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0023] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the information disclosed herein. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this disclosure can be modified or changed according to different viewpoints and application modules without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.

[0024] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement it. This disclosure may be embodied in many different forms and is not limited to the embodiments described herein.

[0025] In this disclosure, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic represented in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in any one or a group of embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples represented in this disclosure, as well as the features of those different embodiments or examples.

[0026] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this disclosure, "a set" means two or more, unless otherwise explicitly specified.

[0027] For the purpose of clarity, devices unrelated to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0028] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0029] While the terms first, second, etc., are used in some examples herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, module, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, modules, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0030] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this disclosure. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0031] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the message of the present disclosure, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0032] Currently, in the chip production testing process, it is usually necessary to perform system-level testing on the chip under test using chip testing equipment to verify the chip's functionality, performance, and stability under preset operating conditions. With the increasing number of chip testing tasks, multiple chip testing work orders and multiple chip testing devices typically exist simultaneously on the production floor. Different chip testing work orders may correspond to different product models, batch information, test programs, test stations, test boards, test sockets, loading and unloading devices, and configuration requirements such as test temperature.

[0033] In existing technologies, operators typically need to manually select or enter work order information on the testing equipment side based on the chip test work order, and then further configure the test program and test stations. Since the portable terminal carried by the operator simultaneously holds electronic work orders from multiple chip testing devices, if the operator mistakenly selects a work order that does not belong to the current chip testing device, the current chip testing device may load an incorrect configuration, leading to incorrect testing of the chip under test. Therefore, it is necessary to perform matching and verification of work orders, chip testing equipment, and chip identification before chip testing, and to monitor the operating status and test data of each test station during the testing process. These are problems that need to be solved in current automated chip testing processes.

[0034] In view of this, the present disclosure provides a chip testing method to solve the above-mentioned technical problems.

[0035] refer to Figure 1 The diagram illustrates a scenario application of the chip testing method in one embodiment of this disclosure. The operator can determine the current chip testing work order based on the work order information displayed on the external terminal 200, and read the corresponding work order identifier pattern using the barcode scanning device 100, so that the host computer 300 obtains the work order identifier of the current chip testing work order.

[0036] The host computer 300 can communicate with the Manufacturing Execution System (MES) 400 via a network. The MES 400 stores test configuration information corresponding to each chip test work order. This test configuration information may include at least one of the following: test equipment identifier, test site identifier, and test program information. After obtaining the work order identifier, the host computer 300 can request the corresponding test configuration information from the MES 400 based on the work order identifier, and then perform subsequent processes such as equipment matching, target test site determination, and test program distribution according to the test configuration information. This reduces errors caused by manual selection of work orders and configuration of test programs or test sites, improving the accuracy and automation of chip testing task execution.

[0037] like Figure 2 The diagram illustrates a flowchart of a chip testing method according to an embodiment of this disclosure. Applied to a host computer system, the host computer system may include a central host computer, or host computers deployed for each chip testing device. Each host computer can complete at least some steps of the following method according to its assigned tasks / functions.

[0038] exist Figure 2 The chip testing method includes:

[0039] Step S110: Read the work order identifier pattern of the current chip test work order displayed on the portable terminal to obtain the work order identifier of the current chip test work order.

[0040] Among them, the chip test work order corresponds to the establishment of chip test tasks. The current chip test work order is determined by matching the work order information displayed on the external terminal from the chip test work orders on the external terminal. The external terminal is implemented as the portable terminal, which is convenient for operators to carry with them to monitor the work orders of each chip test device in real time.

[0041] In some embodiments, a chip test work order corresponds to the creation of a chip test task. The chip test work order can be used to characterize the chip test task to be executed, and the work order information may include at least one of the following: work order number, batch information, chip model information, target test equipment information, target test site information, and test program information.

[0042] In some embodiments, an external terminal may be configured at the production site to display work order information for one or more chip test work orders. The external terminal may be a portable terminal, such as a tablet computer, handheld terminal, or other mobile display terminal. Based on the work order information displayed on the external terminal, the operator can determine the current chip test work order corresponding to the current test equipment from multiple chip test work orders, and then instruct the portable terminal to display the work order identification pattern corresponding to the current chip test work order.

[0043] In some embodiments, the work order identification pattern can be a QR code, barcode, or other graphic encoding that can be recognized by a reading device. The reading device of the chip testing equipment can read the work order identification pattern displayed on the portable terminal and parse the work order identification pattern to obtain the work order identifier of the current chip testing work order. The work order identifier is used as index information to uniquely match the chip testing work order in the production execution system, and may include the work order number, batch number, and test task number. Thus, the host computer can request the test configuration information corresponding to the current chip testing work order from the production execution system in subsequent steps based on the read work order identifier, which also reduces configuration errors caused by manual input of work order information.

[0044] In some embodiments, the work order identifier pattern can also directly carry test configuration information. The test configuration information includes: a test program identifier, which, in response to a communication failure between the chip testing equipment and the production execution system, allows the host computer to directly search for the corresponding test program in its local configuration cache based on the test program identifier.

[0045] Step S120: Obtain the chip test work order corresponding to the current chip test equipment, and match the corresponding test configuration information in the production execution system based on the work order identification information of the chip test work order.

[0046] In some embodiments, after receiving a test configuration retrieval request carrying the work order identifier, the production execution system can match the test configuration information corresponding to each work order identifier pre-stored in the production execution system based on the work order identifier to determine the test configuration information corresponding to the current chip test work order.

[0047] In some embodiments, the chip testing equipment includes at least one test station, and the test configuration information includes: a test equipment identifier, a test station identifier, and test program information. The test equipment identifier indicates the target chip testing equipment assigned to execute the current chip test work order; the test station identifier indicates one or more test stations within the target chip testing equipment assigned to execute the current chip test work order; and the test program information indicates the test program required to execute the current chip test work order. The test program information may include at least one of a test program name and a test program version.

[0048] In some embodiments, the test configuration information may further include test condition information. The test condition information may include at least one of test temperature conditions, power supply parameters, and test duration.

[0049] In some embodiments, the test configuration information may further include site communication configuration information, which may include the site address, communication port, communication protocol, or site control host identifier corresponding to the target test site.

[0050] In some embodiments, the test configuration information further includes loading / unloading device information and loading / unloading communication configuration information. For example, the loading / unloading device may be implemented as a test sorting machine (handler). The loading / unloading device is used to transport the chip under test to the target test station and remove the chip under test after testing. The loading / unloading device information includes a loading / unloading device identifier. The loading / unloading communication configuration information may include at least one of the following: communication address information, communication port information, and communication protocol type of the loading / unloading device.

[0051] In some embodiments, the loading / unloading device can communicate with a host computer via a serial port server. The communication address information of the loading / unloading device may include the IP address of the serial port server, and the communication port information may include the network port number or serial port channel number corresponding to the loading / unloading device in the serial port server. The serial port parameters may include at least one of baud rate, data bits, parity bits, and stop bits. The host computer can establish a communication connection with the loading / unloading device based on the loading / unloading communication configuration information and send a status query command to the loading / unloading device to obtain the operating status, loading status, or alarm status of the loading / unloading device.

[0052] In other examples, when the loading and unloading device can support Ethernet communication, the communication address information of the loading and unloading device can also be the IP address of the loading and unloading device itself, and the communication port information can also be the communication port number opened by the loading and unloading device.

[0053] In some embodiments, reference Figure 3 The diagram shown illustrates a test preparation display interface of the test interaction software in another embodiment of this disclosure. This interface displays test configuration information matched from the production execution system based on work order identification information before the chip test task is initiated. The test configuration information may include at least one of the following: test chip batch number, device name, system-level test (SLT) steps, process (RP) steps, loading / unloading device identification, target test program name, site address information, communication port information, slot (test socket) identification, and test board identification. The system-level test step information indicates the system-level test stage corresponding to the current chip test work order, and the process step information indicates the production process node of the current chip test work order in the production execution system.

[0054] In some embodiments, the test preparation display interface further includes at least one of a check data control, a start batch control, an unload control, a stop batch control, and a log display area. In response to the triggering of the check data control, the host computer can perform a matching verification on at least one of the test device identifier, test site identifier, test program information, test socket identifier, and test board identifier, and output a verification log or an error message in the log display area.

[0055] In some embodiments, the test interaction software further includes a test process monitoring interface, which is used to display at least one of the following during the execution of the test program at each target test site: test log, test progress, current chip test items, site running status, and abnormal prompt information.

[0056] In some embodiments, the test interaction software further includes a test result display interface, which is used to display the test statistics information corresponding to each target test station and the current chip test work order in real time. After each chip under test completes the test, the host computer can obtain the corresponding test result information and respectively count the number of tests, the number of good products, the number of defective products, and the yield information of each target test station, as well as the total number of tests and the total yield information of the current chip test work order.

[0057] In some embodiments, the test result information includes grading result information, which includes grading values. The host computer can calculate the number and percentage of grades corresponding to each target test site and the current chip test work order according to the grading values, and generate data summary information. The data summary information includes at least one of the following: total number of tests, yield rate, statistical results for each grade value, and statistical results for failed items.

[0058] In some embodiments, the host computer can also perform distribution analysis on the target test parameters based on the test data of each chip under test, and display the corresponding normal distribution graph and process capability index information on the test result display interface; wherein, the process capability index information includes the process capability index Cp value and / or the process performance index Cpk value.

[0059] In some embodiments, the host computer responds to the communication connection status of the loading / unloading and / or the communication connection status of the site indicating a communication abnormality, determines that the device communication status of the target test site is abnormal, outputs a communication abnormality prompt, and suspends the running of the test program at the target test site.

[0060] Among them, the loading and unloading communication connection status represents the communication connection status between the loading and unloading device and the host computer, and the station communication connection status represents the communication connection status between the test station and the host computer.

[0061] In some embodiments, to avoid discrepancies between the chip identifier recorded in the chip test work order and the actual model of the chip under test, a model verification can be performed on the chip under test before the test program is executed.

[0062] Specifically, when the chip under test is in the loading / unloading device, the first model identification information of the chip under test can be read through the loading / unloading device. For example, when the chip under test is in the loading area, the picking position, or a preset identification position on the transport path, the loading / unloading device can use a barcode scanner or other visual recognition device to read the identification mark on the chip tray or chip box where the chip under test is located, thereby obtaining the first model identification information of the chip under test. The identification mark may include at least one of a QR code, barcode, character identifier, and tray identifier.

[0063] Once the chip under test (DUT) is transported to the target testing station, its second model identification information can be read through the target testing station. For example, after the DUT is loaded into the testing socket, the target testing station can read the model identifier on the surface of the DUT using a barcode scanner or visual recognition device located at the target testing station to obtain the second model identification information.

[0064] The test configuration information corresponding to the chip test work order includes the target chip model. The host computer can match the first model identification information and the second model identification information with the target chip model, respectively. In response to the first model identification information matching the target chip model and the second model identification information both matching the target chip model, it is determined that the chip under test meets the chip model matching condition corresponding to the current chip test work order, and the target test station is allowed to execute the test program on the chip under test.

[0065] In response to a mismatch between the first model identification information and / or the second model identification information of the chip under test and the target chip model corresponding to the chip test work order, the host computer outputs a chip model anomaly prompt and suspends the execution of the test program at the target test site. The chip model anomaly prompt may include at least one of the following: the target chip model corresponding to the current chip test work order, the read first model identification information, the read second model identification information, the location of the anomaly, and the time of the anomaly.

[0066] In some embodiments, after receiving the test configuration information returned by the production execution system, the host computer can cache the test configuration information in the local storage space of the current chip testing device, and perform subsequent device matching, target test site determination, and test program acquisition processing based on the test configuration information. If the production execution system fails to match the test configuration information corresponding to the work order identifier, or if the returned test configuration information is incomplete, the host computer can output a work order configuration error message and prohibit the execution of subsequent test processes corresponding to the current chip test work order.

[0067] Step S130: Verify whether the test device identifier in the test configuration information matches the current chip test device; if so, determine the test site corresponding to the test site identifier as the target test site.

[0068] In some embodiments, the current chip testing equipment may be pre-configured with a current device identifier, which is used to identify the current chip testing equipment. The current device identifier may include at least one of the following: machine number, equipment serial number, and equipment name. The host computer may obtain the test equipment identifier of the current chip testing equipment from a local configuration file, a device status register, or device binding information issued by the production execution system.

[0069] In some embodiments, the test device identifier in the test configuration information is used to indicate the target chip test device to which the current chip test work order is assigned. After obtaining the test configuration information, the host computer can compare the test device identifier in the test configuration information with the test device identifier of the current chip test device.

[0070] When the host computer detects that the test device identifier matches the current device identifier, it determines that the current chip test device matches the current chip test work order. When the host computer detects that the test device identifier does not match the current device identifier, it determines that the current chip test device does not meet the device matching conditions corresponding to the current chip test work order, and outputs a device mismatch prompt to suspend the current chip test device from continuing to execute the test process corresponding to the current chip test work order.

[0071] Therefore, before the test program is distributed and the chip test is executed, it can be confirmed whether the current chip test work order has been assigned to the current chip test equipment, thereby reducing the risk of false tests caused by incorrect work orders or incorrect machine selection, and then further confirming the target test site used to perform the test in the current chip test equipment.

[0072] Step S140: Based on the test program information, obtain at least one corresponding target test program, and send the at least one target test program to each target test site so that each target test site can run the test program to perform chip test tasks and obtain test results.

[0073] In some embodiments, test program information is used to indicate the test program required to execute the current chip test work order. Test program information may include at least one of the following: test program name, test program version, and test program verification information. Based on the test program information, the host computer can obtain at least one corresponding target test program from the production execution system, the program server, or the local program cache space.

[0074] In some embodiments, during the execution of the chip testing task, temperature monitoring information corresponding to each of the target test stations is acquired; the temperature monitoring information includes the preset test temperature of the target test station and the actual test temperature acquired by the temperature acquisition device; in response to the temperature deviation between the preset test temperature and the actual test temperature meeting the preset temperature abnormality condition, the corresponding target test station is subjected to interruption testing processing.

[0075] In some embodiments, reference Figure 4 The structural block diagram of a chip testing device in one embodiment of the present disclosure shown includes a site control host 510, a test board 520, and a test socket mounted on each test board 520.

[0076] Site control host 510 is used to receive and run the target test program.

[0077] The test board 520 is used to establish a test signal path with the chip under test through a test socket under the control of the site control host 510. The test board 520 can be integrated into the test host as an internal functional board or expansion board of the test host; or, the test board 520 can be set separately from the test host and communicate with the test host through a preset communication interface. The test socket is installed on the test board to directly carry and electrically connect the chip under test.

[0078] The host computer 300 can send the target test program to the site control host 510 of each target test site according to the site communication configuration information corresponding to each target test site.

[0079] In some embodiments, in response to multiple target test sites performing the same chip test task, the host computer 300 can send the same target test program to the multiple target test sites respectively. In response to different target test sites corresponding to different test functions, the host computer can send corresponding target test programs to different target test sites based on the site configuration information of each target test site. The test program includes a test sequence and test cases corresponding to multiple chip test items, and the test cases include at least one of test input information, test item configuration parameters, expected response data, and test judgment rules.

[0080] In some embodiments, the test program includes a test order and test cases corresponding to multiple chip test items, and the test cases include at least one of test item configuration parameters, expected response data, and test judgment rules.

[0081] In some embodiments, reference Figure 5 The diagram shown is a flowchart illustrating the execution of a chip testing project based on test cases in one embodiment of this disclosure. The process of each target test site running the test program to perform chip testing tasks includes the following steps:

[0082] Step S141: Each of the target test sites executes the plurality of chip test items in sequence according to the test order, and when executing any chip test item, at least one of the power supply module, signal excitation module, data acquisition module, interface communication module and test board in the target test site is configured based on the test item configuration parameters of the test program.

[0083] In some embodiments, the test item configuration parameters include at least one of power supply configuration parameters, signal excitation configuration parameters, data acquisition configuration parameters, interface communication configuration parameters, and test board configuration parameters.

[0084] Step S142: Apply test input information from the test case to the chip under test using at least one of the configured power supply module, signal excitation module, interface communication module, and test board. The test input information includes: power supply signal, test excitation signal, or test command.

[0085] Step S143: Collect the test response data returned by the chip under test via the test board through the data acquisition module and / or the interface communication module.

[0086] Step S144: Based on the test judgment rules in the test cases corresponding to the chip test item, compare the test response data with the expected response data to determine the test result corresponding to the chip test item.

[0087] For example, during the power-on current test, the expected response information is "the current should be in the range of 10mA to 50mA"; the test judgment rule is "if the collected current value falls within this range, it passes; if it exceeds this range, it fails." During the communication handshake test, the expected response information is "the response code is 0xA5, and the response time does not exceed 100ms"; the test judgment rule is "if the response code matches and there is no timeout, it passes; otherwise, it fails." During the read / write access test, the expected response information is "the read-back data should be equal to the written data"; the test judgment rule is "if the read-back data matches the access test data, it passes; otherwise, it fails." During the abnormal access test, the expected response information is "a preset abnormal response code is returned"; the test judgment rule is "if the returned abnormal response code meets expectations, it passes; if there is no response, timeout, reset, or an error response code is returned, it fails." During the functional operation test, the expected response information is "the output functional response data meets the preset format, preset status code, or preset result range"; the test judgment rule is "if the functional response data meets the expected response information, it passes; otherwise, it fails."

[0088] Step S145: Based on the test results corresponding to the multiple chip test items, generate the test results corresponding to the chip under test.

[0089] In some embodiments, in response to performing a power-on current test, the target test site is configured with at least one of the power supply module and the data acquisition module. The power supply module is controlled to apply a power supply voltage to the target power pin of the chip under test through the test board according to a preset power-on sequence, and the data acquisition module is controlled to acquire the current value corresponding to the target power pin during the power-on process. The preset power-on sequence may include at least one of the power-on order of multiple power rails, power-on delay time, target voltage value, and voltage ramp-up slope; the current value includes at least one of transient current value, steady-state current value, and peak current value. If the current value is within a preset current judgment range, the power-on current test is determined to have passed; if the current value exceeds the preset current judgment range, the power-on current test is determined to have failed, and the corresponding power supply anomaly information is recorded.

[0090] In response to performing a communication handshake test, the target test site configures at least one of the interface communication module and the test board, configures the communication protocol parameters corresponding to the chip under test based on the test program, and sends a handshake request command to the chip under test through the interface communication module and the test board. The communication protocol parameters may include at least one of communication interface type, communication rate, address information, verification method, and timeout. The target test site receives the handshake response information returned by the chip under test through the interface communication module, and determines the test result of the communication handshake test based on the response code in the handshake response information. For example, when the response code matches a preset successful handshake response code, the communication handshake test is determined to have passed; when no handshake response information is received within a preset time, or when the response code does not match the preset successful handshake response code, the communication handshake test is determined to have failed.

[0091] In response to performing a read / write access test, the target test station configures at least one of the interface communication module, the data acquisition module, and the test board, and determines the read / write access address and access test data based on the test cases corresponding to the test program. The read / write access address may include at least one of a readable / writable register address, a memory address, an interface module address, and an on-chip bus mapping address. The target test station sends a write access command to the chip under test (DUT) through the interface communication module and the test board to write the access test data into the target functional module corresponding to the read / write access address, and sends a read access command to the DUT to collect the readback data returned by the target functional module through the data acquisition module. If the readback data matches the access test data, the read / write access test is determined to have passed; if the readback data does not match the access test data, the read / write access test is determined to have failed, and the corresponding access address, access test data, and readback data are recorded.

[0092] In response to performing an abnormal access test, the target test site configures at least one of the interface communication module, the data acquisition module, and the test board. Based on the test cases corresponding to the test program, it determines the invalid address of the chip under test (DUT) and sends an access test command to the DUT to access the invalid address through the interface communication module and the test board. The invalid address can be an unassigned address or an unauthorized access address. The target test site collects the abnormal response code returned by the DUT through the data acquisition module and determines the test result of the abnormal access test based on the comparison between the abnormal response code and the expected response data. If the abnormal response code matches the expected response data, the abnormal access response of the DUT is determined to be normal; if the abnormal response code does not match the expected response data, or if no response, timeout, or abnormal reset occurs during the access test, the abnormal access test is determined to have failed.

[0093] In response to performing a functional operation test, the target test site configures at least one of the interface communication module, the signal excitation module, the data acquisition module, and the test board. It sends a functional test command to the chip under test (DUT) via the interface communication module, and / or applies a functional test excitation signal to the DUT via the test board through the signal excitation module, thereby triggering the DUT to execute a corresponding functional operation process. The functional operation process may include at least one of the following: preset algorithm execution, interface transmission and reception, data processing, internal module call, or system startup process. The target test site collects the functional response data output by the DUT through the data acquisition module, and determines the test result of the functional operation test based on a comparison between the functional response data and the expected response data. If the functional response data meets the expected response data, the functional operation test is determined to have passed; if the functional response data does not meet the expected response data, the functional operation test is determined to have failed.

[0094] In response to performing a power consumption test, the target test station configures at least one of the power supply module, the signal excitation module, the data acquisition module, and the test board. It controls the power supply module to supply power to the chip under test (DUT) and controls the DUT to enter a preset operating mode via the signal excitation module. The preset operating mode includes at least one of standby mode, normal operation mode, high-load operation mode, and low-power mode. The target test station collects voltage and current sampling values ​​of the DUT corresponding to the preset operating mode via the data acquisition module. Based on the voltage and current sampling values, it determines the power consumption test value of the DUT and determines the test result based on a comparison between the power consumption test value and a preset power consumption judgment range. If the power consumption test value is within the preset power consumption judgment range, the power consumption test is deemed passed; if the power consumption test value exceeds the preset power consumption judgment range, the power consumption test is deemed failed.

[0095] In some embodiments, each target test station can generate test data and test result information corresponding to the chip under test based on the test results of each chip test item. The test data may include at least one of the following: test response data, test judgment value, test pass identifier, test failure identifier, failed item identifier, and abnormal status information for each chip test item. The test result information may include at least one of the following: good / defective product identifier, grading result information, and test log information.

[0096] In some embodiments, the target test site may also determine the bin value corresponding to the chip under test based on the binning rules preset in the test program. The binning rules may include at least one of the following: chip test item priority, mapping relationship between chip test item results and bin values, and mapping relationship between test response data and performance level. For example, in response to the chip under test passing all chip test items, the chip under test is classified into the good product bin; in response to the power-on current test failure, the chip under test is classified into the power supply abnormality bin; in response to the communication handshake test failure, the chip under test is classified into the communication abnormality bin; in response to the read / write access test failure, the chip under test is classified into the access abnormality bin; in response to the functional operation test failure, the chip under test is classified into the functional abnormality bin; and in response to the power consumption test failure, the chip under test is classified into the power consumption abnormality bin.

[0097] In some embodiments, the target test station can send the test result information to a host computer. The host computer can, based on the test result information returned by each target test station, calculate the number of tests, the number of good products, the number of defective products, the yield rate, the number of chips corresponding to each grade value, and the test log information for the current chip test work order. Furthermore, the host computer can also generate material sorting control information based on the grade values ​​and send the material sorting control information to the loading and unloading device, so that the loading and unloading device can move chips with different defects to the corresponding sorting positions.

[0098] In some embodiments, test results may include at least one of the following: test pass result, test failure result, chip test item result, test log, test response data, test time information, and abnormal status information. Each target test station can upload the test results to a host computer, which then summarizes, displays, stores, and / or uploads the test results from multiple target test stations to the production execution system. This enables the automatic acquisition, automatic distribution, and parallel execution of test programs corresponding to the current chip test work order across multiple stations, reducing the risk of mistesting caused by manual selection of test programs.

[0099] In some embodiments, reference Figure 6 The flowchart of a test site anomaly detection method in one embodiment of this disclosure is shown. Step S140 includes the following steps:

[0100] Step S1410: During the execution of the chip testing task at each of the target test sites, each of the target test sites is traversed, and the currently traversed target test site is determined as the site to be evaluated, and the target test sites other than the site to be evaluated are determined as the test reference site set.

[0101] In some embodiments, the test reference site can be one or more. For example, when the current chip testing equipment includes four target test sites, if the current traversal reaches the first target test site, then the first target test site is the site to be evaluated, and the second target test site, the third target test site, and the fourth target test site are test reference sites.

[0102] Step S1420: Obtain the project measurement statistics of the site to be evaluated for several chip test items within a preset statistical window, and obtain the project reference statistics of each test reference site for each chip test item within the preset statistical window.

[0103] In some embodiments, the measured statistical value of the project is used to characterize the statistical test results of the site under the corresponding chip test project, and the project reference statistical value is used to characterize the statistical test results of the reference test site under the corresponding chip test project. For example, in response to the chip test project being a power-on current test, the measured statistical value and the project reference statistical value may be the average power-on current of multiple chips under test within a preset statistical window; in response to the chip test project being a communication handshake test or a read / write access test, the measured statistical value and the project reference statistical value may be the communication failure rate, read / write failure rate, or number of abnormal responses of multiple chips under test within a preset statistical window; in response to the chip test project being a tiered statistical project, the measured statistical value and the project reference statistical value may be the percentage of chips corresponding to a specific tier value.

[0104] For example, taking the i-th target test site as the site to be evaluated and the k-th chip test item as the current chip test item, within a preset statistical window, the i-th site to be evaluated performs the k-th chip test item on each of the M chips to be tested, and obtains multiple test values. , ……, .in, This represents the test value obtained by the i-th evaluation site performing the k-th chip test item on the m-th chip under test, where m = 1, 2, ..., M. The host computer can determine the project measurement statistics value of the i-th evaluation site under the k-th chip test item based on the fusion processing of the project test values ​​of the multiple chips under test. The fusion process includes at least one of mean processing, median processing, outlier removal processing, and weighted processing.

[0105] Step S1430: For any of the chip test items, perform fusion processing on the project reference statistics of each of the test reference sites to obtain the fused project reference statistics corresponding to the chip test item.

[0106] For example, for the k-th chip test item, the host computer can obtain the project reference statistics corresponding to each test reference station under the k-th chip test item, and perform fusion processing on the project reference statistics of multiple test reference stations to obtain the fused project reference statistics corresponding to the k-th chip test item. The fusion processing includes at least one of mean processing, median processing, extreme value removal processing, and weighted processing.

[0107] For example, for the k-th chip test item, the host computer can obtain the project reference value corresponding to each test reference station under the k-th chip test item, and calculate the average of multiple project reference values ​​to obtain the fused project reference statistical value corresponding to the k-th chip test item; or, the host computer can first perform extreme value removal processing on multiple project reference values, and then calculate the average of the remaining project reference values ​​to obtain the fused project reference statistical value corresponding to the k-th chip test item, so as to reduce the impact of short-term anomalies of individual test reference stations on the fused project reference statistical value.

[0108] In some embodiments, the reference statistic value corresponding to the k-th chip test item can be expressed as: If the test reference site includes the j-th target test site, then the reference value of the j-th test reference site under the k-th chip test item can be expressed as: The host computer can reference values ​​for multiple items. Perform fusion processing to obtain .

[0109] Step S1440: Based on the difference between the project measurement statistics and the fusion project reference statistics of the site to be evaluated under each chip test item, determine the project offset evaluation value corresponding to the site to be evaluated under each chip test item.

[0110] In some embodiments, the project offset evaluation value D_i,k of the i-th site to be evaluated under the k-th chip test item can be determined according to the project offset evaluation formula, which can be expressed as:

[0111] (1)

[0112] In equation (1), For the i-th site to be evaluated, the project measurement statistics are for the k-th chip test item. This is a reference statistical value for the fusion project corresponding to the k-th chip test item; This represents the allowable deviation value corresponding to the k-th chip test item. Let be the fluctuation value of the i-th site to be evaluated under the k-th chip test item. This represents the allowable fluctuation value corresponding to the k-th chip test item. The weights for the preset fluctuation terms are set.

[0113] Project fluctuation value in formula (1) It can be determined using the standard deviation calculation formula. The standard deviation calculation formula can be expressed as:

[0114] (2)

[0115] Among them, the allowable deviation values ​​for different chip test items Different, for example, the current chip test item corresponds to a preset current allowable deviation value, the voltage chip test item corresponds to a preset voltage allowable deviation value, the power consumption chip test item corresponds to a preset power consumption allowable deviation value, and the communication chip test item corresponds to a preset communication failure rate allowable deviation value.

[0116] For example, taking the chip power-on test as the k-th chip test item, within a preset statistical window, the i-th evaluation site sequentially performs chip power-on tests on M chips under test, and collects the power-on current value of each chip under test. The host computer can determine the average power-on current of the i-th evaluation site based on multiple power-on current values. and the standard deviation of the on-current And based on the average power-on current of each test reference site, the reference statistical value of the fusion project is obtained. This allows us to determine the project offset evaluation value of the i-th site under chip power-on testing. .

[0117] Step S1450: Based on the project offset evaluation values ​​corresponding to the site to be evaluated under each of the chip test items, determine the site offset evaluation value corresponding to the site to be evaluated.

[0118] In some embodiments, the site offset evaluation value corresponding to the site to be evaluated It can be determined using the following formula:

[0119] (3)

[0120] In equation (3), This is the site offset evaluation value. Let be the weight corresponding to the k-th chip test item. The weight corresponding to the chip test item can be a normalized weight value. This is the evaluation value of the project offset for the i-th site to be evaluated under the k-th chip test item. Therefore, the offset of at least one of multiple test items (such as power-on current test, communication handshake test, read / write access test, and power consumption test) can be combined into the site offset evaluation value for the site to be evaluated.

[0121] Step S1460: In response to the site offset evaluation value corresponding to the site to be evaluated meeting the preset offset condition, it is determined that the site to be evaluated has a test anomaly risk, the test is interrupted for the site to be evaluated, and each risk factor item is checked one by one according to the preset risk investigation order.

[0122] In some embodiments, the risk factors include at least one of the following: test program version, test socket identifier, test board identifier, connection status between the test socket and the test board, contact status between the chip under test and the test socket, power output status, temperature status, and communication connection status.

[0123] For example, when four target test sites execute the same test program, if the average power-on current of the chips under test at the first, second, and third target test sites are all within the normal range and the read / write failure rate is within the preset normal range, while the average power-on current, read / write failure rate, and number of specific sub-values ​​of the chips under test at the fourth target test site are all abnormally high in multiple consecutive preset statistical windows, then it can be determined that the site offset evaluation value of the fourth target test site meets the preset offset condition, and the fourth target test site is interrupted or isolated so that each risk factor item can be checked one by one according to the preset risk check order.

[0124] In some embodiments, the preset risk screening order can also be adjusted based on chip test items that meet the project offset conditions. In response to the site offset evaluation value meeting the preset offset conditions, the host computer can determine the target chip test item that meets the preset project offset conditions, and based on the project type corresponding to the target chip test item, determine the corresponding preset risk screening order from the preset screening order table.

[0125] For example, in response to the project offset evaluation value corresponding to the power-on current test or power consumption test meeting the project offset condition, the preset risk investigation sequence may include: power output status, test program version, test board identifier, contact status between the chip under test and the test socket, connection status between the test socket and the test board, temperature status, and abnormal information in the site log.

[0126] In response to the project offset evaluation value corresponding to the communication handshake test or read / write access test meeting the project offset condition, the preset risk investigation order may include, in sequence: communication connection status, test program version, test board identifier, test socket identifier, contact status between the chip under test and the test socket, connection status between the test socket and the test board, and site log abnormal information.

[0127] This disclosure provides a chip testing system. It should be noted that the principle and technical implementation of the chip testing system can be referenced from the chip testing methods in previous embodiments; therefore, they will not be repeated in this embodiment.

[0128] The chip testing system includes:

[0129] A reading device is used to read the work order identifier pattern of the current chip test work order displayed on a portable terminal, and obtain the work order identifier of the current chip test work order.

[0130] Chip testing equipment, each of which is equipped with at least one test station.

[0131] The control system can be implemented as a host computer system, which can communicate with the production execution system, the reading device, and the chip testing equipment. The host computer system includes at least one host computer, which is used to match the corresponding test configuration information in the production execution system based on the work order identifier; wherein, the test configuration information includes test equipment identifier, test site identifier, and test program information.

[0132] The host computer is also used to verify whether the test device identifier in the test configuration information matches the current chip test device.

[0133] The host computer is further configured to respond to the test device identifier in the test configuration information matching the current chip test device, obtain at least one corresponding target test program based on the test program information, and send the at least one target test program to each of the target test sites, so that each of the target test sites can run the test program to perform chip test tasks and obtain test results.

[0134] It should be noted that the various functional modules in this embodiment can be implemented, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, in the form of a computer program or instruction product. A computer program or instruction product includes one or more computer programs or instructions. When a computer program or instruction is loaded and executed on a computer, it produces, in whole or in part, the flow or function according to this disclosure. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another.

[0135] It should be specifically noted that the flowchart representations of the embodiments described above in this disclosure can be understood as representing a module, segment, or portion of code comprising one or more executable instructions configured to implement a specific logical function or process. Furthermore, the scope of the preferred embodiments of this disclosure includes other implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved.

[0136] For example, Figure 2 , 5 The order of the steps in the method embodiments may vary in specific scenarios and is not limited to the above representation.

[0137] like Figure 7 The diagram shown illustrates the structure of a computer device according to an embodiment of the present disclosure.

[0138] The computer device 700 may be exemplified as a portable terminal, external terminal, host computer, site control host and / or production execution system as described in this disclosure, such as a server, desktop computer, laptop computer, tablet computer, smartphone or other terminal.

[0139] The computer device 700 includes a bus 701, a processor 702, and a memory 703. The processor 702 and the memory 703 can communicate via the bus 701. The memory 703 can store computer programs or instructions. The processor 702 implements the method flow or function of the previous embodiments by running the computer program or instructions in the memory 703, for example... Figure 2 , 5 6.

[0140] Bus 701 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, although only one thick line is used in the diagram, this does not indicate that there is only one bus or one type of bus.

[0141] In some embodiments, processor 702 may be implemented as a central processing unit (CPU), microprocessor unit (MCU), system on chip (System on Chip), or field-programmable array (FPGA). Memory 703 may include volatile memory for temporary data storage during program execution, such as random access memory (RAM).

[0142] The memory 703 may also include non-volatile memory for data storage, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state disk (SSD).

[0143] In some embodiments, the computer device 700 may further include a communicator 704. The communicator 704 is used for communication with external devices. In specific examples, the communicator 704 may include one or more wired and / or wireless communication circuit modules. For example, the communicator 704 may include one or more of, for example, a wired network card, a USB module, a serial interface module, etc. The wireless communication protocols followed by the wireless communication module include, for example, Nearfield Communication (NFC) technology, Infrared (IR) technology, Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Bluetooth (BT), Global Navigation Satellite System (GNSS), etc.

[0144] This disclosure also provides a computer-readable storage medium storing a computer program or instructions, which, when run, implement the method flow or function of any of the previous embodiments.

[0145] That is, the method steps in the above embodiments are implemented as software or computer code that can be stored in a recording medium (such as CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as computer code that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium after being downloaded via a network, so that the method represented herein can be stored in such software processing on a recording medium using a general-purpose computer, a special processor or programmable or special hardware (such as ASIC or FPGA).

[0146] This disclosure may also provide a computer program product, comprising one or more computer programs or instructions, which, when run, perform all or part of the processes or functions described in this disclosure. The computer program product includes one or more computer programs or instructions.

[0147] Computer programs or instructions can be stored in a readable storage medium or transferred from one readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The readable storage medium can be any available medium capable of access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video optical disc; or a semiconductor medium, such as a solid-state drive. The computer-readable storage medium can be a volatile or non-volatile storage medium, or it can include both volatile and non-volatile types of storage media.

[0148] In summary, this disclosure provides a chip testing method and system. The method includes: reading the work order identifier pattern of a current chip test work order displayed on a portable terminal to obtain the work order identifier of the current chip test work order; wherein, the chip test work order corresponds to the establishment of a chip test task; the current chip test work order is determined by matching chip test work orders on an external terminal based on work order information displayed on the external terminal; obtaining the chip test work order corresponding to the current chip test equipment, and matching the corresponding test configuration information in the production execution system based on the work order identifier information of the chip test work order; wherein, the chip test equipment includes at least one test station; the test configuration information includes: test equipment identifier, test station identifier, and test program information; verifying whether the test equipment identifier in the test configuration information matches the current chip test equipment; if so, determining the test station corresponding to the test station identifier as a target test station; obtaining at least one corresponding target test program based on the test program information, and sending the at least one target test program to each target test station so that each target test station runs the test program to execute the chip test task and obtain test results. This disclosure enables the automatic completion of work order identification, test configuration information matching, equipment and site verification, and test program distribution in a production testing environment where multiple chip test work orders and multiple chip test devices coexist. This avoids incorrect test configurations for the chip under test due to manual selection or incorrect entry of work orders.

[0149] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the protection scope of this disclosure.

Claims

1. A chip testing method, characterized in that, include: The work order identifier of the current chip test work order is obtained by reading the work order identifier pattern displayed on the portable terminal; wherein, the chip test work order corresponds to the chip test task establishment; the current chip test work order is determined by matching the chip test work orders on the external terminal based on the work order information displayed on the external terminal. Obtain the chip test work order corresponding to the current chip test equipment, and match the corresponding test configuration information in the production execution system based on the work order identification information of the chip test work order; wherein, the chip test equipment includes at least one test station; the test configuration information includes: test equipment identifier, test station identifier, and test program information; Verify whether the test device identifier in the test configuration information matches the current chip test device; if so, determine the test site corresponding to the test site identifier as the target test site. Based on the test program information, at least one target test program is obtained, and the at least one target test program is sent to each of the target test sites, so that each of the target test sites can run the test program to perform chip test tasks and obtain test results.

2. The chip testing method according to claim 1, characterized in that, The chip testing equipment further includes a loading and unloading device for transporting the chip to be tested to the testing station. The method further includes: When the chip under test is in the loading and unloading device, the first model identification information of the chip under test is read through the loading and unloading device; When the chip under test is at the target test site, the second model identification information of the chip under test is read through the target test site; In response to a mismatch between the first or second model identification information of the chip under test and the target chip model corresponding to the chip test work order, a chip model error message is output, and the test program is suspended at the target test site.

3. The chip testing method according to claim 1, characterized in that, The chip testing equipment includes a loading and unloading device and a station host corresponding to at least one testing station. The chip testing equipment is configured with a host computer for communication connection. The method further includes: Detect the loading and unloading communication connection status between the host computer and the loading and unloading device; Detect the site communication connection status between the host computer and the site host corresponding to the target test site; In response to the communication connection status of the loading / unloading and / or the communication connection status of the station indicating a communication abnormality, a communication abnormality prompt is output, and the test program is suspended from running at the target test station.

4. The chip testing method according to claim 1, characterized in that, Also includes: The test interaction software runs on the host computer, and the test interaction software includes a test preparation display interface, a test process monitoring interface, and a test result display interface. The test preparation display interface is used to display test configuration information obtained from the production execution system based on the work order identification information; The test process monitoring interface is used to display the test logs of each of the target test sites respectively; The test result display interface is used to display the test results of each of the target test sites.

5. The chip testing method according to claim 1, characterized in that, The step of having each of the target test sites run the test program to perform chip testing tasks includes: During the execution of the chip testing task, temperature monitoring information corresponding to each of the target test stations is acquired; the temperature monitoring information includes the preset test temperature of the target test station and the actual test temperature acquired by the temperature acquisition device. In response to the temperature deviation between the preset test temperature and the actual test temperature meeting the preset temperature anomaly condition, the test is interrupted at the corresponding target test site.

6. The chip testing method according to claim 1, characterized in that, The step of having each of the target test sites run the test program to perform chip testing tasks includes: The target test station applies preset excitation signals to multiple input pins of the chip under test through the corresponding test board, and collects the pin output signals fed back by the chip under test through multiple output pins; Based on the pin output signals of the multiple output pins, the pin output feature information corresponding to the chip under test is generated; Verify whether the pin output feature information matches the preset chip feature information corresponding to the chip test work order; if not, output a chip matching error message and pause the test program running at the target test site.

7. The chip testing method according to claim 1, characterized in that, The chip testing task includes multiple chip testing items, and the step of each target testing station running the test program to execute the chip testing task includes: During the execution of the chip testing task at each of the target test sites, each of the target test sites is traversed, and the target test site currently traversed is determined as the site to be evaluated, and the target test sites other than the site to be evaluated are determined as the test reference site set. Obtain the project measurement statistics of the site to be evaluated for several chip test items within a preset statistical window, and obtain the project reference statistics of each test reference site for each chip test item within the preset statistical window. For any of the chip test items, the project reference statistical values ​​of each of the test reference sites are fused to obtain the fused project reference statistical value corresponding to the chip test item; Based on the difference between the project measurement statistics of the site to be evaluated under each chip test item and the reference statistics of the fusion project, the project offset evaluation value of the site to be evaluated under each chip test item is determined. Based on the project offset evaluation value corresponding to each chip test item of the site to be evaluated, the site offset evaluation value corresponding to the site to be evaluated is determined. In response to the site offset evaluation value corresponding to the site to be evaluated meeting the preset offset conditions, it is determined that the site to be evaluated has a test anomaly risk, the test is interrupted for the site to be evaluated, and each risk factor item is checked one by one according to the preset risk investigation order.

8. The chip testing method according to claim 1, characterized in that, The test program includes test sequences and test cases corresponding to multiple chip test items. Each test case includes at least one of test input information, test item configuration parameters, expected response data, and test judgment rules. The test program is run by each of the target test sites to perform chip test tasks and obtain test results, including: Each of the target test sites executes the plurality of chip test items sequentially according to the test order, and when executing any chip test item, at least one of the power module, signal excitation module, data acquisition module, interface communication module and test board in the target test site is configured based on the test item configuration parameters of the test program; By using at least one of the configured power module, signal excitation module, interface communication module and test board, test input information from the test case is applied to the chip under test; The test response data returned by the chip under test via the test board is acquired through the data acquisition module and / or the interface communication module. Based on the test judgment rules in the test cases corresponding to the chip test item, the test response data is compared with the expected response data to determine the test result of the chip test item. Based on the test results of the various chip test items, the test results corresponding to the chip under test are generated.

9. The chip testing method according to claim 8, characterized in that, The chip testing tasks include at least one of power-on current testing, communication handshake testing, read / write access testing, abnormal access testing, functional operation testing, and power consumption testing. The method further includes: In response to performing the power-on current test, the target test site is configured with the power module and the data acquisition module. The power module is controlled to apply the power supply voltage to the target power pin of the chip under test through the test board according to the preset power-on sequence, and the data acquisition module is controlled to collect the current value corresponding to the target power pin during the power-on process. Based on the comparison between the current value and the preset current judgment range, the test result of the power-on current test is determined. In response to performing the communication handshake test, the target test site configures the interface communication module and the test board, sends a handshake request instruction to the chip under test through the test board based on the communication protocol parameters corresponding to the interface communication module, and receives the handshake response information returned by the chip under test. Based on the response code in the handshake response information, the test result of the communication handshake test is determined. In response to the execution of the read / write access test, the target test site configures the interface communication module, the data acquisition module, and the test board. Based on the test cases corresponding to the test program, it determines the address to be read / written and the access test data. Through the interface communication module and the test board, it sends a write access command to the chip under test to write the access test data into the target functional module corresponding to the address to be read / written. It also sends a read access command to read the readback data returned by the target functional module. Based on the consistency between the readback data and the access test data, it determines the test result of the read / write access test. In response to the execution of the abnormal access test, the target test site configures the interface communication module, the data acquisition module, and the test board. Based on the test cases corresponding to the test program, it determines the invalid address of the chip under test, sends an access test command for the invalid address to the chip under test, and collects the abnormal response code returned by the chip under test through the data acquisition module. Based on the comparison between the abnormal response code and the expected response data, it determines the test result of the abnormal access test. In response to performing the functional operation test, the target test site is configured with the signal excitation module, the data acquisition module, and the test board. The signal excitation module is controlled to apply a functional test excitation signal to the chip under test through the test board to trigger the chip under test to execute the corresponding functional operation process. The data acquisition module is controlled to collect the functional response data output by the chip under test. Based on the comparison between the functional response data and the expected response data, the test result of the functional operation test is determined. In response to performing the power consumption test, the target test site is configured with the power module, the signal excitation module, the data acquisition module, and the test board. The test site controls the chip under test to enter a preset working mode. In the preset working mode, the data acquisition module collects the voltage and current sampling values ​​corresponding to the chip under test. Based on the voltage and current sampling values, the power consumption test value of the chip under test is determined. Based on the comparison between the power consumption test value and the preset power consumption judgment range, the test result of the power consumption test is determined.

10. A chip testing system, characterized in that, include: A reading device is used to read the work order identifier pattern of the current chip test work order displayed on a portable terminal, and obtain the work order identifier of the current chip test work order; Chip testing equipment, each of the chip testing equipment is equipped with at least one test station; The control system is communicatively connected to the production execution system, the reading device, and the chip testing equipment, and is used to execute the chip testing method according to any one of claims 1 to 9.

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