A semiconductor testing apparatus

Abstract

This invention discloses a semiconductor testing apparatus, relating to the field of chip testing technology, including a test head and pin cards detachably connected to the test head; wherein, the pin cards are used to connect to the chip under test; the test head includes a main control board and multiple line cards; the main control board and the pin cards are connected only through the multiple line cards to transmit test signals, and the multiple line cards share the communication management functions between the main control board and the pin cards. By directly connecting the main control board to the pin cards through multiple line cards, the main control board no longer needs to be configured with connection ports for connecting pin cards. That is, by removing the connection ports of the main control board and further increasing the number of line cards on the main control board at the removal locations, the test resources can be effectively expanded, solving the problem of insufficient pin card test resources in high-density test scenarios.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more particularly to a semiconductor testing apparatus. Background Technology

[0002] ATE (Automatic Test Equipment) testers are key devices used for automated testing of semiconductor chips. In an ATE tester, a pin header serves as the communication medium between the test head and the device under test (DUT). It is typically a circular PCB board, mounted to the test head using structural components. The pin header is equipped with cantilever pins and multiple connectors. During use, the cantilever pins connect to the DUT, and the connectors connect to the test resources within the test head, enabling chip testing.

[0003] The size and weight of pin cards are limited by factors such as probe stations and PCB manufacturing processes, and cannot be arbitrarily increased. Therefore, the connector resources on pin cards are very limited. In the traditional ATE tester architecture, the test head includes a main control board and multiple line cards. The main control board, as the core control unit, needs to be directly connected to the pin cards via dedicated connectors to transmit four types of signals: management channel signals, presence identification signals, CBIT (Control Bit) control signals, and relay power supply signals. The connector space occupied by the main control board cannot be used for test signal transmission. As the density requirements of test chips increase, the digital and power resources required from the test head also increase. The resource allocation of pin card connectors can no longer meet the high-density testing needs of some customers. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor testing device to solve the technical problem that the resource allocation of pin-card connectors can no longer meet the high-density testing requirements.

[0005] Specifically, the present invention provides the following technical solution: a semiconductor testing device, comprising a test head and pin cards detachably connected to the test head; wherein, the pin cards are used to connect to the chip under test; the test head includes a main control board and multiple line cards; the main control board and the pin cards are connected only through the multiple line cards to transmit test signals and the multiple line cards share the communication management function between the main control board and the pin cards, wherein the communication management function includes at least one of pin card identification management, presence status detection, CBIT control signal transmission, and relay power supply.

[0006] As a preferred embodiment of the semiconductor testing device of the present invention, the pin card is configured with an electronic tag module, an in-situ detection circuit, multiple I2C expansion circuits, and multiple relays.

[0007] In a preferred embodiment of the semiconductor testing apparatus of the present invention, the plurality of line cards include at least one independent line card configured with an I2C management interface and connected to the pin card to read the pin card identity information contained in the electronic tag module.

[0008] In a preferred embodiment of the semiconductor testing apparatus of the present invention, the plurality of line cards include at least one independent line card configured with an in-situ detection interface and connected to the in-situ detection circuit of the pin card to detect the in-situ status information of the pin card.

[0009] In a preferred embodiment of the semiconductor testing apparatus of the present invention, each of the plurality of line cards is configured with an independent I2C expansion interface and connected to the plurality of I2C expansion circuits corresponding to the pin cards. The plurality of I2C expansion circuits expand the serial I2C signals from the plurality of line cards into parallel CBIT signals to control the plurality of relays.

[0010] In a preferred embodiment of the semiconductor testing apparatus of the present invention, the plurality of relays are jointly controlled by the plurality of I2C expansion circuits.

[0011] In a preferred embodiment of the semiconductor testing apparatus of the present invention, each of the plurality of line cards is equipped with an independent power output interface and connected to the pin card, for providing operating power to the plurality of relays.

[0012] In a preferred embodiment of the semiconductor testing apparatus of the present invention, the pin card is configured with a plurality of connectors D for connecting the plurality of line cards.

[0013] In a preferred embodiment of the semiconductor testing apparatus of the present invention, each of the plurality of line cards is equipped with a connector C, and the connector C on the plurality of line cards is connected to the plurality of connectors D with corresponding numbers. The I2C management interface, the in-situ detection interface, the I2C expansion interface and the power output interface are all disposed on the connector C.

[0014] In a preferred embodiment of the semiconductor testing apparatus of the present invention, a serial communication channel is provided between the main control board and the plurality of line cards, so that the main control board can indirectly manage the pin cards through the plurality of line cards.

[0015] The beneficial effects of this invention are as follows: By connecting the main control board directly to the pin cards through multiple line cards, the main control board no longer needs to be configured with connection ports for connecting pin cards. That is, by removing the connection ports of the main control board and further increasing the number of line cards on the main control board at the removal locations, the test resources can be effectively expanded, solving the problem of insufficient pin card test resources in high-density test scenarios. In addition, by adopting the above method, the communication management functions originally borne centrally by the main control board are distributed to multiple line cards. Through the function sharing mechanism, the overload of a single line card is avoided, the reliability and maintainability of the system are improved, and the core control tasks of the main control board and the execution tasks of the line cards are reasonably allocated. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a top view of the pin card in one embodiment of the present invention; Figure 2 This is a diagram showing the connection relationship between the test head and the pin holder in one embodiment of the present invention; Figure 3 This is a simplified diagram of the test head structure in one embodiment of the present invention. Detailed Implementation

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0020] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0021] Furthermore, the present invention will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present invention in detail, for ease of explanation, the cross-sectional views of the device structure will be partially enlarged without adhering to the general scale. Moreover, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention.

[0022] I2C: Inter-Integrated Circuit, a serial communication bus protocol that includes two signal lines: SDA (data line) and SCL (clock line).

[0023] SDA: Serial Data, is a bidirectional signal line responsible for transmitting data in the I2C bus. Together with the clock signal line SCL, it forms a serial communication bus.

[0024] SCL: Serial Clock Line, used to synchronize data transmission and ensure that the sender and receiver exchange data according to the same timing.

[0025] Reference Figures 1-3 In this embodiment, a semiconductor testing device is proposed for automated testing of semiconductor chips, including a test head and pin clips detachably connected to the test head.

[0026] Specifically, the test head includes a main control board and multiple line cards, namely line card 1 to line card N, where N≥2; in this embodiment, N=21 is taken as an example for specific explanation, that is, the test head is configured with twenty-one line cards (numbered 1 to 21); among them, the main control board is the core control unit of the ATE test machine, which is responsible for test process control and resource scheduling; the line cards are the functional boards of the ATE test machine, which are responsible for providing test channels and power.

[0027] Specifically, the pin card is a circular PCB board equipped with cantilever pins and multiple connectors D, which are line cards 1 to M, where M ≥ 2; in this embodiment, M = 21, and the connectors D are numbered 1 to 21. The cantilever pins are used to connect to the chip under test (DUT), and the connectors D are used to connect to the line cards. In use, the pin card connects to the DUT via the cantilever pins and to the corresponding line cards via the multiple connectors D, thereby completing the test resource setup in the semiconductor testing device and enabling the transmission of test signals.

[0028] In this embodiment, the main control board and the pin card are connected only through multiple line cards to transmit test signals and the communication management function between the main control board and the pin card is shared by multiple line cards. This setting distributes the communication management function originally borne by the main control board to multiple line cards. At the same time, the function sharing mechanism avoids the overload of a single line card.

[0029] It is worth noting that in this embodiment, the main control board and the pin card are connected only through multiple line cards. That is, the main control board no longer needs to be configured with a connection port for direct connection to the pin card. In other words, the connection port of the main control board can be removed, and the number of line cards on the main control board can be increased in the removed position. This changes the position from being used only for the transmission of management signals to being used for the transmission of test signals. Thus, the test resources are effectively expanded without increasing the physical size of the pin card. For example, the main control board of the test head of a traditional semiconductor test device is configured with 20 line cards. With the technical solution of this embodiment, the main control board is configured with 21 line cards. That is, by removing the connection port of the main control board and adding 1 line card, the resources are increased by 5%, which solves the problem of insufficient pin card test resources in high-density test scenarios.

[0030] Specifically, the communication management functions include at least one of pin card identification management, presence status detection, CBIT control signal transmission, and power supply.

[0031] Furthermore, the needle card is equipped with an electronic tag module, an in-situ detection circuit, multiple I2C expansion circuits, and multiple relays. The multiple I2C expansion circuits are I2C expansion circuit 1 to I2C expansion circuit X, where X≥2, and the multiple relays are relay 1 to relay Y, where Y≥2. In this embodiment, X=21, and the I2C expansion circuits are numbered 1 to 21. In this embodiment, Y=16, meaning the needle card is equipped with 16 relays. The electronic tag contains needle card identification information, such as the needle card number and model. The in-situ detection circuit is used to generate an in-situ status signal for the needle card to confirm the connection status between the needle card and the test head. The multiple I2C expansion circuits are used to expand the serial I2C signals from multiple line cards into parallel CBIT control signals for controlling multiple relays. The multiple relays are used to perform switching control of the test channel.

[0032] Specifically, multiple line cards, including at least one independent line card configured with an I2C management interface (two signal lines, namely the SDA data line and the SCL clock line), are connected to the pin card to read the pin card identification information contained in the electronic tag module. In this example, line card number 1 is configured with an I2C management interface and is connected to the free pin of connector D numbered 1.

[0033] Specifically, the multiple line cards include at least one independent line card configured with an presence detection interface and connected to the presence detection circuit of the pin card to detect the presence status information of the pin card. In this embodiment, line card number 2 is configured with an presence detection interface and is connected to the free pin of connector D numbered 2.

[0034] It is worth noting that in this embodiment, the in-situ detection interface is a GPIO interface (GPIO: General-Purpose Input Output).

[0035] Specifically, each line card is equipped with an independent I2C expansion interface (two signal lines, namely SDA data line and SCL clock line) and is connected to multiple I2C expansion circuits with corresponding numbers on the pin card. The multiple I2C expansion circuits expand the serial I2C signals from multiple line cards into parallel CBIT signals (CBIT: Control Bit) to control multiple relays.

[0036] It is worth noting that in this embodiment, multiple relays are jointly controlled by multiple I2C expansion circuits. This configuration achieves redundant configuration of control resources. Furthermore, when some line cards or I2C expansion circuits fail, the remaining normal line cards can still continue to control the relays, ensuring the continuity and stability of the testing process.

[0037] That is, in this embodiment, the I2C expansion interface of line card number 1 is connected to the free pin of connector D corresponding to number 1 on pin card, and thus connects to I2C expansion circuit number 1; the I2C expansion interface of line card number 2 is connected to the free pin of connector D corresponding to number 2 on pin card, and thus connects to I2C expansion circuit number 2; and so on, the I2C expansion interface of line card number 21 is connected to the free pin of connector D corresponding to number 21 on pin card, and thus connects to I2C expansion circuit number 21; this arrangement enables 21 I2C expansion circuits to control 16 relays together.

[0038] It is worth noting that in this embodiment, the method of using the I2C expansion interface to connect the I2C expansion circuit greatly saves the pin resources of the connector D of the pin card. For example, in the traditional technical solution, there are 20 line cards and 16 relays. In the traditional technology, CBIT control signal lines are used to connect them. 20 line cards control 16 relays, which requires 20×16=320 CBIT control signal lines. That is, in the traditional technology, the connector D of the pin card needs to provide 320 pins. However, with the 21 line cards (20 inherent line cards + 1 additional line card) controlling 16 relays in this solution, only 21×2=42 I2C signal lines are needed. That is, with this solution, the connector D of the pin card only needs to provide 42 pins, which greatly alleviates the pressure of limited pin resources of the high-density pin card connector D and provides hardware feasibility for connecting higher-density test resources.

[0039] Specifically, each of the multiple line cards is equipped with an independent power output interface and connects to the pin card to provide operating power to multiple relays. In this embodiment, line cards numbered 1 to 21 are connected to the power pins of the corresponding numbered connector D (i.e., numbers 1 to 21) of the pin card through their respective power output interfaces, outputting 5V / 2A power to the pin card to power the relays in a distributed power supply manner, ensuring the relays work normally; at the same time, the distributed power supply can also effectively reduce the power load of a single line card (both added line cards and any existing line cards) and reduce the current density of the power lines.

[0040] Furthermore, a serial communication channel is provided between the main control board and multiple line cards, enabling the main control board to indirectly manage the pin cards through multiple line cards. In this embodiment, the pin card identity information contained in the electronic tag module of the pin card obtained by line card number 1 is reported to the main control board via the serial communication channel. In addition, when the presence detection interface of line card number 2 is successfully connected to the idle pin of connector D of the pin card, the presence detection circuit of the pin card can generate a corresponding presence status signal. The presence status signal is reported to the main control board via the serial communication channel to realize real-time monitoring of the connection status between the pin card and the test head, ensuring that the pin card is correctly installed.

[0041] Furthermore, each of the multiple line cards is equipped with a connector C, and the connector C on the multiple line cards is connected to the multiple connectors D with corresponding numbers to realize the direct connection between the line card and the pin card; in this embodiment, the I2C management interface, in-situ detection interface, I2C expansion interface and power output interface configured on the line card are all set on the connector C.

[0042] In summary, by connecting the main control board directly to the pin cards via multiple line cards, the main control board no longer needs to be configured with connection ports for connecting pin cards. This allows for the removal of connection ports on the main control board and the addition of more line cards at the removal locations, effectively expanding test resources and solving the problem of insufficient pin card test resources in high-density testing scenarios. For example, in this embodiment, adding one line card increases test resources by 5% compared to the traditional 20 line cards. Furthermore, using this method, the communication management functions originally centrally handled by the main control board are distributed across multiple line cards. This function-sharing mechanism avoids overloading a single line card, improving system reliability and maintainability, and achieving a reasonable allocation between the core control tasks of the main control board and the execution tasks of the line cards.

[0043] Furthermore, the adoption of the I2C serial communication protocol to replace the traditional parallel CBIT control method greatly alleviates the pressure of limited D pin resources of high-density pin card connectors, and provides hardware feasibility for connecting higher-density test resources. For example, in this embodiment, the number of signal lines required to control 16 relays is reduced from 320 to 42, with a saving rate of over 85%.

[0044] Furthermore, by using multiple I2C expansion circuits to coordinate the control of relays and multiple line cards to provide distributed power to relays, redundant configuration of control and power resources is achieved, avoiding the risk of system failure due to a single point of failure and improving the continuity and stability of the testing process.

[0045] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A semiconductor testing apparatus, characterized in that, The device includes a test head and pin clips detachably connected to the test head; wherein the pin clips are used to connect to the chip under test; the test head includes a main control board and multiple line clips; The main control board and the pin card are connected only through the multiple line cards to transmit test signals and the multiple line cards share the communication management function between the main control board and the pin card. The communication management function includes at least one of the following: pin card identification management, presence status detection, CBIT control signal transmission, and relay power supply.

2. The semiconductor testing apparatus as described in claim 1, characterized in that, The pin card is equipped with an electronic tag module, an in-situ detection circuit, multiple I2C expansion circuits, and multiple relays.

3. The semiconductor testing apparatus as described in claim 2, characterized in that, The plurality of line cards includes at least one independent line card configured with an I2C management interface and connected to the pin card to read the pin card identity information contained in the electronic tag module.

4. The semiconductor testing apparatus as described in claim 3, characterized in that, The plurality of line cards includes at least one independent line card configured with an in-situ detection interface and connected to the in-situ detection circuit of the pin card to detect the in-situ status information of the pin card.

5. The semiconductor testing apparatus as described in claim 4, characterized in that, Each of the multiple line cards is equipped with an independent I2C expansion interface and is connected to the multiple I2C expansion circuits with corresponding numbers on the pin cards. The multiple I2C expansion circuits expand the serial I2C signals from the multiple line cards into parallel CBIT signals to control the multiple relays.

6. The semiconductor testing apparatus as described in claim 5, characterized in that, The multiple relays are jointly controlled by the multiple I2C expansion circuits.

7. The semiconductor testing apparatus as described in claim 6, characterized in that, Each of the multiple line cards is equipped with an independent power output interface and is connected to the pin card to provide operating power to the multiple relays.

8. The semiconductor testing apparatus as described in claim 7, characterized in that, The pin card is equipped with multiple connectors D for connecting the multiple line cards.

9. The semiconductor testing apparatus as described in claim 8, characterized in that, Each of the multiple line cards is equipped with a connector C. The connector C on the multiple line cards is connected to the multiple connectors D with corresponding numbers. The I2C management interface, the presence detection interface, the I2C expansion interface, and the power output interface are all located on the connector C.

10. The semiconductor testing apparatus as described in claim 1, characterized in that, The main control board and the multiple line cards are all provided with a serial communication channel, so that the main control board can indirectly manage the pin cards through the multiple line cards.

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