Digital integrated circuit testing method and device in multi-task concurrent scene of ship

Abstract

The application relates to the technical field of circuit testing, and particularly discloses a digital integrated circuit testing method and device in a ship multi-task concurrent scene, which comprises the following steps: collecting bit-level event streams of each interface of a ship electronic system, and constructing a system fusion model; constructing a ship multi-task scene library based on the system fusion model; obtaining a fault injection test target of a to-be-tested integrated circuit, generating a cross-interface fault injection script by using the ship multi-task scene library; generating a global time table by using the system fusion model and the cross-interface fault injection script, and performing cross-interface cooperative fault testing on the to-be-tested integrated circuit; and during the testing, real-time statistics of coverage and power consumption are performed. The application adopts an adaptive load modeling technology, introduces a multi-interface cooperative fault injection mechanism, establishes a hardware-accelerated coverage collection and dynamic power consumption perception interface scheduling engine, and improves the coverage of digital application multi-task concurrent scene digital integrated circuit application verification.

Description

Technical Field

[0001] This invention relates to the field of circuit testing technology, and in particular to a method and apparatus for testing digital integrated circuits in a multi-task concurrent scenario on a ship. Background Technology

[0002] With the increasing complexity of digitalization in ship electronic systems, data interaction and control signals between various modules within the ship are becoming more frequent and complex. Modern ships integrate multiple subsystems such as radio detection equipment systems, navigation systems, power control systems, and communication systems. These systems are beginning to use digital integrated circuits with high-speed interfaces such as 1000M Ethernet, PCIe (High-Speed ​​Peripheral Interconnect Bus), and SerDes (serializer / deserializer) as their processing core. Currently, application verification schemes for these integrated circuits require the fabrication of a series of dedicated boards or the use of high-end ATE equipment such as Teradyne and Advantest, which are costly and lack effective verification of high-speed, multi-channel concurrent process load capabilities. Summary of the Invention

[0003] This invention aims to solve the aforementioned problems. To this end, this invention provides a method and apparatus for testing digital integrated circuits in multi-task concurrent scenarios on ships. By leveraging the full programmability of the SoC architecture, employing adaptive load modeling technology, introducing a multi-interface collaborative fault injection mechanism, and establishing a hardware-accelerated coverage collection and a dynamic power consumption-aware interface scheduling engine, this invention improves the coverage of digital integrated circuit application verification in multi-task concurrent scenarios of digital applications.

[0004] This invention provides a method for testing digital integrated circuits in a multi-task concurrent scenario on a ship, and the technical solution adopted is as follows: including: S1: Collect bit-level event streams from each interface of the ship's electronic system during actual operation, and extract the feature vectors for each interface; generate a three-dimensional correlation matrix, saliency matrix, and burst window set for each interface based on the feature vectors; construct a parameterized generator based on the feature vectors and burst window set; construct a system fusion model based on the three-dimensional correlation matrix, saliency matrix, burst window set, and parameterized generator, with a semi-Markov process as the upper-level state driver, the parameterized generator as the lower-level execution unit, and cross-interface correlation as the coupling link; construct a ship multi-task scenario library based on the system fusion model. S2: Obtain the fault injection test target of the integrated circuit under test, and generate a cross-interface fault injection script using the ship multi-task scenario library; S3: Utilize the system fusion model and cross-interface fault injection script to generate a global timetable and perform cross-interface collaborative fault testing on the integrated circuit under test; during testing, real-time statistics of coverage and power consumption are generated.

[0005] Furthermore, the feature vector includes load features, frame structure features, interval features, burst features, error features, and state features.

[0006] Furthermore, cross-interface correlation analysis is performed based on eigenvectors, using a unified PTP clock to calculate cross-correlation and significance on the same time axis, generating a three-dimensional correlation matrix and significance matrix; Periodic and burst structures are identified in the feature vectors, and the main period and burst windows are separated to obtain a set of burst windows.

[0007] Furthermore, the parameterization generators include Ethernet generators, PCIe generators, and SerDes generators.

[0008] Furthermore, the process of constructing the system fusion model is as follows: Constructing the state of a semi-Markov process-driven system And determine the state transition probability matrix corresponding to the system state; This indicates the system's operational phase, including patrol monitoring, scanning, calculation, control issuance, and waiting for feedback. Each time a system state is entered Each parameterization generator uses a subset of parameters corresponding to that state; A three-dimensional correlation matrix is ​​used to determine the burst trigger probability between interfaces, and a coupling function is constructed. From system state The system fusion model is formed by the state transition probability matrix, parameter subset, and coupling function.

[0009] Furthermore, coupling functions Represented as: in, Based on the basic coupling probability, The maximum coupling probability, For interfaces i and j in the lag time The cross-correlation coefficients under the following conditions For interfaces i and j in the lag time The correlation significance index is as follows.

[0010] Furthermore, step S2 includes the following steps: S2.1: Obtain the fault injection test target and select the verification scenario library from the ship multi-task scenario library; S2.2: Based on the three-dimensional correlation matrix of the scenarios in the verification scenario library, filter out the interface combinations; S2.3: Establish a linkage trigger chain for each interface combination, define the type and parameters of interface fault injection, and generate cross-interface fault injection scripts; The methods for generating the linkage trigger chain include: For each interface combination (i, j), select interface i as the main triggering interface and interface j as the related interface; For the main triggering interface, select the fault applicable to that interface; The failure probability of the relevant interface is determined by the coupling function, and the coupling failure strength is the main failure strength multiplied by the coupling function. The start time of the coupled fault is the sum of the start time of the primary fault and the start time of the primary fault. .

[0011] Furthermore, the scenarios involving multiple concurrent tasks on board include emergency response, adverse sea conditions, and increased high load coverage; fault injection test objectives are set based on the characteristics of these scenarios.

[0012] Furthermore, when performing cross-interface collaborative fault testing, dual-loop scheduling is performed based on power consumption; the dual-loop scheduling includes a fast loop and a slow loop; if the instantaneous power consumption is greater than or equal to the power soft threshold, the system enters the fast peak shaving mode and uses the fast loop to quickly reduce power consumption; otherwise, the slow loop is used.

[0013] This invention also provides a digital integrated circuit testing device for multi-task concurrent scenarios on ships, and the technical solution adopted is as follows: including: a host computer and a SOC control unit; The host computer is used to obtain the fault injection test target of the integrated circuit under test and generate a cross-interface fault injection script using the ship multi-task scenario library; The SOC control unit is used to generate a global timetable using a system fusion model and cross-interface fault injection script, and to perform cross-interface collaborative fault testing on the integrated circuit under test; during testing, coverage and power consumption are statistically analyzed in real time and transmitted to the host computer. The construction process of the system fusion model and the ship multi-task scenario library includes: collecting bit-level event streams of each interface of the ship's electronic system during actual operation, and extracting feature vectors for each interface; generating a three-dimensional correlation matrix, saliency matrix, and burst window set for the interface based on the feature vectors; constructing a parameterized generator based on the feature vectors and burst window set; constructing a system fusion model based on the three-dimensional correlation matrix, saliency matrix, burst window set, and parameterized generator, with a semi-Markov process as the upper-level state driver, the parameterized generator as the lower-level execution unit, and cross-interface correlation as the coupling link; and constructing a ship multi-task scenario library based on the system fusion model.

[0014] The above-described one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects: 1. This invention constructs a system fusion model with a semi-Markov process as the upper-level driver and various interface parameterization generators as the lower-level execution units. Combined with a cross-interface three-dimensional correlation matrix as the coupling link, it can generate collaborative traffic across multiple interfaces (such as Ethernet, PCIe, and SerDes) under a unified system state. This invention can realistically simulate the complex data interaction and coupling effects between high-speed interfaces in real-world multi-task concurrent scenarios on ships, such as cruising, emergency response, and severe sea conditions, thus overcoming the shortcomings of existing solutions in verifying the load capacity of high-speed, multi-channel concurrent processes.

[0015] 2. This invention uses a correlation matrix to filter strongly correlated interface combinations and establishes a linked fault injection script that includes a master trigger-coupled propagation mechanism. It can not only inject faults into the main interface, but also automatically and quantitatively propagate cascading faults to related interfaces based on coupling strength and lag time, forming a complete cross-interface fault chain reaction. This provides a direct and effective means to evaluate the system's recovery time, power consumption peak-shaving capability, and adaptive stability under extreme conditions.

[0016] 3. This invention acquires real-time voltage, current, and temperature data of the integrated circuit under test and introduces a dual-loop control logic combining a fast loop and a slow loop. This allows for dynamic adjustment of the test load based on real-time power consumption feedback. While ensuring the chip does not exceed power or temperature limits, the slow loop specifically enhances the testing intensity of low-coverage interfaces, thereby maximizing verification coverage within power consumption constraints.

[0017] 4. This invention utilizes a software-defined approach, employing a parameter generator to simulate the protocol mechanisms and traffic characteristics of various high-speed interfaces, and combines this with hardware acceleration for coverage statistics and power consumption monitoring, thus constructing a complete automated testing system. This completely replaces the traditional approach of manufacturing dedicated test boards for each project or using high-end ATE equipment such as Teradyne and Advantest, significantly reducing the verification cost and test development cycle of digital integrated circuits in marine electronic systems.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a structural block diagram of the device provided by the present invention.

[0021] Figure 2 This is a flowchart of the method provided by the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention. The following embodiments are used to illustrate this invention but should not be used to limit the scope of this invention.

[0023] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0024] The following is combined with Figure 1 and Figure 2 The present invention will be further described in detail below, providing a method and apparatus for testing digital integrated circuits in a multi-tasking concurrent scenario on a ship: This embodiment provides a digital integrated circuit testing device for multi-tasking concurrent scenarios on ships, such as... Figure 1 As shown, the technical solution adopted is as follows: it includes a host computer and a SOC control unit.

[0025] The host computer is used to obtain the fault injection test target of the integrated circuit under test and generate a cross-interface fault injection script using the ship multi-task scenario library; The SOC control unit is used to generate a global timetable using a system fusion model and cross-interface fault injection script, and to perform cross-interface collaborative fault testing on the integrated circuit under test; during testing, coverage and power consumption are statistically analyzed in real time and transmitted to the host computer. The construction process of the system fusion model and the ship multi-task scenario library includes: collecting bit-level event streams of each interface of the ship's electronic system during actual operation, and extracting feature vectors for each interface; generating a three-dimensional correlation matrix, saliency matrix, and burst window set for the interface based on the feature vectors; constructing a parameterized generator based on the feature vectors and burst window set; constructing a system fusion model based on the three-dimensional correlation matrix, saliency matrix, burst window set, and parameterized generator, with a semi-Markov process as the upper-level state driver, the parameterized generator as the lower-level execution unit, and cross-interface correlation as the coupling link; and constructing a ship multi-task scenario library based on the system fusion model.

[0026] The host computer is a computer system that configures application verification parameters and collects test results via Ethernet and other means.

[0027] The SOC control unit includes a PS (Processing System) processor, a PL (Programmable Logic) logic output module, and a power output circuit.

[0028] The PS processor is responsible for scheduling, receiving instructions from the host computer and transmitting test results to the host computer; configuring the simulation of the digital interface; managing the priority of task execution and power-on control; and transmitting logic configuration, timing control requirements and communication protocols to the PL logic output module.

[0029] The PL logic output module (FPGA logic) is responsible for the execution of interface logic, fault generation, and test timing. The concurrency control logic is responsible for controlling the timing of interface simulation communication according to the PS processor configuration; the fault injection control logic is responsible for generating interface communication fault information according to the PS processor configuration; the digital interface simulation logic connects all interface logic to the specified ports according to the PS processor configuration, and performs routine, concurrent, and fault tests and verifications according to the set timing and interface protocol.

[0030] The power output circuit supplies power to the integrated circuit under test according to the configured power-on voltage and power-on sequence.

[0031] The integrated circuit under test uses a PCB with the device to be verified soldered on it or a dedicated IC fixture PCB. It adopts a standardized fan-out method to distinguish between power supply and I / O interfaces, and connects to the SOC control unit through high-speed connectors.

[0032] In this embodiment, as Figure 2 As shown, a method for testing digital integrated circuits in a multi-task concurrent scenario on a ship is provided, including the following steps: S1: Constructing a system fusion model and a ship multi-task scenario library. This involves collecting bit-level event streams from various interfaces of the ship's electronic systems during actual operation, extracting feature vectors for each interface, generating a 3D correlation matrix, saliency matrix, and burst window set based on the feature vectors, constructing a parameterized generator based on the feature vectors and burst window set, and building a system fusion model with a semi-Markov process as the upper-level state driver, the parameterized generator as the lower-level execution unit, and cross-interface correlation as the coupling link based on the system fusion model. Finally, a ship multi-task scenario library is constructed based on this system fusion model.

[0033] This step involves extracting the time-series correlation matrix of high-speed interfaces based on the bit-level event streams of ship electronic systems such as radio detection equipment, navigation, power control, and communication subsystems during actual ship operation (e.g., the correlation between radio detection equipment scanning cycle and data bursts, the correlation between navigation information and power, etc.). A time-dependent system fusion model is then established, with model parameters dynamically adjusted based on interface bandwidth utilization and burst traffic characteristics. Specifically, the steps include: S1.1: Collect bit-level event streams from various high-speed interfaces of the ship's electronic system to form raw data samples with µs-level time precision.

[0034] Collect reproducible bit-level event streams across interfaces to provide a unified timeline sample for subsequent statistical and coupled modeling, with a time accuracy of µs. Obtain the raw log set (µs-level timestamps) and metadata (sampling frequency, synchronization source, clock quality) of the ship's actual operation through data acquisition.

[0035] S1.2: Perform quality cleaning on the original data samples and use the PTP / 1PPS protocol to achieve global clock alignment, forming a consistent event sequence for each interface under the same time base.

[0036] The original data samples are cleaned to remove abnormal data such as missing fields, negative frame lengths, CRC errors, and duplicate sampling. Then, global clock alignment is achieved using PTP / 1PPS. Finally, drift monitoring is performed to retain sequences that meet the synchronization accuracy threshold (<2µs) and generate a consistent event sequence.

[0037] S1.3: Extract features from the consistent event sequence, extract bit-level modelable features on an interface-by-interface basis, and generate a feature vector for each interface.

[0038] For each interface, features are extracted along the time axis in multiple dimensions. The interface feature vector includes load features, frame structure features, interval features, burst features, error features, and state features.

[0039] In ship digital systems, load characteristics include bit rate and utilization rate; Frame structure features include length distribution; Interval characteristics include arrival intervals; Burst characteristics include burst (burst traffic) window statistics and duration distribution; Error characteristics include error rate, retransmission rate, and number of times credit (credit balance) has been exhausted; State characteristics include the LTSSM (Link Training and State Machine) dwell rate and flow-control oscillation frequency.

[0040] S1.4: Cross-interface correlation analysis is performed based on eigenvectors. A unified PTP clock is used to directly calculate cross-correlation and significance on the same time axis, generating a three-dimensional correlation matrix and significance matrix, revealing the coupling strength and hysteresis structure between multiple interfaces of the ship.

[0041] The loading features are extracted from the feature vectors, and the three-dimensional correlation matrix is ​​calculated as follows: in, For interfaces i and j in the lag time The cross-correlation coefficients under the following conditions As expected, Let i be the load characteristic sequence of interface i at time t. For interface j at time t+ The load characteristic sequence, Let be the mean of the sequence at interface i. Let be the mean of the sequence of interface j. Let i be the standard deviation of the sequence at interface i. Let j be the standard deviation of the interface j sequence. The time lag is expressed in µs.

[0042] Permutation is used to evaluate the cross-correlation coefficients in the three-dimensional correlation matrix, generating a significance matrix: in, For interfaces i and j in the lag time The correlation significance index below, The cross-correlation coefficient is calculated from actual observation data. This is the p-value for the permutation test.

[0043] Specific parameters for the displacement test: Number of displacements: 2000; Displacement method: Pair The time index is randomly cyclically shifted to maintain the autocorrelation structure of the sequence. The shift amount is extracted independently for each permutation. Multiple comparison correction: Benjamini-Hochberg FDR control is used to correct for the expansion of the three-dimensional search space. The permutation test outputs significance of 0~1.

[0044] S1.5: Perform periodic and burst structure identification on the feature vector, separate the main period and burst window, and obtain the burst window set.

[0045] The load characteristics of the feature vector are detected in the frequency domain, and the FFT algorithm is used to extract the main period peak (such as the rotation speed of a radio detection device), forming the main period and the secondary period. FFT parameter settings: the number of transform points is set to 2. 18 A Hann window is used as the window function to suppress spectral leakage. Constant false alarm rate (CFAR) peak detection is performed on the power spectral density. Only peaks with a power spectral density exceeding the local noise floor by more than 6 dB are considered effective periodic peaks. The principal period and secondary period are calculated based on the frequencies corresponding to the highest and second-highest effective peaks. If the frequency ratio of the two peaks is close to an integer ratio (tolerance ±2%), it is determined to be a harmonic relationship, and only the principal period corresponding to the fundamental frequency is retained.

[0046] A cumulative sum algorithm is used to detect sudden boundaries in load characteristics. The algorithm parameters are set as follows: the reference mean is the median of the sliding window over the past second of the load characteristic sequence; the minimum detection offset is 2σ, where σ is the standard deviation of the same sliding window; the drift parameter is σ; and the decision threshold is 5σ to ensure that the average running length under steady state is greater than 10. 6 Each sample point is used. The upper and lower cumulative sums are recursively calculated. When the upper cumulative sum is greater than the decision threshold, the time is determined to be the start time. When the lower cumulative sum is greater than the decision threshold, the time is determined to be the end time.

[0047] The second-order autoregressive model AR(2) is used to predict the onset of sudden events.

[0048] For each detected burst, the following structured record is generated and summarized to obtain a burst window set. The structured record of the burst includes the start time, end time, burst intensity, burst prediction, and burst stability. Among them, burst intensity is the ratio of the mean of the load feature sequence within the burst interval to the reference mean; burst prediction is the starting point of the next burst predicted by the AR(2) model; burst stability is the complementary value of the coefficient of variation of the duration of the last 5 bursts.

[0049] S1.6: Based on the feature vectors and burst window sets, construct parameter generators for each typical high-speed interface in the ship system, taking into account the protocol mechanism and flow characteristics of each high-speed interface.

[0050] In this embodiment, typical high-speed interfaces include Ethernet, PCIe, and SerDes.

[0051] (1) The Ethernet generator adopts a model architecture of hybrid arrival process superimposed burst window.

[0052] The arrival process consists of two complex levels: The underlying layer is the update process, and the inter-frame interval follows a truncated normal distribution with a lower truncation limit of 40 bits.

[0053] The upper layer uses a batch arrival mechanism, where the number of frames in each batch follows a geometric distribution, and the batch termination probability is estimated by the reciprocal of the measured average batch frame count.

[0054] The frame length is sampled from the frame structure features.

[0055] The burst mechanism is a two-state Markov modulation process: the arrival rate and window duration of the burst state, as well as the arrival rate and interval duration of the silent state, are all calibrated according to the burst window set.

[0056] The output is a sequence of µs-level bit streams, with priority tags for each frame.

[0057] (2) The PCIe generator adopts a model architecture that combines transaction layer packet-level generation with flow control and link state constraints.

[0058] The generated items include: The proportion of transaction types—MRd (memory read), MWr (memory write), Cpl (completion), Cfg (configuration), and Msg (message)—is statistically determined by frame structure features. Payload size distribution: Payload length distribution grouped by transaction type, determined by actual measurement.

[0059] The constraints include: Credit dynamic management: Employs a three-queue independent credit counting model (Posted, Non-Posted, and Completion). Initial credit values ​​are read from the PCIe configuration space or estimated from state features. Each issued TLP consumes the corresponding type of credit value; credit values ​​are restored upon receiving a Completion TLP or Flow Control Update DLLP. LTSSM state dwell time: The time percentage of each state is driven by the measured values ​​of state characteristics.

[0060] The output is a TLP bit stream sequence, with credit consumption / recovery records and link state transition logs for each TLP.

[0061] (3) The SerDes generator adopts the coding layer bitstream model and supports two mainstream coding schemes: 8b / 10b and 64b / 66b.

[0062] In 8b / 10b encoding mode: Real-time tracking of inconsistencies in the running state (RD- or RD+). The RD state is updated after each code group is output, and the next code group selects the encoding column that matches the current RD state to ensure DC balance; the alignment marker (comma K28.5, etc.), idle sequence, insertion frequency and mode of training sequence are identified by state features.

[0063] In 64b / 66b encoding mode: the initial seed of the scrambler is derived from the burst window number to ensure that the generated sequence is reproducible; a 2-bit synchronization header is inserted every 64 / 66-bit frame header; the proportion of control frame types (idle, error forwarding, etc.) is determined by actual measurement. Common parameters, including line rate, code group / frame length distribution, idle ratio, etc., are all determined by feature vectors.

[0064] Ultimately, by unifying the Ethernet generator, PCIe generator, and SerDes generator, a parameterized generator is obtained. and the corresponding parameter set . Each parameter in the table is accompanied by a label indicating its source, specifying which feature dimension of the feature vector or which burst window of the burst window set it comes from.

[0065] S1.7: Based on the three-dimensional correlation matrix, significance matrix, burst window set and parameterized generator, construct a system fusion model with a semi-Markov process as the upper-level state driver, the parameterized generator of each interface as the lower-level execution unit, and cross-interface correlation as the coupling link, so that it can generate multi-interface collaborative traffic in a unified system state.

[0066] The upper layer of the system fusion model is driven by a semi-Markov process (HSMM) that drives the system state. , This indicates the system's operational phase, including patrol monitoring, scanning, calculation, control issuance, and waiting for feedback. In this embodiment, State transition probability matrix for: The row number corresponds to the current state, and the column number corresponds to the next state. The initial probability vector is [0.85, 0.05, 0.03, 0.05, 0.02], reflecting that the ship spends most of its time in a patrol and surveillance state.

[0067] The lower layer of the system fusion model: each time the system enters a state Each parameterization generator uses a subset of parameters corresponding to that state. , Parameters related to suddenness and load intensity are as follows: Values ​​are retrieved in tiers.

[0068] When coupling the upper and lower layers of the system fusion model, a three-dimensional correlation matrix is ​​used to determine the burst trigger probability between interfaces, and the coupling function is used. Represented as: in, Based on the basic coupling probability, This represents the maximum coupling probability. In this embodiment, =0.05, =0.95.

[0069] From system state State transition probability matrix Parameter subset Coupling function A system fusion model is formed, which is directly loaded into the simulator to generate a multi-interface linked bit stream under a specified initial state and random seed.

[0070] S1.8: During the operation of the system fusion model, the deviation between the simulation output and the actual measurement is monitored in real time. The generator parameters are continuously fine-tuned using a PI control law to ensure that the system fusion model maintains statistical consistency with the real system during operation. Through multi-dimensional statistical verification, the consistency between the simulation output of the system fusion model and the original measured data is comprehensively evaluated, verifying the fidelity of the system fusion model in all dimensions. The verified model parameters and configurations are encapsulated into reproducible scene snapshots to construct a ship multi-mission scene library.

[0071] S2: Generate a cross-interface collaborative fault injection script. Obtain the fault injection test target of the integrated circuit under test, and generate a cross-interface fault injection script using the ship multi-task scenario library.

[0072] S2.1: Obtain the fault injection test target and select the verification scenario library from the ship multi-task scenario library.

[0073] The scenarios involving multiple concurrent tasks on a ship mainly include three types: emergency response, adverse sea conditions, and increased high load coverage. The characteristics that need to be verified for each of these scenarios are as follows: 1. Emergency Response Scenario: HSMM status switches to emergency mode; Ethernet control link load increases; PCIe data transfer tasks are enhanced; SerDes (serial deserializer) link enters high throughput mode; monitor Ethernet frame loss and observe PCIe retransmission storms; verify system recovery time and power consumption peak-shaving capabilities.

[0074] 2. Severe sea conditions: Enhanced periodic disturbances; synchronous jitter across multiple interfaces; increased SerDes symbol error rate; bursty traffic on Ethernet; PCIe credit resources strained; verification of cross-interface propagation relationships and adaptive stability.

[0075] 3. High-load coverage improvement scenarios: Increase the frequency of low-coverage interface tasks; increase low-coverage fault combinations; increase coverage weight in slow loops; limit peak power consumption in fast loops; verify the balance between coverage improvement and power consumption constraints.

[0076] Based on the above characteristics, the specific content of the fault injection test target is set.

[0077] Obtain the fault injection test target and determine the scenario constraints. Scenario constraints include: (1) Operating conditions: cruise, scanning, emergency response, severe sea conditions; (2) Interface combination requirements: It must contain at least two high-speed interfaces of different types, such as Ethernet + PCIe or PCIe + SerDes.

[0078] The index of the ship multi-task scenario library is traversed, and a list of scenario IDs that meet the scenario constraints is filtered to obtain the verification scenario library. For each candidate scenario, the corresponding scenario snapshot file is loaded, and the snapshot integrity is verified.

[0079] After successful verification, the random seed value in the scene is loaded into the global random number generator of the fault injection experiment. This ensures that all randomization operations in subsequent fault injection experiments (such as bit flip position selection, frame drop timing determination, clock drift direction, etc.) are based on this seed, thereby guaranteeing the complete reproducibility of the entire injection experiment. At the same time, the scene version number, loading time, and verification hash value are recorded and written into the metadata header of the injection experiment.

[0080] S2.2: Based on the three-dimensional correlation matrix of the scenarios in the verification scenario library, select interface combinations with sufficiently strong correlation as candidate coupling channels for subsequent linkage fault injection.

[0081] The filtering criteria in this embodiment are: ≥0.80 excludes insignificant combinations. Then, sort the interface combinations from largest to smallest according to the three-dimensional correlation matrix. The higher the ranking of the interface combination, the stronger its coupling strength, the higher the propagation probability in subsequent linkage fault injection, and the more significant the expected response. The screening criteria can also be set as the top-K of the three-dimensional correlation matrix.

[0082] S2.3: Establish a linkage trigger chain for each interface combination, define fault types and fault parameters, and generate cross-interface fault injection scripts.

[0083] Based on the hardware characteristics of the ship system, the main interface fault injection fault types are shown in Table 1, and the fault parameter configurations are shown in Table 2.

[0084] Table 1

[0085] Table 2

[0086] Methods for generating linkage trigger chains include: For each interface combination (i, j), select interface i as the main triggering interface and interface j as the related interface; For the main triggering interface, select the fault applicable to the interface: select the fault type applicable to the interface from the fault type definition table (Table 1), and set the corresponding fault parameters to be injected into the main triggering interface according to Table 2; Coupled propagation fault: Faults at relevant interfaces are defined, with the trigger probability determined by the coupling function. The strength of the coupled fault is the principal fault strength multiplied by [the factor]. That is, the stronger the correlation, the greater the propagation intensity; the weaker the correlation, the weaker the propagation intensity; the coupling fault start time is the fault start time of the main fault plus τ. Each injection script is assigned an independent random seed (derived from the global seed and script number), and a complete versioned snapshot is recorded.

[0087] S3: Utilize the system fusion model and cross-interface fault injection script to generate a global timetable and perform cross-interface collaborative fault testing on the integrated circuit under test; during testing, real-time statistics of coverage and power consumption are generated.

[0088] S3.1: Generate task descriptions based on cross-interface fault injection scripts. A unified JSON data structure is used to describe each task, interface event, and fault injection point. Each scenario consists of several tasks, and each task is bound to an interface, load model, state conditions, priority, period, phase, and fault triggering conditions.

[0089] S3.2: Based on the task description and system fusion model, generate a global timetable with a Gantt-like structure.

[0090] Table 3 shows an example global timeline for emergency response scenarios.

[0091] Table 3

[0092] The output file contains the following information: task start time, interface traffic generation window, fault injection time, cross-interface linkage trigger time, coverage sampling window, power consumption sampling window, adaptive update window, and scene end and replay markers.

[0093] S3.3: Construct the trigger matrix. Convert the global timetable into an executable trigger matrix at the PL end. The trigger matrix is ​​used to control the synchronous operation of various interfaces, fault modules, coverage counters, and power monitoring modules under a unified timeline. This matrix transforms software-layer scenario planning into deterministic trigger signals at the hardware layer.

[0094] Examples of trigger matrices are shown in Table 4.

[0095] Table 4

[0096] S3.4: Perform multi-interface load generation and perform cross-interface collaborative fault injection.

[0097] The parameterization generator is initiated based on the trigger matrix. Interface outputs maintain a consistent microsecond-level timestamp for subsequent fault injection, coverage statistics, and power consumption analysis. When the trigger matrix triggers a fault injection event, the injection script is invoked to perturb the data stream output by the interface generator. On the bit stream output by the parameterization generator, according to the injection script definition, fault perturbation is independently performed on the main trigger interface, generating the perturbed bit stream, and recording the precise time and impact range of the single-interface injection. After the main interface fault is triggered, the fault is propagated to related interfaces after a specified lag time, achieving fault chain propagation and triggering cross-interface collaborative injection.

[0098] Real-time coverage statistics: Hardware acceleration coverage statistics aim to evaluate the simulation integrity and computational coverage of the hardware acceleration link at µs-level high resolution, measure the trigger ratio and path traversal depth of each module, state, and interface event, provide quantitative basis for subsequent model parameter tuning or fault injection strategies, and improve system reproducibility.

[0099] During testing, the PL logic output module is responsible for high-speed execution and counting, while the PS processor performs integrated analysis.

[0100] Coverage indicators are divided according to system structure, as shown in Table 5.

[0101] Table 5

[0102] High-speed event counting logic is embedded next to the hardware acceleration core of each parameter generator and the cross-interface collaborative fault injection module to achieve zero-loss real-time counting of µs-level events, and the collected counting signals are periodically uploaded to the PS processor via AXI bus communication in the PL logic output module.

[0103] The counting logic includes: bit / frame trigger statistics, HSMM state transition records, number of errors, number of successful recoverys, and µs-level timestamps.

[0104] Each coverage index is calculated based on the counting signal.

[0105] The collected counting signals are summarized into a coverage matrix. : The PS processor can obtain the coverage metrics for each dimension by summing the coverage matrix.

[0106] Real-time power consumption-aware dual-loop scheduling: Based on the real-time power consumption feedback of the integrated circuit under test, the load intensity and concurrency of each interface are dynamically adjusted to obtain the correlation test data between interface coverage and power consumption, and a calculation model that can be used for evaluation is established.

[0107] The power consumption sensing and sampling method involves acquiring voltage and current for each voltage rail of the integrated circuit under test, calculating instantaneous power consumption and cumulative energy, and simultaneously acquiring chip temperature through a temperature sensor.

[0108] The PL logic output module collects the voltage and current of each voltage rail with a sampling period of 100 µs, calculates the instantaneous power consumption, and integrates to obtain the cumulative energy; at the same time, it reads the chip temperature; and uses IIR / moving average filtering to suppress the noise of the above sampling to obtain power consumption monitoring data.

[0109] The PS processor uses dual-loop control logic to schedule power consumption based on monitoring data. Specifically: Based on the electrical specifications and thermal design parameters of the integrated circuit under test, constraint parameters are set. The PS processor first uses these constraint parameters to evaluate the power consumption monitoring data. These constraint parameters include the maximum allowable instantaneous power consumption, power soft threshold, maximum allowable current for each power supply rail, and upper limit of chip temperature. The PS processor collects instantaneous power consumption, current for each power supply rail, and chip temperature in real time, and determines whether the system exceeds the limits based on a decision function.

[0110] in, For the decision function, when When =1, execute an emergency stop and trigger an alarm. Instantaneous power consumption For the maximum allowable instantaneous power consumption, To obtain the maximum value, Let r be the current in the electric rail. The maximum permissible current for rail r is... For chip temperature, This is the upper limit of the chip's temperature.

[0111] Set scheduling factors, which include load intensity, concurrency, duty cycle, rate, and coding control parameters.

[0112] when ≥ hour, With a soft power threshold, a fast loop is activated, entering a fast peak shaving mode. Based on task priority and a comparison of coverage benefits / power consumption costs, progressive peak shaving control is performed on interfaces or threads to quickly reduce power consumption. Priority is given to reducing the lowest priority interfaces, followed by reducing traffic arrival rate or burst size, and finally pausing some non-critical task threads.

[0113] when < If the timeout period is greater than or equal to 2 seconds, switch back to the slow loop. The slow loop balances energy consumption and coverage quality, achieving long-term optimization.

[0114] During slow-loop control, the weight of the corresponding interface is increased based on the coverage gap to enhance the probability of event triggering. Specifically: Based on the coverage matrix, the coverage gap is calculated using the following formula: in, For the coverage gap of interface i, Let i be the target coverage. Let be the coverage matrix at time t for interface i.

[0115] Update interface weights based on coverage gaps: in, Let i be the weight at time t+1. To truncate the amplitude limiting function, Let i be the weight of interface at time t. This is the coverage error gain coefficient. This is the lower bound of the interface weight. This represents the upper limit of the interface weight.

[0116] The updated interface weights are mapped to event trigger probabilities (Softmax normalization), and a normalized preference allocation is performed. In this way, the system will not only target one interface for detection, but will also incentivize under-covered interfaces more frequently with a "higher probability," thus achieving long-term coverage optimization.

[0117] Each scheduling action records the scheduling configuration, power consumption and performance observations, and coverage information, forming a three-data set. All three-data sets constitute the test result dataset.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing digital integrated circuits in a multi-task concurrent scenario on a ship, characterized in that, include: S1: Collect bit-level event streams of each interface of the ship's electronic system during actual operation and extract the feature vector of each interface; based on The system generates a 3D correlation matrix, a significance matrix, and a burst window set from the feature vector generation interface. Based on the feature vectors and the burst window set, a parameterized generator is constructed. Based on the 3D correlation matrix, significance matrix, burst window set, and parameterized generator, a system fusion model is constructed with a semi-Markov process as the upper-level state driver, the parameterized generator as the lower-level execution unit, and cross-interface correlation as the coupling link. A ship multi-task scenario library is constructed based on the system fusion model. S2: Obtain the fault injection test target of the integrated circuit under test, and generate a cross-interface fault injection script using the ship multi-task scenario library; S3: Utilize the system fusion model and cross-interface fault injection script to generate a global timetable and perform cross-interface collaborative fault testing on the integrated circuit under test; during testing, real-time statistics of coverage and power consumption are generated.

2. The digital integrated circuit testing method under a multi-task concurrent scenario on a ship as described in claim 1, characterized in that, The feature vector includes load features, frame structure features, interval features, burst features, error features, and state features.

3. The digital integrated circuit testing method under a multi-task concurrent scenario on a ship as described in claim 1, characterized in that, Cross-interface correlation analysis is performed based on eigenvectors, using a unified PTP clock to calculate cross-correlation and significance on the same time axis, generating a three-dimensional correlation matrix and significance matrix; Periodic and burst structures are identified in the feature vectors, and the main period and burst windows are separated to obtain a set of burst windows.

4. The digital integrated circuit testing method under a multi-task concurrent scenario on a ship as described in claim 1, characterized in that, The parameterization generators include Ethernet generators, PCIe generators, and SerDes generators.

5. The digital integrated circuit testing method under a multi-task concurrent scenario on a ship as described in claim 1, characterized in that, The process of constructing the system fusion model is as follows: Constructing the state of a semi-Markov process-driven system And determine the state transition probability matrix corresponding to the system state; This indicates the system's operational phase, including patrol monitoring, scanning, calculation, control issuance, and waiting for feedback. Each time a system state is entered Each parameterized generator uses a subset of parameters corresponding to that state; A three-dimensional correlation matrix is ​​used to determine the burst trigger probability between interfaces, and a coupling function is constructed. From system state The system fusion model is formed by the state transition probability matrix, parameter subset, and coupling function.

6. The digital integrated circuit testing method under a multi-task concurrent scenario on a ship as described in claim 5, characterized in that, Coupling function Represented as: in, Based on the basic coupling probability, The maximum coupling probability, For interfaces i and j in the lag time The cross-correlation coefficients under the following conditions For interfaces i and j in the lag time The correlation significance index is as follows.

7. A method for testing digital integrated circuits in a multi-task concurrent scenario on a ship, as described in claim 6, characterized in that, Step S2 includes the following steps: S2.1: Obtain the fault injection test target and select the verification scenario library from the ship multi-task scenario library; S2.2: Based on the three-dimensional correlation matrix of the scenarios in the verification scenario library, filter out the interface combinations; S2.3: Establish a linkage trigger chain for each interface combination, define the type and parameters of interface fault injection, and generate cross-interface fault injection scripts; The methods for generating the linkage trigger chain include: For each interface combination (i, j), select interface i as the main triggering interface and interface j as the related interface; For the main triggering interface, select the fault applicable to that interface; The failure probability of the relevant interface is determined by the coupling function, and the coupling failure strength is the main failure strength multiplied by the coupling function. The start time of the coupled fault is the sum of the start time of the primary fault and the start time of the secondary fault. .

8. The digital integrated circuit testing method under a multi-task concurrent scenario on a ship as described in claim 1, characterized in that, Ships are subject to multiple concurrent tasks, including emergency response, adverse sea conditions, and high load coverage enhancement; fault injection test objectives are set based on the characteristics of these situations.

9. A method for testing digital integrated circuits in a multi-task concurrent scenario on a ship, as described in claim 1, characterized in that, When performing cross-interface collaborative fault testing, dual-loop scheduling is performed based on power consumption; the dual-loop scheduling includes a fast loop and a slow loop; if the instantaneous power consumption is greater than or equal to the power soft threshold, the fast peak shaving mode is entered, and the fast loop is used to quickly reduce power consumption; otherwise, the slow loop is used.

10. A digital integrated circuit testing device for multi-task concurrent scenarios on ships, characterized in that, A method for testing digital integrated circuits in a multi-task concurrent scenario on a ship, as described in any one of claims 1 to 9, includes: Host computer and SOC control unit; The host computer is used to obtain the fault injection test target of the integrated circuit under test and generate a cross-interface fault injection script using the ship multi-task scenario library; The SOC control unit is used to generate a global timetable using a system fusion model and cross-interface fault injection script, and to perform cross-interface collaborative fault testing on the integrated circuit under test; during testing, coverage and power consumption are statistically analyzed in real time and transmitted to the host computer. The construction process of the system fusion model and the ship multi-task scenario library includes: collecting bit-level event streams of each interface of the ship's electronic system during actual operation, and extracting feature vectors for each interface; generating a three-dimensional correlation matrix, saliency matrix, and burst window set for the interface based on the feature vectors; constructing a parameterized generator based on the feature vectors and burst window set; constructing a system fusion model based on the three-dimensional correlation matrix, saliency matrix, burst window set, and parameterized generator, with a semi-Markov process as the upper-level state driver, the parameterized generator as the lower-level execution unit, and cross-interface correlation as the coupling link; and constructing a ship multi-task scenario library based on the system fusion model.

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