Electronic load-based current adjustment method and device, computer device and medium

Abstract

The application relates to an electronic load-based current adjustment method and device, computer equipment and a medium, comprising the following steps: S11, determining an adjustment parameter; S12, when the adjustment parameter is a peak value, determining an ascending duration based on a direct current offset value of a sine wave and a preset slope, and controlling the direct current offset value to ascend for the ascending duration according to the preset slope; S13, controlling a reading address of a DMA to be switched from a first cache to a second cache; S14, reading second DAC data from a first address of the second cache, transmitting the second DAC data to a DAC chip, timing a first duration for transmitting the second DAC data through a timer, and clearing the timer when the first duration is a period of the timer; and S15, repeating S14 to obtain a first adjusted sine wave, and adjusting a waveform of current drawn from a to-be-tested power supply through the first adjusted sine wave. The method can avoid phase mutation, thereby improving the accuracy of impedance testing and reducing risks.

Description

Technical Field

[0001] This application relates to the field of power supply testing technology, and in particular to a current regulation method, apparatus, computer equipment, and medium based on an electronic load. Background Technology

[0002] Electronic loads, as key equipment in power supply testing, are widely used in the performance verification and parameter testing of various power supply products. In specific application scenarios, such as the AC impedance testing (EIS) of fuel cells, electronic loads are required to have dynamic load-bearing capabilities, meaning they must be able to control the output current of the power supply to change according to a preset sine wave, and the frequency and amplitude of this sine wave need to support continuous adjustment. In such tests, the phase continuity of the waveform is crucial; any abrupt change in phase will lead to serious deviations in the impedance calculation results, and may even damage the power supply or electronic load under test due to current surges.

[0003] To meet the demands of high-frequency dynamic response, existing technologies typically employ a hardware current loop as the core control architecture. Compared to traditional digital current loops, hardware current loops offer superior dynamic response speeds, with control bandwidths typically reaching tens of kHz, enabling precise tracking of high-frequency changing reference signals. In practical circuit implementation, a central processing unit (CPU) usually outputs an analog reference voltage via a digital-to-analog converter (DAC). Subsequently, the hardware current loop circuit controls the conduction of the power transistor based on this reference voltage, thereby regulating the output current.

[0004] To ensure a smooth and low-distortion sinusoidal waveform during hardware current loop loading, the CPU-output DAC reference signal theoretically requires an extremely short update interval (i.e., a high sampling rate). In practical engineering, to reduce CPU load and meet the requirements of high-frequency updates, the microcontroller's direct memory access (DMA) function is typically used to automatically transfer pre-generated waveform data to the DAC peripheral.

[0005] However, limited by the physical length of the DMA cache within the microcontroller, existing solutions struggle to simultaneously meet the conflicting demands of extremely short DAC update intervals and massive waveform data storage. This hardware limitation leads to a significant technical flaw: when the frequency or amplitude of the sine wave changes, the data transmitted to the DAC often jumps because the data in the DMA cache cannot achieve a seamless transition. This discontinuity at the data level manifests as a phase abrupt change in the sine wave. This phase abrupt change not only severely affects the accuracy of power supply impedance testing, but in extreme cases, the instantaneous phase jump can also generate high-frequency harmonic components, impacting the power stage circuitry of the electronic load or the power supply under test, posing a risk of damaging the instrument. Summary of the Invention

[0006] Therefore, it is necessary to provide a current adjustment method, apparatus, computer equipment, and dielectric based on an electronic load to address the aforementioned technical problems. This method can avoid phase abrupt changes, thereby improving the accuracy of impedance testing and reducing risks.

[0007] A current regulation method based on an electronic load, the method comprising: S11. In response to a parameter adjustment operation for a sine wave, determine adjustment parameters; the sine wave is used to draw current from the power supply under test; the sine wave is obtained by the DMA of the electronic load transmitting the first DAC data in the first buffer to the DAC chip of the electronic load; S12. When the adjustment parameter is at its peak value, the rise time is determined based on the DC offset value of the sine wave and the preset slope, and the DC offset value of the sine wave is controlled to rise for the rise time according to the preset slope. S13. Control the DMA read address to switch from the first cache to the second cache containing multiple second DAC data; S14. Starting from the first address of the second cache, read each of the second DAC data sequentially, transmit the read second DAC data to the DAC chip, and use a timer to count the first duration of transmitting the second DAC data. When the first duration reaches the period of the timer, clear the timer. S15. Repeat S14 to obtain a first adjustment sine wave with continuous phase, so as to adjust the waveform of the current drawn from the power supply under test through the first adjustment sine wave.

[0008] In this application, by responding to the parameter adjustment operation for the sine wave, the adjustment parameter is determined. When the adjustment parameter is at its peak, the rise time is determined based on the DC offset value and preset slope of the sine wave. The DC offset value of the sine wave is controlled to rise according to the preset slope for the rise time. The read address of the DMA is controlled to switch from the first cache to the second cache containing multiple second DAC data. Starting from the first address of the second cache, each second DAC data is read sequentially and the read second DAC data is transmitted to the DAC chip. This eliminates the need to overwrite the first DAC data in the first cache, directly saving the steps of real-time calculation of the second DAC data and caching the second DAC data into the first cache. This allows the DMA to seamlessly output the second DAC data by directly switching the cache address, avoiding transmission pauses caused by cache updates. It effectively suppresses the phase change phenomenon of the first adjusted sine wave, so that the waveform of the current drawn from the power supply under test will not have a phase change. This provides a highly continuous excitation signal for impedance testing, improves the accuracy of test results, and reduces potential operational risks.

[0009] In one embodiment, the method further includes: S21. When the adjustment parameter is frequency, the waveform period of the sine wave is updated based on the frequency to obtain the update period; S22. Based on the update cycle and the DMA cache capacity, determine the first amount of data to be transmitted; S23. Based on the first data volume, calculate multiple third DAC data to be transmitted; S24. Store each of the third DAC data into the third cache, and detect in real time whether the DMA has completed the interrupt; S25. When an interrupt signal indicating that the DMA completion interruption is detected, the read address of the DMA is controlled to be switched from the first cache to the third cache; S26. Control the DMA to read each of the third DAC data sequentially starting from the first address of the third cache, transmit the read third DAC data to the DAC chip, and use the timer to count the second duration of transmitting the third DAC data. When the second duration reaches the period of the timer, clear the timer. S27. Repeat S26 to obtain a second adjustment sine wave with continuous phase, so as to adjust the waveform of the current drawn from the power supply under test by means of the second adjustment sine wave.

[0010] In this application, by storing each third DAC data in a third buffer and detecting in real time whether the DMA has completed an interrupt, when an interrupt signal indicating that the DMA has completed an interrupt is detected, the read address of the DMA is controlled to switch from the first buffer to the third buffer, and the DMA is controlled to read the third DAC data from the third buffer and transmit the read third DAC data to the DAC chip. In this way, each waveform cycle of each second adjusted sine wave will be output from zero phase, thereby avoiding the phase switching problem, improving the accuracy of impedance testing and reducing risks.

[0011] In one embodiment, the method further includes: When the expected amount of data to be transmitted corresponding to the waveform period of the sine wave is greater than the cache capacity of the DMA, a prescaler of the timer is calculated based on the waveform period, the maximum count value of the timer, and the cache capacity. The period of the timer is calculated based on the pre-calibration, the waveform period, and the buffer capacity; Based on the second data volume The pre-defined target T4 psc and the period T4 of the timer arr ,pass Calculate the true frequency f0 of the sinusoidal current drawn from the power supply under test; the second data quantity is the amount of the second DAC data stored in the second buffer; the second data quantity is determined based on the waveform period of the sine wave and the buffer capacity of the DMA; The impedance of the power supply under test is determined based on the actual frequency.

[0012] In this application, the impedance of the power supply under test is calculated based on the actual frequency. This avoids calculating the impedance by setting the wrong frequency when there is a deviation between the frequency of the set sinusoidal current and the actual frequency, thereby improving the accuracy of the calculated impedance.

[0013] In one embodiment, the process of determining the second data volume includes: When the expected data volume corresponding to the waveform period is less than or equal to the cache capacity of the DMA, the waveform period is rounded down, and the rounded result is used as the second data volume. When the expected amount of data to be transmitted corresponding to the waveform period is greater than the buffer capacity, the buffer capacity shall be used as the second amount of data.

[0014] In this application, when the expected data transfer amount corresponding to the waveform period is less than or equal to the DMA buffer capacity, the waveform period is rounded down and the rounded result is used as the second data amount. This avoids the distortion of the sinusoidal current pulled out, thereby avoiding errors in calculating the impedance of the power supply under test.

[0015] In one embodiment, the pre-target T4 psc The calculation formula is: ; Where T is the period of the sine wave, and A 缓存 For cache capacity, A 计数 This is the maximum count value of the timer.

[0016] In this application, by means of Calculate the pre-target to obtain an accurate pre-target.

[0017] In one embodiment, the period T4 of the timer arr The calculation formula is: ; Where T is the period of the sine wave, and A 缓存 For cache capacity, T4 psc This is a prescaler for the timer.

[0018] In this application, by means of Calculate the period T4 of the timer. arr This allows for the attainment of a suitable cycle.

[0019] In one embodiment, the method further includes; Upon receiving a pause current-drawing command, the electronic load is prohibited from drawing current from the power supply under test based on the pause current-drawing command.

[0020] In this application, by receiving a command to suspend current drawing, the electronic load is prohibited from drawing current from the power supply under test. This can quickly disconnect the load circuit in case of sudden abnormalities or emergency intervention, effectively preventing the risk of overcurrent damage or thermal runaway of the power supply under test caused by continuous high current drawing. It also avoids damage to the electronic load itself due to long-term overload operation, significantly improving the safety and reliability of the test.

[0021] A current regulation device based on an electronic load, the device comprising: A parameter determination module is used to determine adjustment parameters in response to a parameter adjustment operation for a sine wave; the sine wave is used to draw current from the power supply under test; the sine wave is obtained by the electronic load's DMA transmitting the first DAC data in the first buffer to the DAC chip of the electronic load; The duration calculation module is used to, when the adjustment parameter is at its peak, control the DC offset value of the sine wave to increase the rise time according to the preset slope based on the rise time and the rise time of the sine wave. The address translation module is used to control the DMA read address to be translated from the first cache to the second cache containing multiple second DAC data; The data transmission module is used to sequentially read each of the second DAC data starting from the first address of the second buffer, transmit the read second DAC data to the DAC chip, and use a timer to time a first duration of transmitting the second DAC data, and clear the timer when the first duration reaches the period of the timer; The current adjustment module is used to repeatedly perform the reading and output operations of the second DAC data to obtain a first adjustment sine wave with continuous phase, so as to adjust the waveform of the current drawn from the power supply under test through the first adjustment sine wave.

[0022] A computer device includes a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described above.

[0023] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0024] The aforementioned current adjustment device, computer equipment, and medium based on electronic load determine adjustment parameters in response to parameter adjustment operations for a sine wave. When the adjustment parameters are at their peak, the rise time is determined based on the DC offset value and preset slope of the sine wave. The DC offset value of the sine wave is controlled to rise according to the preset slope for the rise time. The read address of the DMA is controlled to switch from the first cache to the second cache containing multiple second DAC data. Starting from the first address of the second cache, each second DAC data is read sequentially, and the read second DAC data is transmitted to the DAC chip. This eliminates the need to overwrite the first DAC data in the first cache, directly saving the steps of real-time calculation of the second DAC data and caching the second DAC data into the first cache. This allows the DMA to seamlessly output the second DAC data by directly switching the cache address, avoiding transmission pauses caused by cache updates. It effectively suppresses the phase change phenomenon of the first adjusted sine wave, thus ensuring that the waveform of the current drawn from the power supply under test does not exhibit phase changes. This provides a highly continuous excitation signal for impedance testing, improves the accuracy of test results, and reduces potential operational risks. Attached Figure Description

[0025] Figure 1 This is an application environment diagram of a current regulation method based on electronic load in one embodiment; Figure 2 This is a flowchart illustrating a current adjustment method based on an electronic load in one embodiment; Figure 3 The waveform of a sine wave is shown in one embodiment. Figure 4 This is a flowchart of obtaining the second adjusted sine wave in one embodiment; Figure 5 This is a flowchart of obtaining the first adjusted sine wave in one embodiment; Figure 6 This is a schematic diagram of a second adjusted sine wave with the frequency adjusted from 400 Hz to 600 Hz in one embodiment; Figure 7 This is a schematic diagram of a second adjusted sine wave whose frequency is adjusted from 20 kHz to 10 kHz in one embodiment; Figure 8 This is a schematic diagram of the first adjusted sine wave in one embodiment, where the peak value (maximum amplitude) is adjusted from 4A to 24A; Figure 9 This is a waveform diagram showing the frequency being adjusted from 400 Hz to 600 Hz in one embodiment. Figure 10 This is a waveform diagram showing the frequency being adjusted from 20kHz to 10kHz in one embodiment. Figure 11This is a waveform diagram showing the peak value (maximum amplitude) adjusted from 4A to 24A in one embodiment. Figure 12 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0027] The current adjustment method based on electronic load provided in this application embodiment can be applied to, for example... Figure 1 The application environment shown is illustrated. In this environment, an electronic load is electrically connected to the power supply under test (PST), and the electronic load is used to draw current from the PST through a connection channel.

[0028] In one embodiment, such as Figure 2 As shown, a current regulation method based on an electronic load is provided, which can be applied to... Figure 1 Taking the electronic load in the example, the following steps are included: S11. In response to the parameter adjustment operation for the sine wave, determine the adjustment parameters; the sine wave is used to draw current from the power supply under test; the sine wave is obtained by the DMA of the electronic load transmitting the first DAC data in the first buffer to the DAC chip of the electronic load; The parameter adjustment operation is triggered by the user through the electronic load's panel. Specifically, the user inputs adjustment parameters through the electronic load's panel to adjust the electronic load accordingly.

[0029] Outputting a high-frequency sine wave and carrying current are important functions of electronic loads, primarily used for testing the impedance characteristics of the power supply under test. This function also requires the electronic load to support flexible configuration of waveform parameters such as the frequency and peak value (maximum amplitude) of the sine wave.

[0030] The current drawn from the power supply under test (DUT) via a sinusoidal wave is an alternating current whose amplitude varies sinusoidally with time. The first DAC (Digital-to-Analog Converter) data is essentially a set of digital control quantities used to control the magnitude of the output current of the DUT; it is a digital instruction given to precisely control "how much current to draw" from the electronic load. Therefore, by transmitting the first DAC data to the DAC chip of the electronic load, the instantaneous value of the drawn current changes periodically according to a sinusoidal function, that is, the waveform of the drawn current is consistent with a sine wave, and the drawn current is called a sinusoidal current.

[0031] The first DAC data is essentially a set of digital control quantities used to control the output current of the power supply under test. It is a digital instruction given to precisely control "how much current to draw" from the electronic load. During the transmission of the first DAC data, a timer periodically triggers DMA (Direct Memory Access), which in turn triggers SPI (Serial Peripheral Interface) to output the first DAC data to an external DAC chip. The DAC chip then outputs an analog reference current signal to cause the power supply under test to output a sinusoidal current. The entire process is completed automatically without CPU (Central Processing Unit) intervention. Although DMA is fast, the response speed of the DAC chip and the transmission speed of SPI limit the transmission speed of the first DAC data. Therefore, the shortest interval between two consecutive outputs of the first DAC data in this application is 1.0 μs. Considering practical considerations, the maximum cache capacity of DMA is 2048, i.e., the cache capacity is 2048.

[0032] The DAC chip can be 16 bits or other bit widths. Among them, 16-bit DAC chips have high local precision, with a minimum data update period (or setup time) of 1.0μs and a corresponding maximum sampling update rate of 1MHz, thus ensuring that the hardware current loop can acquire a high-frequency, smooth analog reference signal.

[0033] The power source under test includes, but is not limited to, fuel cells, and the impedance refers to AC impedance. Impedance testing of the power source under test includes AC impedance testing of fuel cells.

[0034] In a specific application, the waveform of a sine wave is as follows: Figure 3 As shown. Figure 3 In the diagram, T represents the waveform period of the sine wave, I1 is the current peak value of the sine wave when it is not adjusted, and I0 is the DC offset value / static operating point. The waveform period T, current peak value I1, and DC offset value I0 are all floating-point numbers. These values ​​can all be set via the electronic load's control panel.

[0035] S12. When the adjustment parameter is at its peak value, the rise time is determined based on the DC offset value of the sine wave and the preset slope, and the rise time is controlled to be increased according to the preset slope of the DC offset value of the sine wave. The peak value refers to the maximum amplitude that the first adjusted sine wave is expected to have after adjustment. The preset slope is data that the user sets in advance in the electronic load.

[0036] The formula for determining the rise time is (desired DC offset value - current DC offset value) / preset slope = rise time. Here, the current DC offset value refers to the current DC offset value of the sine wave. The desired DC offset value can be obtained in response to the offset value parameter setting operation; that is, after the user sets the desired DC offset value through the electronic load panel, the desired DC offset value of the first adjusted sine wave can be determined. Alternatively, it can be determined based on the peak value adjustment parameter. Specifically, when the adjustment parameter is at its peak value, the minimum amplitude of the sine wave is taken as the minimum amplitude of the desired first adjusted sine wave, and the average value between the minimum amplitude and the peak value of the first adjusted sine wave is taken as the DC offset value of the first adjusted sine wave. The DC offset value of the first adjusted sine wave is the desired DC offset value.

[0037] The time required to calculate the rise time is very short, so the time to obtain the rise time is negligible. Therefore, in response to the parameter adjustment operation for the sine wave, the DC offset value of the sine wave is controlled to rise at a preset slope for a predetermined rise time. The preset slope is a pre-set value. The result of the DC offset value of the sine wave rising at the preset slope for the predetermined rise time is the DC offset value of the first adjusted sine wave.

[0038] When the peak value changes, the DAC data transferred via DMA needs to first increase the DC offset value of the sine wave to the DC offset value of another sine wave (the desired first adjusted sine wave) according to a preset slope before it can start outputting the adjusted first adjusted sine wave. This process of outputting according to the preset slope is also completed by DMA. The purpose is to prevent abrupt changes in the output first DAC data, that is, to prevent the output DAC data from directly changing from the first DAC data to the second DAC data after responding to the parameter adjustment operation for the sine wave current.

[0039] S13. Control the DMA read address to switch from the first cache to the second cache which contains multiple second DAC data; The second DAC data is essentially a set of digital control quantities used to control the current output of the power supply under test. It is a digital instruction given to precisely control "how much current to draw" of the electronic load.

[0040] The second DAC data stored in the second cache can be predetermined based on the second data volume. The second data volume can be predetermined based on the waveform period of the sine wave and the cache capacity of the DMA. The calculation process for the second DAC data includes: using the second data volume as the desired total number of sampling points M within a complete waveform period of the first adjusted sine wave; for each sampling point index j in the total number of sampling points M, performing a sine function operation to generate the corresponding second DAC data; the specific formula for generating the second DAC data is as follows: d jLet C be the second DAC data corresponding to the j-th sampling point, where C is the preset amplitude coefficient (the difference between the maximum amplitude of the first adjusted sine wave and the DC offset value of the first adjusted sine wave), and D is the preset DC offset value (the DC offset value of the first adjusted sine wave). The calculation of the second DAC data is also called the equal phase interval calculation method.

[0041] After the DC offset value of the sine wave rises according to a preset slope for a certain duration, the read address of the DMA is switched from the first cache to the second cache containing multiple second DAC data.

[0042] S14. Starting from the first address of the second buffer, read the data of each second DAC in sequence, transfer the read second DAC data to the DAC chip, and use a timer to count the first duration of the second DAC data transmission. When the first duration reaches the timer period, clear the timer. The timer period refers to the timer's timing cycle. For example, if the timer period is 100, then after counting to 100, the timer's timing result is reset to zero and it starts timing again from zero.

[0043] S15. Repeat S14 to obtain a first adjustment sine wave with continuous phase, so as to adjust the waveform of the current drawn from the power supply under test through the first adjustment sine wave.

[0044] The first adjusted sine wave is the waveform after adjusting the maximum amplitude of the sine wave. The only difference between the first adjusted sine wave and the sine wave is the maximum amplitude; that is, the maximum amplitude of the first adjusted sine wave is the peak value input through the parameter adjustment operation, while the maximum amplitude of the sine wave is the original peak value.

[0045] When the power supply under test is normal, the waveform of the load current after adjustment by the first adjustment sine wave is almost identical to that of the first adjustment sine wave.

[0046] In the aforementioned current adjustment method based on electronic load, the adjustment parameters are determined in response to the parameter adjustment operation for the sine wave. When the adjustment parameters are at their peak, the rise time is determined based on the DC offset value and preset slope of the sine wave. The DC offset value of the sine wave is controlled to rise according to the preset slope for the rise time. The read address of the DMA is controlled to switch from the first cache to the second cache containing multiple second DAC data. Starting from the first address of the second cache, each second DAC data is read sequentially, and the read second DAC data is transmitted to the DAC chip. This eliminates the need to overwrite the first DAC data in the first cache, directly saving the steps of real-time calculation of the second DAC data and caching the second DAC data into the first cache. This allows the DMA to seamlessly output the second DAC data by directly switching the cache address, avoiding transmission pauses caused by cache updates. It effectively suppresses the phase change phenomenon of the first adjusted sine wave, thus ensuring that the waveform of the current drawn from the power supply under test does not exhibit phase change. This provides a highly continuous excitation signal for impedance testing, improves the accuracy of test results, and reduces potential operational risks.

[0047] In one embodiment, the method further includes: S21. When adjusting the parameter to frequency, update the waveform period of the sine wave based on the frequency to obtain the updated period; The waveform period of a sine wave refers to the time it takes for the amplitude of a sine wave to complete one full sinusoidal change, that is, the time required for the amplitude to go from zero to its positive maximum value, fall back to zero, go to its negative maximum value, and then return to zero.

[0048] The update cycle is calculated as: unit time / f, where unit time is in microseconds (µs) and f is the frequency. For example, the update cycle is calculated as 1,000,000 / f.

[0049] S22. Determine the first amount of data to be transmitted based on the update cycle and the DMA cache capacity; The first data volume to be transmitted refers to the amount of third DAC data stored in the third buffer.

[0050] S23. Based on the first data volume, calculate multiple third DAC data to be transmitted; The calculation process for the third DAC data includes: obtaining the total number of sampling points N of the second adjusted sine wave within a complete update cycle, with the first data volume as the desired value; performing a sine function operation on each sampling point index i in the total number of sampling points to generate the third DAC data; the specific formula for generating the third DAC data is as follows: D iFor the third DAC data corresponding to the i-th sampling point, A is the preset amplitude coefficient (the difference between the maximum amplitude of the second adjusted sine wave and the DC offset value of the first adjusted sine wave), and B is the DC offset value of the second adjusted sine wave.

[0051] S24. Store each third DAC data into the third buffer and detect in real time whether the DMA interrupt has been completed; Specifically, whether the DMA interrupt is complete refers to whether, after responding to the parameter adjustment operation, the DMA has read and output the first DAC data stored at the tail address of the first buffer. If the DMA has read and output the first DAC data from the tail address of the first buffer after responding to the parameter adjustment operation, then the DMA interrupt is considered complete after reading and outputting the first DAC data stored at the tail address, and an interrupt signal is triggered; otherwise, the DMA interrupt is not complete. The DMA interrupt completion status can also be understood as whether the currently output first DAC data is the current controlling the output of the power supply under test with a DC offset value. If so, the DMA interrupt is considered complete, and an interrupt signal is triggered; otherwise, the DMA interrupt is not complete.

[0052] S25. When an interrupt signal indicating a DMA completion interruption is detected, the DMA read address is switched from the first cache to the third cache. Specifically, upon detecting an interrupt signal indicating a DMA completion interruption, the DMA read address is switched from the first buffer to the third buffer, ensuring that the waveform output in each update cycle starts from zero phase, thus effectively avoiding phase switching issues during waveform output. Simultaneously, the DMA is rapidly restarted when the read address is switched from the first buffer to the third buffer.

[0053] When reading data from the third DAC, each data DAC is read sequentially from the starting address in the third buffer.

[0054] When the DMA is rapidly transferring the first DAC data, directly modifying the data in the first buffer would cause a phase shift in the second adjusted sine wave, and the location of this phase shift would be random. Furthermore, if the DMA is stopped during a completion interrupt, then new data is loaded, and the DMA is restarted after loading, the CPU interrupt and data loading processes require time, resulting in a pause at the end of each sine wave cycle. This pause becomes more pronounced at higher frequencies, and the method consumes significant CPU resources. Loading large amounts of data also takes considerable time, and the process of loading new data cannot be interrupted. Therefore, this application directly controls the DMA read address to switch from the first buffer to the third buffer upon detecting an interrupt signal indicating a DMA completion interrupt. Moreover, the third DAC data is pre-buried in the third buffer before detecting the interrupt signal, ensuring that the waveform output in each update cycle starts from zero phase. This effectively avoids phase switching issues during waveform output and saves the waiting time required for data loading.

[0055] S26. Control the DMA to read the data of each third DAC sequentially starting from the first address of the third cache, transfer the read third DAC data to the DAC chip, and use a timer to count the second duration of the third DAC data transmission. When the second duration reaches the timer period, clear the timer. S27. Repeat S26 to obtain a second adjustment sine wave with continuous phase, so as to adjust the waveform of the current drawn from the power supply under test through the second adjustment sine wave.

[0056] In subsequent repetitions of S26, each repetition reads the data from each of the third DACs sequentially, starting from the first address of the third buffer.

[0057] When the power supply under test is normal, the waveform of the load current after adjustment by the second adjustment sine wave is almost identical to that of the second adjustment sine wave.

[0058] In a specific application, the flowchart for obtaining the phase-continuous second adjusted sine wave is as follows: Figure 4As shown. Specifically, in response to the parameter adjustment operation, when the adjustment parameter is frequency, the waveform period of the sine wave is updated based on the frequency to obtain the update period; based on the update period and the DMA cache capacity, the first amount of data to be transmitted is determined; based on the first amount of data, multiple third DAC data to be transmitted are calculated; each third DAC data is stored in the third cache, and the DMA completion interruption is detected in real time; when an interrupt signal indicating DMA completion interruption is detected, the DMA read address is switched from the first cache to the third cache; each third DAC data is read sequentially from the starting address in the third cache; the read third DAC data is transmitted to the DAC chip, and a timer is used to time the second duration of transmitting the third DAC data. When the second duration reaches the timer period, the timer is cleared; if no pause current load command is received, the reading and transmission operation of the third DAC data continues to repeat to output the second adjusted sine wave until a pause current load command is received, and the current load is stopped.

[0059] In this embodiment, by storing each third DAC data in the third buffer and detecting whether the DMA has completed an interrupt in real time, when an interrupt signal indicating that the DMA has completed an interrupt is detected, the DMA read address is controlled to switch from the first buffer to the third buffer, and the DMA is controlled to read the third DAC data from the third buffer and transmit the read third DAC data to the DAC chip. In this way, each waveform cycle of each second adjusted sine wave will be output from zero phase, thereby avoiding the phase switching problem, improving the accuracy of impedance testing and reducing risks.

[0060] In one embodiment, the method further includes: when the adjustment parameter is frequency, if the expected data transfer amount corresponding to the update period of the sine wave is greater than the cache capacity of the DMA, calculating a prescaler of the timer based on the update period, the maximum count value of the timer, and the cache capacity; calculating the period of the timer based on the prescaler, the waveform period, and the cache capacity; and calculating the period of the timer based on the second data amount. The pre-defined target T4 psc and the period T4 of the timer arr ,pass Calculate the true frequency f0 of the sinusoidal current drawn from the power supply under test; the second data quantity is the amount of the second DAC data stored in the second buffer; the second data quantity is determined based on the update period of the sinusoidal wave and the buffer capacity of the DMA; based on the true frequency, determine the impedance of the power supply under test. Further, when the expected data quantity to be transmitted corresponding to the update period is less than or equal to the buffer capacity of the DMA, the update period is rounded down, and the rounded result is used as the second data quantity; when the expected data quantity to be transmitted corresponding to the update period is greater than the buffer capacity, the buffer capacity is used as the second data quantity.

[0061] In one embodiment, the method further includes: When the expected data transfer amount corresponding to the waveform period of a sine wave is greater than the DMA buffer capacity, the timer's prescaler is calculated based on the waveform period, the timer's maximum count value, and the buffer capacity. Calculate the timer period based on the prescaler, waveform period, and buffer capacity; Based on the second data volume Pre-order T4 psc and the timer period T4 arr ,pass Calculate the true frequency f0 of the sinusoidal current drawn from the power supply under test; the second data quantity is the amount of second DAC data stored in the second buffer; the second data quantity is determined based on the waveform period of the sine wave and the buffer capacity of the DMA; The impedance of the power supply under test is determined based on the actual frequency.

[0062] The expected data transmission amount corresponding to the waveform period of a sine wave refers to the expected data transmission amount within one waveform period of a sine wave.

[0063] The maximum count value of a timer is the highest value that the timer can count to. For example, if the timer is a 16-bit timer, then the maximum count value of the timer is 65535.

[0064] The prescaler of a timer is essentially the input clock divider. It determines how many system clock pulses the timer receives before incrementing its internal count by 1. The smallest prescaler unit is 1.0 / 84MHz, meaning that the smallest adjustable frequency step (accuracy) during frequency pre-correction (or pre-compensation) is 1.0 / 84MHz. If the timer period T4 arr If it exceeds 65535 / 84, then increase the minimum unit of the pre-order.

[0065] The formula for calculating the impedance of the power supply under test is: Here, f1 is the true frequency, Z is the impedance of the power supply under test, |Z(f1)| is the impedance magnitude, and θ(f1) is the impedance phase angle. |Z(f1)| = V(f1) / I(f1), where I(f1) is the magnitude of the current drawn by the electronic load, and V(f1) is the voltage fluctuation generated across the power supply under test by the current drawn by the electronic load. The impedance phase angle θ(f1) is the phase difference between the first phase and the second phase. The first phase is the phase of the current drawn by the electronic load, and the second phase is the phase of the voltage generated across the power supply by the current drawn by the electronic load.

[0066] Furthermore, the actual frequency is displayed on the panel of the electronic load.

[0067] In this embodiment, the impedance of the power supply under test is calculated based on the actual frequency. This avoids calculating the impedance by setting the wrong frequency when there is a deviation between the frequency of the set sinusoidal current and the actual frequency, thereby improving the accuracy of the calculated impedance.

[0068] In one embodiment, the process of determining the second data volume includes: When the expected data transfer amount corresponding to the waveform period is less than or equal to the DMA buffer capacity, the waveform period is rounded down, and the rounded result is used as the second data amount. When the expected amount of data to be transmitted corresponding to the waveform period is greater than the buffer capacity, the buffer capacity is used as the second amount of data.

[0069] The expression for rounding down the waveform period T is as follows: , This is the second data volume. This is the floor symbol.

[0070] When the second data quantity is the result of rounding down the waveform period, it may cause a deviation between the actual frequency of the sinusoidal current and the set frequency. Therefore, it is necessary to calculate the actual frequency to avoid determining the impedance of the power supply under test based on an incorrect set frequency.

[0071] The waveform period is data with units, but when using the rounded-down result of the waveform period as the second data value, the unit is disregarded; only the specific value is used as the second data value. For example, if the waveform period is rounded down to 2000µs and the cache capacity is 2048, then 2000µs is used as the second data value. Similarly, when using the cache capacity as the second data value, only the specific value is used. For example, if the cache capacity is 2048, then 2048 is used as the second data value.

[0072] When the expected data transfer amount corresponding to the waveform period is less than or equal to the DMA buffer capacity, if one waveform period is 50µs and DMA takes at least 1µs to transfer one data point, and the data to be transferred is still 2048, then 2048 data points cannot be transferred within one waveform period. Therefore, the transfer amount must be reduced, meaning the second data point must be the result of rounding down the waveform period. If the buffer capacity is still used as the second data point, then waveform distortion will occur. For example, the desired output is a 1kHz sine wave current (waveform period 1000µs). If we insist on using 2048 data points to describe it, then 2048 transfers need to be completed within 1000µs. However, the hardware limit is that transferring one data point takes at least 1µs, meaning that transferring 2048 data points takes at least 2048µs. This makes it impossible to send 2048 data points within the predetermined 1000µs, forcing an extension of the transmission time. This will cause what should have been a 1kHz sine wave to actually become a low-frequency sine wave with a period of approximately 2048µs (approximately 488Hz). Therefore, when the expected amount of data to be transmitted corresponding to the waveform period is less than or equal to the DMA buffer capacity, the waveform period is rounded down and the rounded result is used as the second data amount. This can avoid the distortion of the sinusoidal current and thus avoid errors when calculating the impedance of the power supply under test.

[0073] Furthermore, when the expected data transmission amount corresponding to the waveform period of the sine wave is less than the buffer capacity, the timer's prescaler is a preset value, and the timer's period is a preset period. For example, when the expected data transmission amount corresponding to the waveform period of the sine wave is less than the buffer capacity, the timer's prescaler is 0, and the timer's period is 83µs.

[0074] In this embodiment, when the expected data transfer amount corresponding to the waveform period is less than or equal to the DMA buffer capacity, the waveform period is rounded down and the rounded result is used as the second data amount. This can avoid the distortion of the sinusoidal current pulled out, thereby avoiding errors when calculating the impedance of the power supply under test.

[0075] In one embodiment, the standard T4 psc The calculation formula is: ; Where T is the period of the sine wave, and A 缓存 For cache capacity, A 计数 This is the maximum count value of the timer.

[0076] Pre-order T4 psc yes The result of rounding down.

[0077] Furthermore, when the adjustment parameter is frequency, the formula... In this context, T represents the update period of the sine wave.

[0078] In a specific application, cache capacity A 缓存 The maximum count value A of the timer is 2048. 计数 The maximum count value is 65535. 计数 and cache capacity A 缓存 It is a dimensionless parameter.

[0079] In a specific application, T is 10,000,000 microseconds, A 缓存 For 2048, A 计数 If the value is 65535, then the pre-selected standard is T4. psc The first data point is 6, and the second data point is 2048. The unit of measurement is time.

[0080] In this embodiment, through Calculate the pre-target to obtain an accurate pre-target.

[0081] In one embodiment, the timer period T4 arr The calculation formula is: ; Where T is the period of the sine wave, and A 缓存 For cache capacity, T4 psc This is a prescaler for the timer.

[0082] Timer period T4 arr yes The result of rounding down.

[0083] Furthermore, when the adjustment parameter is frequency, the formula... In this context, T represents the update period of the sine wave.

[0084] In a specific application, T is 10,000,000 microseconds, A 缓存 For 2048, A 计数 The value is 65535, and the pre-order is for T4. psc If the value is 6, then the timer period T4 arr The value is 58593. The period is a dimensionless parameter.

[0085] In this embodiment, through Calculate the period T4 of the timer. arr This allows for the attainment of a suitable cycle.

[0086] In one embodiment, the method further includes; Upon receiving a pause current-drawing command, the electronic load is prohibited from drawing current from the power supply under test based on the pause current-drawing command.

[0087] The electronic load draws current from the power supply under test, including a sinusoidal current, a first adjusted sinusoidal current, and a second adjusted sinusoidal current.

[0088] In this embodiment, when a pause current-drawing command is received, the electronic load is prohibited from drawing current from the power supply under test based on the pause current-drawing command. This can quickly disconnect the load circuit in case of sudden abnormality or emergency intervention, effectively preventing the risk of overcurrent damage or thermal runaway of the power supply under test caused by continuous high current drawing. At the same time, it also avoids damage to the electronic load itself due to long-term overload operation, significantly improving the safety and reliability of the test.

[0089] This application also provides an application scenario in which the above-described current regulation method based on electronic load is applied. Specifically, the application of the current regulation method based on electronic load in this scenario is as follows: like Figure 5 As shown, when the adjustment parameter is at its peak, the timer's preset target, period, and the amount of second data to be transferred via DMA are calculated. Based on the phase interval of the second data amount, the amount of second DAC data to be transferred in one sine wave cycle is calculated. The sine DMA is stopped, and simultaneously, output is started from one sine wave center value to another sine wave center value at a certain slope (the DC offset value of the sine wave rises according to the preset slope for a certain duration). This continues until the slope DMA is complete. The DMA read address is switched from the first cache to the second cache containing multiple second DAC data, and each second DAC data is read sequentially starting from the first address of the second cache, transferring the read second DAC data to the DAC chip. The first duration of the second DAC data transfer is timed using a timer, and the timer is reset when the first duration reaches the timer's period. Until a pause current load command is received, the second DAC data reading and transfer operations continue to repeat, obtaining the first adjusted sine wave, until a pause current load command is received, at which point the current load is stopped.

[0090] Figure 6 To use the second adjusted sine wave output by this application when adjusting the frequency from 400 Hz to 600 Hz, Figure 7 To use the second adjusted sine wave output by this application when adjusting the frequency from 20kHz to 10kHz, Figure 8 To adjust the peak value (maximum amplitude) from 4A to 24A, the first adjusted sine wave output by this application is used. Figure 6 and Figure 7 As can be seen, there was no abrupt phase change during frequency switching. When the signal frequency reached 20kHz, the signal remained relatively smooth without any step changes. Figure 9 The waveform diagram is generated when the frequency is adjusted from 400Hz to 600Hz, and the data in the DMA cache is directly rewritten. Figure 10 The waveform diagram is generated when the frequency is adjusted from 10kHz to 20kHz, and the data in the DMA cache is directly rewritten. Figure 11 This is a waveform diagram showing the direct rewriting of data in the DMA cache when the peak value (maximum amplitude) is adjusted from 4A to 24A. From Figure 9 , Figure 10 , Figure 11 As can be seen, the sine wave phase undergoes multiple abrupt changes during switching. These abrupt changes in the reference signal can potentially damage the equipment, and using an incorrect sampling signal to calculate the AC impedance of the fuel cell can lead to erroneous results. There are two reasons for these multiple phase abrupt changes: First, if the DMA is using cached data while the CPU is rewriting the data in the cache, a data conflict will occur. Second, even if the CPU rewrites the cached data quickly, the DMA's current output data is uncertain when it reloads new data, but the new data always starts from the center value (DC offset value), so a phase abrupt change will still occur. Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The horizontal axis represents time, and the vertical axis represents amplitude.

[0091] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0092] Based on the same inventive concept, this application also provides an electronic load-based current regulation device for implementing the above-described electronic load-based current regulation method. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more electronic load-based current regulation device embodiments provided below can be found in the limitations of the electronic load-based current regulation method described above, and will not be repeated here.

[0093] In one embodiment, a current regulation device based on an electronic load is provided, comprising: A parameter determination module is used to determine adjustment parameters in response to a parameter adjustment operation for a sine wave; the sine wave is used to draw current from the power supply under test; the sine wave is obtained by the electronic load's DMA transmitting the first DAC data in the first buffer to the DAC chip of the electronic load; The duration calculation module is used to determine the rise duration based on the DC offset value of the sine wave and the preset slope when the adjustment parameter is at its peak, and to control the DC offset value of the sine wave to rise for the rise duration according to the preset slope. The address translation module is used to control the DMA read address to be translated from the first cache to the second cache containing multiple second DAC data; The data transmission module is used to sequentially read each of the second DAC data starting from the first address of the second buffer, transmit the read second DAC data to the DAC chip, and use a timer to time a first duration of transmitting the second DAC data, and clear the timer when the first duration reaches the period of the timer; The current adjustment module is used to repeatedly perform the reading and output operations of the second DAC data to obtain a first adjustment sine wave with continuous phase, so as to adjust the waveform of the current drawn from the power supply under test through the first adjustment sine wave.

[0094] Each module in the aforementioned current regulation device based on electronic load can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0095] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 12 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores various types of data. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a current regulation method based on an electronic load.

[0096] Those skilled in the art will understand that Figure 12 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0097] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0098] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0099] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0100] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0101] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A current regulation method based on an electronic load, characterized in that, The method includes: S11. In response to a parameter adjustment operation for a sine wave, determine adjustment parameters; the sine wave is used to draw current from the power supply under test; the sine wave is obtained by the DMA of the electronic load transmitting the first DAC data in the first buffer to the DAC chip of the electronic load; S12. When the adjustment parameter is at its peak value, the rise time is determined based on the DC offset value of the sine wave and the preset slope, and the DC offset value of the sine wave is controlled to rise for the rise time according to the preset slope; the formula for determining the rise time is (expected DC offset value - current DC offset value) / preset slope; S13. After controlling the DC offset value of the sine wave to rise for the rise time according to the preset slope, control the read address of the DMA to switch from the first cache to the second cache containing multiple second DAC data. S14. Starting from the first address of the second cache, read each of the second DAC data sequentially, transmit the read second DAC data to the DAC chip, and use a timer to count the first duration of transmitting the second DAC data. When the first duration reaches the period of the timer, clear the timer. S15. Repeat S14 to obtain a first adjustment sine wave with continuous phase, so as to adjust the waveform of the current drawn from the power supply under test through the first adjustment sine wave. The method further includes: S21. When the adjustment parameter is frequency, the waveform period of the sine wave is updated based on the frequency to obtain the update period; S22. Based on the update cycle and the DMA cache capacity, determine the first amount of data to be transmitted; S23. Based on the first data volume, calculate multiple third DAC data to be transmitted; S24. Store each of the third DAC data into the third cache, and detect in real time whether the DMA has completed the interrupt; S25. When an interrupt signal indicating that the DMA completion interruption is detected, the read address of the DMA is controlled to be switched from the first cache to the third cache; S26. Control the DMA to read each of the third DAC data sequentially starting from the first address of the third cache, transmit the read third DAC data to the DAC chip, and use the timer to count the second duration of transmitting the third DAC data. When the second duration reaches the period of the timer, clear the timer. S27. Repeat S26 to obtain a second adjustment sine wave with continuous phase, so as to adjust the waveform of the current drawn from the power supply under test by means of the second adjustment sine wave.

2. The method according to claim 1, characterized in that, The method further includes: When the expected amount of data to be transmitted corresponding to the waveform period of the sine wave is greater than the cache capacity of the DMA, a prescaler of the timer is calculated based on the waveform period, the maximum count value of the timer, and the cache capacity. The period of the timer is calculated based on the pre-calibration, the waveform period, and the buffer capacity; Based on the second data volume The pre-defined target T4 psc and the period T4 of the timer arr ,pass Calculate the true frequency f0 of the sinusoidal current drawn from the power supply under test; the second data quantity is the amount of the second DAC data stored in the second buffer; the second data quantity is determined based on the waveform period of the sine wave and the buffer capacity of the DMA; The impedance of the power supply under test is determined based on the actual frequency.

3. The method according to claim 2, characterized in that, The process of determining the second data volume includes: When the expected data volume corresponding to the waveform period is less than or equal to the cache capacity of the DMA, the waveform period is rounded down, and the rounded result is used as the second data volume. When the expected amount of data to be transmitted corresponding to the waveform period is greater than the buffer capacity, the buffer capacity shall be used as the second amount of data.

4. The method according to claim 2, characterized in that, The predetermined target T4 psc The calculation formula is: ; Where T is the period of the sine wave, and A 缓存 For cache capacity, A 计数 This is the maximum count value of the timer.

5. The method according to claim 2, characterized in that, The period T4 of the timer arr The calculation formula is: ; Where T is the period of the sine wave, and A 缓存 For cache capacity, T4 psc This is a prescaler for the timer.

6. The method according to claim 1, characterized in that, The method further includes; Upon receiving a pause current-drawing command, the electronic load is prohibited from drawing current from the power supply under test based on the pause current-drawing command.

7. A current regulation device based on an electronic load, used to perform the method according to any one of claims 1-6, characterized in that, The device includes: A parameter determination module is used to determine adjustment parameters in response to a parameter adjustment operation for a sine wave; the sine wave is used to draw current from the power supply under test; the sine wave is obtained by the electronic load's DMA transmitting the first DAC data in the first buffer to the DAC chip of the electronic load; The duration calculation module is used to determine the rise duration based on the DC offset value and preset slope of the sine wave when the adjustment parameter is at its peak, and to control the DC offset value of the sine wave to rise for the rise duration according to the preset slope; the formula for determining the rise duration is (expected DC offset value - current DC offset value) / preset slope; The address translation module is used to control the read address of the DMA to be translated from the first cache to the second cache containing multiple second DAC data after the DC offset value of the sine wave is increased according to the preset slope for the rise time. The data transmission module is used to sequentially read each of the second DAC data starting from the first address of the second buffer, transmit the read second DAC data to the DAC chip, and use a timer to time a first duration of transmitting the second DAC data, and clear the timer when the first duration reaches the period of the timer; The current adjustment module is used to repeatedly perform the reading and output operations of the second DAC data to obtain a first adjustment sine wave with continuous phase, so as to adjust the waveform of the current drawn from the power supply under test through the first adjustment sine wave.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 6.

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