Black phosphorus-based wide-spectrum mid-infrared m-z electro-optic modulator and preparation method thereof

CN122546482APending Publication Date: 2026-08-11SHANGHAI INSTITUTE OF TECHNICAL PHYSICS CHINESE ACADEMY OF SCIENCES
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-03-13
Publication Date
2026-08-11

AI Technical Summary

Technical Problem

[0009]本发明的目的在于提供一种基于多层黑磷(Black phosphorus , BP)作为多量子阱的n-i-n异质结结构的Mach-Zehnder电光调制器(MZM),解决现有技术中存在的调制效率低、工作波段窄、功耗高的技术问题之一

Benefits of technology

将基于多层BP层的n-i-n异质结结构应用在电光调制器中,利用多层BP层的高载流子迁移率和强量子限制斯塔克效应,实现低驱动电压下的高效调制。

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Abstract

This invention belongs to the field of modulator technology, and particularly relates to a broadband mid-infrared M-Z electro-optic modulator based on black phosphorus and its fabrication method. It addresses one of the technical problems existing in the prior art: low modulation efficiency, narrow operating band, and high power consumption. The key technical points are: using a SiO2 / Si substrate; an n-i-n heterojunction is disposed above the substrate layer, consisting of two n-type semiconductor layers and a quantum well composite layer sandwiched between the two n-type semiconductor layers; all n-type semiconductor layers are n-type Si layers; the i-layer consists of two intrinsic SiO2 layers and multiple BP layers located between the two intrinsic SiO2 layers; the intrinsic SiO2 layers are respectively connected to the n-type semiconductor layers; a waveguide structure is built based on the n-i-n heterostructure; the electrodes include a capacitively loaded traveling wave electrode disposed on the top of the n-i-n heterojunction structure; and a bias electrode disposed on the bottom n-type semiconductor layer.
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Description

Technical Field

[0001] This invention belongs to the field of modulator technology, and particularly relates to a broadband mid-infrared MZ electro-optic modulator based on black phosphorus and its preparation method. Background Technology

[0002] The mid-infrared band (usually referring to the 2-5 μm wavelength range) has unique spectral response characteristics in the thermal infrared band and is very sensitive to the thermal radiation of high-temperature targets (it can penetrate clouds and fog to continuously capture the thermal radiation of objects themselves day and night). Therefore, it has important application value in environmental monitoring, medical diagnosis, national defense security, communication technology and other fields.

[0003] In modern mid-infrared photonic systems, electro-optic modulators are key functional components, responsible for converting electrical signals into optical signals. By precisely controlling parameters such as the intensity, phase, and polarization of the optical carrier, efficient information loading and transmission are achieved. The performance of mid-infrared electro-optic modulation determines the information processing efficiency of the entire photonic system.

[0004] Disadvantages of conventional technologies:

[0005] The performance of current mid-infrared electro-optic modulators is limited by the inherent limitations of traditional material systems (lithium niobate, gallium arsenide, etc.), specifically in the following four aspects: 1. Lithium niobate (LiNbO3) is a mature electro-optic material with excellent performance in the visible to near-infrared band, but its electro-optic coefficient (e.g., ro) in the mid-infrared (2-5 μm) band is relatively low. 33 The modulation depth decreases significantly (to only 60%–70% of that in the near-infrared band), leading to a reduction in modulation depth and an increase in insertion loss. For example, in the 3.3 μm band (characteristic absorption peak of methane), lithium niobate-based modulators require a longer operating length (typically greater than 10 mm) to achieve the target modulation efficiency, which not only increases the device size but also introduces additional optical losses (typically greater than 3 dB / cm), making it difficult to meet the miniaturization and low power consumption requirements of portable trace gas detection systems.

[0006] 2. Group III-V semiconductor materials, represented by gallium arsenide (GaAs) and indium phosphide (InP), possess high mid-infrared electro-optic activity, but their fabrication relies on complex epitaxial processes such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). Atomic-level thin film growth must be controlled under ultra-high vacuum conditions, resulting in high equipment costs and low growth efficiency. Furthermore, the lattice matching requirements for the epitaxial layer are stringent, and the defect density must be controlled within 10-1. 6 cm - The price of the device is below 2, which further increases the unit manufacturing cost (currently, the price of a single semiconductor modulator chip is about 5 to 8 times that of a lithium niobate device).

[0007] 3. Most existing commercial modulators cannot meet the requirements for efficient modulation across the entire 2–5 μm spectrum. For example, GaAs modulators based on quantum well structures have good response in the 3–4 μm band, but their modulation efficiency drops sharply above 4.5 μm due to a surge in the absorption coefficient. While emerging materials such as chalcogenide glasses cover a wide spectrum, they suffer from low electro-optic coefficients (typically less than 10 pm / V) and poor thermal stability (temperature coefficient greater than 10 ppm). -4 Issues such as / ℃).

[0008] 4. Traditional modulators often require high drive voltages to achieve deep modulation (typical half-wave voltage V of lithium niobate modulators). π Greater than 10 V, V of semiconductor modulator π With a power consumption of approximately 5–8 V, the overall power consumption can reach hundreds of milliwatts when combined with external drive circuitry. This cannot meet the needs of future low-power applications such as wearable medical devices (e.g., non-invasive blood glucose monitoring bracelets, which require power consumption of less than 10 mW) and drone-borne sensors (which require a battery life of more than 2 hours). Summary of the Invention

[0009] The purpose of this invention is to provide a Mach-Zehnder electro-optic modulator (MZM) based on a nin heterojunction structure with multiple black phosphorus (BP) as a multi-quantum well, which solves one of the technical problems of low modulation efficiency, narrow operating band and high power consumption in the prior art.

[0010] Terminology Explanation: Unless otherwise defined, all technical terms in this document have the same meanings as commonly understood by one of ordinary skill in the art to which the subject matter of the claims pertains. Unless otherwise stated, all patents, patent inventions, and publications cited in this document are incorporated herein by reference in their entirety. If multiple definitions exist for terms in this document, the definitions in this chapter shall prevail.

[0011] It should be understood that the above brief description and the following detailed description are exemplary and for illustrative purposes only, and do not limit the subject matter of the invention in any way. In this invention, the singular is used in conjunction with the plural unless otherwise specifically stated. It should also be noted that, unless otherwise stated, the use of “or” or “or” means “and / or”. Furthermore, the use of the term “comprising” and other forms such as “including,” “containing,” and “contains” are not limiting.

[0012] The term "SiH4" used in this article refers to silane.

[0013] The term "PH3" used in this article refers to phosphine.

[0014] The term "Mach-Zehnder" as used in this article refers to an optical device based on the interference phenomenon of light, which is widely used in optical communication, fiber optic sensing, quantum optics and integrated optics.

[0015] The term “TEOS, Si(OC2H5)4” used in this article refers to tetraethoxysilane. The chemical formula of TEOS is Si(OC2H5)4, and its molecular weight is 208.33.

[0016] The term "O3" used in this article refers to ozone.

[0017] The term "PI" used in this article refers to polyimide.

[0018] The term "CL-TWE" used in this article refers to: capacitively loaded traveling wave electrode.

[0019] The term "ALD" used in this article refers to atomic layer deposition.

[0020] The term "RCA" as used in this article refers to a standard and critical wet cleaning process used in substrate preparation. RCA is primarily used to remove contaminants such as organic residues, metal ions, and particulate matter from the surface of silicon wafers or substrates to ensure high-quality subsequent processes and the reliability of electronic components. The following is a detailed introduction to RCA cleaning: The term "LPCVD" used in this article refers to low-pressure chemical vapor deposition.

[0021] The term “ICP-CVD” used in this article refers to inductively coupled plasma chemical vapor deposition.

[0022] The term "bias electrode" as used in this article refers to an electrode used to apply a fixed DC voltage or current to an electronic or electrochemical system. Its core function is to provide a stable operating point for a device or circuit, or to regulate physical processes through an electric field / potential.

[0023] The term "AZ 5214" used in this article refers to a negative / positive dual-development photoresist developed in the United States. It is a type of ultraviolet photoresist and is widely used in the fields of semiconductors, microelectronics, and photonics.

[0024] The term "BP" used in this article refers to black phosphorus.

[0025] The term "MZ" used in this article refers to Mach-Zehnder.

[0026] The term "MZM" used in this article refers to Mach-Zehnder Electro-Optic Modulator.

[0027] To solve the above-mentioned technical problems, the present invention provides the following specific technical solutions: In a first aspect, the present invention provides a broadband mid-infrared MZ electro-optic modulator based on black phosphorus, comprising: a substrate layer, a nin heterojunction structure, a waveguide structure, and electrodes; The substrate layer uses a SiO2 / Si substrate; A nin heterojunction is set above the substrate layer, which consists of two n-type semiconductor layers on the top and bottom, and a quantum well composite layer sandwiched between the two n-type semiconductor layers; All n-type semiconductor layers use n-type Si layers; The i-layer consists of two intrinsic SiO2 layers and multiple BP layers located between the two intrinsic SiO2 layers; the multiple BP layers serve as quantum wells, the upper and lower intrinsic SiO2 layers serve as insulating layers, and the intrinsic SiO2 layers are respectively connected to the n-type semiconductor layers. Waveguide structures are built based on Nin heterostructures; The electrodes include a bias electrode and a capacitive load traveling wave electrode disposed on the top of the n-type heterojunction structure; and a bias electrode disposed on the bottom n-type semiconductor layer.

[0028] The first preferred option: use a ridge waveguide structure.

[0029] The second preferred option is to use a Ti / Pt / Au multilayer structure for the electrodes.

[0030] Secondly, the present invention provides a method for fabricating a broadband mid-infrared MZ electro-optic modulator based on black phosphorus, for fabricating the aforementioned broadband mid-infrared MZ electro-optic modulator, comprising: S1. On a SiO2 / Si substrate, a bottom n-type Si layer is grown by low-pressure chemical vapor deposition, and then a bottom insulating SiO2 layer is grown on the n-type Si layer by atomic layer deposition. S2. Under nitrogen protection, the prepared multilayer BP layer is transferred onto the bottom SiO2 layer using a dry transfer method. S3. A top insulating SiO2 layer is derived on a multilayer BP layer using inductively coupled plasma chemical vapor deposition, and then a top n-type Si layer is grown on the top SiO2 layer using low-pressure chemical vapor deposition. S4. First, use ALD to epitaxially grow a SiO2 hard mask layer, then spin-coat photoresist for patterning, and after photolithography, use dry etching to create a ridge waveguide structure. S5. First, Ti / Pt / Au is deposited on the underlying n-type Si layer using magnetron sputtering as the bias electrode of the modulator. Then, polyimide resin is embedded in the ridge waveguide structure for planarization. After planarization, the bias electrode is etched using photolithography and dry etching processes. Finally, capacitively loaded traveling wave electrodes are prepared using magnetron sputtering and electrochemical deposition.

[0031] First preferred option: In step S1, the growth conditions for the bottom n-type Si layer are as follows: the silicon source gas is SiH4 with a flow rate of 100 sccm; the doping gas is PH3 with a flow rate of 1 sccm; the carrier gas is N2 with a flow rate of 300 sccm; the pressure environment is 50 Pa; the cavity temperature during deposition is 630 ℃; the deposition time is 1 hour; and the target thickness is 1350 nm. Then, the layer is annealed in an N2 atmosphere for 30 mins at a temperature of 800 ℃.

[0032] Second preferred option: The growth conditions for the bottom insulating SiO2 layer are as follows: the precursor is tetraethoxysilane and O3, the cavity temperature during deposition is 300℃, the number of cycles is 500, the single cycle time is 6 to 8 seconds, and the target thickness is 50 nm.

[0033] Third preferred option: In step S2, a multilayer BP layer is prepared. Specifically, in a nitrogen-filled glove box, BP sheets are mechanically peeled from the bulk BP crystal onto the PDMS substrate using tape. The BP sheets are then identified and selected using an optical microscope, and the multilayer BP sheets form a multilayer BP layer.

[0034] Fourth priority option: Thickness of multi-layer BP: High-purity black phosphorus ≥99.9% is used, with 9 to 11 BP layers, and the thickness of the multi-layer BP is approximately 5nm.

[0035] Fifth priority option: Growth conditions for the insulating SiO2 layer on the BP layer: deposition temperature 75 ℃, power 200 W; silicon source gas is SiH4, flow rate 25 sccm; oxidation gas is O2, flow rate 55 sccm; inert protective gas is Ar, flow rate 30 sccm. The pressure environment was 5–20 mTorr; the deposition rate was 10 nm / min, and the deposition time was 5 minutes.

[0036] Sixth priority option: The growth conditions for the top n-type Si layer are as follows: the silicon source gas is SiH4 with a flow rate of 100 sccm; the doping gas is PH3 with a flow rate of 1 sccm; and the carrier gas is N2 with a flow rate of 300 sccm. The pressure environment was 30 P; the chamber temperature during deposition was 630 °C, the time was 1.37 hours, and the target thickness was 1850 nm; then plasma-assisted annealing was performed below 400 °C.

[0037] Compared with the prior art, the present invention has at least the following beneficial effects: The Nin heterojunction structure based on multilayer BP layers is applied in electro-optic modulators. By utilizing the high carrier mobility and strong quantum confinement Stark effect of multilayer BP layers, efficient modulation under low driving voltage can be achieved.

[0038] Using insulating SiO2 / BP / SiO2 as the i-layer in the nin heterojunction structure, the SiO2 layer not only acts as an insulating spacer but also encapsulates and protects BP, thereby improving the stability of the device.

[0039] The use of CL-TWE avoids the cumulative effect of electrode capacitance, reduces microwave loss, improves signal transmission efficiency, and achieves synchronous and efficient modulation of microwave signals (RF signals) and optical signals.

[0040] The electro-optic modulator device of the present invention has a very low half-wave voltage (V). π It can be reduced to below 2 V, compared to traditional InP-based modulators (V). π The voltage is reduced by more than 60% (≈ 5 V). This is because multilayer BP quantum wells have a strong quantum-confined Stark effect, which can significantly reduce the half-wave voltage.

[0041] The electro-optic modulator device of the present invention has a high modulation bandwidth (50 GHz). This is because the quantum confinement effect of the BP increases the differential gain, and because of the high carrier mobility of the BP itself (greater than 1000 cm² / V·s).

[0042] The electro-optic modulator device of this invention exhibits very low photoelectric loss. Compared to traditional pin waveguide structures, the n-type bottom layer has lower absorption of free carriers than the p-type bottom layer; therefore, the n-type epitaxial structure can effectively reduce the optical and electrical losses of the modulator.

[0043] The device exhibits high stability. Because the SiO2 encapsulation layer effectively isolates the BP from the external environment, preventing water and oxygen from damaging the BP layer, the device's performance degradation is less than 5% after 1000 hours of operation at 85°C and 85% humidity. The device has excellent CMOS compatibility. It is compatible with existing CMOS processes, reducing the cost of large-scale fabrication. Attached Figure Description

[0044] Figure 1 This is a flowchart illustrating the manufacturing process of the MZ electro-optic modulator of the present invention. (a) Material epitaxy; (b) Fabrication of ridge waveguide structure and bias electrode; (c) Planarization and etching of bias electrode; (d) Fabrication of capacitively loaded traveling wave electrode.

[0045] Figure 2 This is a schematic diagram of the three-dimensional structure of the MZ electro-optic modulator of the present invention.

[0046] Figure label: 1. SiO2 / Si substrate; 2. n-type Si layer; 3. SiO2 layer; 4. Multilayer BP layer; 5. Bias electrode; 6. Polyimide adhesive; 7. Capacitively loaded traveling wave electrode; 8. U-shaped electrode; 9. I-shaped electrode; 10. DC bias electrode; 11. Phase electrode. Detailed Implementation

[0047] The following non-limiting embodiments are intended to enable those skilled in the art to gain a more comprehensive understanding of the present invention, but do not limit the invention in any way. The following content is merely an exemplary description of the scope of protection claimed by the present invention, and those skilled in the art can make various changes and modifications to the present invention based on the disclosed content, and such changes should also fall within the scope of protection claimed by the present invention.

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0049] In the description of this invention, it should be noted that the terms "upper", "middle", "lower", "inner", "outer", "both sides", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this invention and do not indicate or imply that the structure or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0050] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0051] See Figure 1 and Figure 2As shown, the present invention provides a broadband mid-infrared MZ electro-optic modulator (abbreviated MZM) based on black phosphorus, comprising: a substrate layer, a nin heterojunction structure, a waveguide structure, and electrodes; The substrate layer uses SiO2 / Si substrate 1, where the Si layer serves as the supporting substrate and the SiO2 layer serves as the insulating transition layer.

[0052] A nin heterojunction is set above the substrate layer, which consists of two n-type semiconductor layers on the top and bottom, and a quantum well composite layer sandwiched between the two n-type semiconductor layers; All n-type semiconductor layers use n-type Si layers 2; The i-layer (or quantum well composite layer) is composed of "intrinsic SiO2 / multilayer BP / intrinsic SiO2", specifically: it consists of two intrinsic SiO2 layers 3 and a multilayer BP layer 4 located between the two intrinsic SiO2 layers 3; wherein the multilayer BP layer 4 serves as a quantum well, and the upper and lower intrinsic SiO2 layers serve as insulating isolation layers, and the intrinsic SiO2 layers are respectively connected to the n-type semiconductor layer. like Figure 2 As shown, a waveguide structure is constructed based on the nin heterostructure to form a nin structure waveguide; The electrodes include two capacitively loaded traveling wave electrodes 7 disposed on the top of the n-type heterojunction structure; and a bias electrode 5 disposed on the bottom n-type semiconductor layer.

[0053] The waveguide structure adopts a ridge waveguide, and the interior is filled with polyimide glue 6 for planarization.

[0054] The electrode adopts a Ti / Pt / Au multilayer structure.

[0055] participate Figure 1 , Figure 2 As shown, this invention provides a method for fabricating a broadband mid-infrared MZ electro-optic modulator based on black phosphorus, comprising the following steps: S1. Underlying structure growth: On a SiO2 / Si substrate, an n-type Si layer 2 is grown by low-pressure chemical vapor deposition (LPCVD), and then an insulating SiO2 layer 3 is grown on the n-type Si layer 2 by atomic layer deposition (ALD).

[0056] S2. Preparation and Transfer of Multilayer BP Layers: In a nitrogen-filled glove box, BP flakes were mechanically peeled from bulk BP crystals onto a PDMS (polydimethylsiloxane) substrate using adhesive tape. The BP flakes were identified and selected using an optical microscope. Under nitrogen protection, multilayer BP layers were then dry-transferred onto a SiO2 insulating layer.

[0057] S3, Top layer structure growth (BP packaging): An insulating SiO2 layer 3 is derived on the multilayer BP layer using inductively coupled plasma chemical vapor deposition (ICP-CVD), and then an n-type Si layer 2 is grown on the insulating SiO2 layer 3 using low-pressure chemical vapor deposition (LPCVD).

[0058] Steps S1-S3 are implemented Figure 1 The material extension of part (a) in the text; S4. Ridge waveguide fabrication: First, an epitaxial SiO2 hard mask layer is used with ALD, then photoresist is spin-coated, and patterning is performed using a stepper lithography machine. After photolithography, the ridge waveguide structure is etched out using dry etching.

[0059] S5. Planarization and Electrode Fabrication: First, Ti / Pt / Au is deposited on the underlying n-type Si layer 2 using magnetron sputtering as the bias electrode 5 of the modulator. Then, polyimide (PI) resin is embedded in the ridge waveguide structure for planarization. After planarization, the bias electrode 5 is etched using photolithography and dry etching processes. Finally, the capacitive-loaded traveling wave electrode 7 (CL-TWE) is fabricated using magnetron sputtering and electrochemical deposition.

[0060] The bias implementation of magnetron sputtering deposition in steps S4 and S5 Figure 1 The fabrication of the ridge waveguide structure and bias electrode 5 in part (b); In step S5, the embedded polyimide (PI) adhesive is planarized, and the bias electrode 5 is etched to achieve... Figure 1 Planarization and etching of the bias electrode 5 in part (c); Step S5 involves fabricating a capacitively loaded traveling wave electrode 7 using magnetron sputtering and electrochemical deposition. Figure 1 The preparation of the capacitively loaded traveling wave electrode 7 in part (d) of the diagram.

[0061] In step S1, the growth conditions for the bottom n-type Si layer 2 are as follows: the silicon source gas is silane (SiH4) at a flow rate of 100 sccm; the doping gas is phosphine (PH3) at a flow rate of 1 sccm; the carrier gas is high-purity nitrogen (N2) at a flow rate of 300 sccm; the pressure environment is 50 Pa; the chamber temperature during deposition is 630 ℃ for 1 hour, and the target thickness is 1350 nm. Then, annealing is performed for 30 mins in an N2 atmosphere at a temperature of 800 ℃.

[0062] In step S1, the growth conditions for the bottom insulating SiO2 layer 3 are as follows: the precursor is tetraethoxysilane (TEOS, Si(OC2H5)4) and ozone (O3), the cavity temperature during deposition is 300 ℃, the number of cycles is 500, the single cycle time is 6 to 8 seconds (including purging), and the target thickness is 50 nm.

[0063] In step S2, the thickness of the multilayer BP layer is as follows: high-purity black phosphorus ≥99.9% is used, the ideal number of BP layers is 9 to 11, and the BP thickness is about 5 nm.

[0064] The number of BP layers can be adjusted: the thickness of the BP layer can be further optimized, and the modulation efficiency and bandwidth can be improved by adjusting the number of layers.

[0065] Growth of the top insulating SiO2 layer 3 on the BP layer: Deposition temperature 75 ℃, power 200 W (power not exceeding 300 W to avoid damaging the BP). Silicon source gas: SiH4, flow rate 25 sccm. Oxidizing gas: O2, flow rate 55 sccm. Inert protective gas: Ar, flow rate 30 sccm. Pressure environment: 5–20 mTorr. Deposition rate: 10 nm / min, deposition time 5 minutes.

[0066] The growth conditions for the top n-type Si layer 2 in step S3 are as follows: the silicon source gas is SiH4, with a flow rate of 100 sccm. The doping gas is PH3, with a flow rate of 1 sccm. The carrier gas is high-purity N2, with a flow rate of 300 sccm. The pressure environment is 30 Pa. The chamber temperature during deposition is 630℃, the deposition time is 1.37 hours, and the target thickness is 1850 nm. Then, plasma-assisted annealing is performed below 400℃ to avoid damage from black phosphorus.

[0067] Example 1: Mach-Zehnder electro-optic modulator with 9-layer BP quantum well 1. Substrate preparation: A 4-inch SiO2 / Si substrate (SiO2 thickness 300 nm, Si thickness 500 μm) was selected and surface impurities were removed by RCA cleaning; 2. Growth of cladding under n-type Si layer: LPCVD growth of 1350 nm thick n-type Si (doping concentration 1×10¹) 8 cm - ³), and then annealed in an N2 atmosphere; 3. Growth of the underlying intrinsic SiO2 layer: A 50 nm intrinsic SiO2 layer was grown by ALD; 4. BP transfer: The bulk BP crystal is mechanically peeled off into a thin layer using adhesive tape. Under an optical microscope, a 9-layer thick BP sheet (10 μm × 5 μm) is selected and bonded to the underlying SiO2 layer using a dry transfer technique. 5. SiO2 encapsulation: 50 nm intrinsic SiO2 was deposited at 75 °C using ICP-CVD to cover the BP surface; 6. Cladding growth on n-type Si layer: LPCVD growth of an 1850 nm thick n-type Si layer with a cladding layer (doping concentration 5 × 10¹).7 cm - ³); 7. Ridge waveguide fabrication: A SiO2 hard mask layer is grown by ALD, photoresist (AZ 5214) is spin-coated, the pattern is defined by photolithography, the ridge waveguide is etched by dry etching, and then the photoresist is removed. 8. Electrode fabrication: Ti / Pt / Au (60 / 150 / 300 nm) was magnetron sputtered to form bias electrode 5, followed by PI photoresist deposition and curing (250 °C, 1 hour). After planarization, the electrode pattern was defined by photolithography, and bias electrode 5 was etched using dry etching. Finally, CL-TWE was fabricated using magnetron sputtering and electrochemical deposition. 9. Thinning and Testing: The substrate is thinned to 180 μm by grinding, and finally the chip is cleaved into strips for testing.

[0068] Example 2: Mach-Zehnder electro-optic modulator with 11-layer BP quantum well 1. Substrate preparation: A 4-inch SiO2 / Si substrate (SiO2 thickness 300 nm, Si thickness 500 μm) was selected and surface impurities were removed by RCA cleaning; 2. Growth of cladding under n-type Si layer: LPCVD growth of 1350 nm thick n-type Si (doping concentration 1×10¹) 8 cm - ³), and then annealed in an N2 atmosphere; 3. Growth of the underlying intrinsic SiO2 layer: A 50 nm intrinsic SiO2 layer was grown by ALD; 4. BP transfer: The bulk BP crystal is mechanically peeled off into a thin layer using adhesive tape. Under an optical microscope, 11-layer thick BP sheets (10 μm × 5 μm in size) are selected and bonded to the underlying SiO2 layer using a dry transfer technique. 5. SiO2 encapsulation: 50 nm intrinsic SiO2 was deposited at 75 °C using ICP-CVD to cover the BP surface; 6. Cladding growth on n-type Si layer: LPCVD growth of an 1850 nm thick n-type Si layer with a cladding layer (doping concentration 5 × 10¹). 7 cm - ³); 7. Ridge waveguide fabrication: A SiO2 hard mask layer is grown by ALD, photoresist (AZ 5214) is spin-coated, the pattern is defined by photolithography, the ridge waveguide is etched by dry etching, and then the photoresist is removed. 8. Electrode fabrication: Ti / Pt / Au (60 / 150 / 300 nm) was magnetron sputtered to form bias electrode 5, followed by PI photoresist deposition and curing (250 °C, 1 hour). After planarization, the electrode pattern was defined by photolithography, and bias electrode 5 was etched using dry etching. Finally, CL-TWE was fabricated using magnetron sputtering and electrochemical deposition. 9. Thinning and Testing: The substrate is thinned to 180 μm by grinding, and finally the chip is cleaved into strips for testing.

[0069] Example 3: Mach-Zehnder electro-optic modulator with 15-layer BP quantum well 1. Substrate preparation: A 4-inch SiO2 / Si substrate (SiO2 thickness 300 nm, Si thickness 500 μm) was selected and surface impurities were removed by RCA cleaning; 2. Growth of cladding under n-type Si layer: LPCVD growth of 1350 nm thick n-type Si (doping concentration 1×10¹) 8 cm - ³), and then annealed in an N2 atmosphere; 3. Growth of the underlying intrinsic SiO2 layer: 50 nm intrinsic SiO2 was grown by ALD; 4. BP transfer: The bulk BP crystal is mechanically peeled off into a thin layer using adhesive tape. Under an optical microscope, a 15-layer thick BP sheet (10 μm × 5 μm in size) is selected and bonded to the underlying SiO2 layer using a dry transfer technique. 5. SiO2 encapsulation: 50 nm intrinsic SiO2 was deposited at 75 °C using ICP-CVD to cover the BP surface; 6. Cladding growth on n-type Si layer: LPCVD growth of an 1850 nm thick n-type Si layer with a cladding layer (doping concentration 5 × 10¹). 7 cm - ³); 7. Ridge waveguide fabrication: A SiO2 hard mask layer is grown by ALD, photoresist (AZ 5214) is spin-coated, the pattern is defined by photolithography, the ridge waveguide is etched by dry etching, and then the photoresist is removed. 8. Electrode fabrication: Ti / Pt / Au (60 / 150 / 300 nm) was magnetron sputtered to form bias electrode 5, followed by PI photoresist deposition and curing (250 °C, 1 hour). After planarization, the electrode pattern was defined by photolithography, and bias electrode 5 was etched using dry etching. Finally, CL-TWE was fabricated using magnetron sputtering and electrochemical deposition. 9. Thinning and Testing: The substrate is thinned to 180 μm by grinding, and finally the chip is cleaved into strips for testing.

[0070] Test results:

[0071] Example 4 Unlike Examples 1-3, the insulating layer material is replaced: intrinsic SiO2 can be replaced with Al2O3 or HfO2 to achieve a higher dielectric constant and improve the electric field confinement effect.

[0072] Example 5 Unlike Examples 1-3, the electrode material was optimized: Cr / Au or Ni / Au was used instead of Ti / Pt / Au to reduce contact resistance and further reduce driving voltage.

[0073] Example 6 Unlike Examples 1-3, the waveguide structure is changed: it can be designed as a buried waveguide, which reduces optical leakage loss by completely wrapping the waveguide core layer.

[0074] Finally, it should be noted that the above content is only used to illustrate the technical solution of the present invention, and is not intended to limit the scope of protection of the present invention. Simple modifications or equivalent substitutions made by those skilled in the art to the technical solution of the present invention do not depart from the essence and scope of the technical solution of the present invention.

Claims

1. A wide-spectrum mid-infrared M-Z electro-optic modulator based on black phosphorus, characterized in that, include: Substrate, N1 heterojunction structure, waveguide structure, electrodes; The substrate layer uses a SiO2 / Si substrate; A nin heterojunction is set above the substrate layer, which consists of two n-type semiconductor layers on the top and bottom, and a quantum well composite layer sandwiched between the two n-type semiconductor layers; All n-type semiconductor layers use n-type Si layers; The i-layer consists of two intrinsic SiO2 layers and multiple BP layers located between the two intrinsic SiO2 layers; the multiple BP layers serve as quantum wells, the upper and lower intrinsic SiO2 layers serve as insulating layers, and the intrinsic SiO2 layers are respectively connected to the n-type semiconductor layers. Waveguide structures are built based on Nin heterostructures; The electrodes include a capacitive load traveling wave electrode disposed on the top of the n-type heterojunction structure and a bias electrode disposed on the bottom n-type semiconductor layer.

2. The black phosphorus-based wide-spectrum mid-infrared M-Z electro-optic modulator of claim 1, wherein, The waveguide structure adopts a ridge waveguide.

3. The broadband mid-infrared MZ electro-optic modulator based on black phosphorus according to claim 1, characterized in that, The electrode adopts a Ti / Pt / Au multilayer structure.

4. A method for fabricating a broadband mid-infrared MZ electro-optic modulator based on black phosphorus, characterized in that, For preparing the broadband mid-infrared MZ electro-optic modulator according to any one of claims 1-3, comprising: S1. On a SiO2 / Si substrate, a bottom n-type Si layer is grown by low-pressure chemical vapor deposition, and then a bottom insulating SiO2 layer is grown on the n-type Si layer by atomic layer deposition. S2. Under nitrogen protection, the prepared multilayer BP layer is transferred onto the bottom SiO2 layer using a dry transfer method. S3. A top insulating SiO2 layer is derived on a multilayer BP layer using inductively coupled plasma chemical vapor deposition, and then a top n-type Si layer is grown on the top SiO2 layer using low-pressure chemical vapor deposition. S4. First, use ALD to epitaxially grow a SiO2 hard mask layer, then spin-coat photoresist for patterning, and after photolithography, use dry etching to create a ridge waveguide structure. S5. First, Ti / Pt / Au is deposited on the underlying n-type Si layer using magnetron sputtering as the bias electrode of the modulator. Then, polyimide resin is embedded in the ridge waveguide structure for planarization. After planarization, the bias electrode is etched using photolithography and dry etching processes. Finally, capacitively loaded traveling wave electrodes are prepared using magnetron sputtering and electrochemical deposition.

5. The method for fabricating a broadband mid-infrared MZ electro-optic modulator based on black phosphorus according to claim 4, characterized in that, In step S1, the growth conditions for the bottom n-type Si layer are as follows: the silicon source gas is SiH4 with a flow rate of 100 sccm; the doping gas is PH3 with a flow rate of 1 sccm; the carrier gas is N2 with a flow rate of 300 sccm; the pressure environment is 50 Pa; the cavity temperature during deposition is 630 ℃; the deposition time is 1 hour; and the target thickness is 1350 nm. Then, the layer is annealed in an N2 atmosphere for 30 mins at a temperature of 800 ℃.

6. The method for fabricating a broadband mid-infrared MZ electro-optic modulator based on black phosphorus according to claim 4, characterized in that, In step S1, the growth conditions for the bottom insulating SiO2 layer are as follows: the precursor is tetraethoxysilane and O3, the cavity temperature during deposition is 300 ℃, the number of cycles is 500, the single cycle time is 6 to 8 seconds, and the target thickness is 50 nm.

7. The method for fabricating a broadband mid-infrared MZ electro-optic modulator based on black phosphorus according to claim 4, characterized in that, In step S2, a multilayer BP layer is prepared. Specifically, in a nitrogen-filled glove box, BP sheets are mechanically peeled from the bulk BP crystal onto the PDMS substrate using tape. The BP sheets are then identified and selected using an optical microscope, and the multilayer BP sheets form a multilayer BP layer.

8. The method for fabricating a broadband mid-infrared MZ electro-optic modulator based on black phosphorus according to claim 7, characterized in that, Thickness of multi-layer BP: High-purity black phosphorus ≥99.9% is used, with 9 to 11 BP layers, and the thickness of the multi-layer BP is 4.8 nm to 5.9 nm.

9. The method for fabricating a broadband mid-infrared MZ electro-optic modulator based on black phosphorus according to claim 4, characterized in that, In step S3, the growth conditions of the insulating SiO2 layer on the multilayer BP layer are as follows: deposition temperature 75 ℃, power 200 W; silicon source gas is SiH4, flow rate 25 sccm; oxidation gas is O2, flow rate 55 sccm; inert protective gas is Ar, flow rate 30 sccm. The pressure environment was 5–20 mTorr; the deposition rate was 10 nm / min, and the deposition time was 5 minutes.

10. The method for fabricating a broadband mid-infrared MZ electro-optic modulator based on black phosphorus according to claim 9, characterized in that, In step S3, the growth conditions for the top n-type Si layer are as follows: the silicon source gas is SiH4 with a flow rate of 100 sccm; the doping gas is PH3 with a flow rate of 1 sccm; and the carrier gas is N2 with a flow rate of 300 sccm. The pressure environment was 30 P; the cavity temperature during deposition was 630 °C, the time was 1.37 hours, and the target thickness was 1850 nm; then plasma-assisted annealing was performed below 400 °C.