A method for determining a process window of a metal interconnection line geometry parameter across a lithography field

CN122546576APending Publication Date: 2026-08-1158TH RES INST OF CETC
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Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-06-25
Publication Date
2026-08-11

AI Technical Summary

Technical Problem

[0008]二是光刻胶“二次曝光”效应影响套刻尺寸(overlap)工艺窗口

Benefits of technology

[0016]本发明提供的一种跨光刻场金属互连线几何参数工艺窗口的确定方法,可以将三个相互影响的几何参数纳入统一框架进行协同优化,直接指导跨光刻场金属互连线掩模版图形的优化设计,避免盲目试错,具有重要意义。

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Abstract

This invention discloses a method for determining the process window of geometric parameters for cross-lithography field metal interconnects, belonging to the field of semiconductor manufacturing. The minimum specification value of the minimum feature size minADI line CD of the unexposed region after development and the minimum specification value of the minimum feature size minADI space CD of the exposed region after development are both set to the same value, S-ADI; similarly, the minimum specification value of the minimum feature size minAEI line CD of the unetched region after etching and the minimum specification value of the minimum feature size minAEI space CD of the etched region after etching are both set to the same value, S-AEI. This invention proposes a method for synergistically optimizing three coupled geometric parameters—linewidth, line spacing, and overlay size—of cross-lithography field metal interconnects and systematically determining their process window. It transforms the abstract process window into a definite numerical range, providing a quantitative basis for mask design and process condition formulation for cross-lithography field metal interconnects, which is of great significance.
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Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for determining the process window of geometric parameters across photolithographic field metal interconnects. Background Technology

[0002] With the continuous development of semiconductor technology, the demand for large-size chips is also increasing. However, due to the limitations of the mask size in step-up lithography processes, the size of a single chip is limited to 26mm × 33mm. This forces the semiconductor industry to adopt cross-lithography field metal interconnect technology to achieve electrical connections between adjacent chips in order to manufacture larger chips.

[0003] To ensure the quality of signal interconnects across lithographic fields, the geometry and parameters of the metal interconnects at the interconnect splicing locations are typically specially designed. However, determining the process window for the geometric parameters of the metal interconnects across lithographic fields presents multiple challenges.

[0004] First, the "secondary exposure" effect of photoresist affects the line width / space process window.

[0005] When using positive photoresist, the aluminum interconnect process employs a subtractive method: first depositing aluminum across the entire surface, then etching the intervening regions. The opaque areas of the photomask represent the shape of the target aluminum interconnect. In the area where photoresist is spliced ​​across photolithography fields, the photoresist from adjacent exposures receives a double dose, leading to excessive chemical reaction and narrowing of the photoresist after development. This effect causes the aluminum interconnect to narrow, increasing its resistance, and in severe cases, even causing the photoresist to break, resulting in an open circuit in the aluminum interconnect.

[0006] When using positive photoresist, the copper interconnect process employs an additive process of "etching trenches first, then electroplating copper," with the transparent area of ​​the photomask representing the shape of the target copper interconnect. In the area spanning the photolithography field, secondary exposure causes the photoresist in the trench region to overreact and widen, corresponding to a wider copper interconnect. This reduces the resistance of the copper interconnect, and in severe cases, photoresist breakage can lead to short circuits between adjacent copper interconnects.

[0007] Therefore, the linewidth / space of the cross-lithography field metal interconnect has a direct impact on the exposure and interconnect quality of the cross-lithography field metal interconnect.

[0008] Second, the "secondary exposure" effect of photoresist affects the overlap process window.

[0009] When using positive photoresist, if the overlay dimension along the cross-photolithography field metal interconnect splicing direction is too small, the photoresist in the splicing area may widen due to insufficient exposure dose. For aluminum interconnect processes, this corresponds to wider aluminum interconnect lines, reduced aluminum metal interconnect resistance, and an increased risk of adjacent photoresist adhesion, potentially leading to short circuits between adjacent aluminum interconnect lines. For copper interconnect processes, this corresponds to narrower copper interconnect lines, increased copper metal interconnect resistance, and even an increased risk of adjacent photoresist adhesion, potentially leading to open circuits in the copper interconnect lines.

[0010] When using positive photoresist, if the overlay size along the cross-photolithography field metal interconnect splicing direction is too large, the photoresist in the splicing area will narrow due to the cumulative dose from the secondary exposure. For aluminum interconnect processes, this corresponds to narrowing of the aluminum interconnect lines, increased resistance of the aluminum metal interconnect, and even adhesion of adjacent gaps due to insufficient photoresist, leading to open circuits in the aluminum interconnect lines. For copper interconnect processes, this corresponds to widening of the copper interconnect lines, decreased resistance of the copper metal interconnect, and even adhesion of adjacent gaps due to insufficient photoresist, leading to short circuits between adjacent copper interconnect lines.

[0011] Therefore, the geometric parameter of the overlap dimension of the cross-lithography field metal interconnect has a direct impact on the exposure and interconnect quality of the cross-lithography field metal interconnect.

[0012] In summary, the three geometric parameters of cross-lithography field metal interconnects—linewidth, line spacing, and overlay size—all have distinct process windows. Furthermore, these three parameters are not independent variables but are coupled with each other, necessitating a method for determining the process window that can collaboratively optimize these three geometric parameters. Summary of the Invention

[0013] The purpose of this invention is to provide a method for determining the process window of geometric parameters of metal interconnects across photolithography fields, so as to solve the problems in the background art.

[0014] To address the aforementioned technical problems, this invention provides a method for determining the process window of geometric parameters for cross-lithography field metal interconnects, comprising: The minimum specification value of the minimum feature size min ADI line CD of the unexposed area after development and the minimum specification value of the minimum feature size min ADI space CD of the exposed area after development are both set to the same value, S-ADI. The minimum specification value of the minimum feature size min AEI line CD of the unetched area after etching and the minimum specification value of the minimum feature size min AEI space CD of the etched area after etching are both set to the same value, S-AEI. Simulation or fabrication tests were conducted on different combinations of stretching values ​​(line width, space, overlap). Measure the minimum feature size min ADI line CD and the minimum feature size min ADI space CD of the unexposed area after development and the exposed area after development in simulation or fabrication, or the minimum feature size min AEI line CD of the unetched area after etching and the minimum feature size min AEI space CD of the etched area after etching, using different combinations of pull values ​​(line width, space, overlap). Taking a combination of (line width, space) as the research object, with the overlap size as the abscissa and the minimum feature size min ADI line CD and min ADI space CD of the unexposed area after development and the minimum feature size min AEI line CD of the exposed area after development and the minimum feature size min AEI space CD of the unetched area after etching and the minimum feature size min AEI space CD of the etched area after etching as the ordinate, a curve is plotted. Draw the S-ADI or S-AEI horizontal line on the graph; the S-ADI line intersects the min ADI line CD and the min ADI space CD at two points X1-ADI and X2-ADI, with the x-coordinates of these two points being O1-ADI and O2-ADI, respectively. The process window is O1-ADI to O2-ADI. The S-AEI line intersects the min AEI line CD and the min AEI space CD at two points X1-AEI and X2-AEI, with the x-coordinates of these two points being O1-AEI and O2-AEI, respectively. The process window is O1-AEI to O2-AEI.

[0015] In one implementation, the process window is determined based on the simulated min ADI line CD, min ADI space CD, and S-ADI, or based on the simulated min AEI line CD, min AEI space CD, and S-AEI, or based on the min ADI line CD, min ADI space CD, and S-ADI from a tape-out experiment, or based on the min AEI line CD, min AEI space CD, and S-AEI from a tape-out experiment.

[0016] The present invention provides a method for determining the process window of geometric parameters for cross-lithography field metal interconnects. This method can incorporate three mutually influential geometric parameters into a unified framework for collaborative optimization, directly guiding the optimized design of cross-lithography field metal interconnect mask patterns and avoiding blind trial and error, which is of great significance. Attached Figure Description

[0017] Figure 1 It is a schematic diagram of two photomasks interconnected through a secondary exposure area.

[0018] Figure 2 It is a schematic diagram of two photomasks interconnected by a small secondary exposure area.

[0019] Figure 3 It is a schematic diagram of two photomasks interconnected by a large secondary exposure area.

[0020] Figure 4 This invention proposes a method for determining the process window of geometric parameters for cross-lithography field metal interconnects.

[0021] Figure 5 This is a schematic diagram of determining the process window using min ADI line CD, min ADI space CD, and S-ADI.

[0022] Figure 6 This is a schematic diagram of determining the process window using min AEI line CD, min AEI space CD, and S-AEI.

[0023] Label Explanation: mask1: Upper mask; mask2: Lower side mask; A1: Single exposure area of ​​the upper mask; A2: Single exposure area of ​​the lower mask; B: Second exposure area; 01: The location of the remaining photoresist after the second exposure; 02: The location without photoresist after the second exposure; line: Width of the opaque area of ​​the mask; space: Width of the light-transmitting area of ​​the photomask; min space: The actual minimum width of the photoresist-free position after the second exposure; min line: The actual minimum width of the photoresist after the second exposure. Detailed Implementation

[0024] The method for determining the process window of geometric parameters for cross-lithographic field metal interconnects proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0025] The present invention provides a method for determining the process window of geometric parameters for cross-photolithography field metal interconnects, applicable to positive photoresist lithography. Positive photoresist refers to photoresist areas not covered by the mask (exposed areas) that undergo a chemical reaction, with the exposed portion dissolving in the developer; while the photoresist areas covered by the mask do not dissolve in the developer.

[0026] This invention applies to both copper interconnect and aluminum interconnect processes. Copper interconnects employ a damascus etching followed by electroplating for filling, while aluminum interconnects employ a process of first depositing a metal layer and then etching the pattern. The mask structure will be described below using copper interconnects as an example. For aluminum interconnects, the mask pattern needs to be adjusted accordingly to match the etching process.

[0027] Figure 1 This is a schematic diagram showing two photomasks interconnected through a secondary exposure area. (See diagram below.) Figure 1 As shown, the upper mask 1 includes a single exposure area A1 and a double exposure area B, and the lower mask 2 includes a single exposure area A2 and a double exposure area B. The double exposure areas B of the upper mask 1 and the lower mask 2 completely overlap, and the size of the double exposure area B is the overlap dimension. Here, 01 represents the remaining photoresist position after the double exposure, and its width is the line width; 02 represents the position where the photoresist is removed after the double exposure, and its width is the space. Other graphics within areas A1 and A2 are represented by ellipses and are not specifically drawn in this embodiment.

[0028] A schematic diagram showing the interconnection of the left and right photomasks through a secondary exposure area. Figure 1 Similarly, simply arrange the two masks horizontally, ensuring their secondary exposure areas overlap; this will not be explained further here. The following examples will use two masks, one above the other.

[0029] In the cross-lithography field splicing region B, the two adjacent exposures cause the photoresist position 01 to receive a double dose, resulting in excessive chemical reaction of the photoresist. After development, the photoresist becomes narrower, that is, the line width becomes narrower, and consequently the space becomes wider. This is the principle behind the "double exposure" effect of photoresist affecting the line width / space ratio.

[0030] Figure 2 This is a schematic diagram showing two photomasks interconnected by a small secondary exposure area. (See diagram below.) Figure 2 As shown, the overlap size (size of the secondary exposure area B) is relatively... Figure 1 Reducing the exposure dose may cause the photoresist in the splicing area to widen due to insufficient exposure, increasing the risk of adjacent photoresist sticking together. In this case, it is necessary to closely monitor the minimum line spacing (min space) between photoresists to avoid photoresist sticking.

[0031] Figure 3 This is a schematic diagram showing two photomasks interconnected by a large secondary exposure area. (See diagram below.) Figure 3 As shown, the overlap size (size of the secondary exposure area B) is relatively... Figure 1 As the exposure dose increases, the photoresist in the splicing area may become narrower due to excessive exposure, and the risk of adhesion between adjacent gaps increases due to insufficient photoresist. In this case, it is necessary to closely monitor the minimum linewidth of the photoresist to avoid photoresist breakage.

[0032] Figure 4 This invention presents a method for determining the process window of geometric parameters for cross-lithographic field metal interconnects. For example... Figure 4 As shown, the method includes the following steps: (1) Set the minimum specification value of "min ADI line CD of the unexposed area after development and min ADI space CD of the exposed area after development", usually set to the same value S-ADI; set the minimum specification value of "min AEIline CD of the unetched area after etching and min AEIspace CD of the etched area after etching", usually set to the same value S-AEI; (2) Simulation or fabrication tests were conducted on different combinations of (line, space, overlap) bias values; (3) Measure different (line, space, overlap) pull values ​​in the simulation or fabrication of "min ADI line CD of the unexposed area after development and min ADI space CD of the exposed area after development" or "min AEI line CD of the unetched area after etching and min AEI space CD of the etched area after etching"; (4) Taking a certain combination of (line, space) as the research object, with overlap as the abscissa and "min ADI line CD of the unexposed area after development and min ADI space CD of the exposed area after development" or "min AEI line CD of the unetched area after etching and min AEI space CD of the etched area after etching" as the ordinate, draw a curve; (5) Draw the S-ADI or S-AEI horizontal line in the above figure. The S-ADI line intersects with "min ADI line CD and min ADI space CD" at two points X1-ADI and X2-ADI. The horizontal coordinates of these two points are O1-ADI and O2-ADI, respectively. O1-ADI~O2-ADI is the process window. The S-AEI line intersects with "min AEI line CD and min AEI space CD" at two points X1-AEI and X2-AEI. The horizontal coordinates of these two points are O1-AEI and O2-AEI, respectively. O1-AEI~O2-AEI is the process window.

[0033] Figure 5 This diagram illustrates the determination of the process window using min ADI line CD, min ADI space CD, and S-ADI. The diagram includes curves showing the variation of min ADI line CD with overlap, min ADI space CD with overlap, and the S-ADI specification curve. The S-ADI specification curve intersects the min ADI space CD curve at point X1-ADI, and the S-ADI specification curve intersects the min ADI line CD curve at point X2-ADI. The x-coordinate of point X1-ADI is O1-ADI, and the x-coordinate of point X2-ADI is O2-ADI. Therefore, O1-ADI to O2-ADI constitute the process window.

[0034] Figure 6 This diagram illustrates the determination of the process window using the min AEI line CD, min AEI space CD, and S-AEI. The diagram includes curves showing the min AEI line CD as a function of overlap, the min AEI space CD as a function of overlap, and the S-AEI specification curve. The S-AEI specification curve intersects the min AEI space CD curve at point X1-AEI, and the S-AEI specification curve intersects the min AEI line CD curve at point X2-AEI. The x-coordinate of point X1-AEI is O1-AEI, and the x-coordinate of point X2-AEI is O2-AEI. Therefore, O1-AEI to O2-AEI constitute the process window.

[0035] The method for determining the process window of geometric parameters of cross-lithography field metal interconnects proposed in this invention can quickly identify the overlap process window corresponding to different (line, space) combinations, achieve synergistic optimization of the three geometric parameters, and provide a quantitative basis for the mask design and process condition selection of cross-lithography field metal interconnects.

[0036] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for determining the process window of geometric parameters for cross-lithographic field metal interconnects, characterized in that, include: The minimum specification value of the minimum feature size min ADI line CD of the unexposed area after development and the minimum specification value of the minimum feature size min ADI space CD of the exposed area after development are both set to the same value, S-ADI. The minimum specification value of the minimum feature size min AEI line CD of the unetched area after etching and the minimum specification value of the minimum feature size min AEI space CD of the etched area after etching are both set to the same value, S-AEI. Simulation or fabrication tests were conducted on different combinations of stretching values ​​(line width, space, overlap). Measure the minimum feature size min ADI line CD and the minimum feature size min ADI space CD of the unexposed area after development and the exposed area after development, or the minimum feature size min AEI line CD and the minimum feature size min AEI space CD of the unetched area after etching and the minimum feature size min AEI space CD of the etched area after etching, for different combinations of pull values ​​(line width, space, overlap). Using any combination of (line width, space) as the research object, with the overlap size as the abscissa and the minimum feature size min ADI line CD and min ADI space CD of the unexposed area after development and the minimum feature size min AEI line CD of the exposed area after development and the minimum feature size min AEI space CD of the unetched area after etching and the minimum feature size min AEI space CD of the etched area after etching as the ordinate, a curve is plotted. Draw the S-ADI or S-AEI horizontal line on the graph; the S-ADI line intersects the min ADI line CD and the min ADI space CD at two points X1-ADI and X2-ADI, with the x-coordinates of these two points being O1-ADI and O2-ADI, respectively. The process window is O1-ADI to O2-ADI. Similarly, the S-AEI line intersects the min AEI line CD and the min AEI space CD at two points X1-AEI and X2-AEI, with the x-coordinates of these two points being O1-AEI and O2-AEI, respectively. The process window is O1-AEI to O2-AEI.

2. The method of determining process window for cross-lithographic field metal interconnect line geometry parameters of claim 1, wherein, The process window can be determined based on the simulated min ADI line CD, min ADI space CD, and S-ADI, or based on the simulated min AEI line CD, min AEI space CD, and S-AEI, or based on the simulated min ADI line CD, min ADI space CD, and S-ADI, or based on the simulated min AEI line CD, min AEI space CD, and S-AEI.