CPLD failure protection heat dissipation system redundancy control circuit and server

Abstract

This application provides a redundant control circuit and server for a heat dissipation system with CPLD failure protection, applicable to the field of heat dissipation control technology for electronic devices. The circuit filters the signal output by the CPLD to obtain a DC level reflecting its state, and uses a voltage detection circuit to compare this DC level with a reference voltage range to determine if the CPLD output is abnormal. When the CPLD is normal, it directly drives the heat dissipation system. When the CPLD malfunctions, it controls an analog switch to switch to a backup PWM generator, which continuously outputs speed control signals. Using this solution, the heat dissipation system control path can be quickly switched when the CPLD fails, avoiding heat dissipation interruption, reducing the risk of single-point failure, and improving the server's heat dissipation continuity, operational reliability, and device safety.

Description

Technical Field

[0001] This application relates to the field of heat dissipation control technology for electronic devices, and in particular to a redundant control circuit for a heat dissipation system and a server for CPLD failure protection. Background Technology

[0002] In server systems, especially high-density heterogeneous computing servers, the stability of the cooling system directly affects the operational safety and reliability of the equipment. Servers typically integrate multiple high-performance hardware computing units, which generate significant heat during sustained high-load operation. To maintain the equipment within a safe temperature range, servers usually rely on fan systems for forced cooling. Complex Programmable Logic Devices (CPLDs), as key control units on the server motherboard, are used to generate Pulse Width Modulation (PWM) signals to adjust fan speeds, achieving dynamic cooling control. Furthermore, the CPLD communicates with the Baseboard Management Controller (BMC) via the IIC interface, providing real-time information such as fan speed to the BMC, which then dynamically adjusts the PWM signal parameters based on system temperature data.

[0003] However, during long-term server operation, the CPLD may malfunction due to hardware aging, electrical overload, or program abnormalities (such as short circuits or open circuits on I / O pins), causing it to fail to output PWM signals normally. In this case, the fan may stop completely due to the loss of the PWM signal, or run at full speed due to signal abnormalities (such as a continuous high level). A fan stopping will cause the server's internal temperature to rise rapidly, potentially leading to hardware overheating and damage; a fan running at full speed will cause a surge in power consumption, cable overload, and even burnout, accompanied by noise pollution.

[0004] Therefore, how to ensure the continuous and reliable operation of the cooling fan when the CPLD fails and the PWM signal becomes abnormal has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This application provides a redundant control circuit and server for a heat dissipation system with CPLD failure protection, which can maintain the control continuity of the heat dissipation system when the CPLD fails and the PWM signal becomes abnormal, thereby improving the stable operation capability of the heat dissipation system under abnormal operating conditions.

[0006] In a first aspect, this application provides a redundant control circuit for a heat dissipation system to protect against CPLD failure, comprising: a filter unit, a voltage detection circuit, an analog switching switch, and a backup PWM generator; wherein:

[0007] The filtering unit includes an input terminal and an output terminal. The input terminal is used to connect to the PWM output terminal of the CPLD, and the output terminal is used to connect to the signal input terminal of the voltage detection circuit.

[0008] The voltage detection circuit also includes a power supply terminal and an output terminal. The power supply terminal is used to connect to the power supply, and the output terminal is used to connect to the control terminal of the analog switching switch.

[0009] The analog switching switch also includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to connect to the output terminal of the backup PWM generator, the second input terminal is used to connect to the PWM output terminal of the CPLD, and the output terminal is used to connect to the heat dissipation system.

[0010] The filtering unit is used to filter the signal output by the CPLD and output a DC level.

[0011] A voltage detection circuit is used to receive DC level and output a fault flag signal when the DC level is greater than a first reference voltage or less than a second reference voltage; and output a normal flag signal when the DC level is greater than or equal to the second reference voltage and less than or equal to the first reference voltage, wherein the first reference voltage is greater than the second reference voltage.

[0012] The analog switch is used to connect the first input and output terminals of the analog switch in response to a fault flag signal, so that the standby PWM generator drives the cooling system; in response to a normal flag signal, it connects the second input and output terminals of the analog switch, so that the CPLD drives the cooling system.

[0013] In one possible implementation, the voltage detection circuit includes: a first comparator, a second comparator, and a level combining circuit;

[0014] The non-inverting input of the first comparator and the inverting input of the second comparator are connected together. This common input serves as the signal input of the voltage detection circuit and is used to connect to the output of the filter unit. The inverting input of the first comparator is connected to the first reference voltage. The output of the first comparator is connected to the first input of the level combining circuit.

[0015] The non-inverting input of the second comparator is connected to the second reference voltage; the output of the second comparator is connected to the second input of the level combining circuit.

[0016] The power supply terminals of the first and second comparators are connected together, serving as the power supply terminal for the voltage detection circuit, and are used to connect to the power supply.

[0017] The output of the level merging circuit serves as the output of the voltage detection circuit, which is used to connect to the control terminal of the analog switching switch.

[0018] In one possible implementation, the level merging circuit includes: a first diode and a second diode;

[0019] The anode of the first diode serves as the first input terminal of the level merging circuit;

[0020] The anode of the second diode serves as the second input terminal of the level merging circuit;

[0021] The cathodes of the first diode and the second diode are connected in the same way, and the common connection terminal serves as the output terminal of the level merging circuit.

[0022] In one possible implementation, the backup PWM generator operates independently to continuously output a backup PWM signal; or...

[0023] The backup PWM generator has an enable terminal, which is connected to the output terminal of the voltage detection circuit. The backup PWM generator is configured such that when the voltage detection circuit outputs a fault flag signal, the backup PWM generator is enabled and outputs a backup PWM signal; when the voltage detection circuit outputs a normal flag signal, the backup PWM generator is disabled.

[0024] In one possible implementation, the filter unit includes: a resistor and a capacitor;

[0025] One end of the resistor serves as the input terminal of the filter unit, which is used to connect to the PWM output terminal of the CPLD; the other end of the resistor is connected together with one end of the capacitor, and the common connection terminal serves as the output terminal of the filter unit.

[0026] The other end of the capacitor is grounded.

[0027] In one possible implementation, the redundant control circuit for the heat dissipation system of CPLD failure protection further includes: a first level conversion unit;

[0028] The input terminal of the first level conversion unit is used to connect to the PWM output terminal of the CPLD, and the output terminal is connected to the input terminal of the filter unit and the second input terminal of the analog switching switch respectively.

[0029] The first level conversion unit is used to convert the high level of the signal output by the CPLD from the first voltage domain to the second voltage domain, where the second voltage domain is higher than the first voltage domain; the low level of the signal output by the CPLD remains unchanged.

[0030] In one possible implementation, the redundant control circuit for the heat dissipation system of CPLD failure protection further includes: a second level conversion unit;

[0031] The input terminal of the second level conversion unit is used to connect to the output terminal of the voltage detection circuit; the output terminal of the second level conversion unit is used to connect to the GPIO port of the BMC.

[0032] The second level conversion unit is used to convert the high level of the signal output by the voltage detection circuit from the second voltage domain to the third voltage domain and then output it to the BMC. The third voltage domain is lower than the second voltage domain; the low level of the signal output by the voltage detection circuit remains unchanged.

[0033] In one possible implementation, the analog switching switch integrates a level conversion function, and the redundant control circuit of the heat dissipation system for CPLD failure protection further includes: a first level conversion unit;

[0034] The input terminal of the first level conversion unit and the second input terminal of the analog switching switch are both used to connect to the PWM output terminal of the CPLD;

[0035] The output of the first level conversion unit is connected to the input of the filter unit;

[0036] The first level conversion unit is used to convert the high level of the signal output by the CPLD from the first voltage domain to the second voltage domain, where the second voltage domain is higher than the first voltage domain; the low level of the signal output by the CPLD remains unchanged.

[0037] The analog switching switch is also used to convert the high level of the signal received at the second input terminal from the CPLD output from the first voltage domain to the second voltage domain.

[0038] Secondly, embodiments of this application provide a redundant control chip for a heat dissipation system to protect against CPLD failure, which integrates the aforementioned redundant control circuit for a heat dissipation system to protect against CPLD failure.

[0039] Thirdly, embodiments of this application provide a server, including:

[0040] CPLD is used to output PWM signals;

[0041] A cooling system is used to dissipate heat from the server; and,

[0042] The aforementioned redundant control circuit for the heat dissipation system of CPLD failure protection is connected to both the CPLD and the heat dissipation system.

[0043] The redundant control circuit and server for the heat dissipation system with CPLD failure protection provided in this application can quickly determine whether the CPLD output is abnormal by filtering the PWM signal output by the CPLD and obtaining a DC level that characterizes its output state based on the relationship between the DC level and the first reference voltage and the second reference voltage. Then, when the CPLD output is abnormal, the analog switch is controlled to switch to the backup PWM generator to drive the heat dissipation system. When the CPLD output is normal, the heat dissipation system is driven by the CPLD. This improves the continuity and switching timeliness of the heat dissipation system control through hardware links, ensures the continuous and stable operation of the heat dissipation system, and improves the reliability of the server. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0045] Figure 1 This is a schematic diagram of the current heat dissipation system control in the server field;

[0046] Figure 2 Schematic diagram of the redundant control circuit for the heat dissipation system for CPLD failure protection provided in the embodiments of this application. Figure 1 ;

[0047] Figure 3 Schematic diagram of the redundant control circuit for the heat dissipation system for CPLD failure protection provided in the embodiments of this application. Figure 2 ;

[0048] Figure 4 A schematic diagram of the signal flow of the redundant control circuit for the heat dissipation system for CPLD failure protection provided in this application embodiment under scenario one (CPLD output is always high level);

[0049] Figure 5 A schematic diagram of the signal flow of the redundant control circuit for the heat dissipation system for CPLD failure protection provided in this application embodiment under scenario two (CPLD output is always low level);

[0050] Figure 6 A schematic diagram of the signal flow of the redundant control circuit for the heat dissipation system for CPLD failure protection provided in this application embodiment under scenario three (CPLD working normally);

[0051] Figure 7 A schematic diagram of the structure of the redundant control chip for the heat dissipation system for CPLD failure protection provided in this application embodiment;

[0052] Figure 8 This is a schematic diagram of the server structure provided in an embodiment of this application.

[0053] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0054] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0055] The terms “first,” “second,” etc., used in this application’s specification are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, products, or apparatus.

[0056] The technology in this application belongs to the field of server thermal control and hardware redundancy protection, and is mainly applied to data center servers, high-density computing devices, and other electronic systems that rely on fans for active cooling. Such systems typically use a main controller (such as a CPLD) to output PWM speed control signals, which work in conjunction with fan actuators to cool the CPU, GPU, storage devices, and power supply modules.

[0057] In existing application architectures, the main controller, as the core node of the fan speed control chain, is responsible for outputting PWM signals based on temperature or preset strategies to adjust the fan speed and maintain the device within a safe temperature range. This type of solution has a relatively centralized structure, and the cooling system is highly dependent on the output state of the main controller.

[0058] Existing server cooling solutions typically use the main controller to directly output PWM signals to drive the fans, such as Figure 1As shown in the schematic diagram of a current server cooling system control, the CPLD controls the fan to operate normally by outputting a PWM signal. The fan speed is adjusted according to the change of the PWM duty cycle. The BMC interacts with the CPLD through the IIC signal to obtain speed information and control the speed, thereby meeting the cooling requirements under different loads. To determine whether the main controller is working properly, the system often indirectly monitors the system by combining temperature data, speed feedback, or bus communication status with the management controller, thus completing the cooling control and fault management.

[0059] However, in actual operation, the main controller may experience PWM output abnormalities due to component aging, abnormal voltage, or program failure. When the output remains at a high or low level for an extended period, the fan may run at full speed continuously or fail to adjust its speed, or even lose its effective heat dissipation capacity. Because existing solutions lack direct and rapid hardware-level identification methods for PWM abnormal states, fault detection often lags behind the occurrence of heat dissipation abnormalities.

[0060] The aforementioned defects further amplify the risk of single-point failure in the cooling system. Once the main controller malfunctions and cannot switch control sources in time, heat will continue to accumulate inside the server. This can lead to increased energy consumption and reduced device lifespan, or even overheating and frequency reduction, service interruption, or hardware damage, making it difficult to meet the continuous cooling requirements of high-reliability scenarios.

[0061] Therefore, how to keep the heat dissipation system continuously under control when the CPLD output is abnormal has become an urgent technical problem to be solved.

[0062] To address the aforementioned issues, this application provides a redundant control circuit for a heat dissipation system with CPLD failure protection. A filtering unit filters the CPLD output signal and outputs a DC level. A voltage detection circuit then determines whether to output a fault or normal signal based on a first and second reference voltage. It controls an analog switching switch to switch the drive path between a backup PWM generator and the CPLD, thus allowing the backup PWM generator to drive the heat dissipation system when the CPLD malfunctions. In other words, a failure protection mechanism is established around the PWM control link in the heat dissipation system to determine the CPLD output state and maintain the control continuity of the heat dissipation system when the CPLD output is abnormal. This prevents the fan from losing its normal speed regulation capability due to CPLD hardware failure, program failure, or output abnormality, thereby improving the stable operation of the heat dissipation system under abnormal conditions.

[0063] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0064] Figure 2 Schematic diagram of the redundant control circuit for the heat dissipation system for CPLD failure protection provided in the embodiments of this application. Figure 1 .like Figure 2 As shown, the redundant control circuit 20 for the heat dissipation system of the CPLD failure protection includes: a filter unit 21, a voltage detection circuit 22, an analog switch 23, and a backup PWM generator 24. The input terminal of the filter unit 21 is connected to the PWM output terminal of the CPLD, and its output terminal is used to connect to the signal input terminal of the voltage detection circuit 22. The power supply terminal of the voltage detection circuit 22 is connected to the power supply, and its output terminal is used to connect to the control terminal of the analog switch 23. The first input terminal of the analog switch 23 is used to connect to the output terminal of the backup PWM generator 24, the second input terminal is used to connect to the PWM output terminal of the CPLD, and the output terminal is used to connect to the heat dissipation system. The filter unit 21 is used to filter the signal output by the CPLD and output DC power. The voltage detection circuit 22 receives the DC level and outputs a fault flag signal when the DC level is greater than the first reference voltage or less than the second reference voltage; it outputs a normal flag signal when the DC level is greater than or equal to the second reference voltage and less than or equal to the first reference voltage. The analog switch 23 is used to connect the first input and output terminals of the analog switch 23 in response to the fault flag signal, so that the standby PWM generator 24 drives the heat dissipation system; in response to the normal flag signal, it connects the second input and output terminals of the analog switch 23, so that the CPLD drives the heat dissipation system. That is, the analog switch 23 is used to switch the drive path between the standby PWM generator 24 and the CPLD in response to the flag signal.

[0065] In this embodiment, the filtering unit 21 refers to a signal shaping module located between the PWM output terminal of the CPLD and the voltage detection circuit. It is used to smooth the signal output by the CPLD into a DC level that is easy to compare and judge, and provide the DC level to the subsequent voltage detection circuit 22 so that the subsequent circuit can judge whether the CPLD output is in an abnormal state based on the level range. The filtering unit 21 is located between the CPLD output side and the detection side in the circuit layout, and is usually connected in series. Its input terminal is used to receive the PWM signal of the CPLD, and its output terminal serves as the sampling point of the voltage detection circuit. During operation, it does not change the fan drive link itself, but only processes the signal used for state identification. In one possible embodiment, the filtering unit 21 can be implemented as a circuit structure that can filter the PWM signal and form a DC level. The device is generally mounted on a printed circuit board (PCB) and kept shortly connected to the adjacent detection circuit to reduce interference. Its size and proportion can be set according to the PWM period, sampling response requirements and board space. Usually, its response characteristics are matched with the PWM period so that the output terminal forms a stable DC level without significantly delaying fault identification.

[0066] The voltage detection circuit 22 is a detection module that determines the range of the DC level output by the filter unit 21 and outputs a flag signal. It is used to generate a fault flag signal when the CPLD output level exceeds a preset range and to generate a normal flag signal when the level is within a preset range, thus serving as the control basis for the analog switch 23. The input terminal of the voltage detection circuit 22 is connected to the output terminal of the filter unit 21, the power supply terminal is connected to the power supply, and the output terminal is connected to the control terminal of the analog switch 23. It is usually installed after the filter unit 21 and forms a direct electrical connection with the control line of the analog switch 23. In one possible embodiment, the voltage detection circuit 22 can be implemented as a detection module that can perform threshold comparison of the DC level and output a flag signal, which is convenient for layout according to the space of the server motherboard or control board. Its size design is usually matched with the CPLD output level range, reference voltage setting, and wiring noise tolerance. The first reference voltage is greater than the second reference voltage, and a normal window range is formed between the two. The voltage detection circuit 22 outputs a normal flag signal for the level within this range and outputs a fault flag signal for the level higher than the first reference voltage or lower than the second reference voltage.

[0067] The analog switch 23 is a switching device that selectively connects the heat dissipation system between the standby PWM generator 24 and the CPLD output based on the flag signal output by the voltage detection circuit 22. It is used to switch the heat dissipation system to be driven by the standby PWM generator when a fault flag signal is detected, and to keep the CPLD directly driving the heat dissipation system when a normal flag signal is detected. The first input terminal of the analog switch 23 is connected to the output terminal of the standby PWM generator 24, the second input terminal is connected to the PWM output terminal of the CPLD, and the output terminal of the analog switch 23 is connected to a fan, duct actuator, or other heat dissipation system load that relies on PWM speed regulation. The control terminal receives the flag signal output by the voltage detection circuit 22, thus forming an electrical path that can quickly switch between two signals. In one possible embodiment, the analog switch 23 can be implemented as an analog multiplexer or a MOSFET (Metal-Oxide-Semiconductor Field-Effect MOSFET). Transistor (switch array, relay switching circuit or analog switch chip) can be structurally a single-pole double-throw structure, a dual-input single-output structure or an integrated switching chip. Electrically, it can be implemented using silicon-based MOS technology, mechanical contact metal materials or semiconductor analog switch structure. Its size and conduction characteristics usually require low channel on-resistance, and the level compatibility of the two inputs and outputs must meet the fan PWM drive specification to ensure that the output can maintain a continuously controlled state during switching.

[0068] The backup PWM generator 24 refers to a redundant signal source that can continuously provide PWM signals when the CPLD fails or its output is abnormal. It is used to take over driving the cooling system when the main control path is unavailable, so that the fan can continue to run according to the preset strategy. The output terminal of the backup PWM generator 24 is connected to the first input terminal of the analog switch 23 and is usually installed in an independent functional area on the control board. In one possible embodiment, the backup PWM generator 24 can be composed of a circuit module that can output a backup PWM signal, and is usually combined with related devices to form a stable output. Its size and output parameters are usually compatible with the original cooling PWM specification. The output frequency, duty cycle and level amplitude should meet the requirements of the fan drive interface so that it can be directly connected to the cooling system without conversion after switching.

[0069] Based on the above analysis, when the system starts up, the CPLD first outputs a PWM signal for fan speed control. This PWM signal is sent directly to the cooling system via an analog switch, and simultaneously enters a filter unit for smoothing and forming a DC level. The DC level is then sampled in real-time by a voltage detection circuit and compared with a first reference voltage and a second reference voltage within a window. When the CPLD output is in normal modulation, the DC level falls within a preset window range, and the voltage detection circuit outputs a normal indicator signal. The analog switch accordingly keeps the second input and output terminals connected, allowing the CPLD to continuously act as the cooling drive source. When the CPLD's PWM output remains at a high, low, or other out-of-bounds state for an extended period due to device aging, abnormal voltage, or program failure, the corresponding DC level output by the filter unit deviates from the normal window. The voltage detection circuit then outputs a fault indicator signal, and the analog switch switches to connect the first input and output terminals, allowing the backup PWM generator to take over the drive of the cooling system. Through this electrical detection and switching method, abnormal CPLD states can be directly converted into control path switching commands, thereby achieving redundant drive switching for the cooling system and ensuring continuous control of the fan speed control link even when the main controller malfunctions.

[0070] The analog switching switch dynamically switches the control path based on the fault or normal indicator signal output by the voltage detection circuit. When the voltage detection circuit outputs a fault indicator signal, the control terminal of the analog switching switch receives a high-level signal, triggering the internal switching circuit to connect the output path of the backup PWM generator to the cooling system, while simultaneously disconnecting the PWM output path of the CPLD. When the voltage detection circuit outputs a normal indicator signal, the analog switching switch maintains the path where the CPLD directly drives the cooling system. Through this switching logic, the analog switching switch seamlessly takes over control when the CPLD malfunctions, ensuring the continuous operation of the cooling system.

[0071] In this embodiment, by filtering the PWM signal output by the CPLD and obtaining a DC level characterizing its output state, it is possible to quickly determine whether the CPLD output is abnormal based on the relationship between the DC level and the first reference voltage and the second reference voltage. Then, when the CPLD output is abnormal, the analog switching switch is controlled to switch to the backup PWM generator to drive the heat dissipation system, and when the CPLD output is normal, the heat dissipation system is kept driven by the CPLD. This improves the continuity and switching timeliness of the heat dissipation system control through hardware links, ensures the continuous and stable operation of the heat dissipation system, and improves the reliability of the server.

[0072] Next, combined Figure 3 The redundant control circuit of the heat dissipation system for CPLD failure protection is further explained.

[0073] Figure 3Schematic diagram of the redundant control circuit for the heat dissipation system for CPLD failure protection provided in the embodiments of this application. Figure 2 ,like Figure 3 As shown, in some embodiments, the voltage detection circuit 22 includes: a first comparator U1, a second comparator U2, and a level combining circuit 221; the non-inverting input of the first comparator U1 and the inverting input of the second comparator U2 are connected together, and the common input is used as the signal input of the voltage detection circuit 22, which is connected to the output of the filter unit 21; the inverting input of the first comparator U1 is connected to a first reference voltage; the output of the first comparator U1 is connected to the first input of the level combining circuit 221; the non-inverting input of the second comparator U2 is connected to a second reference voltage; the output of the second comparator U2 is connected to the second input of the level combining circuit 221; the power supply terminals of the first comparator U1 and the second comparator U2 are connected together (…). Figure 3 (Not shown in the image), serving as the power supply terminal of the voltage detection circuit 22, is used to connect to the power supply ( Figure 3 (not shown in the image); the output of the level combining circuit 221 serves as the output of the voltage detection circuit 22, and is used to connect to the control terminal of the analog switching switch 23.

[0074] The first comparator U1 is used to compare the input level U0 with the first reference voltage U. RH The function of the second comparator is to compare and output the corresponding logic state. Its purpose is to detect whether the DC level output by the filter unit 21 is higher than the upper threshold, thereby generating a corresponding electrical response when the input level abnormally increases. The second comparator U2 is used to compare the input level U0 with the second reference voltage U. RL The comparison and output of the corresponding logic state are used to detect whether the DC level output by the filter unit 21 is lower than the lower threshold, thereby generating a corresponding electrical response when the input level abnormally decreases; the first reference voltage U RH For example, the voltage detection circuit 22 is supplied with 80% of the power supply voltage, and the second reference voltage U... RL For example, the voltage detection circuit 22 is supplied with 20% of the power supply voltage. The power supply voltage is usually designed to be consistent with the high-level voltage of the PWM signal of the back-end cooling system (such as the fan), for example, both are 5V.

[0075] The level combining circuit 221 is used to logically synthesize multiple comparison results. Its function is to combine the output states of the first comparator and the second comparator into a single flag signal to drive the subsequent analog switch 23 to complete the control path switching. The first comparator U1 and the second comparator U2 can be located on the same printed circuit board and arranged close to the filter unit 21 and the analog switch 23. The non-inverting input of the first comparator U1 and the inverting input of the second comparator U2 are connected together to form a single signal input node. This node is connected to the output of the filter unit 21 through a short trace or via to reduce parasitic inductance and interference coupling on the transmission path. The inverting input of the first comparator U1 is connected to a preset first reference voltage source, and the non-inverting input of the second comparator U2 is connected to a preset second reference voltage source. The first reference voltage is greater than the second reference voltage to form a window threshold for identifying the normal level range. The power supply terminals of the first comparator U1 and the second comparator U2 are connected to a common power supply. The power supply can be a 3-volt, 5-volt, or other regulated power supply adapted to the logic devices within the system to ensure that the comparators output a definite logic state within a stable operating range. The first comparator U1 and the second comparator U2 can be implemented using independent comparator chips, dual-channel comparator chips, or window comparator integrated circuits. The level merging circuit 221 can adopt a diode-isolated common connection structure (i.e., the output terminals of each comparator are connected in series with a diode and then connected to a common node, and the common node is connected to the power supply through a pull-up resistor), an open-collector or open-drain parallel pull-up structure, or it can be implemented by a logic gate array. Its materials are usually composed of silicon-based semiconductor chips, metal interconnect layers, and encapsulating resin, and electrical connections are completed with PCB pads, copper foil traces, and necessary pull-up resistors. In terms of size, the comparator can be packaged in conventional miniaturized packages such as Small Outline Transistor (SOT), Small Outline Integrated Circuit (SOIC), Thin Shrink Small Outline Package (TSSOP), or Quad Flat No-leads (QFN). The device's footprint typically meets the compact layout requirements of server control boards. Threshold accuracy, input bias current, and output drive capability should meet the need for rapid discrimination of the DC level after PWM filtering. Sufficient voltage spacing should be maintained between the first and second reference voltages to avoid misjudgments caused by input level jitter near the window boundary. It should be understood that the above examples are for illustrative purposes only and are not limiting. In specific implementations, equivalent substitutions of device models and threshold parameters can be made based on the control board's power supply conditions, signal amplitude, and the control strategy of the heat dissipation system.

[0076] When the system starts, the filter unit 21 first performs low-pass filtering on the PWM output from the CPLD and converts it into a DC level corresponding to the duty cycle. This DC level is simultaneously sent to the first comparator U1 and the second comparator U2 via the signal input terminal of the voltage detection circuit 22. The first comparator compares this level with the first reference voltage, and the second comparator U2 compares this level with the second reference voltage. When the input level is between the first reference voltage and the second reference voltage, the two comparison results are combined by the level combining circuit 221 to form the output logic corresponding to the normal state and sent to the control terminal of the analog switch 23, so that the analog switch 23 connects the second input terminal and the output terminal, thereby allowing the CPLD to maintain control of the heat dissipation system. When the input level is higher than the first reference voltage or lower than the second reference voltage, at least one comparator output state changes. After being combined by the level combining circuit 221, a fault flag signal is formed at the output terminal. This fault flag signal further drives the analog switch 23 to switch to the first input terminal and the output terminal being connected, so that the backup PWM generator takes over the drive path of the heat dissipation system. Therefore, the voltage detection circuit 22 can provide a stable logic judgment in a timely manner when the CPLD output abnormally rises, abnormally falls, or loses its normal modulation characteristics for a long time, avoiding the direct transmission of single-path faults to the fan actuator. This improves the continuity and redundancy protection capability of the heat dissipation control link and reduces the risk of fan malfunction or heat dissipation failure due to PWM abnormalities. It should be understood that the above example is only illustrative and not limiting. Without departing from the spirit of this application, the number of comparators, the logic synthesis method, and the reference voltage setting method can all be equivalently modified according to specific applications.

[0077] In this embodiment, a dual-threshold detection of DC levels is achieved through the collaborative design of a first comparator and a second comparator, ensuring the accuracy of the fault flag signal. The level merging circuit implements the logic AND function, simplifying the hardware structure and improving detection efficiency, thereby enhancing the system's response speed and reliability to abnormal CPLD output signals.

[0078] See also Figure 3 In one possible implementation, the level merging circuit 221 includes: a first diode D1 and a second diode D2; the anode of the first diode D1 serves as the first input terminal of the level merging circuit; the anode of the second diode D2 serves as the second input terminal of the level merging circuit 221; the cathodes of the first diode D1 and the second diode D2 are connected together, and the common connection terminal serves as the output terminal of the level merging circuit 221.

[0079] In this embodiment, the level combining circuit utilizes the unidirectional conduction characteristic of diodes to aggregate the output signals from different comparators to the same control node, while suppressing reverse crosstalk between the input terminals. This level combining circuit is used in the voltage detection circuit to logically synthesize the outputs of the first and second comparators, ensuring that the analog switch receives only a single flag signal interface. When both comparator outputs are high, the level combining circuit outputs a high-level fault flag signal; when both comparator outputs are low, the level combining circuit outputs a low-level normal flag signal; and when only one comparator outputs a high level, the level combining circuit outputs a high-level fault flag signal. This logical synthesis mechanism ensures that the voltage detection circuit can accurately distinguish between the normal and abnormal states of the CPLD output signal. The first diode D1 and the second diode D2 respectively serve as the isolation and merging functions of the two comparator outputs. The anode of the first diode D1 serves as the first input terminal of the level merging circuit, which is electrically connected to the output terminal of the first comparator U1. The anode of the second diode D2 serves as the second input terminal of the level merging circuit, which is electrically connected to the output terminal of the second comparator U2. The cathodes of the first diode D1 and the second diode D2 are connected together to form a common node. This common node serves as the output terminal of the level merging circuit and is consistent with the output terminal of the voltage detection circuit, thereby directly outputting the level after diode merging to the subsequent control terminal.

[0080] Based on the above structure, this circuit can complete the logical merging of two electrical signals without relying on mechanical contacts. Furthermore, due to the unidirectional conduction of each diode, when either comparator output is valid, the corresponding diode conducts, and the common output terminal obtains the corresponding control level, while the other input terminal will not be reverse-driven due to changes in the common node level. In circuit implementation, the first diode D1 and the second diode D2 can be Schottky diodes, small-signal switching diodes, or rectifier diodes. The package type can be surface mount, through-hole, or dual-diode integrated package. Their semiconductor structure can be a silicon-based PN junction structure or a metal-semiconductor junction structure to adapt to different supply voltages, logic thresholds, and switching speed requirements. To ensure output consistency and logic decision stability, the forward voltage drop, reverse leakage current, reverse withstand voltage, and reverse recovery time of the two diodes should be matched as much as possible. Specifically, the forward voltage drop should ensure that the comparator output level can still be correctly identified by the subsequent control terminal after the diode voltage drop. The reverse withstand voltage should be higher than the highest possible control voltage of the system, and the reverse recovery time should be coordinated with the response speed of the voltage detection circuit. In terms of size, in one possible embodiment, the diode can be selected as a miniature surface-mount device based on board space, switching frequency, and drive current. Its pin spacing, chip size, and package height can be adapted to the high-density layout of server control boards. When using discrete packaging, its rated forward current can be determined based on the comparator output current, typically ranging from milliamps to tens of milliamps. When using a dual-diode integrated package, wiring length can be reduced and parasitic inductance lowered within a similar chip area, thereby improving the response consistency of the level merging circuit. It should be understood that the above examples are merely illustrative and not limiting.

[0081] In one possible embodiment, when the system starts up, the first and second comparators in the voltage detection circuit compare the DC level output by the filter unit with the first and second reference voltages, respectively, and send the comparison results to the first and second input terminals of the level combining circuit. If the filtered level is within the normal range, the comparator corresponding to the normal flag outputs a valid level, which, after being unidirectionally turned on by its corresponding diode, forms a control state that can be recognized by the analog switching switch at the common output terminal. If the filtered level is higher than the first reference voltage or lower than the second reference voltage, the corresponding fault determination path outputs a valid level, and the common output terminal also forms a fault flag signal through the diode bus. Since the cathodes of the two diodes are connected together, any valid output can be transmitted to the output terminal without mutual interference, while the other input path is cut off, thereby avoiding reverse current sinking or mutual pull-down of the output level between the comparators.

[0082] This structure enables the voltage detection circuit to integrate signals after multi-condition judgment with a relatively simple number of components, and outputs the final flag signal stably to the control terminal of the analog switching switch. This allows for timely switching to the backup PWM generator to drive the cooling system when an abnormal CPLD output is detected, while maintaining direct control of the cooling system by the CPLD when the CPLD output is normal. Therefore, this level merging circuit improves the isolation and response reliability of the control path while ensuring signal convergence, reduces the risk of misjudgment due to comparator output conflicts, and helps maintain continuous operation of the cooling control link under abnormal conditions.

[0083] Based on the aforementioned embodiments, the backup PWM generator operates independently to continuously output a backup PWM signal;

[0084] Alternatively, the backup PWM generator has an enable terminal connected to the output of the voltage detection circuit; the backup PWM generator is configured such that when the voltage detection circuit outputs a fault flag signal, the backup PWM generator is enabled and outputs a backup PWM signal; when the voltage detection circuit outputs a normal flag signal, the backup PWM generator is disabled.

[0085] In this embodiment, a backup PWM generator is used to provide a usable alternative PWM drive to the cooling system when the CPLD output is abnormal. Its function is to ensure that the analog switching switch can obtain a stable second drive source when needed by continuously or in a controlled manner outputting a backup PWM signal, thereby maintaining the continuous speed regulation capability of the fan or other cooling actuators. The output terminal of the backup PWM generator is typically connected to the first input terminal of the analog switching switch, so that its output PWM signal can be directly sent to the cooling system after a fault switch. When the backup PWM generator is equipped with an enable terminal, this enable terminal is connected to the output terminal of a voltage detection circuit to receive a fault flag signal or a normal flag signal, and control its output state accordingly.

[0086] In one possible embodiment, the backup PWM generator can be implemented by an independent oscillator, a PWM control chip, a timer module of a microcontroller, or a programmable logic output unit, or any of these combined with a peripheral driver stage. Its form can be an independent working board, an on-chip peripheral unit, or a discrete functional module. Its materials typically consist mainly of silicon-based integrated circuits, quartz oscillators, RC (Resistor-Capacitor) timing elements, and peripheral filtering devices. The oscillation core can be implemented using a semiconductor chip, the timing reference can be implemented using a crystal or RC network, and the peripheral connections can be completed using printed circuit board copper traces and package pins. Its output frequency, duty cycle, and drive capability should generally match the PWM interface specification of the cooling system fan. In common cases, it can be set to the same or equivalent control parameters as the original CPLD output to ensure consistent fan response after switching. Its enable response time should also meet the fault takeover requirements so that it can quickly enter the output state after the voltage detection circuit detects an anomaly. The size of a backup PWM generator is generally not mechanically constrained, but its board area, package size, and pin pitch can be selected according to the system integration space. Examples include small surface-mount packages, plug-in modules, or embedded daughterboards to accommodate the layout requirements of server motherboards or control backplanes. It should be understood that the above examples are for illustrative purposes only and are not limiting.

[0087] For example, when the system starts up, the backup PWM generator can enter an independent operating state according to the implementation method adopted, continuously generating a backup PWM signal that meets the fan control requirements and maintaining a stable PWM signal at the output. Alternatively, in an implementation with an enable terminal, the backup PWM generator is initially in a disabled or standby state. Its enable terminal receives a flag signal output by the voltage detection circuit in real time. When the voltage detection circuit determines that the CPLD output is abnormal based on the filtered DC level and issues a fault flag signal, the enable terminal is triggered, and the backup PWM generator starts up and outputs a backup PWM signal. The analog switch then switches this backup PWM signal to the cooling system. When the voltage detection circuit determines that the CPLD output is within the normal range and outputs a normal flag signal, the enable terminal keeps the backup PWM generator disabled, thereby avoiding simultaneous driving of the backup channel and the main channel. Through the control logic of the enable terminal, the backup PWM generator is enabled on demand, avoiding the ineffective operation of redundant control paths, thereby reducing system energy consumption and extending hardware life, while ensuring the priority of the main control path when the CPLD is working normally.

[0088] Based on the above working process, it can be seen that this embodiment can quickly activate the backup PWM drive path when the CPLD fails or the output is abnormal, so that the heat dissipation system remains continuously controlled during the control source switching process, reducing the risk of fan stall, full-speed runaway or heat dissipation interruption caused by the failure of the main controller, and giving the redundant control circuit higher fault takeover capability and heat dissipation continuity.

[0089] See also Figure 3 In one possible implementation, the filter unit 21 includes: a resistor R1 and a capacitor C1; one end of the resistor R1 serves as the input terminal of the filter unit 21 and is used to connect to the PWM output terminal of the CPLD; the other end of the resistor R1 is connected to one end of the capacitor C1, and the common connection terminal serves as the output terminal of the filter unit 21; the other end of the capacitor C1 is grounded.

[0090] A resistor and capacitor form an RC low-pass filter to average the PWM signal output by the CPLD. The high and low levels of the PWM signal are integrated in the RC charging and discharging circuit to form a DC level corresponding to the duty cycle. The energy storage characteristics of the capacitor smooth the high-frequency switching of the PWM signal, and the DC level at the output terminal U0 directly reflects the CPLD's PWM output state (such as constantly high, constantly low, or normal modulation). This passive filter structure provides a stable DC level input to the voltage detection circuit without requiring an external power supply.

[0091] In this embodiment, the filter unit composed of resistors and capacitors is used to average the PWM signal output by the CPLD. Its function is to convert the high-frequency switching quantity corresponding to the duty cycle change of the PWM signal into a DC level that can be recognized by the voltage detection circuit, so that the subsequent stage can determine whether the CPLD output is in a normal state based on the level. The resistor is set between the PWM output terminal of the CPLD and the filter node, serving as an input current limiting and charging / discharging channel. The capacitor is grounded from the filter node to utilize its energy storage and discharging characteristics to smooth the PWM signal. One end of the resistor serves as the input terminal of the filter unit and is electrically connected to the PWM output terminal of the CPLD. The other end of the resistor and one end of the capacitor are connected together to form the output terminal of the filter unit. This output terminal is further connected to the signal input terminal of the voltage detection circuit, while the other end of the capacitor is grounded to form a complete RC circuit. Based on the above connection relationships, it can be seen that the filter unit is usually physically arranged near the CPLD output pin to shorten the high-frequency pulse traces and reduce parasitic interference. In one possible embodiment, the resistor can be a surface-mount resistor, a thin-film resistor, or a metal film resistor, and the capacitor can be a ceramic capacitor, an electrolytic capacitor, or a tantalum capacitor. The specific device type can be selected according to the withstand voltage, capacitance accuracy, and temperature stability. In terms of form, the filter unit can form a single-stage RC low-pass filter network, a two-stage RC cascade filter network, or add a buffer amplifier after the filter node to form a buffered RC filter structure to adapt to different PWM frequencies and detection response time requirements. In terms of materials, the resistor can be a metal oxide film, thick-film ceramic, or metal film resistor material, and the capacitor can be an alumina ceramic dielectric, a polymer dielectric, or an organic electrolyte structure, all of which are common electronic component forms that can achieve resistance-capacitance integration characteristics. Regarding size and proportions, the time constant formed by the product of the resistor value and the capacitor value should match the PWM period. It can usually be set to a number of times the PWM period to ensure a stable average output level while avoiding slow fault detection response. For example, if the PWM frequency is high, a smaller resistor value and a moderate capacitor value can be selected to maintain sufficient filtering bandwidth. If the PWM frequency is low or stronger ripple suppression is required, the RC time constant can be appropriately increased. The package size of the resistor and capacitor can be determined according to the space available on the server motherboard.

[0092] For example, when the system starts up, the PWM signal output by the CPLD is first applied to the filter node via a resistor. The PWM signal is continuously integrated and smoothed in the charging and discharging loop formed by the resistor and the grounding capacitor, so that the output of the filter node is an approximate DC level corresponding to the PWM duty cycle. When the PWM signal is in normal speed regulation state, the capacitor continuously completes charging and discharging in each cycle, and the output level stably falls within the predetermined detection range. The voltage detection circuit outputs a normal flag signal accordingly and keeps the subsequent analog switching switch driven by the CPLD side to drive the heat dissipation system. However, when the CPLD fails, causing the PWM output to be at a high level, low level or abnormal fixed duty cycle for a long time, the DC level of the filter node will deviate from the normal range. The voltage detection circuit can quickly identify the deviation and output a fault flag signal, thereby triggering the backup PWM generator to intervene in the control.

[0093] Since the resistor and capacitor together achieve passive averaging of the PWM signal, the structure is simple, the cost is low and no mechanical action is introduced. It can improve the feasibility of anomaly identification without increasing the complexity of the main control link, and provide a stable and discernible level basis for subsequent control switching. This is conducive to maintaining continuous control of the heat dissipation system when the CPLD is abnormal, and reducing the risk of overheating caused by PWM output failure.

[0094] In practical applications, the operating voltage domain of the CPLD often differs from that of the subsequent circuits. If the signal output from the CPLD is directly connected to the subsequent circuit, the subsequent circuit may be unable to correctly identify the signal logic level, leading to misjudgment and affecting the normal operation of the heat dissipation system. To solve this technical problem, based on the aforementioned embodiments, the redundant control circuit 20 for the heat dissipation system under CPLD failure protection further includes: a first level conversion unit 25. See also... Figure 3 The input terminal of the first level conversion unit 25 is used to connect to the PWM output terminal of the CPLD, and the output terminal is connected to the input terminal of the filter unit 21 and the second input terminal of the analog switching switch 23 respectively. The first level conversion unit 25 is used to convert the high level of the signal output by the CPLD from the first voltage domain to the second voltage domain, and the second voltage domain is higher than the first voltage domain. The low level of the signal output by the CPLD remains unchanged.

[0095] In this embodiment, the first level conversion unit 25 is used to perform voltage domain adaptation on the PWM signal output by the CPLD. Its function is to boost the high-level amplitude without changing the PWM duty cycle logic relationship, so as to meet the input level threshold requirements of the subsequent filter unit 21 and the second input terminal of the analog switch 23, while keeping the low level unchanged to avoid unnecessary disturbance to the reference state of the PWM signal. The first level conversion unit 25 is usually installed between the PWM output terminal of the CPLD and the filter unit 21 and the analog switch 23. Its input terminal directly receives the PWM signal from the CPLD, and its output terminal is connected in parallel to the input terminal of the filter unit 21 and the second input terminal of the analog switch 23, so that the same PWM signal after level conversion is simultaneously supplied to the filter detection link and the main drive switching link.

[0096] In one possible embodiment, the first level conversion unit 25 can be implemented using a MOSFET bidirectional level conversion circuit, a dedicated level shifting chip, a voltage divider buffer circuit, or a transistor open-collector conversion structure. The MOSFET bidirectional level conversion circuit is suitable for using gate-source threshold voltages to achieve signal transmission between two voltage domains. The dedicated level shifting chip is suitable for providing stable edge shaping and driving capabilities under high-frequency PWM conditions. The voltage divider buffer circuit is suitable for use at the detection end with high input impedance to reduce device complexity. The transistor open-collector conversion structure is suitable for achieving level boosting and providing a certain degree of isolation through external pull-up resistors. In terms of form, it can be an independent chip, a discrete component board, or an interface module integrated on a motherboard. In terms of materials, it is mainly composed of silicon-based semiconductor devices, metal interconnect layers, and conventional packaging materials. Since this unit only converts electrical signal levels without involving mechanical movement, its operation process has the characteristics of fast response, low loss, and simple structure. For example, when the first voltage domain corresponds to the original output voltage of the CPLD and the second voltage domain corresponds to the higher logic level required by the filter unit 21 and the analog switching switch 23, the first level conversion unit 25 raises the high level of the PWM signal to the second voltage domain so that the low level remains in the original low level state. This ensures that the PWM signal input to the subsequent stage can meet the electrical compatibility of comparison detection and switching control without changing the duty cycle information itself.

[0097] When the system starts up, the CPLD first outputs a PWM signal for heat dissipation speed regulation. This PWM signal is voltage-domain adapted by the first level conversion unit, and then one path is sent to the filter unit, while the other path is sent to the second input terminal of the analog switch. This allows the same signal to participate in fault detection and path selection control respectively, provided that the input thresholds of the subsequent devices are met. Since the first level conversion unit only boosts the high level while keeping the low level unchanged, the filter unit can still form a DC level corresponding to the original duty cycle after integrating or low-pass processing the PWM signal. The voltage detection circuit can then accurately determine whether the CPLD output is within the normal range. At the same time, after receiving the level-adapted PWM signal, the second input terminal of the analog switch can stably connect the signal to the heat dissipation system under the action of the normal flag signal, so that the fan runs according to the speed regulation strategy set by the CPLD.

[0098] For example, in a typical server heat dissipation control scenario, the CPLD is powered by 3.3V, while the subsequent filter unit 21 and analog switch 23 operate in the 5V voltage domain, with a logic high-level recognition threshold of approximately 3.5V. If the CPLD's 3.3V signal is directly connected to the subsequent circuit, the high-level 3.3V is lower than the 3.5V recognition threshold, which may cause the filter unit 21 to fail to output a correct DC level and the analog switch 23 to fail to accurately recognize the control signal. Therefore, the first level conversion unit 25 raises the 3.3V high level output by the CPLD to 5V, while keeping the low level unchanged at 0V, enabling the subsequent 5V circuit to reliably recognize the signal output by the CPLD.

[0099] It is worth noting that the first level conversion unit 25 applies regardless of whether the CPLD outputs a normal PWM pulse, a constant high level, or a constant low level: for a normal PWM pulse, the high level is raised from 3.3V to 5V, while the low level remains at 0V; for a constant high level, the 3.3V is raised to a constant high level of 5V; and for a constant low level, 0V remains at 0V. This ensures that the subsequent circuitry can correctly identify the CPLD output signal under different input states, providing a reliable voltage domain matching basis for subsequent fault detection and redundancy switching.

[0100] Based on the above process, it can be seen that the setting of the first level conversion unit eliminates the interface mismatch problem caused by the inconsistency between the CPLD output voltage and the working voltage of the subsequent devices. On the other hand, it ensures the consistent transmission of the PWM signal in the detection link and the control link, thereby improving the compatibility and reliability of the redundant control circuit under different voltage domains, and helps to reduce the risk of abnormal heat dissipation control caused by insufficient level, logic misjudgment or switch drive failure.

[0101] In one possible implementation, the redundant control circuit 20 for the heat dissipation system of the CPLD failure protection further includes: a second level conversion unit 26; the input terminal of the second level conversion unit 26 is used to connect to the output terminal of the voltage detection circuit 22; the output terminal of the second level conversion unit 26 is used to connect to the GPIO port of the BMC; the second level conversion unit 26 is used to convert the high level of the signal output by the voltage detection circuit 22 from the second voltage domain to the third voltage domain and then output it to the BMC, the third voltage domain being lower than the second voltage domain; the low level of the signal output by the voltage detection circuit remains unchanged.

[0102] Understandably, in a server system, the BMC, as the core of system management, typically uses a 3.3V voltage range for its GPIO ports, while the fault or normal flag signals output by the voltage detection circuit 22 operate at a 5V voltage range. Directly connecting a 5V signal to the BMC's 3.3V GPIO port exceeds its voltage tolerance, potentially damaging the BMC's GPIO ports and causing system management functions to fail. To address this technical problem, this embodiment includes a second level conversion unit 26 to adapt the signal output by the voltage detection circuit 22, stepping down the high level from 5V to 3.3V while keeping the low level at 0V. This allows the BMC to safely and reliably identify the status information output by the voltage detection circuit.

[0103] For example, in a typical server thermal management scenario, the voltage detection circuit 22 is powered by 5V, and its output fault flag signal has a high level of 5V and a low level of 0V. The BMC is powered by 3.3V, and the upper limit of its GPIO port input high level tolerance is approximately 3.6V. If a 5V signal is directly connected to the GPIO port of the BMC, exceeding its maximum withstand voltage, it may cause the internal IO protection diode of the BMC to conduct, the port to burn out, or the logic level to be misjudged. Therefore, this embodiment sets up a second level conversion unit 26 to convert the 5V high level to 3.3V before sending it to the BMC, ensuring that the BMC can safely and stably receive the output state of the voltage detection circuit 22.

[0104] It is worth noting that the second level conversion unit 26 converts two status signals output by the voltage detection circuit 22: when the CPLD is working normally and the voltage detection circuit 22 outputs a normal flag signal (low level 0V), the second level conversion unit 26 outputs a low level 0V to the BMC; when the CPLD malfunctions and the voltage detection circuit 22 outputs a fault flag signal (high level 5V), the second level conversion unit 26 steps down the high level from 5V to 3.3V before outputting it to the BMC, while keeping the low level at 0V. The BMC identifies this level state through the GPIO port: receiving a high level of 3.3V determines that the CPLD is faulty, and receiving a low level of 0V determines that the CPLD is normal, thereby realizing remote monitoring and alarm reporting of the CPLD status.

[0105] With the above settings, the second level conversion unit 26 not only protects the GPIO port of the BMC from high voltage damage, but also ensures that the output signal of the voltage detection circuit 22 can be accurately identified by the BMC when the power supply standards of different devices are inconsistent, thus providing a reliable signal interface for system management.

[0106] In other words, the second level conversion unit 26 is used to perform level adaptation on the fault flag signal output by the voltage detection circuit 22. Its function is to convert the high-level logic signal from the higher voltage domain into a lower voltage domain signal that meets the input threshold of the BMC's GPIO port, thereby enabling the BMC to reliably identify the status information output by the voltage detection circuit without changing the low-level logic characteristics of the output signal. The second level conversion unit 26 is located between the voltage detection circuit 22 and the BMC. Its input terminal is electrically connected to the output terminal of the voltage detection circuit 22, and its output terminal is electrically connected to the GPIO port of the BMC. Signal transmission is typically achieved through wires, on-board traces, or connector pins. For example, the second level conversion unit 26 can be implemented using a MOSFET level conversion circuit, a conversion circuit with open-drain pull-down and pull-up resistors, a dedicated logic level conversion chip, or a buffer / inverting conversion circuit composed of transistors. In other embodiments, opto-isolated output and logic level reconstruction after digital isolators can also be used to adapt to the input level specifications of different BMC platforms. Its device material is generally silicon-based semiconductor material, the internal conductor part is composed of metal interconnects, and it can be encapsulated in a plastic package or ceramic package. It can be arranged on the control circuit board as an independent conversion module, integrated interface chip or discrete device network. Since the second voltage domain is higher than the third voltage domain, the second level conversion unit 26 needs to ensure that the high level on the input side is stably pulled down to the target domain voltage after being transmitted to the output side, while the low level on the input side remains close to the original low level, without introducing additional logic flips or unnecessary level drift.

[0107] For example, when the system starts up, the BMC receives status information from the voltage detection circuit through its GPIO port. The second level conversion unit first performs voltage domain adaptation on this status information, converting the high level output by the voltage detection circuit from the second voltage domain to the third voltage domain before sending it to the BMC. This ensures that the BMC can accurately identify fault or normal flag signals even when the power supply standards of different devices are inconsistent. At the same time, the low-level signal remains unchanged during the conversion process, so that the logic "0" state is not distorted due to level conversion. Since this conversion process only involves adjusting the amplitude of the logic level and does not change the timing relationship and polarity characteristics of the signal, the BMC can stably obtain the output status of the voltage detection circuit without increasing the complexity of the judgment.

[0108] Based on the above analysis, it can be seen that the second level conversion unit can effectively solve the problem of mismatch between the output voltage domain of the voltage detection circuit and the input voltage domain of the BMC, avoid misidentification, missed identification or input damage caused by incompatibility of high-level thresholds, and maintain low-level consistency, thereby improving the compatibility, reliability and cross-platform adaptability of the redundant control link of the heat dissipation system.

[0109] In some embodiments, the analog switch 23 integrates a level conversion function, and the redundant control circuit 20 for the heat dissipation system of the CPLD failure protection further includes: a first level conversion unit 25; the input terminal of the first level conversion unit 25 and the second input terminal of the analog switch 23 are both used to connect to the PWM output terminal of the CPLD; the output terminal of the first level conversion unit 25 is connected to the input terminal of the filter unit 21; the first level conversion unit 25 is used to convert the high level of the signal output by the CPLD from the first voltage domain to the second voltage domain, the second voltage domain being higher than the first voltage domain; the low level of the signal output by the CPLD remains unchanged; the analog switch 23 is also used to convert the high level of the signal output by the CPLD received at the second input terminal from the first voltage domain to the second voltage domain.

[0110] Understandably, the first level conversion unit 25 is used to perform level adaptation on the PWM signal output by the CPLD. Its function is to boost the high level from the first voltage domain to the second voltage domain while keeping the low level potential unchanged, so that the same PWM signal can meet the level requirements of the filter detection link and the analog switch input link respectively. This first level conversion unit 25 is usually arranged near the PWM output terminal of the CPLD and is connected to the second input terminal of the filter unit 21 and the analog switch 23 respectively through parallel branches. This allows the signal output by the CPLD to undergo voltage domain conversion before entering the filter unit 21, while the original signal can also be directly sent to the integrated level conversion channel inside the analog switch 23. Since the analog switch 23 integrates level conversion function, the low-voltage PWM signal received at the second input terminal can be boosted to the second voltage domain inside the switch before participating in channel selection. Therefore, the number of external discrete components can be reduced and the interface inconsistency problem in the signal link can be reduced. The first level conversion unit 25 can be implemented as a level shifter chip, a MOSFET bidirectional conversion circuit, a transistor conversion network, or a buffer driver. It can also be integrated into a single chip and co-packaged with the analog switch, or set up as an independent module on a system-level interface board. Its device materials are typically silicon-based CMOS, BiCMOS, or hybrid circuit structures composed of discrete semiconductor devices. For example, if the first voltage domain is 1.8V and the second voltage domain is 3.3V, this unit must ensure that the amplitude of the high-level boost meets the recognition threshold of the subsequent comparator or switching logic, while the low-level should be kept close to ground potential to avoid false triggering of the filter unit output or analog switch state drift. Its size and proportion can be designed according to the required driving capability. When implemented on a single board, the first level conversion unit can occupy an area of ​​several square millimeters to tens of square millimeters. Its input and output trace lengths should be as short as possible to reduce edge distortion and parasitic coupling. If an independent chip solution is adopted, its package size can be common specifications such as SOT, QFN or Ball Grid Array (BGA) packages, and the corresponding number of channels can be selected according to the signal frequency and number of channels of the fan control system.

[0111] When the system starts up, the PWM signal output by the CPLD is first split into two paths. One path enters the first level conversion unit, which boosts the high level of the PWM signal from the first voltage domain to the second voltage domain, while keeping the low level unchanged. The converted signal is then sent to the filtering unit, which filters the PWM signal that meets the requirements of the subsequent voltage domain and outputs a stable DC level. The other path is directly sent to the second input terminal of the analog switch. Since the analog switch integrates a level conversion function, the low-voltage high-level signal received at the second input terminal is also boosted to the second voltage domain and participates in the switching channel control. Thus, when the CPLD is working normally, the voltage detection link can maintain a normal flag signal based on the DC level output by the filtering unit, and the analog switch maintains the conduction state from the second input terminal to the output terminal, allowing the CPLD to directly drive the cooling system. However, when the CPLD experiences a PWM abnormality, the DC level output by the filtering unit exceeds the set range, the voltage detection circuit outputs a fault flag signal, and the analog switch switches to the first input terminal, allowing the backup PWM generator to take over the cooling system drive.

[0112] In this embodiment, since the first level conversion unit and the internal level conversion path of the analog switching switch jointly ensure the compatibility between different voltage domains, the system can take into account both signal detection and drive switching without increasing the output burden of the CPLD. This reduces the problems of misjudgment, missed judgment or ineffective channel conduction caused by level mismatch, thereby improving the interface adaptability and fault switching reliability of the redundant control circuit, and ensuring that the heat dissipation system can remain continuously controlled when the main control output is abnormal.

[0113] Next, combine Figures 4-7 This paper provides a detailed explanation of the specific implementation method of the redundant control circuit for the heat dissipation system for CPLD failure protection provided in the embodiments of this application, which addresses the three working states of CPLD: normal output of PWM signal, abnormal output of constant high-level signal, and abnormal output of constant low-level signal.

[0114] For ease of description, the output voltage of the filter unit is denoted as U0, the output voltage of the first comparator U1 is denoted as U01, the output voltage of the second comparator U2 is denoted as U02, the output voltage of the voltage detection circuit (i.e., the common junction of the first diode D1 and the second diode D2) is denoted as U03, and the output voltage of the second level conversion unit is denoted as U04.

[0115] Figure 4 This is a schematic diagram of the signal flow of the redundant control circuit for the heat dissipation system providing CPLD failure protection according to an embodiment of this application, under scenario one (CPLD output is always high). Figure 4As shown, when the CPLD's IO pin output is constantly high due to a fault such as hang-up, the CPLD_PWM signal is a constant 3.3V high level. After passing through the first level conversion unit (i.e., the 3V3_5V level conversion circuit), the output PWM_OUT is a constant 5V high level. After passing through the filtering unit, the output U0 of the filtering unit is still a constant 5V high level. At this time, the voltage U0 (5V) at the non-inverting input of the first comparator U1 is greater than the first reference voltage (4V) at its inverting input, and U01 outputs a 5V high level; the voltage (1V) at the non-inverting input of the second comparator U2 is less than the voltage U0 (5V) at its inverting input, and U02 outputs a 0V low level. Therefore, the first diode D1 is turned on, the second diode D2 is turned off, and U03 is pulled high to a 5V high level. The 5V signal is stepped down by the second level conversion unit (i.e., the 5V-3V3 level conversion circuit), and U04 outputs a 3.3V high level to the GPIO port of the BMC to report CPLD PWM signal abnormality information. At the same time, U03 (5V high level, i.e., fault flag signal) controls the analog switch to cut off the default source (NC terminal, i.e., CPLD signal path), connect the backup source (NO terminal, i.e., backup PWM generator signal path), and start the backup PWM generator to output the backup PWM signal, which then takes over the driving of the heat dissipation system.

[0116] Figure 5 This is a schematic diagram of the signal flow of the redundant control circuit for the heat dissipation system providing CPLD failure protection according to an embodiment of this application in scenario two (CPLD output is always low). Figure 5 As shown, when the CPLD_PWM signal is a constant 0V low level due to a fault such as a short circuit to ground on the IO pin, the signal remains 0V after passing through the first level conversion unit (PWM_OUT) and 0V after passing through the filter unit (U0). At this time, the voltage U0 (0V) at the non-inverting input of the first comparator U1 is less than the first reference voltage (4V) at its inverting input, so U01 outputs a 0V low level. The voltage (1V) at the non-inverting input of the second comparator U2 is greater than the voltage U0 (0V) at its inverting input, so U02 outputs a 5V high level. Therefore, the first diode D1 is cut off, the second diode D2 is turned on, and U03 is pulled high to a 5V high level. After being stepped down by the second level conversion unit, this 5V signal outputs a 3.3V high level to the GPIO port of the BMC to report CPLD PWM signal abnormality information. Similarly, U03 (5V high level, i.e. fault indicator signal) controls the analog switch to cut off the default source, connect the backup source, and start the backup PWM generator, which then takes over the driving of the heat dissipation system.

[0117] Figure 6This is a schematic diagram of the signal flow of the redundant control circuit for the heat dissipation system providing CPLD failure protection according to an embodiment of this application under scenario three (CPLD working normally). Figure 6 As shown, when the CPLD is working normally, CPLD_PWM is a normal pulse width modulation (PWM) pulse signal with a high level of 3.3V and a low level of 0V. After passing through the first level conversion unit, this signal outputs PWM_OUT as a PWM pulse signal with a high level of 5V and a low level of 0V. After being smoothed by the filtering unit, U0 is an approximate DC level in the range of 2V to 3V (the time constant of the RC filter circuit must be much larger than the PWM signal period, i.e., RC >> T). At this time, the voltage U0 (approximately 2.5V) at the non-inverting input terminal of the first comparator U1 is less than the first reference voltage (4V) at its inverting input terminal, and U01 outputs a low level of 0V; the voltage (1V) at the non-inverting input terminal of the second comparator U2 is less than the voltage U0 (approximately 2.5V) at its inverting input terminal, and U02 outputs a low level of 0V. Therefore, both the first diode D1 and the second diode D2 are cut off, and U03 is a low level of 0V (i.e., a normal flag signal). After the 0V signal passes through the second level conversion unit, U04 becomes a low level of 0V. The BMC receives this low level through the GPIO port and determines that the CPLD is working normally. At the same time, U03 (0V low level, i.e., normal indicator signal) controls the analog switch to maintain the default source (NC terminal, i.e., the second input terminal and output terminal are connected), and the CPLD continues to output PWM signals to drive the heat dissipation system.

[0118] Figure 7 This is a schematic diagram of the redundant control chip for the heat dissipation system providing CPLD failure protection according to an embodiment of this application, as shown below. Figure 7 As shown, the CPLD failure protection heat dissipation system redundancy control chip 70 integrates the aforementioned CPLD failure protection heat dissipation system redundancy control circuit 20.

[0119] By integrating the redundant control circuitry for the CPLD failure protection cooling system into a single chip, the detection of the CPLD output status, fault diagnosis, and drive switching can be centrally handled on the hardware side, thereby shortening the signal transmission path and reducing the complexity of external connections. The chip can directly integrate filtering, voltage detection, and switching control functions to quickly identify CPLD output anomalies and switch to a backup PWM generator to continue driving the cooling system in case of an anomaly. This ensures that the fan speed control link remains continuously controlled even after the main control source fails, thus reducing the risk of single-point failure in the cooling system. Therefore, it can improve the thermal stability and operational safety of servers and other equipment in high-reliability application scenarios.

[0120] Figure 8 This is a schematic diagram of the server structure provided in the embodiments of this application, such as... Figure 8As shown, the server includes: a CPLD for outputting PWM signals; a heat dissipation system for dissipating heat from the server; and a redundant control circuit for the heat dissipation system to protect against CPLD failure, wherein the redundant control circuit for the heat dissipation system to protect against CPLD failure is connected to the CPLD and the heat dissipation system respectively.

[0121] In the server, the CPLD handles the PWM signal output, and the cooling system adjusts the fan speed based on the PWM signal. A redundant control circuit for CPLD failure protection is connected between the CPLD and the cooling system. This circuit performs hardware-level identification of the CPLD output status and switches the control path in case of anomalies. Therefore, even when the CPLD output is continuously high, low, or distorted, the backup control source can still maintain controlled operation of the cooling system. This eliminates reliance on a single CPLD node for cooling control, reducing the risk of single-point failure due to the main speed control link failure. Consequently, it improves the server's cooling continuity, operational reliability, and device thermal safety under high load and long-term operation scenarios.

[0122] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A redundant control circuit for a heat dissipation system with CPLD failure protection, characterized in that, include: The system includes a filter unit, a voltage detection circuit, an analog switching switch, and a backup pulse width modulation (PWM) generator; among which: The filtering unit includes an input terminal and an output terminal. The input terminal is used to connect to the PWM output terminal of the complex programmable logic device (CPLD), and the output terminal is used to connect to the signal input terminal of the voltage detection circuit. The voltage detection circuit also includes a power supply terminal and an output terminal. The power supply terminal is used to connect to the power supply, and the output terminal is used to connect to the control terminal of the analog switching switch. The analog switching switch also includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to connect to the output terminal of the backup PWM generator, the second input terminal is used to connect to the PWM output terminal of the CPLD, and the output terminal is used to connect to the heat dissipation system. The filtering unit is used to filter the signal output by the CPLD and output a DC level. The voltage detection circuit is used to receive the DC level and output a fault flag signal when the DC level is greater than a first reference voltage or less than a second reference voltage; and output a normal flag signal when the DC level is greater than or equal to the second reference voltage and less than or equal to the first reference voltage, wherein the first reference voltage is greater than the second reference voltage. The analog switch is used to connect the first input and output terminals of the analog switch in response to the fault flag signal, so that the backup PWM generator drives the heat dissipation system; and to connect the second input and output terminals of the analog switch in response to the normal flag signal, so that the CPLD drives the heat dissipation system.

2. The CPLD fail-safe thermal system redundancy control circuit of claim 1, wherein, The voltage detection circuit includes: a first comparator, a second comparator, and a level combining circuit; The non-inverting input of the first comparator and the inverting input of the second comparator are connected together, and the common input is used as the signal input of the voltage detection circuit and is connected to the output of the filter unit; the inverting input of the first comparator is connected to the first reference voltage; the output of the first comparator is connected to the first input of the level combining circuit. The non-inverting input of the second comparator is connected to the second reference voltage; the output of the second comparator is connected to the second input of the level combining circuit. The power supply terminals of the first comparator and the second comparator are connected together, serving as the power supply terminal of the voltage detection circuit for connecting to the power supply. The output terminal of the level merging circuit serves as the output terminal of the voltage detection circuit and is used to connect to the control terminal of the analog switching switch.

3. The CPLD fail-safe thermal system redundancy control circuit of claim 2, wherein, The level merging circuit includes: a first diode and a second diode; The anode of the first diode serves as the first input terminal of the level merging circuit; The anode of the second diode serves as the second input terminal of the level merging circuit; The cathodes of the first diode and the second diode are connected in the same way, and the common connection terminal serves as the output terminal of the level merging circuit.

4. The CPLD fail-safe thermal system redundancy control circuit of any of claims 1-3, wherein, The backup PWM generator operates independently to continuously output a backup PWM signal; or, The backup PWM generator has an enable terminal, which is connected to the output terminal of the voltage detection circuit. The backup PWM generator is configured such that when the voltage detection circuit outputs a fault flag signal, the backup PWM generator is enabled and outputs a backup PWM signal; when the voltage detection circuit outputs a normal flag signal, the backup PWM generator is disabled.

5. The CPLD fail-safe thermal system redundancy control circuit of any of claims 1-3, wherein, The filtering unit includes: resistors and capacitors; One end of the resistor serves as the input terminal of the filter unit, which is used to connect to the PWM output terminal of the CPLD; the other end of the resistor is connected to one end of the capacitor, and the common connection terminal serves as the output terminal of the filter unit. The other end of the capacitor is grounded.

6. The CPLD fail-safe thermal system redundancy control circuit of any of claims 1-3, wherein, It also includes: a first level conversion unit; The input terminal of the first level conversion unit is used to connect to the PWM output terminal of the CPLD, and the output terminal is connected to the input terminal of the filter unit and the second input terminal of the analog switching switch, respectively. The first level conversion unit is used to convert the high level of the signal output by the CPLD from a first voltage domain to a second voltage domain, wherein the second voltage domain is higher than the first voltage domain; the low level of the signal output by the CPLD remains unchanged.

7. The CPLD fail-safe thermal system redundancy control circuit of claim 6, wherein, Also includes: Second level conversion unit; The input terminal of the second level conversion unit is used to connect to the output terminal of the voltage detection circuit; The output of the second level conversion unit is used to connect to the GPIO port of the BMC; The second level conversion unit is used to convert the high level of the signal output by the voltage detection circuit from the second voltage domain to the third voltage domain and then output it to the BMC. The third voltage domain is lower than the second voltage domain. The low level of the signal output by the voltage detection circuit remains unchanged.

8. The CPLD fail-safe thermal system redundancy control circuit of any of claims 1-3, wherein, The analog switching switch integrates a level conversion function, and the redundant control circuit of the heat dissipation system for CPLD failure protection further includes: a first level conversion unit; The input terminal of the first level conversion unit and the second input terminal of the analog switching switch are both used to connect to the PWM output terminal of the CPLD; The output of the first level conversion unit is connected to the input of the filtering unit; The first level conversion unit is used to convert the high level of the signal output by the CPLD from a first voltage domain to a second voltage domain, wherein the second voltage domain is higher than the first voltage domain; the low level of the signal output by the CPLD remains unchanged. The analog switching switch is also used to convert the high level of the signal output by the CPLD received at the second input terminal from the first voltage domain to the second voltage domain.

9. A CPLD fail-safe heat dissipation system redundancy control chip, characterized in that, The heat dissipation system has a redundant control circuit for CPLD failure protection as described in any one of claims 1 to 8.

10. A server, characterized by include: Complex programmable logic devices (CPLDs) are used to output pulse width modulation (PWM) signals. A cooling system for dissipating heat from the server; and, The redundant control circuit for heat dissipation system for CPLD failure protection as described in any one of claims 1 to 8, wherein the redundant control circuit for heat dissipation system for CPLD failure protection is connected to the CPLD and the heat dissipation system respectively.

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