Method for precise regulation of output voltage of linear voltage regulator based on feedback compensation

Abstract

This invention discloses a method for precise output voltage regulation of a linear regulator based on feedback compensation, specifically relating to the field of linear regulator technology. It involves real-time detection of the output current change rate, jump amplitude, and load range to generate transient and status signals. Based on these signals, the zeros and poles of the feedback compensation network are calculated and dynamically adjusted to match the frequency response. If the change rate exceeds a threshold, the slew rate and gate drive current are temporarily increased. Residual oscillations are then monitored; if present, a hysteresis threshold and correction current are calculated and introduced to suppress the oscillations. Simultaneously, the phase margin and gain margin across the entire frequency domain are monitored; if they fall below a preset threshold, the compensation network is reconfigured or the drive strategy is switched. This invention reduces transient drops and overshoot by dynamically adjusting the zeros and poles to match the load; further increases the slew rate and injects a nonlinear correction current to eliminate residual oscillations; and simultaneously monitors the full-frequency margin in real time and triggers reconfiguration or switching, achieving closed-loop self-healing and significantly improving the output voltage accuracy and stability under all operating conditions.

Description

Technical Field

[0001] This invention relates to the field of linear regulator technology, and more specifically, to a method for precise adjustment of the output voltage of a linear regulator based on feedback compensation. Background Technology

[0002] Linear regulators are widely used in power management systems for electronic devices due to their low output voltage ripple, low noise, and relatively simple circuit structure. In the design of linear regulators, feedback compensation networks are used to ensure the stability of the closed-loop system and achieve precise regulation of the output voltage. Common feedback compensation methods include Miller compensation, RC series compensation, and transconductance-capacitor compensation. Most of these schemes use compensation networks with fixed parameters, where the positions of the compensation zeros and poles are preset according to typical load conditions.

[0003] With the increasing demands for dynamic performance in modern electronic systems, the load conditions faced by linear regulators are becoming increasingly complex. Loads such as processor cores, RF power amplifiers, and high-speed digital circuits can experience operating currents that jump from microamps to amperes within sub-microseconds, with transition rates reaching several amperes per microsecond. Under such highly dynamic loads, if the frequency characteristics of the compensation network cannot adapt to the real-time load conditions, the loop's phase margin or gain margin may decrease, leading to undershoot, overshoot, or residual oscillations in the output voltage during transient processes. These transient disturbances can not only affect the correct operation of the load circuit but may also couple to other parts of the system through the power supply network, posing a challenge to overall reliability. Therefore, this invention proposes a method for precise adjustment of the output voltage of a linear regulator based on feedback compensation to address these problems. Summary of the Invention

[0004] To achieve the above objectives, the present invention provides the following technical solution: A method for precise adjustment of the output voltage of a linear regulator based on feedback compensation includes the following steps: Real-time detection of the output current change rate, output current jump amplitude, and load range of the linear regulator, generating load transient characteristic signals and load status signals; Based on the load transient characteristic signal and the load state signal, calculate the required compensation zero point position and compensation pole position, and dynamically adjust the zero point and pole of the feedback compensation network in the linear regulator to obtain the loop response after frequency matching. After dynamic adjustment is completed, if the output current change rate exceeds the preset change rate threshold, the slew rate of the error amplifier in the linear regulator is temporarily increased and the gate drive current of the power transistor is increased. Subsequently, the residual oscillation characteristics in the output voltage waveform of the linear regulator are monitored. If nonlinear oscillation or underdamped oscillation exists, the required hysteresis comparison threshold and nonlinear correction current value are calculated, and the hysteresis comparison threshold and nonlinear correction current value are introduced to suppress residual oscillation. Simultaneously, the loop phase margin and gain margin in the entire frequency domain are monitored in real time. When the loop phase margin or gain margin of any frequency band is lower than the preset stability threshold, the compensation network reconstruction or drive strategy switching is automatically triggered.

[0005] Real-time monitoring of the linear regulator's output current change rate, output current jump amplitude, and load range is achieved through the following methods: A lossless current sensing transistor is connected in series at the output of the linear regulator. The aspect ratio of this transistor is in a fixed ratio with that of the power transistor, and it is used to mirror the output current. The mirror current is passed through a high-speed transimpedance amplifier and two parallel differentiating circuits. The time constant of the first differentiating circuit is set to a short time constant to extract the output current change rate, and the time constant of the second differentiating circuit is set to a long time constant to extract the output current jump amplitude. Simultaneously, the mirror current is input into a load range discrimination network composed of multiple hysteresis comparators. The threshold of each hysteresis comparator is set to a different ratio of the maximum output current to distinguish between light load range, medium load range and heavy load range. The load transient characteristic signal includes the instantaneous value of the output current change rate and the instantaneous value of the output current jump amplitude, and the load status signal includes the current load range identifier.

[0006] In a preferred embodiment, calculating the required compensation zero-point and compensation pole positions further includes numerical calculations of at least one adjustable capacitor array and at least one adjustable resistor array in the feedback compensation network, specifically using the following steps: Obtain the instantaneous value of the output current change rate in the load transient characteristic signal, multiply the instantaneous value by the capacitance value at the output of the linear regulator, and then divide it by the transconductance value of the error amplifier to obtain the first intermediate result; Add the first intermediate result to the product of the output current jump amplitude and the load regulation rate, and add a preset positive base value to obtain the compensation depth factor, where the positive base value ensures that the compensation depth factor is always greater than zero. Obtain the load interval identifier from the load status signal. When the load interval identifier is a light load interval, multiply the compensation depth factor by the zero-point offset coefficient. The zero-point offset coefficient is equal to the ratio of the input resistance of the feedback network to the feedback resistance of the feedback network. When the load range is identified as a heavy load range, the compensation depth factor is multiplied by the pole offset coefficient, which is equal to the ratio of the power transistor gate capacitance to the error amplifier output capacitance. When the load range is identified as the medium load range, the compensation depth factor remains unchanged; The adjusted compensation depth factor is used as the scaling factor for the target zero frequency and the target pole frequency, respectively. The target zero frequency is equal to the reference zero frequency multiplied by the adjusted compensation depth factor, and the target pole frequency is equal to the reference pole frequency divided by the adjusted compensation depth factor. Based on the target zero frequency, the product of the target resistance value of the adjustable resistor array and the target capacitance value of the adjustable capacitor array is calculated. Based on the target pole frequency, the product of another adjustable resistor array and the adjustable capacitor array is calculated, such that the reciprocal of the product is equal to the target zero frequency and the target pole frequency, respectively. The location of the compensation zero is characterized by the frequency corresponding to the reciprocal of the product of the adjustable resistor array and the adjustable capacitor array, and the location of the compensation pole is characterized by the frequency corresponding to the reciprocal of another set of products.

[0007] In a preferred embodiment, after obtaining the target value of the product of the adjustable resistor array and the adjustable capacitor array, a successive approximation algorithm is used to adjust the switching states of the adjustable capacitor array and the adjustable resistor array so that the actual product approximates the target value. Close the highest bit switch of the capacitor array, compare the difference between the product of the current actual capacitance value and the current connected resistance value of the resistor array and the target product. If the actual product is less than the target product, keep the switch closed; otherwise, open the switch and close the next bit switch. Repeat this process for all bits until the lowest bit. The same algorithm is used for resistor arrays, but the comparison benchmark is changed to the difference between the product of the actual resistance value and the currently connected capacitor value and the target product. After each switch state transition, a preset waiting period is inserted, during which no new switching action is allowed to ensure that the voltage and current of the feedback compensation network are fully established.

[0008] In a preferred embodiment, the slew rate of the error amplifier in the linear regulator is temporarily increased and the gate drive current of the power transistor is increased, specifically by the following method: A transient boost current source is connected in parallel at the internal node of the error amplifier. The control terminal of the transient boost current source is connected to an edge-triggered monostable circuit. When the output current change rate exceeds a preset change rate threshold, the edge-triggered monostable circuit generates a pulse signal of preset width. This pulse signal turns on the transient boost current source, causing the tail current of the error amplifier to increase several times, thereby increasing the slew rate from the nominal value to several times the nominal value. The current-limiting resistor that was originally connected in series in the power transistor gate drive circuit is shorted by a bypass switch. This bypass switch is controlled by the same pulse signal. After the switch is turned on, the peak value of the gate drive current reaches several times the nominal drive current. The above boost action automatically returns to the nominal state after the pulse signal ends. During the recovery process, a soft release method is adopted, that is, the transient boost current source and bypass switch are gradually turned off through a low-pass filter with a preset time constant to avoid introducing new voltage disturbances during recovery.

[0009] In a preferred embodiment, the required hysteresis comparison threshold and nonlinear correction current value are calculated using the following steps: The output voltage waveform of the linear regulator is continuously sampled. The sampling frequency is set to a preset multiple of the unity-gain bandwidth of the feedback loop. The voltage values ​​of four consecutive sampling points are recorded and denoted as the first voltage, the second voltage, the third voltage, and the fourth voltage, respectively. The first difference is calculated as the second voltage minus the first voltage; the second difference is calculated as the third voltage minus the second voltage; and the third difference is calculated as the fourth voltage minus the third voltage. When the sum of the absolute values ​​of the first difference, the second difference, and the third difference is less than the preset lower limit, it is determined that there is no oscillation and no calculation is required; otherwise, when the product of the first difference and the second difference is negative and the product of the second difference and the third difference is negative, it is determined to be an underdamped oscillation. When the absolute values ​​of the first and second differences are both less than the absolute value of the third difference, it is determined to be a nonlinear oscillation. When it is determined to be an underdamped oscillation, the hysteresis comparison threshold is set to a preset ratio of the nominal output voltage value multiplied by the arithmetic mean of the absolute values ​​of the first and second differences. The nonlinear correction current value is set as the instantaneous value of the output current change rate multiplied by the hysteresis comparison threshold and then divided by the product of the preset ratio of the nominal output voltage value and the feedback network gain. When nonlinear oscillation is determined, the hysteresis comparison threshold is set to the absolute value of the third difference multiplied by another preset ratio of the nominal output voltage value, and the nonlinear correction current value is set to the hysteresis comparison threshold multiplied by the product of the power transistor transconductance and the load resistance and then divided by another preset ratio of the nominal output voltage value.

[0010] In a preferred embodiment, a hysteresis comparison threshold and a nonlinear correction current value are introduced to suppress residual oscillations, specifically: A hysteresis comparison threshold is applied to the toggle threshold of a hysteresis comparator connected in series between the output of the error amplifier and the gate of the power transistor. When the fluctuation amplitude of the output voltage is less than the hysteresis comparison threshold, the hysteresis comparator keeps the output unchanged and blocks the transmission of minute noise. When the fluctuation of the output voltage exceeds the hysteresis comparison threshold, the output of the hysteresis comparator flips and injects the nonlinear correction current value into the summing node of the error amplifier. The direction of this injected current is opposite to the direction of the output voltage deviation. A high-speed switch is connected in series on the nonlinear correction current injection path. This high-speed switch is turned on only during the first oscillation cycle after the residual oscillation is detected, and then automatically turned off to avoid introducing additional current consumption in steady state.

[0011] In a preferred embodiment, real-time monitoring of the loop phase margin and gain margin across the entire frequency domain specifically includes the following steps: A sinusoidal disturbance sequence of preset amplitude is injected into the input of the feedback network of the linear regulator. The sinusoidal disturbance sequence contains multiple different test frequencies, each of which is set to a different proportion of the unity-gain bandwidth of the feedback loop. The voltage response signal is synchronously sampled at the output of the linear regulator. The sampling window length is set to a preset multiple of the lowest test frequency period. The sampled voltage response signal is digitally phase-locked amplified to extract the amplitude attenuation and phase delay of the output voltage relative to the injected disturbance at each test frequency. Skip the frequency point when the output voltage response amplitude is less than the preset lower limit; otherwise, calculate the loop gain as equal to the injected disturbance amplitude divided by the output voltage response amplitude, and the loop phase as equal to the output voltage response phase minus the injected disturbance phase. Add 180 degrees to the loop phase value and take the absolute value to get the phase margin at that frequency. Take the reciprocal of the loop gain value to get the gain margin. Record multiple phase margin values ​​and multiple gain margin values ​​at each test frequency, take the minimum value as the current minimum phase margin and minimum gain margin in the full frequency domain, and compare it with the preset stability threshold.

[0012] In a preferred embodiment, the specific method for automatically triggering compensation network reconstruction or driving strategy switching is determined by the values ​​of the minimum phase margin and the minimum gain margin: The preset stability threshold includes two independent values: the phase margin threshold and the gain margin threshold. When the minimum phase margin is lower than the phase margin threshold and the minimum gain margin is higher than the gain margin threshold, the compensation network reconstruction is triggered. The reconstruction action is to increase the product of the adjustable resistor array and the adjustable capacitor array by a preset ratio, and at the same time decrease the product of another set of adjustable resistor arrays and the adjustable capacitor array by the same preset ratio, so as to introduce additional left half-plane zeros to improve the phase margin. When the minimum phase margin is equal to the phase margin threshold or the minimum gain margin is equal to the gain margin threshold, no reconstruction or switching action is triggered. When the minimum gain margin is lower than the gain margin threshold and the minimum phase margin is higher than the phase margin threshold, the drive strategy is switched. The switching action is to increase the static operating current of the error amplifier by a preset factor to reduce the output impedance and increase the gain margin. When the minimum phase margin is lower than the phase margin threshold and the minimum gain margin is lower than the gain margin threshold, the compensation network reconstruction and driving strategy switching are performed simultaneously, and the switched state is locked for a duration window. The length of the time window is equal to a preset multiple of the minimum test frequency period. Any new reconstruction or switching action is prohibited within the time window to avoid oscillating switching.

[0013] In a preferred embodiment, the preset rate of change threshold, the phase margin threshold, and the gain margin threshold are adjusted in real time according to the junction temperature of the linear regulator: A temperature-sensitive diode is integrated near the power transistor of the linear regulator, and the current junction temperature is obtained through the forward voltage drop of the diode; The preset rate of change threshold is adjusted according to the following rules: when the junction temperature is lower than or equal to the first temperature threshold, the preset rate of change threshold remains at the nominal value; when the junction temperature is higher than the first temperature threshold and lower than the second temperature threshold, the preset rate of change threshold is linearly reduced to a preset proportion of the nominal value; when the junction temperature is higher than or equal to the second temperature threshold, the preset rate of change threshold is reduced to another preset proportion of the nominal value. The phase margin threshold and the gain margin threshold are adjusted according to the following rules: when the junction temperature is lower than or equal to the first temperature threshold, both maintain their respective nominal values; when the junction temperature is higher than the first temperature threshold, both increase linearly to another preset proportion of their respective nominal values. The above adjustments are performed at the beginning of each monitoring period, and the adjusted thresholds are used for comparison and judgment within the current monitoring period.

[0014] The technical effects and advantages of this invention are as follows: This invention, by real-time detection of the output current change rate, output current jump amplitude, and load range, dynamically adjusts the zeros and poles of the feedback compensation network accordingly. This ensures that the loop response matches the current operating state even during high-rate load jumps, significantly reducing transient voltage drops and overshoot. Traditional fixed compensation methods maintain optimal performance only near a single load point. When the load current jumps from light to heavy load or in the opposite direction, a deviation occurs between the frequency characteristics of the compensation network and the load demand, causing a drop or spike in the output voltage of tens or even hundreds of millivolts at the moment of the jump. This invention, upon detecting a load jump, immediately calculates the required compensation zero and pole positions and adjusts the adjustable resistor and capacitor arrays to the target values, ensuring that the loop's phase margin remains within a safe range across the entire load range.

[0015] After completing dynamic zero-pole matching, this invention further temporarily increases the slew rate of the error amplifier and the gate drive current of the power transistor when the output current change rate exceeds a threshold. Subsequently, it monitors the residual oscillation characteristics in the output voltage waveform. When nonlinear or underdamped oscillations are identified, a hysteresis comparison threshold and a nonlinear correction current value are calculated and introduced, thus achieving multi-stage suppression from coarse to fine adjustment and effectively eliminating residual oscillation components in the output voltage. This invention adds a residual oscillation detection and correction stage after the drive boost. By continuously sampling the voltage waveform and calculating the difference value, it accurately distinguishes between underdamped and nonlinear oscillations and generates appropriate hysteresis comparison thresholds and nonlinear correction current values ​​respectively. Injecting this correction current in the opposite direction into the summing node of the error amplifier actively cancels out oscillation energy. Experimental data shows that after adopting this method, the output voltage can enter a completely stable state within fifty microseconds after the transient event ends, with no visible oscillation ripple, providing a cleaner power supply environment for modules sensitive to power supply noise, such as RF circuits and phase-locked loops.

[0016] This invention simultaneously monitors the loop phase margin and gain margin across the entire frequency domain in real time. When the loop phase margin falls below a phase margin threshold or the gain margin falls below a gain margin threshold in any frequency band, it automatically triggers compensation network reconstruction or drive strategy switching, forming a closed-loop self-healing capability. This effectively solves the hidden instability problems caused by temperature changes, device aging, or extreme load conditions. This invention injects a multi-frequency sinusoidal perturbation sequence into the feedback network input to accurately extract the gain and phase at each frequency point, calculating the current minimum phase margin and minimum gain margin across the entire frequency domain. When insufficient margin is detected, depending on which condition is not met, selective compensation network reconstruction (adjusting the resistor-capacitor array to move the zero-point position) or drive strategy switching (increasing the error amplifier's quiescent current to reduce output impedance) is performed, thereby pulling the margin back to a safe range. This active self-healing mechanism enables the linear regulator to withstand various environmental changes and parameter drift throughout its entire lifespan, significantly improving the system's long-term reliability and robustness. Attached Figure Description

[0017] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings; Figure 1 This is a schematic diagram of the method for precise adjustment of the output voltage of a linear regulator based on feedback compensation in this invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Reference Figure 1 The following examples were obtained: Example 1: A method for precise adjustment of the output voltage of a linear regulator based on feedback compensation, comprising the following steps: Real-time detection of the output current change rate, output current jump amplitude, and load range of the linear regulator, generating load transient characteristic signals and load status signals; Based on the load transient characteristic signal and the load state signal, calculate the required compensation zero point position and compensation pole position, and dynamically adjust the zero point and pole of the feedback compensation network in the linear regulator to obtain the loop response after frequency matching. After dynamic adjustment is completed, if the output current change rate exceeds the preset change rate threshold, the slew rate of the error amplifier in the linear regulator is temporarily increased and the gate drive current of the power transistor is increased. Subsequently, the residual oscillation characteristics in the output voltage waveform of the linear regulator are monitored. If nonlinear oscillation or underdamped oscillation exists, the required hysteresis comparison threshold and nonlinear correction current value are calculated, and the hysteresis comparison threshold and nonlinear correction current value are introduced to suppress residual oscillation. Simultaneously, the loop phase margin and gain margin in the entire frequency domain are monitored in real time. When the loop phase margin or gain margin of any frequency band is lower than the preset stability threshold, the compensation network reconstruction or drive strategy switching is automatically triggered.

[0020] Real-time monitoring of the linear regulator's output current change rate, output current jump amplitude, and load range is achieved through the following methods: A lossless current sensing transistor is connected in series at the output of the linear regulator. This lossless current sensing transistor is a metal-oxide-semiconductor field-effect transistor of the same type as the power transistor. Its source and drain are connected in series in the output path of the linear regulator, and its gate is connected to the same drive voltage signal as the gate of the power transistor. The aspect ratio of the transistor is in a fixed ratio with that of the power transistor. This fixed ratio is set according to the size of the power transistor and the required detection accuracy. The typical value range is 1:1000 to 1:10000. Therefore, the mirror current is one-thousandth to one-ten-thousandth of the output current, and the voltage drop across the sensing transistor is extremely low, which is approximately lossless.

[0021] The mirror current is first input into a high-speed transimpedance amplifier, which converts the mirror current into a voltage signal. Its bandwidth is set to be more than ten times the unity-gain bandwidth of the linear regulator feedback loop. For example, when the loop bandwidth is 500 kHz, the transimpedance amplifier bandwidth is set to 5 MHz. This bandwidth value is selected based on empirical values ​​to ensure that the high-frequency components of the current change rate are not attenuated. The voltage signal output from the transimpedance amplifier is simultaneously fed into two parallel differentiating circuits. The time constant of the first differentiating circuit is set to a short time constant, which is 0.1 microsecond to 0.5 microseconds. This short time constant is determined based on the fastest rise time of the load current change. For example, when the rise time of the load from complete off to rated current is 200 nanoseconds, the short time constant is set to 0.2 microseconds. The output of the differentiating circuit is a voltage signal proportional to the rate of change of the output current. The time constant of the second differentiating circuit is set to a long time constant, which is between fifty and two hundred microseconds. The time constant is set according to the duration of the output current jump amplitude. For example, when the duration after the load current jump is greater than one hundred microseconds, the time constant is set to eighty microseconds. The output of the differentiating circuit is a voltage signal proportional to the output current jump amplitude.

[0022] The mirrored current is simultaneously input into a load range discrimination network, which consists of two hysteresis comparators connected in series. The toggling threshold of each hysteresis comparator is set to a different percentage of the maximum output current. Specifically, the rising threshold of the first hysteresis comparator is set to 30% of the maximum output current, and the falling threshold is set to 25%. The rising threshold of the second hysteresis comparator is set to 70% of the maximum output current, and the falling threshold is set to 65%. These thresholds are selected based on the typical boundary points of light load, medium load, and heavy load in the experimental data. For example, when the maximum output current is 2 amps, the light load range is 0 to 0.6 amps, the medium load range is 0.6 amps to 1.4 amps, and the heavy load range is 1.4 amps to 2 amps. The hysteresis width is 5% of the threshold to avoid frequent switching when the load current fluctuates near the boundary.

[0023] The load transient characteristic signal includes the instantaneous values ​​of the output current change rate and the output current jump amplitude. The instantaneous value of the output current change rate is in amperes per second. For example, when the output current jumps from 10 milliamperes to 1 ampere in 200 nanoseconds, the change rate is 4.95 x 10^9 amperes per second. This value is directly obtained from the output of the first differentiating circuit after analog-to-digital conversion. The instantaneous value of the output current jump amplitude is in amperes. For example, if the jump amplitude in the same jump is 0.99 amperes, it is obtained from the output of the second differentiating circuit after peak hold circuit, representing the difference between the stable value after the jump and the value before the jump. The load status signal includes the current load range identifier, which is a two-bit binary code. "00" represents a light load range, "01" represents a medium load range, and "10" represents a heavy load range. This identifier is generated by combining the outputs of two hysteresis comparators.

[0024] The calculation of the required zero-point and pole-point locations for compensation further includes numerical calculations of at least one adjustable capacitor array and at least one adjustable resistor array in the feedback compensation network, specifically using the following steps: The instantaneous value of the output current change rate in the load transient characteristic signal is obtained. This instantaneous value is multiplied by the capacitance value at the output terminal of the linear regulator, and then divided by the transconductance value of the error amplifier to obtain the first intermediate result. The output capacitance value is the total capacitance from the output terminal to ground, including on-chip and off-chip capacitances. Its value is selected based on the load transient response index, typically ranging from one microfarad to one hundred microfarads. The transconductance value of the error amplifier is the transconductance of the input differential pair of the error amplifier, typically ranging from ten microsiemens to one hundred microsiemens. For example, if the output current change rate is one thousand amperes per second, the output capacitance is ten microfarads, and the transconductance is fifty microsiemens, the first intermediate result is one thousand multiplied by ten to the power of negative six and then divided by fifty multiplied by ten to the power of negative six, resulting in 0.2.

[0025] The compensation depth factor is obtained by adding the product of the output current jump amplitude and the load regulation rate to the first intermediate result, and then adding a preset positive base value. The positive base value ensures that the compensation depth factor is always greater than zero. The load regulation rate is defined as the change in output voltage when the output current changes by one ampere. It is given according to the design specifications of the linear regulator, with a typical value of 0.001 volts per ampere to 0.01 volts per ampere. The positive base value is set to between 0.01 and 0.1 based on experimental data. For example, when the output current jump amplitude is 0.5 amperes and the load regulation rate is 0.005 volts per ampere, the product is 0.0025. The first intermediate result is 0.2, so the sum is 0.2025. Adding the positive base value of 0.01, the compensation depth factor is 0.2125.

[0026] Obtain the load range identifier from the load status signal. When the load range identifier is a light load range, multiply the compensation depth factor by the zero-point offset coefficient. The zero-point offset coefficient is equal to the ratio of the feedback network input resistance to the feedback network feedback resistance. The feedback network input resistance is the resistance seen from the input terminal of the error amplifier, and the feedback network feedback resistance is the resistance in the output voltage divider branch. This ratio is determined based on the actual voltage division ratio, typically ranging from 0.1 to 10. For example, in the light load range, the compensation depth factor is 0.2125, and the zero-point offset coefficient is 2, so the product is 0.425.

[0027] When the load range is identified as a heavy load range, the compensation depth factor is multiplied by the pole offset coefficient, which is equal to the ratio of the power transistor's gate capacitance to the error amplifier's output capacitance. The power transistor's gate capacitance is the equivalent capacitance at the power transistor's input, typically ranging from 100 to 1000 picofarads. The error amplifier's output capacitance is the equivalent capacitance at the error amplifier's output, typically ranging from 10 to 50 picofarads. Therefore, the ratio is usually between 2 and 100. For example, in the heavy load range, the compensation depth factor is 0.2125, and the pole offset coefficient is 20, resulting in a product of 4.25. When the load range is identified as a medium load range, the compensation depth factor remains unchanged; for example, in the medium load range, the compensation depth factor is still 0.2125.

[0028] The adjusted compensation depth factor is used as the scaling factor for the target zero-frequency and target pole-frequency, respectively. The target zero-frequency is equal to the reference zero-frequency multiplied by the adjusted compensation depth factor, and the target pole-frequency is equal to the reference pole-frequency divided by the adjusted compensation depth factor. The reference zero-frequency and reference pole-frequency are determined based on the frequency compensation design of the linear regulator under typical load. The typical value of the reference zero-frequency is 10 kHz to 100 kHz, and the typical value of the reference pole-frequency is 100 kHz to 1 MHz. For example, if the adjusted compensation depth factor is 4.25, the target zero-frequency is 212.5 kHz when the reference zero-frequency is 50 kHz, and the target pole-frequency is 117.65 kHz when the reference pole-frequency is 500 kHz.

[0029] The product of the target resistance value of the adjustable resistor array and the target capacitance value of the adjustable capacitor array is calculated by inverse solving based on the target zero-point frequency. Similarly, the product of another adjustable resistor array and the adjustable capacitor array is calculated by inverse solving based on the target pole frequency, such that the reciprocals of these products are equal to the target zero-point frequency and the target pole frequency, respectively. The adjustable resistor array consists of multiple parallel or series resistor units, each with a resistance value equal to a power of two based on a reference resistance value. The same principle applies to the adjustable capacitor array; the reciprocal of the product is the frequency. For example, if the target zero-point frequency is 212.5 kHz, the product of the resistance and capacitance should be 1.477 microseconds. Therefore, the target resistance value of the adjustable resistor array is set to 10 kiloohms, and the target capacitance value of the adjustable capacitor array is set to 147.7 picofarads, with a product of 1.477 microseconds.

[0030] The zero-compensation location is characterized by the frequency corresponding to the reciprocal of the product of the adjustable resistor array and the adjustable capacitor array, while the pole-compensation location is characterized by the frequency corresponding to the reciprocal of another product. For example, if the reciprocal of the product of one set of adjustable resistors and adjustable capacitors is 212.5 kHz, then that frequency is the zero-compensation location, and the reciprocal of the other set of products is 117.65 kHz, which is the pole-compensation location.

[0031] After obtaining the target value of the product of the adjustable resistor array and the adjustable capacitor array, a successive approximation algorithm is used to adjust the switching states of the adjustable capacitor array and the adjustable resistor array, making the actual product approximate the target value. The adjustable capacitor array adopts a binary weighted structure, which contains multiple capacitor units. The capacitance value of each capacitor unit increases in powers of two. For example, the lowest-order capacitor unit has a reference capacitance value of 1 picofarad, the second lowest-order unit has 2 picofarads, the third unit has 4 picofarads, and so on, until the highest-order unit is 2^N minus one times the reference capacitance value, where N is the total number of bits in the array, typically six to ten bits. Each capacitor unit is connected in series with a switch. When the switch is closed, the capacitor unit is connected in parallel to the network; when the switch is open, the capacitor unit is disconnected. The adjustable resistor array also adopts a binary weighted structure, with each resistor unit connected in parallel or series. The reference resistance value is typically one ohm. The target product is obtained from the above calculation, for example, the target product is 1.477 microseconds.

[0032] The successive approximation algorithm starts from the most significant bit and simultaneously attempts various switching combinations of the capacitor array and resistor array. First, it closes the most significant bit of the capacitor array (corresponding to 128 picofarads) and the most significant bit of the resistor array (corresponding to 256 ohms). The current product is 128 picofarads multiplied by 256 ohms, equaling 0.03277 microseconds, which is less than the target product of 1.477 microseconds. Therefore, both switches remain closed. Next, it attempts the second most significant bit of the capacitor array (64 picofarads), maintaining the current value of the resistor array. The product is now (128 plus 64) multiplied by 256, equaling 0.04915 microseconds, still less than the target value. Therefore, the capacitor switch remains closed.

[0033] Continuing with the third most significant bit of the capacitor array (32 picofarads), the product is (128 + 64 + 32) multiplied by 256, equaling 0.05734 microseconds, still less than the target value, so it remains unchanged. After adding the fourth most significant bit (16 picofarads), the product is (128 + 64 + 32 + 16) multiplied by 256, equaling 0.06144 microseconds, still less than the target value, so it remains unchanged. Continuing with the addition of the fifth most significant bit (8 picofarads), the product is (128 + 64 + 32 + 16 + 8) multiplied by 256, equaling 0.06349 microseconds, less than the target value, so it remains unchanged. Adding the sixth most significant bit (4 picofarads), the product is (the sum of the first five terms plus 4) multiplied by 256, equaling 0.06452 microseconds, so it remains unchanged. Adding the seventh most significant bit (2 picofarads), the product is (the sum of the first six terms plus 2) multiplied by 256, equaling 0.06503 microseconds, so it remains unchanged. Adding the eighth high bit (one picofarad), the product is (the sum of the first seven terms plus one) multiplied by 256, which equals 0.06528 microseconds. This is still much less than the target value of 1.477 microseconds, indicating that adjusting the capacitor array alone cannot achieve the target, and the resistor array needs to be adjusted at the same time.

[0034] Keeping the current capacitor array fully open (i.e., all capacitor positions closed, total capacitance 255 picofarads), begin adjusting the resistor array. Close the second highest resistor position (128 ohms). The current product is 255 picofarads multiplied by (256 plus 128) ohms, which equals 255 multiplied by 384, equaling 0.09792 microseconds. This is still less than the target value, so maintain this position. Gradually close the lower resistor switches, calculating the difference between the product and the target value after each closure. For example, when all resistor positions are fully open, the total resistance is 511 ohms, and the product is 255 picofarads multiplied by 511 ohms, equaling 0.1303 microseconds, which is still far less than 1.477 microseconds. This indicates that relying solely on the current capacitor and resistor array ranges cannot achieve the target product. Therefore, it is necessary to adjust the reference resistance and capacitance values ​​(i.e., switch ranges), or to first fix the resistor array and then adjust the capacitor array.

[0035] In practice, range selection can be performed before successive approximations: if the target product is large, a larger reference resistance value (e.g., 10 kiloohms) and reference capacitance value (e.g., 10 picofarads) should be selected. Taking a reference resistance value of 10 kiloohms and a reference capacitance value of 10 picofarads as an example, a target product of 1.477 microseconds corresponds to a resistance value of 10 kiloohms and a capacitance value of 147.7 picofarads (product of 1.477 microseconds). In this case, the above algorithm is used: the capacitance array attempts bit by bit starting from the highest bit (1280 picofarads), comparing it with the target capacitance value of 147.7 picofarads; the resistance array attempts bit by bit starting from the highest bit (2560 ohms), comparing it with the target resistance value of 10 kiloohms. The specific comparison process is the same as the algorithm for independently adjusting the resistance and capacitance values ​​described in the text, but the comparison object is the actual product and the target product, rather than individual values. For example, if the highest bit switch of the capacitor array is closed, and the actual capacitance value is 1280 picofarads, the actual product is the actual capacitance value multiplied by the current resistance value. If the current resistance value is 10 kiloohms (using a reference value), the product is 12.8 microseconds, which is much larger than the target value. Therefore, the switch is opened, and the next bit is tried. Eventually, the product is brought closer to 1.477 microseconds.

[0036] Each switching state change alters the impedance characteristics of the feedback compensation network, causing a redistribution of voltage and current and generating a transient process. The time constant of this transient process is determined by the parasitic capacitance and resistance in the network. Therefore, a preset waiting period is inserted after each switch, during which no new switching action is allowed to ensure that the voltage and current of the feedback compensation network fully establish themselves at the new steady-state values. The length of the waiting period is determined based on the maximum time constant of the feedback compensation network, with typical values ​​set to 20 to 100 microseconds based on experimental data. For example, when the maximum resistance in the network is 10 kiloohms and the maximum parasitic capacitance is 100 picofarads, the time constant is 10 kiloohms multiplied by 100 picofarads, which equals 1 microsecond. The waiting period is set to ten times this time constant, i.e., 10 microseconds, to ensure that the voltage and current stabilize to within one-thousandth of their original values.

[0037] Temporarily increasing the slew rate of the error amplifier in the linear regulator and increasing the gate drive current of the power transistor is achieved through the following methods: A transient boost current source is connected in parallel at the internal node of the error amplifier. The control terminal of the transient boost current source is connected to an edge-triggered monostable circuit. When the output current change rate exceeds a preset change rate threshold, the edge-triggered monostable circuit generates a pulse signal of preset width. This pulse signal turns on the transient boost current source, causing the tail current of the error amplifier to increase several times, thereby increasing the slew rate from the nominal value to several times the nominal value. The internal node of an error amplifier refers to the common source node of the tail current sources or the common source node of the differential pair in the error amplifier. The voltage change rate of this node determines the slew rate of the error amplifier. The transient boost current source is an independent current source branch, and its output is connected in parallel to this internal node. The control terminal is connected to the output of an edge-triggered monostable circuit. The preset rate of change threshold is set according to the load characteristics driven by the linear regulator. Typical values ​​are taken from 0.5 amps per microsecond to 5 amps per microsecond based on experimental data. For example, when the load is a processor core, its current change rate can reach 2 amps per microsecond, so the threshold is set to 1 amp per microsecond.

[0038] When the output current change rate exceeds the threshold, the edge-triggered monostable circuit detects a rising or falling edge trigger signal and generates a pulse signal of a preset width. This pulse width is set based on the duration of the load transient, typically ranging from 100 to 500 nanoseconds based on experience. For example, if the rise time of the load transient is 200 nanoseconds, the pulse width is set to 250 nanoseconds. The pulse signal activates the transient boost current source, which provides an additional current several times the nominal tail current of the error amplifier. The value of this multiple is determined based on the required slew rate boost factor, typically ranging from three to ten times. For example, if the nominal tail current is 50 microamps, the transient boost current source provides 400 microamps, resulting in a total tail current of 450 microamps, increasing the slew rate from the nominal 1.5 V / µs to 13.5 V / µs.

[0039] The power transistor gate drive circuit consists of a driver stage amplifier, a series current-limiting resistor, and a power transistor gate capacitor. The current-limiting resistor is used to limit the output current of the driver stage to control the switching speed of the power transistor and prevent overshoot. This current-limiting resistor is connected in parallel with a bypass switch, which is a metal-oxide-semiconductor field-effect transistor or a transmission gate. Its control terminal is also connected to the output terminal of the edge-triggered monostable circuit, so it is controlled by the same pulse signal as the transient boost current source.

[0040] When the pulse signal is high, the bypass switch is turned on, shorting the current-limiting resistor. The output current of the driver stage is no longer limited by this resistor, and the peak value of the gate drive current is only constrained by the maximum current capability of the output transistor of the driver stage. This peak value reaches several times the nominal drive current. The value of several times is set according to the size of the power transistor and the load requirements. The typical range is two to five times. For example, if the nominal drive current is fifty milliamps, the peak current after shorting is one hundred and fifty milliamps. When the pulse signal ends, the bypass switch is turned off, the current-limiting resistor is reconnected in series in the circuit, and the gate drive current returns to the nominal value.

[0041] The above boost action automatically returns to the nominal state after the pulse signal ends. If the transient boost current source and bypass switch are directly and instantaneously turned off, a current surge will occur. This surge will introduce new voltage disturbances through the output node of the error amplifier or the gate of the power transistor, manifesting as glitches or secondary transient undershoots in the output voltage. Therefore, a soft-release method is used during the recovery process. Specifically, the soft-release method triggers a monostable delay circuit on the falling edge of the pulse signal. This delay circuit outputs a gradually changing control signal. This gradually changing control signal is applied to the turn-off control terminals of the transient boost current source and the bypass switch after passing through a low-pass filter with a preset time constant.

[0042] The preset time constant is set according to the sensitivity of the entire loop to disturbances. Typical values ​​are taken from one microsecond to ten microseconds based on experimental data. For example, the time constant of the low-pass filter is set to five microseconds, so that the transient boost current source gradually decreases from its maximum value to zero within five microseconds. At the same time, the on-resistance of the bypass switch gradually increases from near zero ohms to the nominal value of the current-limiting resistor. This gradual release method avoids sudden changes in current and voltage, thus not introducing new voltage disturbances.

[0043] The required hysteresis comparison threshold and nonlinear correction current value are calculated using the following steps: The output voltage waveform of the linear regulator is continuously sampled. The sampling frequency is set to a preset multiple of the unity-gain bandwidth of the feedback loop. This preset multiple is determined based on the Nyquist sampling theorem and the actual oscillation frequency detection requirements. A typical value is taken as ten to twenty times based on experimental data. For example, when the unity-gain bandwidth of the feedback loop is 500 kHz, a preset multiple of ten results in a sampling frequency of 5 MHz. The voltage values ​​of four consecutive sampling points are recorded and sequentially labeled as the first voltage, second voltage, third voltage, and fourth voltage. For example, if the sampled voltage values ​​are 1.998 V, 2.002 V, 1.996 V, and 2.004 V, then the first voltage is 1.998 V, the second voltage is 2.002 V, the third voltage is 1.996 V, and the fourth voltage is 2.004 V.

[0044] The first difference is calculated as the second voltage minus the first voltage. The second difference is calculated as the third voltage minus the second voltage. The third difference is calculated as the fourth voltage minus the third voltage. For example, 2.002 volts minus 1.998 volts gives a first difference of 0.004 volts. 1.996 volts minus 2.002 volts gives a second difference of -0.006 volts. 2.004 volts minus 1.996 volts gives a third difference of 0.008 volts.

[0045] When the sum of the absolute values ​​of the first, second, and third differences is less than a preset lower limit, no oscillation is determined, and no calculation is required. The preset lower limit is set based on the peak-to-peak value of the output voltage noise and the quantization error of the analog-to-digital converter. Typical values ​​are taken from 0.001 volt to 0.005 volt according to the equipment manual. For example, if the nominal output voltage is 2.5 volts and the peak-to-peak noise is 3 millivolts, the preset lower limit is set to 4 millivolts. If the sum of the absolute values ​​of the three differences is 0.38 millivolts, which is less than 4 millivolts, then no oscillation is determined. Otherwise, when the product of the first and second differences is negative and the product of the second and third differences is negative, it is determined to be underdamped oscillation. For example, 0.004 volts multiplied by -0.006 volts equals -0.000024 volts squared, which is negative; -0.006 volts multiplied by 0.008 volts equals -0.000048 volts squared, which is negative. If these conditions are met, it is determined to be underdamped oscillation.

[0046] When the absolute values ​​of the first and second differences are both less than the absolute value of the third difference, it is determined to be a nonlinear oscillation. For example, if the absolute values ​​of the first, second, and third differences are 0.004 volts, respectively, and the absolute value of the third difference is 0.008 volts, then the first two are both less than the third, and it is determined to be a nonlinear oscillation. Both criteria may be met simultaneously. In this case, the result of the nonlinear oscillation is given priority because the amplitude of the nonlinear oscillation is larger and poses a greater threat to system stability.

[0047] When an underdamped oscillation is detected, the hysteresis comparison threshold is set to a preset percentage of the nominal output voltage multiplied by the arithmetic mean of the absolute values ​​of the first and second differences. The preset percentage is based on experience and ranges from 0.5% to 2%. For example, if the nominal output voltage is 3.3 volts, the preset percentage is 1%, the first difference is 0.004 volts, the second difference is 0.006 volts, and the arithmetic mean is 0.005 volts. Therefore, the hysteresis comparison threshold is 3.3 volts multiplied by 1% and then multiplied by 0.005 volts, resulting in 0.000165 volts.

[0048] The nonlinear correction current value is set as the instantaneous value of the output current change rate multiplied by the hysteresis comparison threshold, then divided by the product of a preset ratio of the nominal output voltage value and the feedback network gain. The feedback network gain is the DC gain from the error amplifier to the output voltage, typically ranging from 1,000 to 10,000. For example, if the output current change rate is 1,000 amperes per second, the hysteresis comparison threshold is 0.000165 volts, the nominal output voltage is 3.3 volts, the preset ratio is 1%, which is 0.033, and the feedback network gain is 3,000, then the nonlinear correction current value is 1,000 multiplied by 0.000165 and then divided by the product of 0.033 and 3,000, resulting in 0.0000165 amperes, or 1.65 microamps.

[0049] When nonlinear oscillation is determined, the hysteresis comparison threshold is set to another preset percentage of the nominal output voltage value multiplied by the absolute value of the third difference. The other preset percentage is taken as 1% to 5% based on experimental data. For example, if the nominal output voltage is 3.3 volts, the other preset percentage is 3%, and the absolute value of the third difference is 0.008 volts, then the hysteresis comparison threshold is 3.3 volts multiplied by 3% and then multiplied by 0.008 volts, resulting in 0.000792 volts.

[0050] The nonlinear correction current value is set as another preset ratio of the hysteresis comparison threshold multiplied by the product of the power transistor's transconductance and the load resistance, divided by the nominal output voltage. The power transistor's transconductance is the control capability of the gate-source voltage on the drain current, typically ranging from one to ten Siemens. The load resistance is the equivalent resistance of the linear regulator's output terminal to ground, determined by the load current. For example, if the output current is one ampere, the output voltage is 3.3 volts, the load resistance is 3.3 ohms, and the power transistor's transconductance is five Siemens, then the product is 5.0 multiplied by 3.3, which equals 16.5. Assuming the hysteresis comparison threshold is 0.000792 volts, the nominal output voltage is 3.3 volts, and another preset ratio of 3 percent is 0.099, then the nonlinear correction current value is 0.000792 multiplied by 16.5 and then divided by 0.099, resulting in 0.132 milliamperes.

[0051] Hysteresis comparison threshold and nonlinear correction current value are introduced to suppress residual oscillations, specifically as follows: The hysteresis comparator has two different toggling thresholds, and the difference between the positive and negative toggling thresholds is the hysteresis comparison threshold. This hysteresis comparison threshold is applied to the toggling thresholds of the hysteresis comparator. Specifically, the positive threshold of the hysteresis comparator is set to the reference voltage plus half of the hysteresis comparison threshold, and the negative threshold is set to the reference voltage minus half of the hysteresis comparison threshold. The reference voltage is the quiescent operating voltage at the output of the error amplifier.

[0052] A hysteresis comparator is connected in series between the output of the error amplifier and the gate of the power transistor. This means the output signal of the error amplifier first passes through the hysteresis comparator before being fed into the gate drive circuit of the power transistor, filtering out minute fluctuations in the error amplifier's output signal. For example, if the hysteresis comparison threshold is 0.000165 volts and the reference voltage is 1.2 volts, then the positive threshold is 1.2000825 volts and the negative threshold is 1.1999175 volts.

[0053] When the output voltage fluctuation is less than the hysteresis comparison threshold, the hysteresis comparator maintains its output, blocking the transmission of minute noise. Specifically, the output voltage fluctuation refers to the peak value of the output voltage deviating from its nominal value. This fluctuation is transmitted to the output of the error amplifier through the feedback network. If the equivalent fluctuation is less than the hysteresis comparison threshold, the output of the hysteresis comparator remains in the current logic state and does not flip. Therefore, minute changes at the output of the error amplifier are blocked before reaching the gate of the power transistor by the hysteresis comparator, thus avoiding unnecessary switching of the power transistor caused by noise. For example, if the output voltage fluctuation is 0.0001 volts, after being amplified tenfold by the feedback network, the fluctuation reaching the output of the error amplifier is 1 millivolt. If the hysteresis comparison threshold is 0.165 millivolts, then 1 millivolt is greater than 0.165 millivolts, which should actually trigger a flip in this example. However, the case here is less: assuming the fluctuation is 0.00001 volts, after amplification it is 0.1 millivolts, which is less than 0.165 millivolts, so the hysteresis comparator maintains its output.

[0054] When the output voltage fluctuation exceeds the hysteresis comparison threshold, the hysteresis comparator output flips, injecting a nonlinear correction current value into the summing node of the error amplifier. The direction of this injected current is opposite to the direction of the output voltage deviation. Specifically, when the hysteresis comparator output flips, it generates a pulse or level transition. This transition signal controls a current source to send the nonlinear correction current value into the summing node of the error amplifier. The summing node is typically located at the source or output of the differential input pair transistors of the error amplifier, and is used to superimpose the correction signal.

[0055] The direction of the injected current is determined by the direction of the output voltage deviation: if the output voltage is higher than the nominal value (overshoot), the injected current pulls down the summing node voltage, reducing the error amplifier output, which in turn reduces the power transistor gate voltage, lowers the output current, and thus lowers the output voltage. If the output voltage is lower than the nominal value (undershoot), the injected current raises the summing node voltage, increasing the error amplifier output, increasing the power transistor gate voltage, and raising the output current, thus raising the output voltage. For example, if the output voltage overshoots to 3.4 volts, which is higher than the nominal value of 3.3 volts, the injected current will pull down the voltage, and the nonlinear correction current will be 0.132 mA, flowing from the summing node to ground.

[0056] A high-speed switch is connected in series in the nonlinear correction current injection path. This high-speed switch only turns on during the first oscillation cycle after residual oscillation is detected, and then automatically turns off to avoid introducing additional current consumption in steady state. The high-speed switch is a metal-oxide-semiconductor field-effect transistor or a transmission gate with an on-resistance of less than ten ohms and a switching speed of less than ten nanoseconds. The first oscillation cycle is determined by the frequency of the residual oscillation. For example, if the residual oscillation frequency is one megahertz, then the first oscillation cycle is one microsecond. The high-speed switch turns on at the beginning of this cycle and turns off at the end. The detection of residual oscillation is indicated by the moment when underdamped or nonlinear oscillation is determined, which is the starting point of the first oscillation cycle. During the high-speed switch's conduction, the nonlinear correction current is injected. After the switch is turned off, the injection path is disconnected. Therefore, in steady state without oscillation, the injection path is in a high-resistance state and does not consume additional quiescent current. For example, the high-speed switch turns off automatically after 0.8 microseconds. The control signal for the disconnection is generated by a monostable circuit, and its pulse width is set to the reciprocal of the residual oscillation frequency.

[0057] Real-time monitoring of loop phase margin and gain margin across the entire frequency domain includes the following steps: The feedback network input refers to the input node of the resistive voltage divider feedback network in a linear regulator, typically located at the inverting input of the error amplifier. A sinusoidal disturbance sequence of preset amplitude is injected. The preset amplitude is set based on the nominal output voltage value, with typical values ​​ranging from one-thousandth to five-thousandths of the nominal output voltage value based on experimental data. For example, when the output voltage is 3.3 volts, the injected amplitude is 3 millivolts. This sinusoidal disturbance sequence includes multiple different test frequencies, each set as a different proportion of the unity-gain bandwidth of the feedback loop. For example, when the unity-gain bandwidth is 500 kHz, the test frequencies are set to 0.1, 0.3, 0.5, 0.7, and 0.9 times, resulting in 50 kHz, 150 kHz, 250 kHz, 350 kHz, and 450 kHz. These proportions are selected empirically to cover the main frequency band of the loop.

[0058] The voltage response signal is synchronously sampled at the output of the linear regulator. The sampling window length is set to a preset multiple of the lowest test frequency period. The lowest test frequency is the first injection frequency, for example, 50 kHz, with a period of 20 microseconds. The preset multiple is determined based on the frequency resolution and settling time, with typical values ​​ranging from 10 to 50 according to the equipment manual. For example, a sampling window length of 20 times results in 400 microseconds. The sampled voltage response signal is then digitally locked in phase (PLC) amplified. PLC amplification is a synchronous demodulation technique that involves multiplying the sampled signal by a sine reference signal and a cosine reference signal at the same frequency as the injected disturbance, respectively. After low-pass filtering, the in-phase and quadrature components are extracted, allowing for the calculation of amplitude attenuation and phase delay. For example, if the injected disturbance frequency is 50 kHz, the amplitude attenuation after PLC amplification is 1:10, resulting in an output voltage response amplitude of 0.3 millivolts and a phase delay of -45 degrees.

[0059] When the output voltage response amplitude is less than a preset lower limit, the frequency point is skipped. The preset lower limit is set based on the noise floor and measurement accuracy of the analog-to-digital converter, with typical values ​​ranging from 10 microvolts to 50 microvolts based on statistical results. For example, if the response amplitude is 5 microvolts, which is less than the 20 microvolt threshold, the frequency point is skipped, and the loop gain and phase at that frequency point are not calculated. Otherwise, the loop gain is calculated as the injected disturbance amplitude divided by the output voltage response amplitude. For example, if the injected disturbance amplitude is 3 millivolts and the output voltage response amplitude is 0.3 millivolts, the loop gain is 10, which is expressed in decibels as 20 decibels. The loop phase is equal to the output voltage response phase minus the injected disturbance phase. For example, if the output voltage response phase is -45 degrees and the injected disturbance phase is 0 degrees, the loop phase is -45 degrees.

[0060] The phase margin at a given frequency is obtained by adding 180 degrees to the loop phase value and taking the absolute value. For example, -45 degrees plus 180 degrees equals 135 degrees, and taking the absolute value of 135 degrees gives the phase margin. The gain margin is obtained by taking the reciprocal of the loop gain value. For example, if the loop gain is 10, the reciprocal is 0.1. Note that phase margin is usually expressed in degrees, while gain margin is expressed as a linear multiple. It can also be converted to decibels, but the units must be consistent when comparing them.

[0061] Record multiple phase margin and gain margin values ​​at various test frequencies. For example, at a test frequency of 50 kHz, the phase margin is 135 degrees and the gain margin is 0.1; at 150 kHz, the phase margin is 98 degrees and the gain margin is 0.2; at 250 kHz, the phase margin is 52 degrees and the gain margin is 0.35; at 350 kHz, the phase margin is 30 degrees and the gain margin is 0.5; and at 450 kHz, the phase margin is 20 degrees and the gain margin is 0.7. Take the minimum value as the lowest phase margin and lowest gain margin in the current full-frequency domain, and compare this minimum value with the phase margin threshold and gain margin threshold, respectively. The phase margin threshold and gain margin threshold are set according to the stability and transient response requirements of the linear regulator.

[0062] The specific method for automatically triggering compensation network reconstruction or driving strategy switching is jointly determined by the values ​​of the minimum phase margin and the minimum gain margin: In this invention, the preset stability threshold is specifically divided into two independent values: the phase margin threshold and the gain margin threshold. The phase margin threshold is set according to the minimum stability margin required by the linear regulator, and the typical value is 45 degrees based on control theory experience. The gain margin threshold is set to a linear multiple of 0.16 (corresponding to -16 dB) based on engineering practice.

[0063] The minimum phase margin and minimum gain margin are derived from the aforementioned real-time monitoring results. For example, the monitoring shows that the minimum phase margin is 20 degrees and the minimum gain margin is 0.3. At this time, 20 degrees is lower than the phase margin threshold (45 degrees) and 0.3 is higher than the gain margin threshold (0.16), satisfying the first condition: the minimum phase margin is lower than the phase margin threshold and the minimum gain margin is higher than the gain margin threshold, thus triggering the reconstruction of the compensation network.

[0064] The specific action of the compensation network reconstruction is to increase the product of the adjustable resistor array and the adjustable capacitor array (corresponding to zeros) by a preset ratio, while simultaneously decreasing the product of another adjustable resistor array and the adjustable capacitor array (corresponding to poles) by the same preset ratio. This introduces additional left-half-plane zeros to improve the phase margin. The preset ratio is set according to the required phase boost, with typical values ​​ranging from 10% to 50% based on experimental data. For example, if the target resistance of the current adjustable resistor array is 10 kiloohms and the target capacitance of the adjustable capacitor array is 147.7 picofarads, and the preset ratio is 20%, then the increased resistance will be 12 kiloohms, and the decreased capacitance will be 118.16 picofarads. The product of this resistance and capacitance changes from 1.477 microseconds to 1.418 microseconds, and the reciprocal frequency increases from 0.676 MHz to 0.705 MHz. This newly added zero appears at a higher frequency, reducing the phase lag of the loop near the unity-gain bandwidth, thereby improving the phase margin. For example, the phase margin increases from 20 degrees to 48 degrees, exceeding the 45-degree threshold.

[0065] When the minimum gain margin is lower than the gain margin threshold and the minimum phase margin is higher than the phase margin threshold, the drive strategy switching is triggered. For example, if the monitored minimum gain margin is 0.1, lower than the gain margin threshold (0.16), and the minimum phase margin is 50 degrees, higher than the phase margin threshold (45 degrees), the specific action of the drive strategy switching is to increase the quiescent current of the error amplifier by a preset factor to reduce the output impedance and increase the gain margin. The preset factor is set according to the required gain margin increase, and a typical value is two to five times based on experience. For example, if the nominal quiescent current is 100 microamps, and the preset factor is three times, it will be increased to 300 microamps. The output impedance of the error amplifier is inversely proportional to the quiescent current. After increasing the current, the output impedance is reduced to one-third of its original value, which reduces the gain of the loop in the low-frequency range, thereby increasing the gain margin. For example, the gain margin is increased from 0.1 (-20 dB) to 0.25 (-12 dB), which is higher than the 0.16 threshold.

[0066] When the minimum phase margin is lower than the phase margin threshold and the minimum gain margin is lower than the gain margin threshold, for example, a minimum phase margin of 20 degrees (lower than the phase margin threshold of 45 degrees) and a minimum gain margin of 0.1 (lower than the gain margin threshold of 0.16), then compensation network reconstruction and drive strategy switching are performed simultaneously. When the minimum phase margin is equal to the phase margin threshold or the minimum gain margin is equal to the gain margin threshold, no reconstruction or switching action is triggered, and the current state is maintained. First, the resistor-capacitor array is adjusted according to a preset ratio, and the static operating current of the error amplifier is increased by a preset factor. The switched state is then locked for a duration window, the length of which is equal to a preset multiple of the minimum test frequency period. The minimum test frequency comes from the lowest frequency in the aforementioned sinusoidal perturbation sequence, for example, 50 kHz, with a period of 20 microseconds. The preset factor is set based on the waiting time required for remeasurement after loop stabilization; a typical value is 10 to 50 times based on experimental data. For example, if it is 20 times, the time window length is 400 microseconds. Within this time window, any new reconstruction or switching actions are prohibited to avoid repeated switching and oscillating switching due to the loop not being fully established. For example, within 400 microseconds, even if the margin is not yet met, no new actions are executed. A new round of monitoring and judgment will be carried out after the time window ends.

[0067] The preset rate of change threshold, phase margin threshold, and gain margin threshold are adjusted in real time based on the junction temperature of the linear regulator. The temperature-sensitive diode is a PN junction diode whose forward voltage drop is linearly negatively correlated with its junction temperature, with a typical temperature coefficient of -2 millivolts per degree Celsius. This diode is integrated near the power transistor of the linear regulator. The power transistor is the main heat source, so the junction temperature of the diode is basically the same as that of the power transistor. By measuring the forward voltage drop of the diode, the junction temperature corresponding to different voltage drops is pre-calibrated. For example, if the forward voltage drop is 0.7 volts at 25 degrees Celsius and 0.5 volts at 125 degrees Celsius, then the voltage drop decreases by 2 millivolts for every degree Celsius increase. The method for obtaining the current junction temperature value is as follows: inject a constant small current, typically 100 microamps, into the temperature-sensitive diode, measure the voltage across it, and then deduce the junction temperature from the calibration curve.

[0068] The preset rate of change threshold is adjusted based on the reliability requirements of the linear regulator at different temperatures: when the junction temperature is below or equal to the first temperature threshold, the preset rate of change threshold remains at the nominal value. The first temperature threshold is a safe temperature boundary, typically 85 degrees Celsius according to the equipment manual. The nominal value is set based on the most severe rate of change of load at room temperature, for example, one ampere per microsecond. When the junction temperature is above the first temperature threshold but below the second temperature threshold, the preset rate of change threshold linearly decreases to a preset percentage of the nominal value. The second temperature threshold is an extreme temperature boundary, typically 125 degrees Celsius based on the maximum allowable junction temperature of the power transistor.

[0069] The linear reduction method is as follows: when the junction temperature rises from 85 degrees Celsius to 125 degrees Celsius, the preset rate of change threshold decreases linearly from the nominal value of 1 ampere per microsecond to a preset percentage of the nominal value. This preset percentage is determined based on the safe switching speed of the power transistor at high temperatures, and a typical value is taken as 0.5 based on experimental data, i.e., 0.5 amperes per microsecond. For example, when the junction temperature is 105 degrees Celsius, the temperature has already risen by 20 degrees Celsius, and the total temperature rise range is 40 degrees Celsius. The proportionality coefficient is 20 divided by 40, which equals 0.5. Therefore, the preset rate of change threshold is the nominal value multiplied by (1 minus 0.5 multiplied by 0.5), which equals 0.75 amperes per microsecond. When the junction temperature is higher than or equal to a second temperature threshold, the preset rate of change threshold decreases to another preset percentage of the nominal value. This other preset percentage is set based on the protection requirements at extreme temperatures, and a typical value is taken as 0.3 based on statistical results, i.e., 0.3 amperes per microsecond.

[0070] The phase margin threshold and gain margin threshold are also adjusted in real time according to the junction temperature. When the junction temperature is lower than or equal to the first temperature threshold, both maintain their nominal values. For example, the nominal value of the phase margin threshold is 45 degrees, and the nominal value of the gain margin threshold is a linear multiple of 0.16 (corresponding to -16 dB). When the junction temperature is higher than the first temperature threshold, both increase linearly to another preset percentage of their respective nominal values. The reason for the increase is that at high temperatures, parameters such as the transconductance and output impedance of the power transistor and error amplifier degrade, and the loop gain decreases, requiring a higher stability margin to ensure robustness.

[0071] The linear increase occurs as follows: when the junction temperature rises from 85 degrees Celsius to 125 degrees Celsius, the phase margin threshold increases linearly from 45 degrees to 1.2 times the nominal value, i.e., 54 degrees; the gain margin threshold increases linearly from 0.16 to 1.2 times the nominal value, i.e., 0.192. For example, when the junction temperature is 105 degrees Celsius, the temperature has already increased by 20 degrees Celsius, and the total temperature increase range is 40 degrees Celsius. The scaling factor is 20 divided by 40, which equals 0.5. Therefore, the phase margin threshold is 45 multiplied by (1 plus 0.5 multiplied by 0.2), which equals 49.5 degrees, and the gain margin threshold is 0.16 multiplied by (1 plus 0.5 multiplied by 0.2), which equals 0.176. The above adjustments are performed at the beginning of each monitoring cycle, which is the cycle of the aforementioned real-time monitoring. For example, the threshold is updated once every 100 microseconds. The adjusted threshold is then used for comparison and judgment within the current monitoring cycle. For example, 49.5 degrees is used instead of 45 degrees for comparison with the measured phase margin, and 0.176 degrees is used instead of 0.16 degrees for comparison with the measured gain margin.

[0072] The above algorithms or formulas are all dimensionless and numerical calculations, and the results are obtained by software simulation based on a large amount of collected data to obtain the most recent real-world results. The preset parameters are set by those skilled in the art according to the actual situation.

[0073] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0074] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0075] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0076] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for accurate regulation of the output voltage of a feedback-compensated linear voltage regulator, characterized in that, Includes the following steps: Real-time detection of the output current change rate, output current jump amplitude, and load range of the linear regulator, generating load transient characteristic signals and load status signals; Based on the load transient characteristic signal and the load state signal, calculate the required compensation zero point position and compensation pole position, and dynamically adjust the zero point and pole of the feedback compensation network in the linear regulator to obtain the loop response after frequency matching. After dynamic adjustment is completed, if the output current change rate exceeds the preset change rate threshold, the slew rate of the error amplifier in the linear regulator is temporarily increased and the gate drive current of the power transistor is increased. Subsequently, the residual oscillation characteristics in the output voltage waveform of the linear regulator are monitored. If nonlinear oscillation or underdamped oscillation exists, the required hysteresis comparison threshold and nonlinear correction current value are calculated, and the hysteresis comparison threshold and nonlinear correction current value are introduced to suppress residual oscillation. Simultaneously, the loop phase margin and gain margin in the entire frequency domain are monitored in real time. When the loop phase margin or gain margin of any frequency band is lower than the preset stability threshold, the compensation network reconstruction or drive strategy switching is automatically triggered.

2. The method for accurate regulation of the output voltage of a feedback compensation based linear voltage regulator according to claim 1, wherein, Real-time monitoring of the linear regulator's output current change rate, output current jump amplitude, and load range is achieved through the following methods: A lossless current sensing transistor is connected in series at the output of the linear regulator. The aspect ratio of this transistor is in a fixed ratio with that of the power transistor, and it is used to mirror the output current. The mirror current is passed through a high-speed transimpedance amplifier and two parallel differentiating circuits. The time constant of the first differentiating circuit is set to a short time constant to extract the output current change rate, and the time constant of the second differentiating circuit is set to a long time constant to extract the output current jump amplitude. Simultaneously, the mirror current is input into a load range discrimination network composed of multiple hysteresis comparators. The threshold of each hysteresis comparator is set to a different ratio of the maximum output current to distinguish between light load range, medium load range and heavy load range. The load transient characteristic signal includes the instantaneous value of the output current change rate and the instantaneous value of the output current jump amplitude, and the load status signal includes the current load range identifier.

3. The method for accurate regulation of output voltage of feedback compensation based linear voltage regulator according to claim 1, wherein, The calculation of the required zero-point and pole-point locations for compensation further includes numerical calculations of at least one adjustable capacitor array and at least one adjustable resistor array in the feedback compensation network, specifically using the following steps: Obtain the instantaneous value of the output current change rate in the load transient characteristic signal, multiply the instantaneous value by the capacitance value at the output of the linear regulator, and then divide it by the transconductance value of the error amplifier to obtain the first intermediate result; The compensation depth factor is obtained based on the first intermediate result, the product of the output current jump amplitude and the load regulation rate, and the preset base value. Obtain the load interval identifier from the load status signal. When the load interval identifier is a light load interval, multiply the compensation depth factor by the zero-point offset coefficient. The zero-point offset coefficient is equal to the ratio of the input resistance of the feedback network to the feedback resistance of the feedback network. When the load range is identified as a heavy load range, the compensation depth factor is multiplied by the pole offset coefficient, which is equal to the ratio of the power transistor gate capacitance to the error amplifier output capacitance. When the load range is identified as the medium load range, the compensation depth factor remains unchanged; The adjusted compensation depth factor is used as the scaling factor for the target zero frequency and the target pole frequency, respectively. The target zero frequency is equal to the reference zero frequency multiplied by the adjusted compensation depth factor, and the target pole frequency is equal to the reference pole frequency divided by the adjusted compensation depth factor. Based on the target zero frequency, the product of the target resistance value of the adjustable resistor array and the target capacitance value of the adjustable capacitor array is calculated. Based on the target pole frequency, the product of another adjustable resistor array and the adjustable capacitor array is calculated, such that the reciprocal of the product is equal to the target zero frequency and the target pole frequency, respectively. The location of the compensation zero is characterized by the frequency corresponding to the reciprocal of the product of the adjustable resistor array and the adjustable capacitor array, and the location of the compensation pole is characterized by the frequency corresponding to the reciprocal of another set of products.

4. The method for accurate regulation of the output voltage of a feedback compensation based linear voltage regulator according to claim 3, wherein, After obtaining the target value of the product of the adjustable resistor array and the adjustable capacitor array, a successive approximation algorithm is used to adjust the switching states of the adjustable capacitor array and the adjustable resistor array so that the actual product approximates the target value. Close the highest bit switch of the capacitor array, compare the difference between the product of the current actual capacitance value and the current connected resistance value of the resistor array and the target product. If the actual product is less than the target product, keep the bit switch closed; otherwise, open the bit switch and close the next bit switch. Repeat this process for all bits until the lowest bit. The same algorithm is used for resistor arrays, but the comparison benchmark is changed to the difference between the product of the actual resistance value and the currently connected capacitor value and the target product. After each switch state transition, a preset waiting period is inserted, during which no new switching action is allowed to ensure that the voltage and current of the feedback compensation network are fully established.

5. The method for accurate regulation of output voltage of feedback compensation based linear voltage regulator according to claim 1, wherein, Temporarily increasing the slew rate of the error amplifier in the linear regulator and increasing the gate drive current of the power transistor is achieved through the following methods: A transient boost current source is connected in parallel at the internal node of the error amplifier. The control terminal of the transient boost current source is connected to an edge-triggered monostable circuit. When the output current change rate exceeds a preset change rate threshold, the edge-triggered monostable circuit generates a pulse signal of preset width. This pulse signal turns on the transient boost current source, causing the tail current of the error amplifier to increase several times, thereby increasing the slew rate from the nominal value to several times the nominal value. The current-limiting resistor that was originally connected in series in the power transistor gate drive circuit is shorted by a bypass switch. This bypass switch is controlled by the same pulse signal. After the switch is turned on, the peak value of the gate drive current reaches several times the nominal drive current. The above boost action automatically returns to the nominal state after the pulse signal ends. During the recovery process, a soft release method is adopted, that is, the transient boost current source and bypass switch are gradually turned off through a low-pass filter with a preset time constant to avoid introducing new voltage disturbances during recovery.

6. The method for accurate regulation of output voltage of feedback compensation based linear voltage regulator according to claim 1, wherein, The required hysteresis comparison threshold and nonlinear correction current value are calculated using the following steps: The output voltage waveform of the linear regulator is continuously sampled. The sampling frequency is set to a preset multiple of the unity-gain bandwidth of the feedback loop. The voltage values ​​of four consecutive sampling points are recorded and denoted as the first voltage, the second voltage, the third voltage, and the fourth voltage, respectively. The first difference is calculated as the second voltage minus the first voltage; the second difference is calculated as the third voltage minus the second voltage; and the third difference is calculated as the fourth voltage minus the third voltage. When the sum of the absolute values ​​of the first difference, the second difference, and the third difference is less than the preset lower limit, it is determined that there is no oscillation and no calculation is required; Otherwise, if the product of the first difference and the second difference is negative and the product of the second difference and the third difference is negative, it is determined to be an underdamped oscillation. When the absolute values ​​of the first and second differences are both less than the absolute value of the third difference, it is determined to be a nonlinear oscillation. When it is determined to be an underdamped oscillation, the hysteresis comparison threshold is set to a preset ratio of the nominal output voltage value multiplied by the arithmetic mean of the absolute values ​​of the first and second differences. The nonlinear correction current value is set as the instantaneous value of the output current change rate multiplied by the hysteresis comparison threshold and then divided by the product of the preset ratio of the nominal output voltage value and the feedback network gain. When nonlinear oscillation is determined, the hysteresis comparison threshold is set to the absolute value of the third difference multiplied by another preset ratio of the nominal output voltage value, and the nonlinear correction current value is set to the hysteresis comparison threshold multiplied by the product of the power transistor transconductance and the load resistance and then divided by another preset ratio of the nominal output voltage value.

7. The method for precise adjustment of the output voltage of a linear regulator based on feedback compensation according to claim 6, characterized in that, Hysteresis comparison threshold and nonlinear correction current value are introduced to suppress residual oscillations, specifically as follows: A hysteresis comparison threshold is applied to the toggle threshold of a hysteresis comparator connected in series between the output of the error amplifier and the gate of the power transistor. When the fluctuation amplitude of the output voltage is less than the hysteresis comparison threshold, the hysteresis comparator keeps the output unchanged and blocks the transmission of minute noise. When the fluctuation of the output voltage exceeds the hysteresis comparison threshold, the output of the hysteresis comparator flips and injects the nonlinear correction current value into the summing node of the error amplifier. The direction of this injected current is opposite to the direction of the output voltage deviation. A high-speed switch is connected in series on the nonlinear correction current injection path. This high-speed switch is turned on only during the first oscillation cycle after the residual oscillation is detected, and then automatically turned off to avoid introducing additional current consumption in steady state.

8. The method for accurate regulation of output voltage of feedback compensation based linear voltage regulator according to claim 1, wherein, Real-time monitoring of loop phase margin and gain margin across the entire frequency domain includes the following steps: A sinusoidal disturbance sequence of preset amplitude is injected into the input of the feedback network of the linear regulator. The sinusoidal disturbance sequence contains multiple different test frequencies, each of which is set to a different proportion of the unity-gain bandwidth of the feedback loop. The voltage response signal is synchronously sampled at the output of the linear regulator. The sampling window length is set to a preset multiple of the lowest test frequency period. The sampled voltage response signal is digitally phase-locked amplified to extract the amplitude attenuation and phase delay of the output voltage relative to the injected disturbance at each test frequency. Skip the frequency point when the output voltage response amplitude is less than the preset lower limit; otherwise, calculate the loop gain as equal to the injected disturbance amplitude divided by the output voltage response amplitude, and the loop phase as equal to the output voltage response phase minus the injected disturbance phase. Add 180 degrees to the loop phase value and take the absolute value to get the phase margin at that frequency. Take the reciprocal of the loop gain value to get the gain margin. Record multiple phase margin values ​​and multiple gain margin values ​​at each test frequency, take the minimum value as the current minimum phase margin and minimum gain margin in the full frequency domain, and compare it with the preset stability threshold.

9. The method for accurate regulation of the output voltage of a feedback compensation based linear voltage regulator according to claim 8, wherein, The specific method for automatically triggering compensation network reconstruction or driving strategy switching is jointly determined by the values ​​of the minimum phase margin and the minimum gain margin: The preset stability threshold includes two independent values: the phase margin threshold and the gain margin threshold. When the minimum phase margin is lower than the phase margin threshold and the minimum gain margin is higher than the gain margin threshold, the compensation network reconstruction is triggered. The reconstruction action is to increase the product of the adjustable resistor array and the adjustable capacitor array by a preset ratio, and at the same time decrease the product of another set of adjustable resistor arrays and the adjustable capacitor array by the same preset ratio, so as to introduce additional left half-plane zeros to improve the phase margin. When the minimum phase margin is equal to the phase margin threshold or the minimum gain margin is equal to the gain margin threshold, no reconstruction or switching action is triggered. When the minimum gain margin is lower than the gain margin threshold and the minimum phase margin is higher than the phase margin threshold, the drive strategy is switched. The switching action is to increase the static operating current of the error amplifier by a preset factor to reduce the output impedance and increase the gain margin. When the minimum phase margin is lower than the phase margin threshold and the minimum gain margin is lower than the gain margin threshold, the compensation network reconstruction and driving strategy switching are performed simultaneously, and the switched state is locked for a duration window. The length of the time window is equal to a preset multiple of the minimum test frequency period. Any new reconstruction or switching action is prohibited within the time window to avoid oscillating switching.

10. The method for accurate regulation of the output voltage of a feedback compensation based linear voltage regulator according to claim 9, wherein, The preset rate of change threshold, phase margin threshold, and gain margin threshold are adjusted in real time based on the junction temperature of the linear regulator. A temperature-sensitive diode is integrated near the power transistor of the linear regulator, and the current junction temperature is obtained through the forward voltage drop of the diode; The preset rate of change threshold is adjusted according to the following rules: when the junction temperature is lower than or equal to the first temperature threshold, the preset rate of change threshold remains at the nominal value; when the junction temperature is higher than the first temperature threshold and lower than the second temperature threshold, the preset rate of change threshold is linearly reduced to a preset proportion of the nominal value; when the junction temperature is higher than or equal to the second temperature threshold, the preset rate of change threshold is reduced to another preset proportion of the nominal value. The phase margin threshold and the gain margin threshold are adjusted according to the following rules: when the junction temperature is lower than or equal to the first temperature threshold, both maintain their respective nominal values; when the junction temperature is higher than the first temperature threshold, both increase linearly to another preset proportion of their respective nominal values. The above adjustments are performed at the beginning of each monitoring period, and the adjusted thresholds are used for comparison and judgment within the current monitoring period.

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