Low power CMOS voltage reference source based on DIBL and temperature combined compensation and compensation method

Abstract

The application discloses a low-power CMOS voltage reference source based on DIBL and temperature joint compensation and a compensation method, and belongs to the technical field of integrated circuits. The voltage reference source comprises a starting circuit module, a sub-threshold reference core module, a DIBL compensation current generator module, a temperature compensation current synthesis module and an output buffer module. The DIBL compensation current generator module utilizes the drain-induced barrier lowering effect of a short-channel MOS transistor to generate a first compensation current positively related to a power supply voltage; the temperature compensation current synthesis module utilizes an on-chip temperature sensor to generate a second compensation current related to temperature; and the two are weighted and summed to be injected into the reference core to realize joint optimization of line sensitivity and temperature coefficient. The application solves the technical problem that line sensitivity and temperature coefficient are difficult to be simultaneously optimized in the existing sub-threshold CMOS reference, and has the advantages of low power consumption, low line sensitivity, low temperature coefficient and full CMOS process compatibility.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-power CMOS voltage reference source based on DIBL and temperature joint compensation. Background Technology

[0002] With the rapid development of IoT technology, energy-constrained systems such as energy harvesting sensor nodes and wearable medical devices are placing stringent demands on the power consumption of integrated circuits. As a core module of analog and mixed-signal chips, the power consumption of the voltage reference source directly determines the system's standby endurance.

[0003] Traditional bandgap voltage references (BGRs) utilize the negative temperature characteristic of the base-emitter voltage (VBE) and the positive temperature characteristic of ΔVBE of a bipolar transistor to compensate for each other, generating a temperature-independent reference voltage. However, BGRs require a relatively large operating current (typically in the microamplitude range) to ensure the stability of the saturation current characteristics of the bipolar junction transistor (BJT), which limits their application in ultra-low power scenarios. Furthermore, BGRs require resistors, BJTs, and other components, necessitating additional mask layers or special structures in standard CMOS processes, increasing manufacturing costs and chip area.

[0004] As an alternative, all-CMOS voltage references have gained widespread attention in ultra-low-power applications. The classic subthreshold CMOS reference architecture utilizes picoampere-level current flowing through a diode-connected active load to generate a reference voltage. It leverages the negative temperature coefficient of the CMOS threshold voltage to compensate for the temperature coefficient, achieving extremely low power consumption without relying on BJTs and resistors. However, traditional subthreshold CMOS references suffer from the following technical problems:

[0005] (1) Poor linear sensitivity: In typical energy harvesting systems, the input power fluctuates significantly under different environments, and the power supply voltage may fluctuate within a wide range of 0.8V to 1.8V. Due to the drain-induced barrier lowering effect of short-channel MOSFETs, the bias current and reference output voltage will drift significantly with changes in the power supply voltage. In the prior art, the idea of ​​using the drain-induced barrier lowering (DIBL) effect itself for compensation has been proposed. However, the compensation current is only injected into a single node, which limits the compensation effect.

[0006] (2) Insufficient temperature coefficient optimization: Subthreshold CMOS references typically employ first-order temperature compensation (utilizing voltage difference). Positive temperature coefficient compensation (negative temperature coefficient), but after first-order compensation, approximately Temperature drift is a significant concern in applications such as high-precision sensors and RF transceivers. While some high-order curvature compensation schemes achieve excellent temperature drift performance, they require additional circuitry and consume more power, making them unsuitable for nanowatt-level power consumption scenarios. In existing technologies, DIBL compensation and temperature compensation are typically independent of each other, failing to achieve synergistic optimization between the two.

[0007] Therefore, how to simultaneously achieve ultra-low power consumption, low line sensitivity, and low temperature coefficient of a subthreshold CMOS reference is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0008] Purpose of the invention: To address the above problems, the purpose of this invention is to provide a low-power CMOS voltage reference source based on DIBL and temperature joint compensation.

[0009] Technical solution: The first aspect of this invention provides a low-power CMOS voltage reference source based on DIBL and temperature joint compensation, comprising:

[0010] Start the circuit module and connect it to the power supply voltage;

[0011] The subthreshold reference core module is connected to the startup circuit module and is used to generate the initial reference voltage after first-order temperature compensation.

[0012] The DIBL compensation current generator module is connected to the subthreshold reference core module and is used to generate a first compensation current that is positively correlated with the power supply voltage.

[0013] A temperature-compensated current synthesis module, whose input terminals are respectively connected to the DIBL compensation current generator module and the subthreshold reference core module, is used to generate a temperature-related second compensation current.

[0014] An output buffer module is connected to the output terminal of the temperature-compensated current synthesis module and is used to output a reference voltage.

[0015] Specifically, the first compensation current is injected simultaneously into the second and third nodes of the subthreshold reference core module through dual injection points, and the weighting coefficients injected into the second node and the third node are independently adjusted; the second compensation current is injected into the second node; the current injected into the second node by the first compensation current and the second compensation current at the second node are weighted and summed to generate a joint compensation current, which is used to jointly compensate the initial reference voltage.

[0016] Preferably, the DIBL compensation current generator module includes:

[0017] A short-channel NMOS transistor has its source grounded, its gate connected to a first bias voltage, and its drain connected to a first node. The channel length of the short-channel NMOS transistor is taken as the minimum dimension.

[0018] The first PMOS transistor has its source connected to the power supply voltage, and its drain and gate shorted together and connected to the first node, forming a diode connection structure.

[0019] The second PMOS transistor has its source connected to the power supply voltage, its gate connected to the first node, and its drain outputting the first compensation current.

[0020] The first PMOS transistor and the second PMOS transistor form a current mirror, and the width-to-length ratio of the first PMOS transistor and the second PMOS transistor is the same.

[0021] Preferably, the temperature-compensated current synthesis module includes:

[0022] The temperature detection unit includes an on-chip temperature sensor and a temperature comparator array, used to detect the chip temperature and output a temperature range code;

[0023] A programmable current synthesis network includes M parallel trimming current source units. Each trimming current source unit includes a trimming PMOS transistor and a switching transistor. The source of the trimming PMOS transistor is connected to the power supply voltage, and its drain is connected to the joint compensation current output node. Its gate is connected to the second bias voltage through the switching transistor. The control terminal of the switching transistor receives the corresponding bit of the temperature range code.

[0024] Among them, the channel width-to-length ratio of the M trimmed PMOS transistors is set according to binary weights, and the first... The aspect ratio of each trimmed PMOS transistor is the same as that of the 0th trimmed PMOS transistor. times, .

[0025] Preferably, the temperature comparator array includes a first comparator, a second comparator, and a third comparator. The negative input terminal of the first comparator is connected to a first reference voltage to set a low temperature threshold. The negative input terminal of the second comparator is connected to a second reference voltage to set a normal temperature threshold. The negative input terminal of the third comparator is connected to a third reference voltage to set a high temperature threshold. The outputs of the first comparator, the second comparator, and the third comparator are processed by decoding logic to generate the temperature range code.

[0026] Preferably, the subthreshold benchmark core module includes:

[0027] The first NMOS transistor has its source grounded and its drain shorted to its gate and connected to the second node; the first NMOS transistor is a native threshold device.

[0028] The second NMOS transistor has its source connected to the second node, its drain connected to the third node, and its gate connected to the third bias voltage; the second NMOS transistor is a standard threshold voltage device.

[0029] A bias current source is connected between the power supply voltage and the third node.

[0030] Preferably, the startup circuit module includes multiple PMOS and NMOS transistors connected in series. The output terminal of the startup circuit module is connected to the third node of the subthreshold reference core module. During power-on, startup current is injected into the reference core module. After the circuit is established, it is automatically turned off and enters a zero static power consumption state.

[0031] Preferably, the weighting coefficient of the injected second node is dynamically adjusted according to the temperature range code output by the temperature compensation current synthesis module, so as to realize the temperature adaptive adjustment of the DIBL compensation intensity.

[0032] Preferably, the rate of change of the first compensation current with respect to the power supply voltage is achieved by adjusting the channel length of the short-channel NMOS transistor and the first bias voltage.

[0033] Preferably, the voltage reference source further includes a process corner detection module, which includes a ring oscillator and a frequency counter for detecting the current process corner and adjusting the current mirror ratio of the DIBL compensation current generator module and the weighting coefficient of the temperature compensation current synthesis module according to the detection result.

[0034] A second aspect of the present invention provides a method for joint compensation of a low-power CMOS voltage reference source based on DIBL and temperature joint compensation, comprising the following steps:

[0035] Step 1: The subthreshold reference core module generates an initial reference voltage after first-order temperature compensation using the threshold voltage difference between the first NMOS transistor and the second NMOS transistor.

[0036] Step 2: The DIBL compensation current generator module utilizes the drain-induced barrier reduction effect of the short-channel MOSFET to detect changes in the power supply voltage and generate a first compensation current that is positively correlated with the power supply voltage.

[0037] Step 3: The temperature detection unit in the temperature compensation current synthesis module detects the chip temperature and compares the temperature with a preset threshold through a temperature comparator array to generate a temperature range code.

[0038] Step 4: The programmable current synthesis network, based on the temperature range encoding, turns on the corresponding weighted adjustment current source units to generate a second compensation current related to temperature.

[0039] Step 5: Divide the first compensation current into two paths and inject them into the third node and the second node respectively with the first weighting coefficient and the second weighting coefficient; at the same time, inject the second compensation current into the second node;

[0040] Step 6: At the second node, the second path of the first compensation current and the second compensation current are weighted and summed to generate a joint compensation current, which is used to jointly compensate the initial reference voltage and output the compensated reference voltage.

[0041] Beneficial effects: Compared with the prior art, the significant advantages of this invention are:

[0042] 1. Ultra-low power consumption: The entire circuit of the voltage reference source of this invention operates in the subthreshold region, with no resistors, no capacitors, and no bipolar transistors. The typical static power consumption is 68nW, which is more than two orders of magnitude lower than that of traditional bandgap references, meeting the long-term battery power requirements of IoT devices.

[0043] 2. Low line sensitivity: This invention utilizes a dual-injection-point DIBL compensation architecture to simultaneously inject DIBL compensation current with different weights into the bias node and output node, achieving a sensitivity of less than 0.6V within a power supply voltage range of 0.6V to 1.8V. The linear sensitivity, compared to the uncompensated scheme (greater than), is significantly higher. This represents an improvement of more than an order of magnitude. Specifically, within a power supply voltage range of 1.4V to 2.0V, the line sensitivity of this invention can reach [value missing]. .

[0044] 3. Low temperature coefficient: This invention achieves low temperature coefficient across the entire temperature range through joint optimization of segmented temperature compensation and DIBL compensation. The internal temperature coefficient is controlled within Within this range, the problem of large temperature drift in traditional subthreshold CMOS reference temperatures has been solved.

[0045] 4. Full CMOS process compatibility: This invention uses only MOSFETs in standard CMOS processes, eliminating the need for resistors, capacitors, BJTs, and depletion-mode devices. It is compatible with all standard CMOS processes of 0.18um and above, reducing manufacturing costs and chip area.

[0046] 5. No adjustment required: The parameters of DIBL compensation and segmented temperature compensation in this invention are fixed through circuit design and do not require factory adjustment, thus reducing testing costs.

[0047] 6. Fast Start-up: In this invention, the startup circuit automatically shuts off after the circuit is established, without consuming static power consumption, while ensuring fast power-on startup with a setup time of less than 10μs. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the overall circuit structure of the voltage reference source in Example 1;

[0049] Figure 2 Detailed circuit diagram of the DIBL compensated current generator module;

[0050] Figure 3 Detailed circuit diagram of the temperature-compensated current synthesis module;

[0051] Figure 4 This is a schematic diagram of a dual-injection-point compensation architecture;

[0052] Figure 5 This is a comparison curve of the reference output voltage-temperature characteristics between the embodiments of the present invention and the prior art. Detailed Implementation

[0053] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit the scope of the invention. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the embodiments of the present invention, and not all structures.

[0054] In the following description, specific details such as target system architecture and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.

[0055] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0056] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0057] Furthermore, in the description of this application and the appended claims, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0058] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include the target features, structures, or characteristics described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0059] Example 1

[0060] like Figure 1 As shown, this embodiment provides a low-power CMOS voltage reference source based on DIBL and temperature joint compensation, including a startup circuit module 100, a subthreshold reference core module 200, a DIBL compensation current generator module 300, a temperature compensation current synthesis module 400, and an output buffer module 500.

[0061] Specifically, the startup circuit module 100 consists of a PMOS transistor MP10 and seven NMOS transistors, denoted as MN10~MN16. The source of PMOS transistor MP10 is connected to the power supply voltage VDD, its drain is connected to node START, and its gate is connected to node DET. The drain and gate of NMOS transistor MN10 are shorted and connected to node START, with its source grounded. The drain of NMOS transistor MN11 is connected to node DET, its gate is connected to node START, and its source is grounded. The drain of NMOS transistor MN12 is connected to node DET, its gate is connected to the third node B (an internal node of the reference core), and its source is grounded. NMOS transistors MN13, MN14, MN15, and MN16 form a bias chain connected in series with diodes. The source of NMOS transistor MN13 is grounded, and the drain and gate of NMOS transistor MN16 are shorted and connected to node START. The transistors are connected in series.

[0062] Specifically, the subthreshold reference core module 200 includes a first NMOS transistor MN1, a second NMOS transistor MN2, and a bias current source. Among them, the first NMOS transistor MN1 is a native threshold NMOS transistor, and its channel width / length are as follows: The source of the first NMOS transistor MN1 is grounded to GND, and its drain is shorted to the gate and connected to the second node A. The second NMOS transistor MN2 is a standard threshold NMOS transistor. The source of the second NMOS transistor MN2 is connected to the second node A, the drain is connected to the third node B, and the gate is connected to the bias voltage. The typical value is 0.3V. Bias current source. The positive terminal is connected to the power supply voltage VDD, and the negative terminal is connected to the third node B, with a typical value of 10nA.

[0063] like Figure 2 As shown, the DIBL compensated current generator module 300 includes a short-channel NMOS transistor MD1, a first PMOS current mirror MP1, and a second PMOS current mirror MP2. The parameters of the short-channel NMOS transistor MD1 are set as follows: (Ditch length) (To minimize the size and enhance the DIBL effect), the source and substrate of the short-channel NMOS transistor MD1 are grounded to GND, and the gate is connected to the first bias voltage. (Typical value 0.4V), drain connected to first node D. The parameters of the first PMOS current mirror MP1 are set as follows: The source of the first PMOS current mirror is connected to the power supply voltage VDD, and its drain and gate are shorted and connected to the first node D. The parameters of the second PMOS current mirror MP2 are set as follows: W / L = 2μm / 0.5μm. Its source is connected to the power supply voltage VDD, its gate is connected to the first node D, and its drain is the compensation current output terminal. .

[0064] like Figure 3 As shown, the temperature-compensated current synthesis module 400 includes a temperature detection unit and a programmable current synthesis network. The temperature detection unit includes an on-chip temperature sensor TEMP, a temperature comparator array, and a temperature range decoder. The temperature comparator array includes three comparators, denoted as COMP1 to COMP3. The on-chip temperature sensor TEMP is used to generate a voltage signal proportional to the temperature. Sensitivity approximately The first comparator, COMP1, has a voltage signal connected to its positive input. The negative input terminal is connected to the first reference voltage. (Corresponds to -20℃). The second comparator COMP2 has a voltage signal connected to its positive input. The negative input terminal is connected to the second reference voltage. (Corresponding to 40℃). The third comparator COMP3 has a voltage signal connected to its positive input. The negative input terminal is connected to the third reference voltage. (Corresponding to 100℃). The three input terminals of the temperature range decoder receive the output signals of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3, respectively. After combinational logic decoding, a 4-bit temperature range code T_code[3:0] is generated (T_code[3] is the most significant bit, and T_code[0] is the least significant bit). The four output terminals T_code[0]~T_code[3] of the temperature range decoder are connected to the control terminals of the switching transistors SW0~SW3, respectively, to control the conduction and cutoff of the corresponding trimmed PMOS transistors.

[0065] The programmable current synthesis network consists of four parallel trimmer PMOS transistors, denoted as... And the corresponding switching transistors, denoted as SW0~SW3.

[0066] First adjustment PMOS transistor The parameters are set as follows: Its source is connected to the power supply voltage VDD, its drain is connected to the fourth node E, and its gate is connected to the second bias voltage through the first switch SW0. .

[0067] Second adjustment PMOS transistor The parameters are set as follows: W / L = 1.0μm / 1μm, its source is connected to the power supply voltage VDD, its drain is connected to the fourth node E, and its gate is connected to the second bias voltage through the second switch SW1. .

[0068] Third adjustment PMOS transistor The parameters are set as follows: Its source is connected to the power supply voltage VDD, its drain is connected to the fourth node E, and its gate is connected to the second bias voltage through the third switch SW2. .

[0069] Fourth adjustment PMOS transistor The parameters are set as follows: Its source is connected to the power supply voltage VDD, its drain is connected to the fourth node E, and its gate is connected to the second bias voltage through the fourth switch SW3. .

[0070] The control terminals of the switching transistors SW0~SW3 are respectively connected to the temperature range codes T_code[0]~T_code[3] (after decoding logic processing).

[0071] The output buffer module 500 is a unity-gain buffer, consisting of a differential input stage and an output stage. The input terminal of the output buffer module 500 is connected to the second node A, and the output terminal is connected to the reference voltage output. .

[0072] First compensation current The output from the DIBL compensated current generator module 300 is split into two paths: the first path passes through a current mirror (ratio). Injected into the third node B; the second path passes through the current mirror (scale). Inject into the second node A.

[0073] Temperature compensation current After output from module 400, the current is directly injected into the second node A. The second node A simultaneously receives the second current from DIBL. and temperature compensation current This will lead to joint compensation.

[0074] The working principle of the low-power CMOS voltage reference source described in this example includes the following process:

[0075] (1) Startup process:

[0076] Upon power-up, the second node A (reference voltage) is 0V. NMOS transistor MN12 detects the 0V voltage at second node A and is in the off state; node DET is pulled low to GND through NMOS transistor MN11. The gate of PMOS transistor MP10 is pulled low, and MP10 turns on, injecting current into node START. This current flows to GND through PMOS transistor MN10, generating a bias voltage that drives the reference core module to its stable operating point.

[0077] Once the reference voltage is established, the voltage at the second node A rises to the target value (approximately 0.538V), the NMOS transistor MN12 turns on, pulling node DET high to the power supply voltage VDD, turning off the PMOS transistor MP10, ending the startup process, and the startup circuit enters a zero static power consumption state.

[0078] (2) Work on the subthreshold benchmark core:

[0079] The first NMOS transistor MN1 operates in the subthreshold region, and its gate-source voltage... It has a negative temperature coefficient, typically around 0.2V. The second NMOS transistor MN2 also operates in the subthreshold region, with a gate-source voltage of... Because the threshold voltage of the second NMOS transistor MN2 is different from that of the first NMOS transistor MN1 (MN1 has a native threshold voltage of approximately 0.1V, while MN2 has a standard threshold voltage of approximately 0.4V), the gate-source voltage difference between the two is significant. It has a positive temperature coefficient.

[0080] Reference output voltage at the second node A It can be given by the following expression:

[0081] ,

[0082] in, This is the equivalent resistance of the second NMOS transistor MN2.

[0083] When the dimensions and bias conditions of the first NMOS transistor MN1 and the second NMOS transistor MN2 are designed appropriately... negative temperature coefficient and The positive temperature coefficients compensate for each other, achieving first-order temperature compensation.

[0084] (3) Generation of DIBL compensation current:

[0085] As the power supply voltage VDD increases, the voltage at node D in the first node also increases. Due to the DIBL effect, the threshold voltage of the short-channel NMOS transistor MD1... It decreases as the drain voltage increases. At the first bias voltage... Below, the drain current of MD1 The formula for increasing is as follows:

[0086] ,

[0087] in, Indicates electron mobility, This represents the capacitance per unit area of ​​the gate oxide layer.

[0088] Drain current The increment is mirrored through MP1-MP2 current mirrors (1:1 ratio) to obtain a compensation current I that is positively correlated with the power supply voltage VDD. DIBL .

[0089] (4) Generation of temperature compensation current:

[0090] The temperature sensor TEMP generates a voltage signal, represented as:

[0091] , ,

[0092] in, express, Represents absolute temperature. Boltzmann constant.

[0093] The comparator array divides the temperature into four intervals, and the output parameters for each interval are shown in Table 1.

[0094] Table 1

[0095] The temperature compensation current I is generated by switching on different weighted adjustment tubes in different temperature ranges. TEMP for:

[0096] ,

[0097] in, Indicates the total equivalent resistance. The first temperature range code Bit binary value, G represents the transconductance of each adjustment tube. mi It is proportional to the W / L of the adjustment tube, thereby achieving segmented compensation of temperature characteristics.

[0098] (5) Joint compensation:

[0099] Combination Figure 4 As shown, the DIBL compensation current I DIBL The current injected into the third node B and the second node A is injected through two current mirrors with different weights: the current injected into the third node B is... I DIBL This is used to compensate for the dependence of the bias current on the power supply voltage and stabilize the operating point of the second NMOS transistor MN2; the current injected into the second node A is I DIBL This directly compensates for the power supply dependence of the output voltage node. Temperature compensation current I TEMP Inject into the second node A, and I DIBL Weighted summation yields the joint compensation current I. COMP , represented as:

[0100] ,

[0101] The joint compensation current is superimposed on the main reference current at the second node A to jointly compensate for VREF. The weighting coefficients at the two injection points... and It can be designed independently to achieve two-dimensional optimization of line sensitivity; at the same time, temperature compensation corrects the temperature coefficient in stages. The three functions work together to ensure that the reference voltage remains highly stable over a wide power supply voltage and full temperature range.

[0102] In one example, the power supply voltage VDD ranges from 0.8V to 1.8V, and the first bias voltage... Set to 0.4V, the bias voltage of the adjustment tube is also the second bias voltage. Set to 0.5V, reference core bias current Set to 10nA, output reference voltage Set to 0.538V, the typical quiescent power consumption is 68nW, and the line sensitivity is less than... Temperature coefficient less than Full temperature range This embodiment improves line sensitivity by combining DIBL compensation with segmented temperature compensation in a subthreshold CMOS reference core. The line sensitivity is increased from greater than [value missing] through dual-injection-point DIBL compensation. Reduced to less than It also improved the temperature coefficient; segmented temperature compensation reduced the temperature coefficient from greater than [previous value]. Reduced to less than The two work together to achieve Pareto optimality in overall performance.

[0103] To verify the improvement effect of the proposed joint compensation architecture on temperature characteristics, temperature sweep simulations were performed on the reference output voltage under four different configurations, with a temperature range of -40℃ to 130℃. The simulation conditions were a temperature of 27℃ and a power supply voltage VDD scanned from 0.8V to 1.8V. The simulation results are as follows: Figure 5 As shown.

[0104] The uncompensated subthreshold reference core (curve A) output exhibits a significant negative temperature coefficient, with the output voltage dropping from approximately 0.59V to 0.48V across the entire temperature range, representing a temperature drift of approximately [missing value]. When only DIBL compensation (curve B) is added, since DIBL compensation mainly optimizes line sensitivity, its improvement on temperature characteristics is limited, and the temperature drift is approximately [value missing]. When only piecewise temperature compensation (curve C) is added, the temperature drift is improved to approximately [value missing]. However, the output level is too low and the line sensitivity is poor.

[0105] After adopting the combined compensation scheme of this invention (curve D), the output voltage exhibits a flat parabolic shape across the entire temperature range, with a temperature drift of less than 6%. The specific segmentation characteristics are as follows:

[0106] Low temperature zone ( ): The output voltage increases slowly with increasing temperature, and this range is dominated by the low-temperature compensation of the temperature compensation network.

[0107] room temperature zone ( The output voltage curve is relatively flat, with a variation of less than 1.5mV, and the temperature drift is below [value missing]. .

[0108] medium temperature zone ( The output voltage remains stable, and the DIBL compensation and temperature compensation work together to keep the temperature drift below 25ppm / ℃.

[0109] High temperature zone ( The output voltage drops slightly, mainly due to high-temperature compensation from the temperature compensation network.

[0110] The comparison shows that the DIBL compensation and segmented temperature compensation combined architecture proposed in this invention achieves the best voltage temperature stability across the entire temperature range.

[0111] Example 2

[0112] This embodiment, based on Embodiment 1, adds a process corner detection module. This module includes a ring oscillator and a frequency counter. It indirectly determines the current process corner (TT / SS / FF) by detecting the oscillation frequency, and fine-tunes the mirror ratio of the DIBL compensation current and the weighting coefficients of the temperature compensation network based on the detection results, achieving adaptive joint compensation of the process corner. This enhancement is suitable for applications requiring higher mass production consistency.

[0113] Examples of specific adjustment methods are as follows:

[0114] (1) Fine-tune the mirror ratio of the DIBL compensation current:

[0115] In the DIBL compensation current generator module 300, the original fixed ratio current mirror (MP1:MP2 = 1:1) is replaced with a programmable current mirror array. This programmable current mirror array contains multiple parallel PMOS transistors, whose width-to-length ratio is set according to binary weights (e.g., 1:2:4:8). The conduction status of each transistor is controlled by the process corner detection result. When the detection result is SS (slow-slow) process corner, the NMOS transistor driving capability is weak, requiring stronger DIBL compensation. In this case, the mirror ratio is increased (e.g., switching from 1:1 to 1:2). When the detection result is FF (fast-fast) process corner, the mirror ratio is decreased (e.g., switching from 1:1 to 1:0.5).

[0116] (2) Fine-tuning the weighting coefficients of the temperature compensation network:

[0117] In the programmable current synthesis network of the temperature-compensated current synthesis module 400, the gate bias voltage of PMOS transistors MP3_0~MP3_3 is adjusted. Powered by a programmable voltage source. The process corner detection module outputs a 2-bit control code based on the detection result, which is then adjusted via a DAC (digital-to-analog converter). The voltage value. For example: during the TT process corner. During the SS process corner, due to the high threshold voltage of the MOSFET, Increase to 0.55V to maintain the same compensation current; at the FF process corner... The voltage is reduced to 0.45V. Simultaneously, the decoding threshold for the temperature range code (T_code) can be fine-tuned according to the process corner, for example, by adjusting the first reference voltage. The voltage was adjusted from 0.30V to 0.28V (SS) or 0.32V (FF) to compensate for the effect of the process angle on the temperature sensor sensitivity.

[0118] Through the above fine-tuning, it is possible to achieve the following results across all process angles (SS / TT / FF) and all temperatures ( Within the range, the temperature coefficient of the reference output voltage remains stable at... Within this range, the linear sensitivity remains stable. Within this period, mass production consistency has been significantly improved.

[0119] Example 3

[0120] This embodiment, based on Embodiment 1, further integrates the dual-injection-point DIBL compensation architecture with temperature compensation. Specifically, the DIBL compensation current is simultaneously injected into the bias node (third node B) and the output node (second node A). The weight β injected into the output node is dynamically adjusted through temperature range coding, so that the intensity of DIBL compensation changes with temperature, achieving a deep integration of DIBL compensation and temperature compensation.

[0121] The specific implementation method for dynamic adjustment is as follows:

[0122] (1) Hardware implementation of weight β:

[0123] DIBL compensation current The current mirror injected into output node A is designed as a programmable current mirror array. This array contains multiple parallel PMOS transistors with their width-to-length ratio set according to binary weights (e.g., 1:2:4:8). The conduction status of each transistor is controlled by a temperature range code T_code[3:0]. The current injected into output node A is:

[0124] ,

[0125] in, ~ For each digit of T_code[3:0], This represents the unit mirror current. The weights can be changed by altering the values ​​of T_code[3:0]. .

[0126] (2) Temperature range and weight Correspondence:

[0127] The temperature range encoding T_code[3:0] is used not only to control the temperature compensation current I TEMP The weighted summation is used for control. Size

[0128] (3) The specific adjustment logic of weight β:

[0129] The 4-bit temperature range code T_code[3:0] output by the decoder is divided into two paths. The first path directly controls the switching transistors SW0~SW3 in the temperature compensation current synthesis network to generate I. TEMP Second path: A programmable current mirror array that controls the DIBL compensation current injection into the output node, used to dynamically adjust the weight β.

[0130] Through the aforementioned dynamic adjustment mechanism, the DIBL compensation intensity increases in stages with rising temperature, matching the changing trend of the temperature compensation current. This deep integration avoids the problem of fixed DIBL compensation intensity and mismatch with temperature compensation across the entire temperature range, as seen in traditional schemes. Simulation results show that the dynamic adjustment mechanism... After adjustment, the temperature coefficient over the entire temperature range (-40℃ to 130℃) was further optimized to within 35ppm / ℃, and the linear sensitivity remained below 0.02% / V.

[0131] Example 4

[0132] The joint compensation method for a voltage reference source described in this embodiment includes the following steps:

[0133] Step 1: The subthreshold reference core module generates an initial reference voltage after first-order temperature compensation using the threshold voltage difference between the first NMOS transistor and the second NMOS transistor.

[0134] Step 2: The DIBL compensation current generator module utilizes the drain-induced barrier reduction effect of the short-channel MOSFET to detect changes in the power supply voltage and generate a first compensation current that is positively correlated with the power supply voltage.

[0135] Step 3: The temperature detection unit in the temperature compensation current synthesis module detects the chip temperature and compares the temperature with a preset threshold through a temperature comparator array to generate a temperature range code.

[0136] Step 4: The programmable current synthesis network encodes the temperature range and turns on the corresponding weighted adjustment current source units to generate a second compensation current related to the temperature.

[0137] Step 5: Divide the first compensation current into two paths and inject them into the third node and the second node respectively with the first weighting coefficient and the second weighting coefficient; at the same time, inject the second compensation current into the second node.

[0138] Step 6: At the second node, the second path of the first compensation current and the second compensation current are weighted and summed to generate a joint compensation current. The initial reference voltage is jointly compensated, and the compensated reference voltage is output.

[0139] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural modifications made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A low-power CMOS voltage reference source based on DIBL and temperature joint compensation, characterized in that, include: Start the circuit module and connect it to the power supply voltage; The subthreshold reference core module is connected to the startup circuit module and is used to generate the initial reference voltage after first-order temperature compensation. The DIBL compensation current generator module is connected to the subthreshold reference core module and is used to generate a first compensation current that is positively correlated with the power supply voltage. A temperature-compensated current synthesis module, whose input terminals are respectively connected to the DIBL compensation current generator module and the subthreshold reference core module, is used to generate a temperature-related second compensation current. An output buffer module is connected to the output terminal of the temperature-compensated current synthesis module and is used to output a reference voltage. Specifically, the first compensation current is injected simultaneously into the second and third nodes of the subthreshold reference core module through dual injection points, and the weighting coefficients injected into the second node and the third node are independently adjusted; the second compensation current is injected into the second node; the current injected into the second node by the first compensation current and the second compensation current at the second node are weighted and summed to generate a joint compensation current, which is used to jointly compensate the initial reference voltage.

2. The low power CMOS voltage reference source based on DIBL and temperature combined compensation according to claim 1, characterized in that, The DIBL compensated current generator module includes: A short-channel NMOS transistor has its source grounded, its gate connected to a first bias voltage, and its drain connected to a first node. The channel length of the short-channel NMOS transistor is taken as the minimum dimension. The first PMOS transistor has its source connected to the power supply voltage, and its drain and gate shorted together and connected to the first node, forming a diode connection structure. The second PMOS transistor has its source connected to the power supply voltage, its gate connected to the first node, and its drain outputting the first compensation current. The first PMOS transistor and the second PMOS transistor form a current mirror, and the width-to-length ratio of the first PMOS transistor and the second PMOS transistor is the same.

3. The low power CMOS voltage reference source based on combined DIBL and temperature compensation according to claim 1, characterized in that, The temperature-compensated current synthesis module includes: The temperature detection unit includes an on-chip temperature sensor and a temperature comparator array, used to detect the chip temperature and output a temperature range code; A programmable current synthesis network includes M parallel trimming current source units. Each trimming current source unit includes a trimming PMOS transistor and a switching transistor. The source of the trimming PMOS transistor is connected to the power supply voltage, and its drain is connected to the joint compensation current output node. Its gate is connected to the second bias voltage through the switching transistor. The control terminal of the switching transistor receives the corresponding bit of the temperature range code. Wherein, the channel width-length ratios of the M trimming PMOS transistors are set according to binary weights, the width-length ratio of the Mth trimming PMOS transistor is twice the width-length ratio of the 0th trimming PMOS transistor, .​​ 4. The low power CMOS voltage reference source based on DIBL and temperature combined compensation according to claim 3, characterized in that, The temperature comparator array includes a first comparator, a second comparator, and a third comparator. The negative input of the first comparator is connected to a first reference voltage to set a low temperature threshold. The negative input of the second comparator is connected to a second reference voltage to set a normal temperature threshold. The negative input of the third comparator is connected to a third reference voltage to set a high temperature threshold. The outputs of the first comparator, the second comparator, and the third comparator are processed by decoding logic to generate the temperature range code.

5. The low-power CMOS voltage reference source based on DIBL and temperature joint compensation according to claim 1, characterized in that, The subthreshold benchmark core module includes: The first NMOS transistor has its source grounded and its drain shorted to its gate and connected to the second node; the first NMOS transistor is a native threshold device. The second NMOS transistor has its source connected to the second node, its drain connected to the third node, and its gate connected to the third bias voltage; the second NMOS transistor is a standard threshold voltage device. A bias current source is connected between the power supply voltage and the third node.

6. The low power CMOS voltage reference source based on combined DIBL and temperature compensation according to claim 1, characterized in that, The startup circuit module includes multiple PMOS and NMOS transistors connected in series. The output terminal of the startup circuit module is connected to the third node of the subthreshold reference core module. During power-on, startup current is injected into the reference core module. After the circuit is established, it is automatically turned off and enters a zero static power consumption state.

7. The low power CMOS voltage reference source based on combined DIBL and temperature compensation according to claim 1, characterized in that, The weighting coefficient of the injected second node is dynamically adjusted according to the temperature range code output by the temperature compensation current synthesis module, so as to realize the temperature adaptive adjustment of the DIBL compensation intensity.

8. The low power CMOS voltage reference source based on combined DIBL and temperature compensation according to claim 1, characterized in that, The rate of change of the first compensation current with the power supply voltage is achieved by adjusting the channel length of the short-channel NMOS transistor and the first bias voltage.

9. The low power CMOS voltage reference source based on combined DIBL and temperature compensation according to claim 1, characterized in that, It also includes a process corner detection module; The process corner detection module includes a ring oscillator and a frequency counter, which are used to detect the current process corner and adjust the current mirror ratio of the DIBL compensation current generator module and the weighting coefficient of the temperature compensation current synthesis module according to the detection result.

10. A joint compensation method based on the voltage reference source according to any one of claims 1 to 9, characterized in that, Includes the following steps: Step 1: The subthreshold reference core module generates an initial reference voltage after first-order temperature compensation using the threshold voltage difference between the first NMOS transistor and the second NMOS transistor. Step 2: The DIBL compensation current generator module utilizes the drain-induced barrier reduction effect of the short-channel MOSFET to detect changes in the power supply voltage and generate a first compensation current that is positively correlated with the power supply voltage. Step 3: The temperature detection unit in the temperature compensation current synthesis module detects the chip temperature and compares the temperature with a preset threshold through a temperature comparator array to generate a temperature range code. Step 4: The programmable current synthesis network, based on the temperature range encoding, turns on the corresponding weighted adjustment current source units to generate a second compensation current related to temperature. Step 5: Divide the first compensation current into two paths and inject them into the third node and the second node respectively with the first weighting coefficient and the second weighting coefficient; Simultaneously, the second compensation current is injected into the second node; Step 6: At the second node, the second path of the first compensation current and the second compensation current are weighted and summed to generate a joint compensation current, which is used to jointly compensate the initial reference voltage and output the compensated reference voltage.

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