Clock calibration method and apparatus, system for a chip

Abstract

This application relates to the field of clock calibration technology, and discloses a clock calibration method for chips, comprising: obtaining a target clock frequency based on a timing convergence frequency; wherein the timing convergence frequency is an upper limit threshold of a preset frequency tolerance range; writing the target clock frequency to non-volatile memory; and, in the case of restoring the target clock frequency after the chip is powered on, reading the target clock frequency written before the chip is powered on from the non-volatile memory in response to a program execution request; and completing the program clock configuration according to the target clock frequency. This method can improve chip testing yield, as well as product iteration efficiency and adaptation flexibility. This application also discloses a clock calibration apparatus and system for chips.

Description

Technical Field

[0001] This application relates to the field of clock calibration technology, and for example to a clock calibration method, apparatus, and system for chips. Background Technology

[0002] Currently, in modern chip design, the frequency accuracy of internal clocks (such as ring oscillators, RC oscillators, etc.) is crucial to chip performance and functional stability. Due to inherent variations in semiconductor manufacturing processes, the initial clock frequency of manufactured chips often exhibits significant dispersion. Therefore, in the final testing phase of chip manufacturing, clock frequency calibration techniques are required. These testing phases include, for example, CP (Chip Probing, wafer testing) or FT (Final Test).

[0003] In the CP testing phase, the tester tunes the chip's clock circuit to precisely adjust its frequency to a preset, fixed target value F_target (e.g., 108MHz), which must fall within a strict tolerance range (e.g., F_target ±5%). After tuning, the final tuned value (Trim Value) is written to the chip's Flash or other one-time programmable memory. During chip power-on initialization, the initialization module reads this Trim value and configures the clock register to generate the target frequency clock.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: Process variations may prevent some chips from having their clock frequencies adjusted to within the preset frequency tolerance band. Even if the clock frequencies of these chips are very stable and sufficient to meet the timing requirements of all internal logic (i.e., setup and hold times are both met), they will still be judged as defective and scrapped due to substandard clock frequency accuracy, resulting in unnecessary yield losses. Furthermore, related technologies assume a fixed target clock frequency when developing chip firmware. All time-based calculations (such as timer cycles, communication baud rates, and analog sampling intervals) are hard-coded based on this fixed target value. If, for any reason, the target frequency needs to be adjusted during the CP / FT stage (e.g., changed to 100MHz), not only must the adjustment value change, but all the firmware associated with it, especially the bootloader stored in ROM, must be modified and the photomask remade. This is costly, time-consuming, and severely limits product flexibility and the ability to respond quickly to the market.

[0005] Therefore, there is an urgent need for a solution that can overcome the above-mentioned defects, improve chip testing yield, and enhance product iteration efficiency and adaptability.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This disclosure provides a clock calibration method, apparatus, and chip for improving chip testing yield, as well as enhancing product iteration efficiency and adaptability.

[0009] In some embodiments, the method includes: obtaining a target clock frequency based on a timing convergence frequency; wherein the timing convergence frequency is an upper limit threshold of a preset frequency tolerance range; writing the target clock frequency to a non-volatile memory; and, in the case that the target clock frequency is restored after the chip is powered on, reading the target clock frequency written before the chip is powered on from the non-volatile memory in response to a program execution request; and completing the program clock configuration according to the target clock frequency.

[0010] In some embodiments, configuring the program clock according to the target clock frequency includes: determining the clock configuration parameters associated with the program execution request according to the target clock frequency; and configuring the program clock according to the clock configuration parameters.

[0011] In some embodiments, the method further includes: obtaining a target clock frequency based on the timing convergence frequency, and obtaining a trimming value based on the timing convergence frequency; writing the target clock frequency to non-volatile memory, and writing the trimming value to non-volatile memory.

[0012] In some embodiments, writing the adjustment value and the target clock frequency to non-volatile memory includes: updating the target clock frequency according to the nominal clock frequency value corresponding to the target clock frequency; and writing the adjustment value and the updated target clock frequency to non-volatile memory.

[0013] In some embodiments, the non-volatile memory includes a one-time programmable memory area; writing the adjustment value and the updated target clock frequency to the non-volatile memory includes writing the adjustment value and the updated target clock frequency to the one-time programmable memory area.

[0014] In some embodiments, obtaining the adjustment value and the target clock frequency based on the timing convergence frequency includes: adjusting the initial adjustment value and obtaining the actual clock frequency corresponding to the adjusted initial adjustment value; selecting the actual clock frequency lower than the timing convergence frequency as the target clock frequency; and determining the adjusted initial adjustment value corresponding to the target clock frequency as the adjustment value.

[0015] In some embodiments, the chip further includes an initialization INIT module and a calibration register; after the chip is powered on, the target clock frequency is restored in the following manner: after the chip is powered on, the adjustment value is read from the non-volatile memory through the INIT module; the adjustment value is written to the calibration register through the INIT module so that the chip restores the target clock frequency.

[0016] In some embodiments, the apparatus includes a processor and a memory storing program instructions, the processor being configured to perform a clock calibration method for a chip as described above when the program instructions are executed.

[0017] In some embodiments, the clock calibration system for a chip includes: a chip; a test device; and a clock calibration apparatus for a chip as described above, mounted on the chip and / or the test device.

[0018] In some embodiments, the chip includes: non-volatile memory configured to write adjustment values ​​and a target clock frequency to the device under test; a calibration register; and an INIT module configured to read the adjustment values ​​from the non-volatile memory and write them to the calibration register after the chip is powered on.

[0019] The clock calibration method, apparatus, and chip for chips provided in this disclosure can achieve the following technical effects: This disclosed embodiment can complete the adjustment and optimization of the target clock frequency during the testing phase, breaking through the traditional strict preset frequency tolerance range limitations. It can salvage scrapped chips with only slight deviations, improving chip testing yield. After the chip is powered on and the target clock frequency is restored, the target clock frequency written before the chip is powered on is read from non-volatile memory in response to the program execution request, and the program clock configuration is completed accordingly. With the chip restored to the target clock frequency, the program clock can be flexibly configured according to the target clock frequency written before power-on, without modifying the firmware code such as the bootloader or application program. This completely decouples hardware tuning and software design, effectively reducing the change cost of code adjustment and improving product iteration efficiency and adaptability flexibility.

[0020] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of a chip provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a clock calibration method for a chip provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another clock calibration method for a chip provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another clock calibration method for a chip provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of another clock calibration method for a chip provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of a clock calibration device for a chip provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of a clock calibration system for a chip provided in an embodiment of this disclosure. Detailed Implementation

[0022] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0023] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0024] Unless otherwise stated, the term "multiple" means two or more.

[0025] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0026] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0027] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0028] Combination Figure 1 As shown, chip 10 includes a non-volatile memory 101, a calibration register 102, and an INIT (Initialization) module 103. The calibration register 102 stores adjustment values ​​to change the clock frequency of the oscillator output.

[0029] Based on the aforementioned chip 10 architecture, combined with Figure 2 As shown, this disclosure provides a clock calibration method for a chip, including: S01, obtain the target clock frequency based on the timing convergence frequency. The timing convergence frequency is the upper limit threshold of a preset frequency tolerance range.

[0030] S02, write the target clock frequency to non-volatile memory.

[0031] S03, in the case that the target clock frequency is restored after the chip is powered on, in response to the program execution request, reads the target clock frequency written before the chip is powered on from the non-volatile memory.

[0032] S04, complete the program clock configuration according to the target clock frequency.

[0033] The clock calibration method for chips provided in this disclosure allows for the adjustment and optimization of the target clock frequency during the testing phase. This overcomes the traditional limitations of strict preset frequency tolerance ranges, enabling process recovery of scrapped chips with only minor deviations and improving chip testing yield. After the chip is powered on and the target clock frequency is restored, the target clock frequency written before power-on is read from non-volatile memory in response to a program execution request, and the program clock configuration is completed accordingly. With the target clock frequency restored, the program clock can be flexibly configured based on the target clock frequency written before power-on, without modifying firmware code such as the bootloader or application program. This completely decouples hardware tuning from software design, effectively reducing the cost of code adjustments and improving product iteration efficiency and adaptability.

[0034] It should be noted that obtaining the target clock frequency based on the timing convergence frequency and writing the target clock frequency to the non-volatile memory are performed by the test equipment. If the target clock frequency is restored after the chip powers on, the chip executes the following in response to a program execution request: reading the target clock frequency written before chip power-on from the non-volatile memory and completing the program clock configuration based on the target clock frequency.

[0035] Optionally, the chip completes the program clock configuration according to the target clock frequency, including: The chip determines the clock configuration parameters associated with the program execution request based on the target clock frequency; The chip completes the program clock configuration according to the clock configuration parameters.

[0036] This ensures that the chip firmware is fully adapted to the actual operating clock frequency of the individual chip, achieving real-time synchronization between hardware tuning results and software calculations.

[0037] In some alternative embodiments, the program execution request is used to instruct the bootloader or application to perform a program function associated with a clock frequency. As an example, the program execution request may be used to request the configuration of a timer to generate an interrupt of a preset duration, or to request the configuration of a UART (Universal Asynchronous Receiver / Transmitter) module to generate a preset baud rate, or to request control of an ADC (Analog-to-Digital Converter) module to sample at a preset sampling rate. It should be noted that the above program execution requests are merely examples, and this disclosure does not impose specific limitations on them.

[0038] In a specific example, the chip completes the program clock configuration based on the target clock frequency. This includes: determining the clock configuration parameters associated with the program execution request based on the target clock frequency, and completing the program clock configuration according to these target clock configuration parameters. The clock configuration parameters include the timer count value and the baud rate division value. Here, the timer count value is... baud rate division value In the above formula, For the target clock frequency, For frequency division coefficients, This is the baud rate.

[0039] Combination Figure 3 As shown in the embodiments of this disclosure, a clock calibration method for a chip is also provided, including: S11, obtain the target clock frequency and adjustment value based on the timing convergence frequency. The timing convergence frequency is the upper limit threshold of the preset frequency tolerance range.

[0040] S12, write the target clock frequency and adjustment value to non-volatile memory.

[0041] S13, in the case that the target clock frequency is restored after the chip is powered on, in response to the program execution request, the target clock frequency written before the chip is powered on is read from the non-volatile memory.

[0042] S14, completes the program clock configuration according to the target clock frequency.

[0043] The clock calibration method for chips provided in this disclosure allows for the adjustment and optimization of the target clock frequency and tuning values ​​during the testing phase. This overcomes the traditional limitations of strict preset frequency tolerance ranges, enabling process recovery of scrapped chips with only minor deviations, improving chip testing yield, and saving a large number of chips scrapped due to slight frequency deviations. After the chip is powered on and the target clock frequency is restored, the target clock frequency written before power-on is read from non-volatile memory in response to a program execution request, and the program clock configuration is completed accordingly. With the chip restored to the target clock frequency, the program clock can be flexibly configured based on the target clock frequency written before power-on, without modifying firmware code such as the bootloader or application program. This completely decouples hardware tuning from software design, effectively reducing the cost of code adjustments and improving product iteration efficiency and adaptability.

[0044] Optionally, the test device writes the adjustment value and the target clock frequency to non-volatile memory, including: The test equipment updates the target clock frequency according to the nominal value of the clock frequency corresponding to the target clock frequency.

[0045] The test device writes the adjustment value and the updated target clock frequency to the non-volatile memory.

[0046] This breaks through the traditional strict preset frequency tolerance range limitation, enabling process recovery of scrapped chips with only slight deviations, improving chip testing yield, and saving a large number of chips scrapped due to slight frequency deviations.

[0047] In some optional embodiments, the target clock frequency is 100.3MHz, and the nominal clock frequency corresponding to the target clock frequency is 100MHz. Then the test equipment updates the target clock frequency to 100MHz according to the nominal clock frequency corresponding to the target clock frequency, and writes the adjustment value and 100MHz to the non-volatile memory.

[0048] Optionally, the non-volatile memory 102 includes a one-time programmable storage area. The test device writes the adjustment value and the updated target clock frequency to the non-volatile memory, including: The test device writes the adjustment value and the updated target clock frequency to a one-time programmable memory area.

[0049] In this way, after the chip programming operation is successful, the data in the one-time programmable memory area of ​​the non-volatile memory will not be lost regardless of test reset, power failure, or power-on. By writing the adjustment value and the updated target clock frequency into the one-time programmable memory area, it can be ensured that the chip can successfully read the adjustment value and target clock frequency from the non-volatile memory after power-on, thus guaranteeing the reliability of the chip's target clock frequency recovery and hardware adjustment.

[0050] It should be noted that the storage addresses of the adjustment values ​​and target clock frequencies are determined by the hardware and software protocols. In a specific example, the specific examples of data storage in non-volatile memory are shown in Table 1. Trim1, Trim2, and Trim3 represent the OSC1 adjustment value, OSC2 adjustment value, and OSC3 adjustment value, respectively. F1, F2, and F3 represent the OSC1 target clock frequency, OSC2 target clock frequency, and OSC3 target clock frequency, respectively. The storage addresses of the OSC1, OSC2, and OSC3 adjustment values ​​in the hardware and software protocols are 0x00, 0x04, and 0x08, respectively, and the storage addresses of the OSC1 target clock frequency, OSC2 target clock frequency, and OSC3 target clock frequency in the hardware and software protocols are 0x10, 0x14, and 0x18, respectively. The units for the preset frequency tolerance range and the center clock frequency are both MHz.

[0051] The test device writes the adjustment values ​​and target clock frequency to the non-volatile memory, specifically including: writing Trim1 to Flash address 0x00, writing Trim2 to Flash address 0x04, and writing Trim3 to Flash address 0x08; writing F1 to Flash address 0x10, writing F2 to Flash address 0x14, and writing F3 to Flash address 0x18. Based on this, all OSC adjustment values ​​and target clock frequencies are written sequentially.

[0052] Table 1. Specific examples of data storage in non-volatile memory.

[0053] Optionally, combined Figure 4 As shown, the test equipment obtains the adjustment value and the target clock frequency based on the timing convergence frequency, including: S21, the test equipment adjusts the initial tuning value and obtains the actual clock frequency corresponding to the adjusted initial tuning value.

[0054] In this step, the test equipment adjusts the initial trim value and obtains the actual clock frequency corresponding to the adjusted initial trim value. This includes: the test equipment adjusts the initial trim value within a preset trim range and obtains the actual clock frequency corresponding to the adjusted initial trim value. The preset trim range is defined as [lower trim value threshold, upper trim value threshold]. Understandably, both the initial trim value and the adjusted initial trim value are within the preset trim range. Here, the initial trim value includes the trim reset value. The trim reset value refers to the default clock calibration code at the chip's factory setting.

[0055] S22, the test equipment selects the actual clock frequency, which is lower than the timing convergence frequency, as the target clock frequency.

[0056] In this step, the clock frequency is lower than the timing convergence frequency, indicating that under preset operating voltage and preset temperature conditions, the register-to-register path inside the chip simultaneously meets the setup time and hold time requirements.

[0057] S23, the test equipment determines the initial adjustment value corresponding to the target clock frequency after adjustment as the adjustment value.

[0058] In this way, during the testing phase, the initial adjustment value is adjusted using testing equipment to obtain the actual clock frequency corresponding to the adjusted initial adjustment value. The actual clock frequency lower than the timing convergence frequency is selected as the target clock frequency, and its corresponding adjusted initial adjustment value is determined as the adjustment value. Therefore, this embodiment of the present disclosure does not use a preset frequency tolerance range as the clock frequency adjustment benchmark, but instead uses a frequency lower than the timing convergence frequency as the clock frequency adjustment benchmark. This allows chips that are below the lower limit threshold of the preset frequency tolerance range to be judged as good products, thus rescuing chips that are scrapped due to slight frequency deviations.

[0059] Optionally, the preset frequency tolerance range includes [a lower threshold of the preset frequency tolerance range and an upper threshold of the preset frequency tolerance range]. The preset frequency tolerance range has a center clock frequency, which is the average of the lower and upper thresholds of the preset frequency tolerance range. The test equipment selects an actual clock frequency lower than the timing convergence frequency as the target clock frequency, including: the test equipment selects an actual clock frequency lower than the timing convergence frequency and having the smallest absolute value of the difference between it and the center clock frequency as the target clock frequency.

[0060] In some optional embodiments, the test equipment selects an actual clock frequency lower than the timing convergence frequency as the target clock frequency. Specifically, this includes: the test equipment determining whether the actual clock frequency corresponding to the adjusted initial trim value is less than or equal to the center clock frequency. If the actual clock frequency is equal to the center clock frequency, the test equipment selects the center clock frequency as the target clock frequency; or, if the actual clock frequency is less than the center clock frequency, the test equipment selects the actual clock frequency with the smallest absolute value of the difference from the center clock frequency as the target clock frequency. Thus, during the testing phase, the test equipment always selects the actual clock frequency closest to the center clock frequency as the target clock frequency, ensuring that the chip's operating clock is as close as possible to the center clock frequency, guaranteeing that the clock accuracy matches the clock frequency design specifications.

[0061] It should be noted that the test equipment selects the actual clock frequency with the smallest absolute value of the difference from the center clock frequency as the target clock frequency. Specifically, when the actual clock frequency is greater than or equal to the lower limit threshold of the preset frequency tolerance range and less than the center clock frequency, the test equipment selects the actual clock frequency with the smallest absolute value of the difference from the center clock frequency as the target clock frequency; when the actual clock frequency is less than the lower limit threshold of the preset frequency tolerance range, the test equipment selects the actual clock frequency with the smallest absolute value of the difference from the lower limit threshold of the preset frequency tolerance range as the target clock frequency.

[0062] In a specific example, the preset frequency tolerance range is 108MHz ±5% (i.e., 102.6MHz ~ 113.4MHz), and the timing convergence frequency is 113.4MHz. The test equipment adjusts the initial adjustment value within the preset adjustment range, obtaining a maximum actual clock frequency of 100.4MHz corresponding to the adjusted initial adjustment value. This maximum actual clock frequency is less than the lower limit threshold of the preset frequency tolerance range of 102.6MHz, and is the actual clock frequency closest to the center clock frequency of 108MHz. Therefore, the test equipment selects this maximum actual clock frequency of 102.6MHz as the target clock frequency.

[0063] Optionally, the test equipment obtains the adjustment value and the target clock frequency based on the timing convergence frequency, and further includes: after the test equipment selects an actual clock frequency lower than the timing convergence frequency as the target clock frequency, the test equipment determines that the chip with the target clock frequency lower than the timing convergence frequency is a good product.

[0064] This breaks through the traditional strict preset frequency tolerance range limitation, enabling process recovery of scrapped chips with only slight deviations and improving chip testing yield.

[0065] In some optional embodiments, the preset frequency tolerance range is 108MHz ±5% (i.e., 102.6MHz ~ 113.4MHz), and the timing convergence frequency is 113.4MHz. The test equipment obtains the adjustment value and target clock frequency based on the timing convergence frequency. Specifically, the test equipment adjusts the initial adjustment value and obtains the actual clock frequency corresponding to the adjusted initial adjustment value; wherein, the actual clock frequency is 100MHz. Since 100MHz is less than the timing convergence frequency, the test equipment selects this actual clock frequency as the target clock frequency and determines its corresponding adjusted initial adjustment value as the adjustment value; the test equipment determines that the chip is a good product. Based on this, although the above-mentioned actual clock frequency of 100MHz is outside the preset frequency tolerance range, it still meets the condition of being less than the timing convergence frequency and is still determined to be a good product. In this way, the traditional strict preset frequency tolerance range limitation is overcome, allowing for process salvage of scrapped chips with only slight deviations, thus improving chip testing yield.

[0066] Optionally, combined Figure 5 As shown, the target clock frequency is restored in the following manner after the chip is powered on: S31, after the chip is powered on, the chip reads the adjustment value from the non-volatile memory through the INIT module.

[0067] S32, the chip writes the adjustment value to the calibration register through the INIT module so that the chip can restore the target clock frequency.

[0068] In this way, after the chip is powered on, the INIT module reads the adjustment value from the non-volatile memory and writes it to the calibration register. The configuration parameters of the calibration register are then updated and applied to the oscillator, causing the oscillator output frequency to be synchronously adjusted and corrected to achieve hardware adjustment, and finally calibrating the chip clock frequency to the target clock frequency consistent with the testing phase.

[0069] In practical applications, the traditional preset frequency tolerance range is 108MHz ±5%, and the clock convergence frequency is 113.4MHz.

[0070] The related technology obtained an actual clock frequency of 101MHz after clock adjustment of a chip. Although all functions and timings of the chip are normal at this actual clock frequency, it is judged as a defective product because the actual clock frequency is lower than the lower limit threshold of the preset frequency tolerance range.

[0071] For the same chip, the clock calibration method of this application was used to adjust the clock, resulting in an actual clock frequency of 100.4MHz and an adjustment value. Although this actual clock frequency data is outside the preset frequency tolerance range, it meets the condition that the clock frequency is lower than the timing convergence frequency. Therefore, the test equipment still determined that the chip was a good product and selected the actual clock frequency of 100.4MHz as the target clock frequency.

[0072] The test equipment also updates the target clock frequency according to the nominal value of 100MHz corresponding to the target clock frequency, and writes the adjustment value and the updated target clock frequency to the one-time programmable memory area.

[0073] After the chip is powered on, it reads the adjustment value from the one-time programmable memory area through INIT and writes it into the calibration register so that the chip can restore the target clock frequency.

[0074] When the target clock frequency is restored after the chip is powered on, the chip responds to the program execution request by reading the target clock frequency written before the chip was powered on from the non-volatile memory and then completing the program clock configuration according to the target clock frequency.

[0075] Combination Figure 6 As shown, this disclosure provides a clock calibration device 90 for a chip, including a processor 900 and a memory 901. Optionally, the device 90 may further include a communication interface 902 and a bus 903. The processor 900, communication interface 902, and memory 901 can communicate with each other via the bus 903. The communication interface 902 can be used for information transmission. The processor 900 can call logical instructions in the memory 901 to execute the clock calibration method for the chip described in the above embodiment.

[0076] Furthermore, the logic instructions in the aforementioned memory 101 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0077] The memory 901, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 900 executes functional applications and data processing by running the program instructions / modules stored in the memory 901, that is, it implements the clock calibration method for the chip in the above embodiments.

[0078] The memory 901 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 901 may include high-speed random access memory and may also include non-volatile memory.

[0079] Combination Figure 7As shown, this disclosure provides a clock calibration system 1 for a chip, including a chip 10, a test device 20, and the aforementioned clock calibration device 90 for the chip. The clock calibration device 90 for the chip is mounted on the chip 10 and / or the test device 20. The mounting relationship described herein is not limited to placement inside the chip body, but also includes mounting connections with other components of the chip 10 and the test device 20, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the clock calibration device 90 for the chip can be adapted to feasible chip bodies and test device bodies to achieve other feasible embodiments.

[0080] Optionally, combined Figure 1 As shown, chip 10 includes non-volatile memory 101, calibration register 102, and INIT module 103. Non-volatile memory 101 is configured to write adjustment values ​​and target clock frequencies to the device under test. INIT module 103 is configured to read adjustment values ​​from non-volatile memory 102 and write them to calibration register 102 after the chip is powered on.

[0081] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the aforementioned clock calibration method for a chip.

[0082] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0083] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0084] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0085] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0086] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A clock calibration method for a chip, characterized by, include: The target clock frequency is obtained based on the timing convergence frequency; where the timing convergence frequency is the upper limit threshold of the preset frequency tolerance range; Write the target clock frequency to non-volatile memory; If the target clock frequency is restored after the chip is powered on, the target clock frequency written before the chip is powered on is read from the non-volatile memory in response to the program execution request. Configure the program clock according to the target clock frequency.

2. The clock calibration method according to claim 1, characterized in that, Configure the program clock according to the target clock frequency, including: Determine the clock configuration parameters associated with the program execution request based on the target clock frequency; Complete the program clock configuration according to the clock configuration parameters.

3. The clock calibration method of claim 1, wherein, Also includes: While obtaining the target clock frequency based on the timing convergence frequency, the adjustment value is also obtained based on the timing convergence frequency. While writing the target clock frequency to the non-volatile memory, the adjustment value is also written to the non-volatile memory.

4. The clock calibration method of claim 3, wherein, Writing the adjustment value and target clock frequency to non-volatile memory includes: Update the target clock frequency according to the nominal clock frequency value corresponding to the target clock frequency; Write the adjustment value and the updated target clock frequency to the non-volatile memory.

5. The clock calibration method of claim 4, wherein, Non-volatile memory includes a one-time programmable memory area; Writing the adjustment value and the updated target clock frequency to non-volatile memory includes: Write the adjustment value and the updated target clock frequency to the one-time programmable memory area.

6. The clock calibration method of claim 3, wherein, The adjustment value and target clock frequency are obtained based on the timing convergence frequency, including: Adjust the initial tuning value and obtain the actual clock frequency corresponding to the adjusted initial tuning value; Select an actual clock frequency lower than the timing convergence frequency as the target clock frequency; The initial adjustment value corresponding to the target clock frequency is determined to be the adjustment value.

7. The clock calibration method according to claim 3, characterized in that, The chip also includes an initialization INIT module and a calibration register; the target clock frequency is restored after the chip is powered on in the following manner: After the chip is powered on, the adjustment value is read from the non-volatile memory through the INIT module; The adjustment value is written to the calibration register through the INIT module to restore the chip to the target clock frequency.

8. A clock calibration apparatus for a chip, comprising a processor and a memory having stored program instructions, characterized in that, The processor is configured to perform a clock calibration method for a chip as described in any one of claims 1 to 7 when executing the program instructions.

9. A clock calibration system for a chip, characterized by, include: chip; Test equipment; The clock calibration device for a chip as described in claim 8 is installed on the chip and / or testing equipment.

10. The clock calibration system of claim 9, wherein, The chip includes: Non-volatile memory, configured to write trim values ​​and target clock frequency to the device under test; Calibration register; The INIT module is configured to read the trim value from non-volatile memory and write it to the calibration register after the chip is powered on.

Images