An energy efficiency improvement method and system for a reram in-memory computing chip

Abstract

This invention discloses a method and system for improving energy efficiency in ReRAM (Remote RAM In-Memory) computing chips, relating to the field of in-memory computing chip technology. The method includes: acquiring input vector information and array state information of the ReRAM array; predicting output features of columns participating in in-memory computing based on the input vector information and array state information, and obtaining output level information corresponding to each participating column; performing hierarchical quantization control on the analog-to-digital converter circuit according to the output level information corresponding to each participating column; applying input signals to the ReRAM array through an input driving circuit, performing analog multiply-accumulate operations, and reading and quantizing the array output results of each participating column according to a conversion strategy to obtain initial calculation results. This invention achieves adaptive optimization of the quantization strategy through column-level output prediction and hierarchical quantization, combined with multi-dimensional validity judgment and on-demand refined reading, significantly improving energy efficiency while ensuring accuracy and robustness.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing chip technology, and in particular to a method and system for improving the energy efficiency of ReRAM in-memory computing chips. Background Technology

[0002] In recent years, memristor-based in-memory computing architectures have gained increasing attention in power-sensitive applications such as edge AI inference due to their high energy efficiency and strong parallelism. Currently, most ReRAM in-memory computing chips generally use fixed-width analog-to-digital converters (ADCs) to uniformly quantize the column output current when reading the array output. Although some methods attempt to dynamically adjust the quantization accuracy based on the sparsity or weight distribution of the input activation values, these methods mostly rely on offline calibration performed before chip deployment or only use very coarse overall statistical information, lacking a real-time perception and response mechanism for the dynamic characteristics of each column output in a single calculation. Some studies have also introduced simple prediction modules to estimate the approximate range of the output, but these prediction results are usually only used to switch certain circuits to save power, without truly integrating with the quantization process deeply, let alone forming a closed-loop feedback based on current output characteristics, historical behavior, and other information to dynamically optimize subsequent quantization strategies.

[0003] Existing energy efficiency improvement methods for ReRAM memory chips generally suffer from the following limitations: First, the quantization strategy is disconnected from the actual characteristics of the column outputs. Existing technologies do not combine the current input vector, array conductance state, and historical output statistics to perform differentiated and adaptive hierarchical quantization on each column, resulting in low-contribution columns still consuming high-precision quantization energy, while key high-amplitude outputs may be truncated or distorted due to insufficient quantization bit width. Second, there is a lack of online verification and correction mechanisms for the reliability of quantization results. Some methods cannot identify abnormal quantization results caused by device non-idealities, crosstalk, or noise, nor can they trigger local high-precision rereading for situations such as code domain boundary proximity, prediction consistency, neighborhood inconsistency, and perturbation stability. This makes it difficult to ensure computational accuracy and robustness while maintaining high energy efficiency. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a method and system for improving the energy efficiency of ReRAM memory chips, solving the problems of the disconnect between quantization strategy and actual column output characteristics and the lack of online verification and correction mechanisms for the reliability of quantization results.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a method for improving the energy efficiency of ReRAM in-memory computing chips, comprising, Obtain input vector information and array state information of the ReRAM storage array; Based on input vector information and array state information, output feature prediction is performed on the columns participating in in-memory computation, and the output level information corresponding to each participating column is obtained. Based on the output level information corresponding to each participating column, hierarchical quantization control is performed on the analog-to-digital conversion circuit; The input signal is applied to the ReRAM memory array by the input drive circuit to perform analog multiply-accumulate operation, and the array output results of each participating column are read and quantized according to the conversion strategy to obtain the initial calculation result; Based on the initial calculation results, the validity of the participating columns using hierarchical quantization control is determined, and a second-stage refinement reading is triggered for the target columns that do not meet the validity requirements. The target column results after secondary refinement reading are combined with the column results that did not trigger secondary refinement reading to obtain the final result of this in-memory calculation. The final result is then calculated based on the actual distribution of column outputs, the triggering status of secondary refinement reading, and the result error feedback information during this in-memory calculation process.

[0007] As a preferred embodiment of the energy efficiency improvement method for ReRAM memory chips described in this invention, the step of acquiring input vector information and array state information of the ReRAM memory array includes: The control circuit triggers the on-chip cache to read the digital input vector to be processed and converts it into an analog voltage through a digital-to-analog converter. Simultaneously, the conductivity index vector of the corresponding column and three historical state information are acquired in parallel, and the conductivity value of the array cell is reconstructed based on the conductivity index vector; After the analog input voltage stabilizes and is latched, an input vector is formed, and the input vector, conductance information, and state information are packaged together.

[0008] As a preferred embodiment of the energy efficiency improvement method for ReRAM in-memory computing chips described in this invention, the step of predicting the output features of columns participating in in-memory computation based on input vector information and array state information includes: The control circuit starts the output feature prediction module during the clock cycle, reconstructs the equivalent conductance based on the conductance index vector of the current column, and calculates the predicted output value of the current column by combining it with the stabilized analog input vector. The predicted value is Z-score normalized using the historical output mean and historical output variance of the current column to obtain the deviation index, and the amplitude is normalized to extract the normalized output features. The predicted output value and the normalized output features are fused into a column output state representation and written into the predicted feature buffer.

[0009] As a preferred embodiment of the energy efficiency improvement method for ReRAM memory chips described in this invention, the step of obtaining the output level information corresponding to each participating column includes: The control circuit integrates the deviation index of the current column and the secondary refinement flag to generate a comprehensive prediction score, and divides it into high output level, medium output level and low output level according to the preset threshold. After each column is judged, the output level information corresponding to all columns participating in the in-memory calculation is calculated and written into the column level register, and finally a complete column output level vector is generated.

[0010] As a preferred embodiment of the energy efficiency improvement method for ReRAM memory chips described in this invention, the step of performing hierarchical quantization control on the analog-to-digital conversion circuit based on the output level information corresponding to each participating column includes: The control circuit generates a preliminary quantization control parameter set corresponding to the output level for each participating column based on the column output level vector. It then performs coordinated correction of the parameter set by combining the adjacent column level status and ADC resource sharing to determine the initial quantization accuracy mode for each column. The driver analog-to-digital conversion circuit performs coarse quantization and dynamically triggers local fine quantization operations based on whether the quantization result falls within the sensitive range, thereby achieving adaptive hierarchical quantization control that is compatible with the output levels of each column, inter-column correlation, and sensitivity characteristics.

[0011] As a preferred embodiment of the energy efficiency improvement method for ReRAM memory chips described in this invention, the step of applying an input signal to the ReRAM memory array through an input driving circuit, performing analog multiply-accumulate operations, and reading and quantizing the array output results of each participating column according to a conversion strategy to obtain initial calculation results includes: The control circuit applies an input signal to the ReRAM memory array through the input drive circuit, triggering parallel analog multiply-accumulate operations to generate output currents for each column; After column-end conversion and latching, the output voltage is read in column index order, and analog-to-digital conversion of corresponding precision is performed according to the configured quantization control parameter group to obtain the initial calculation result of the current round. After all participating columns have completed analog multiplication and accumulation and hierarchical quantization, the initial calculation result vector of the current calculation round is generated.

[0012] As a preferred embodiment of the energy efficiency improvement method for ReRAM memory chips described in this invention, the step of determining the validity of participating columns using hierarchical quantization control based on initial calculation results, and triggering secondary refinement readings for target columns that do not meet the validity requirements, includes: Based on the initial calculation results, output level, predicted value and quantized state sequence, the control circuit jointly analyzes and generates an effective state description that includes four types of indicators: boundary proximity, prediction consistency, neighborhood ranking consistency and perturbation stability. The validity of a column is determined by counting the anomaly flags. For target columns that do not meet the validity requirements, a secondary refined reading strategy is dynamically configured based on the anomaly type, and the analog-to-digital conversion circuit is driven to perform a high-precision reread to obtain the refined reading result.

[0013] As a preferred embodiment of the energy efficiency improvement method for ReRAM in-memory computing chips described in this invention, the step of combining the target column result after secondary refined reading with the column result that did not trigger secondary refined reading to obtain the final result of this in-memory computation includes: The control circuit establishes a result source identifier for each participating column based on the target column set, and performs a selection operation on the output of each column based on the result source identifier function, generates the final output result of the current column, and generates the final result vector by combining the column indices; The mapping is reconstructed based on the output level information to ensure cross-precision consistency, and the aligned result is written to the output buffer or on-chip SRAM.

[0014] As a preferred embodiment of the energy efficiency improvement method for ReRAM memory chips described in this invention, the step of basing the method on the actual distribution of column outputs, the triggering of secondary refinement reads, and the result error feedback information during the current in-memory calculation process includes: The control circuit generates control strategy update parameters based on the actual distribution of column outputs in this in-memory calculation, the triggering of secondary refinement, and the feedback of result error. The updated parameters are then written into the relevant functional units to optimize the next round of in-memory calculation.

[0015] Secondly, the present invention provides an energy efficiency improvement system for ReRAM in-memory computing chips, comprising, The input and array state loading module is used to load digital input vectors, conductance indices and column history states under clock synchronization control, and to package analog input excitations and array parameters. The output feature prediction and grade determination module is used to predict column output features based on reconstructed conductance, input vector and historical statistical information, calculate comprehensive score and generate three-level output grade information; The graded quantization control and initial reading module is used to configure ADC parameters according to the output level, perform differentiated analog-to-digital conversion, and generate an initial calculation result vector; The validity determination and secondary refinement reading module is used to perform validity checks on low-level columns based on error indicators and preset thresholds, and to trigger high-precision rereading for target columns that do not meet the requirements. The result fusion and adaptive strategy update module is used to fuse the initial and refined results to generate the final output, and dynamically optimize the control strategy for the next calculation round based on the actual distribution, refinement triggering conditions and error feedback.

[0016] The beneficial effects of this invention are as follows: By fusing input vectors, array conductance states, and historical output statistics, this invention predicts and classifies the output characteristics of each column, achieving adaptive hierarchical quantization by column. This allows high-contribution columns to receive high-precision quantization, while low-contribution columns utilize low-power quantization, thereby reducing analog-to-digital conversion energy consumption while maintaining computational accuracy. Simultaneously, a multi-dimensional validity determination mechanism based on code domain boundary proximity, prediction consistency, neighborhood sorting consistency, and perturbation stability is introduced. This mechanism can identify abnormal quantization results online and trigger secondary refinement reads for columns that do not meet validity requirements, improving the reliability of computational results while avoiding redundant high-precision overhead. Furthermore, by statistically analyzing column output distribution, refinement triggering, and error feedback, the quantization control strategy is dynamically updated to achieve closed-loop adaptive optimization. This invention significantly improves the energy efficiency of ReRAM in-memory computing chips while balancing accuracy and robustness. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of an energy efficiency improvement method for a ReRAM memory chip in Example 1.

[0019] Figure 2 This is a structural diagram of an energy efficiency improvement system for a ReRAM memory chip in Example 1.

[0020] Figure 3 This is the flowchart of the hierarchical quantization control in Example 1. Detailed Implementation

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0023] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0024] Example 1, referring to Figures 1-3 This is the first embodiment of the present invention, which provides a method for improving the energy efficiency of ReRAM in-memory computing chips, including the following steps: S1. Obtain input vector information and array state information of the ReRAM storage array.

[0025] S1.1: The control circuit triggers the on-chip cache to read the digital input vector to be processed and converts it into an analog voltage through digital-to-analog conversion.

[0026] Specifically, the control circuit during the clock cycle A "load enable" signal is issued, triggering a burst read of the on-chip SRAM cache to process the digital vector. Loaded into the DAC register, in the following form:

[0027] in, It is an 8-bit unsigned integer. Transpose of the pointer; Using an on-chip DAC array with an R-2R trapezoidal structure, each digital value is... Linear conversion to analog voltage :

[0028] in ， That is the reference voltage.

[0029] S1.2: Simultaneously acquire the conductance index vector of the corresponding column and three historical state information, and reconstruct the conductance value of the array cell based on the conductance index vector.

[0030] Specifically, in the clock cycle The control circuit reads the current processing column in parallel from the state SRAM. Conductivity index vector The data is then fed into the input buffer of the hardware engine to reconstruct the corresponding cell conductance value. Simultaneously, the control circuit reads three historical information items from the column status register file (128 bits per column), including the historical output average. Historical output variance and secondary refining mark ; Conductivity index vector The expression is:

[0031] Reconstruct the corresponding unit conductance value The expression is:

[0032] in, Column index, Refers to global reference conductance. The quantization step size of conductivity. It is a 4-bit integer index that covers the conductance range. .

[0033] S1.3: After the analog input voltage stabilizes and is latched, an input vector is formed, and the input vector, conductance information, and state information are packaged together.

[0034] Specifically, in the clock cycle Before the end, all N-channel DAC output signals complete conversion and stabilize at the target voltage value, then latch the signals to the input of the word line driver, forming the final analog input vector applied to the row lines of the ReRAM array. :

[0035] During the clock cycle Before ending, complete the simulation of the input vector. Current column conductance index vector sum column state triples The packaging.

[0036] S2. Based on the input vector information and array state information, predict the output features of the columns participating in the in-memory computation, and obtain the output level information corresponding to each participating column.

[0037] S2.1: The control circuit starts the output feature prediction module during the clock cycle, reconstructs the equivalent conductance based on the conductance index vector of the current column, and calculates the predicted output value of the current column by combining it with the stabilized analog input vector.

[0038] Specifically, the control circuit during the clock cycle Start the output feature prediction module to process the current column. The prediction is performed by outputting the magnitude of the column, and the specific steps include: The control circuit is based on the current column Conductivity index vector And preset conductance reconstruction parameters to restore the equivalent conductance corresponding to the current column. :

[0039] in, This indicates the number of input dimensions corresponding to the current column; The control circuit is based on the conductance index vector The equivalent conductance values ​​of each cell in the current column are recovered in parallel, and the recovered conductance values ​​are combined to form the equivalent conductance of the current column. ; To complete the current equivalent electric conduction After recovery, the control circuit will simulate the input vector. Equivalent electrical conduction of the current column Input the prediction calculation unit to calculate the predicted output value of the current column. : .

[0040] S2.2: Use the historical output mean and historical output variance of the current column to perform Z-score normalization on the predicted value to obtain the deviation index, and at the same time perform amplitude normalization to extract normalized output features.

[0041] Specifically, and further utilize the current column Historical output average Historical output variance For the predicted output value Perform Z-score normalization to obtain the deviation index of the current column. :

[0042] in, A small positive constant pre-defined to prevent the denominator from being zero; At the same time, for the predicted output value The output amplitude is normalized to obtain the normalized output characteristics. .

[0043] S2.3: Fuse the predicted output value and the normalized output features into a state representation of the column output and write it into the predicted feature buffer.

[0044] Specifically, the control circuit will predict the output value. Normalized output features Deviation index And the secondary refinement mark of the current column. Together, they form the output feature prediction result for this column and are output and written to the prediction feature cache.

[0045] S2.4: The control circuit integrates the deviation index of the current column and the secondary refinement flag to generate a comprehensive prediction score, and divides it into high output level, medium output level and low output level according to the preset threshold.

[0046] Specifically, the control circuit reads the secondary refinement flag of the current column. And the deviation index With secondary refinement mark The common input level determination unit calculates the comprehensive predicted score for the current column. :

[0047] in, Let represent the weighting coefficients of the corresponding indicators, and satisfy . ; It should be noted that the weighting coefficients The range of values ​​is This can be determined through experimental statistical analysis of in-memory computing tasks under typical neural network workloads. Specifically, the method involves running inference tasks on various typical network models and datasets, and collecting the predicted output amplitude of each column under different scenarios. Deviation index and secondary refining mark The weighting of the impact on final energy efficiency and computational accuracy; through grid search or Bayesian optimization, in the case of... Within the constructed parameter space, the optimal configuration is selected by combining coefficients that maximizes energy efficiency gain and minimizes accuracy loss. The value was determined through extensive experimental statistical analysis of typical workloads: Experimental results show that the output amplitude... It is the dominant factor determining quantified energy consumption and should have the highest weight; deviation index It plays a significant role in avoiding misjudgment and should be given moderate weight; while the secondary refinement mark As auxiliary state information, it has the lowest weight. The optimal coefficient can improve energy efficiency moderately while ensuring minimal loss of accuracy. It is the optimal value that achieves the best balance between high energy efficiency and high accuracy. To obtain the comprehensive prediction score for the current column. Then, the control circuit scores the comprehensive prediction according to the preset level classification threshold. Compare and determine the output level information corresponding to the current column. ; Output level information includes high output level, medium output level, and low output level, and the determination rule is as follows: when When the current column is determined to be of a high output level. ; when When the current column is determined to be of medium output level, ; when When the current column is determined to be of a low output level. ; in, Indicates the high output level threshold. The output level threshold is represented, and ; It should be noted that the threshold and The range of values ​​are respectively The energy distribution of the in-memory computation output under typical neural network workloads can be determined through experimental statistical analysis. Specifically, inference tasks are performed on various mainstream deep learning models and diverse datasets, and a complete histogram of the normalized output current distribution of all columns is collected. Analysis shows that the vast majority of effective feature output energy is concentrated in the low-to-medium amplitude region, while high-amplitude outputs, although sparse, dominate the dynamic power consumption of the ADC. Based on this, simulations are used to find the energy-efficient outputs while minimizing model accuracy loss. and Boundary point, preferred The threshold was determined through extensive experimental statistical analysis of typical workloads. When the normalized output amplitude is below 0.25, its contribution to the final decision is weak, and it can be safely assigned to a low-precision, low-power quantization level. Outputs with amplitudes between 0.25 and 0.60 constitute the main information for network discrimination and need to be assigned to a medium-precision level to maintain model performance. Although outputs with amplitudes above 0.60 account for a small proportion, they are key discriminative features and must be quantized with high precision to prevent information loss. The threshold configuration can significantly reduce the overall ADC power consumption while strictly controlling the Top-1 accuracy loss within a very small value. It is the optimal value that achieves the best balance between extreme energy efficiency and model fidelity. The control circuit completes the current column After determining the output level, the corresponding output level information will be displayed in the column. Write to the column-level register, and simultaneously set the predicted output value of the current column. With comprehensive prediction score Write to the prediction result cache.

[0048] S2.5: After completing the judgment column by column, calculate the output level information corresponding to all columns participating in the in-memory calculation and write it into the column level register, and finally generate a complete column output level vector.

[0049] Specifically, the control circuit will index the columns. Updated to The process of performing conductance recovery, prediction output calculation, deviation calculation, comprehensive prediction score calculation, and output level determination is repeated for the next column participating in the in-memory calculation until all columns participating in the in-memory calculation have completed the output feature prediction. After the output level information of all participating columns in the current calculation round is written to the column level register, a complete column output level vector is generated. :

[0050] in, This indicates the total number of columns involved in this in-store calculation.

[0051] S3. Perform hierarchical quantization control on the analog-to-digital conversion circuit according to the output level information corresponding to each participating column.

[0052] S3.1: The control circuit generates a preliminary quantization control parameter set corresponding to the output level for each participating column based on the column output level vector. It then performs coordinated correction of the parameter set by combining the adjacent column level status and ADC resource sharing, and determines the initial quantization accuracy mode for each column.

[0053] Specifically, the control circuit obtains the column output level vector. Then, based on the output level information corresponding to each participating column, analog-to-digital conversion configuration control information corresponding to each participating column is generated, including the following steps: Control circuit for column index Perform initialization, and then read the output level information corresponding to the current column from the column level register in column index order. and output level information Input candidate quantization mapping units to generate the quantization control parameter set corresponding to the current column. ; It should be noted that candidate quantization mapping units refer to a set of optional, structured quantization strategy modules pre-configured in the in-memory computing accelerator architecture. Each unit encapsulates a complete set of quantization control logic, including parameter combinations of reference voltage range, bit width configuration, comparator threshold sequence, and encoding method, used to map the column output current or voltage signal in the analog domain to quantized codewords in the digital domain. These units are not statically fixed, but are designed and organized according to different application scenarios and hardware states. Typically, multiple candidate mapping units are generated offline for different output dynamic ranges, different precision-power trade-offs, and different non-ideal compensation requirements, and are stored in configuration registers or lookup tables. At runtime, through a collaborative correction mechanism and local column characteristics, the most suitable quantization mapping unit is dynamically selected or interpolated from the candidate set to generate the most suitable quantization mapping unit. List the initial quantization control parameter set for the current operating conditions And load the corresponding candidate quantization mapping unit as the execution strategy for the coarse quantization stage; Among them, the quantization control parameter group This includes candidate values ​​for the analog-to-digital conversion bit width, reference voltage range, number of comparisons, number of successive approximation rounds, sub-ADC enable, quantization clock cycle, and output data register format corresponding to the current column. Further read the output level information of the adjacent columns of the current column and the level distribution information of the currently participating columns, and based on the output level information of the current column, the level combination status of the adjacent columns, and the shared resource occupancy status of the current analog-to-digital conversion circuit, adjust the quantization control parameter group. Perform collaborative correction to obtain the initial quantization control parameter set corresponding to the current column. ; It should be noted that the quantization control parameter group The collaborative correction is an adaptive configuration process that integrates offline calibration data with the online task context. The correction goal is to generate a system tailored to the first... Initial quantization control parameter set of the column Parameter group Typically, this includes reference voltage upper and lower limits, effective bit width, and comparator threshold sequences. The specific correction method is as follows: First, based on the weight and activation value distribution of the neural network inference task, the expected dynamic range of each column's output is determined through offline analysis, and all columns are divided into three output levels: High, Medium, and Low. Second, using column-level non-ideal calibration data obtained after chip manufacturing and during startup (including ReRAM cell conductance offset, sense amplifier offset voltage, ADC's own gain / offset error, etc.), the preset basic quantization template for each level is compensated. A global energy efficiency-accuracy co-constraint is introduced. Finally, for the... Initial quantization control parameter set of the column The optimal collaborative correction strategy is determined by three factors: the base template of the output level, the column-specific calibration compensation, and the current global task constraints. The preferred strategy was determined through practical testing of ResNet-18 on 200 inference tasks on the CIFAR-10 dataset. In mini-batch inference scenarios, this method generates... It enables the vast majority of columns to meet accuracy requirements during the coarse quantization stage, with only a very small number of columns needing to trigger the subsequent refinement process. Compared with a solution using uniform fixed parameters, the total energy consumption is significantly reduced, while the Top-1 accuracy only decreases slightly. It is the preferred implementation method that achieves the best balance between hardware non-ideality, task diversity and energy efficiency goals. Cooperative correction is used to prevent adjacent high-output-level columns from collectively calling high-overhead quantization resources within the same clock window, and to keep the quantization accuracy variation between adjacent columns under control. The control circuit determines the output level information corresponding to the current column. And the collaborative correction results determine the initial quantization precision mode corresponding to the current column, specifically including: when When this happens, prioritize assigning a high-precision initial quantization mode to the current column; when When the current column is in use, the initial quantization mode with medium precision is assigned first. when When the current column is in use, a low-precision initial quantization mode is assigned first.

[0054] S3.2: Drive the analog-to-digital conversion circuit to perform coarse quantization, and dynamically trigger local fine quantization operation based on whether the quantization result falls within the sensitive range, so as to realize adaptive hierarchical quantization control that is compatible with the output level of each column, the correlation between columns and the sensitivity characteristics.

[0055] Specifically, after obtaining the initial quantization control parameter set corresponding to the current column... Then, the control circuit will use the column index information. and the corresponding initial quantization control parameter set Write to the ADC control register and quantization configuration buffer, and send the current column quantization mode load instruction to the analog-to-digital converter circuit, so that the analog-to-digital converter circuit follows the initial quantization control parameter set. Perform coarse quantization on the current column to obtain the initial quantization result for the current column. ; During the initial quantization mode loading and coarse quantization readout processes, the control circuit synchronously acquires the quantization state information of the current column in each comparison cycle, including candidate codeword state, comparison flip state, and reference sub-interval assignment state, forming the quantization state sequence corresponding to the current column. And write it to the quantization state buffer; The control circuit will use the initial quantization result Input a sensitive interval determination unit to determine whether the initial quantization result of the current column falls within the preset sensitive interval; The sensitive interval is used to characterize the result range of the current column that is sensitive to quantization error under the current initial quantization precision mode, based on the output level information corresponding to the current column. Initial quantization accuracy mode, reference voltage range configuration, and preset code segment boundary determination; It should be noted that the preset sensitive range is a pre-configured high-risk area parameter for quantization errors. The value range is usually set in the form of numerical codewords, with a typical width and radius. satisfy The quantization error can be determined through task scenario analysis and experimental statistical methods. Specifically, in various typical in-memory computing tasks, analog readout signals of the ReRAM array at different output levels (High / Medium / Low) are collected, and the ideal computation results in the corresponding digital domain are recorded simultaneously. For all valid computation samples, the ADC codeword mapped to the ideal output value is used as the basis for the determination. For reference, key decision boundaries that significantly affect the final task accuracy (such as activation function zeros, the neighborhood of the Softmax maximum, and low-amplitude gradient regions) are identified. The codeword offset range corresponding to the quantization error that causes a decrease in task accuracy exceeding a preset tolerance threshold under the current quantization configuration (bit width N, reference voltage Vref) is calculated. Simultaneously, typical interferences such as Gaussian noise, power supply ripple, and crosstalk are injected under the same configuration, and the resulting quantization result fluctuation distribution is statistically analyzed. Experimental results show that the quantization error sensitive window in the real key region is concentrated within ±(6–10) LSB of the decision boundary, while the codeword jumps caused by random interference are mostly concentrated within ±3 LSB. A dividing point that can effectively distinguish between "key regions requiring refinement" and "tolerable random fluctuations" is selected in the low-overlapping region of the two distributions as... Preferred The optimal configuration was determined through experimental analysis of 1,200 mixed workloads, including CIFAR-10, ImageNet subsets, and custom voice-controlled keyword recognition tasks. This configuration, with an 8-bit ADC and Vref=2.56V, yielded the following results. This allows most precision-sensitive samples to be correctly triggered into the progressive refinement process, while keeping unnecessary refinement rates to a small value, thus achieving the best balance between energy efficiency and model accuracy. It is the optimal value for achieving the best energy efficiency while ensuring high overall accuracy. When the initial quantization result of the current column When the value does not fall within the sensitive range, the control circuit will use the initial quantization result. As the initial calculation result of the current column Output; When the initial quantization result of the current column When the current column falls into the sensitive region, the control circuit determines that the current column has entered the progressive quantization mode and, based on the initial quantization control parameter set corresponding to the current column, enters the progressive quantization mode. Generate the sensitive interval fine-grained control parameter group corresponding to the current column. ; It should be noted that the progressive quantization mode is a phased, coarse-to-fine adaptive quantization strategy. The specific implementation process is as follows: First, before the start of each level of inference, an initial quantization control parameter set corresponding to each column is generated based on a collaborative correction mechanism. Then, the corresponding coarse quantization units are loaded from the candidate quantization mapping units; secondly, the coarse quantization results are quickly verified through a lightweight error evaluation mechanism. If the output is deemed to potentially introduce unacceptable quantization errors, a fine quantization stage is triggered: dynamically switching to a higher-precision candidate quantization mapping unit, and further fine-tuning the upper and lower limits of the reference voltage in conjunction with real-time feedback, to achieve fine reconstruction of the output of that column. The progressive quantization mode has obvious progressive characteristics: the first stage prioritizes energy efficiency, and the second stage specifically ensures local accuracy. Experimental results show that in typical neural network inference tasks, the progressive quantization mode can eliminate the need for most columns to enter the fine quantization stage, thereby significantly reducing high-power analog-to-digital conversion operations and comparator activities. Compared with the use of a high-precision quantization scheme throughout, the overall energy consumption is significantly reduced, while the overall accuracy of the model is only slightly affected. Therefore, the progressive quantization mode is a key technical path to achieve a good balance between energy efficiency and accuracy in resource-constrained edge intelligent hardware. Among them, the sensitive interval fine-tuning control parameter group This includes increasing the number of comparisons, increasing the number of successive approximation rounds, narrowing the local subdivision range of the reference voltage, increasing the enable level of the sub-ADC channel, extending the quantization clock cycle, and switching the output data register format; Refine the control parameter set based on the sensitive interval corresponding to the current column. Send a progressive quantization trigger command to the analog-to-digital conversion circuit and refine the sensitive interval quantization control parameter group. Write to the ADC control register so that the analog-to-digital conversion circuit only applies to the initial quantization result of the current column. The sensitive interval that the column falls into is subjected to local fine-grained quantization, resulting in the fine-grained quantization result for the current column. ; The control circuit will refine the results. The initial calculation result of the current column is output, and the sensitive interval trigger flag of the current column is written into the quantization state buffer. The control circuit loads the quantization control parameters of all participating columns and performs progressive quantization control of the sensitive interval according to the column index order, so that the analog-to-digital conversion circuit enters an adaptive hierarchical quantization working state that matches the output level information of each column, the inter-column correlation state, the distribution of the sensitive interval, and the historical refinement feedback results.

[0056] S4. Apply an input signal to the ReRAM memory array through the input drive circuit to perform analog multiplication and accumulation operations, and read and quantize the array output results of each participating column according to the conversion strategy to obtain the initial calculation results.

[0057] S4.1: The control circuit applies an input signal to the ReRAM memory array through the input drive circuit, triggering parallel analog multiply-accumulate operations to generate the output current of each column.

[0058] Specifically, the control circuit uses the input drive circuit to input the analog input vector. Load each word line of the ReRAM memory array, so that the first... Apply voltage to the line Parallel input excitation is applied to the array; Under the influence of the input voltage, the first line, number The column ReRAM cell generates a current response. :

[0059] The currents in each row converge at the column line to form the column output current. : .

[0060] S4.2: After column-end conversion and latching, the output voltage is read in column index order, and analog-to-digital conversion of corresponding precision is performed according to the configured quantization control parameter group to obtain the initial calculation result of the current round. After all participating columns have completed analog multiplication and accumulation and hierarchical quantization, the initial calculation result vector of the current calculation round is generated.

[0061] Specifically, column current Converted to output voltage via terminal circuit :

[0062] And it is latched by a sample-and-hold circuit; The control circuit reads the output voltage of each column sequentially according to the column index. And synchronize the loaded quantization control parameter group. ; The analog-to-digital converter circuit uses the quantization control parameters of the current column as a guide. Regarding the output voltage Perform an analog-to-digital conversion operation of the corresponding precision to obtain the initial calculation result for the current column. :

[0063] in, Indicates based on bit width and configuration parameters Quantization function; Specifically: For high-output-level columns, high-bit-width and high-resolution quantization is used; For the middle output level column, medium bit width quantization is used; For low-output-level columns, use low-bit-width, low-complexity quantization. The control circuit sequentially performs reading, quantization configuration, and analog-to-digital conversion operations on each participating column according to the column index order. After all participating columns have completed analog multiplication and accumulation and hierarchical quantization, it generates the initial calculation result vector for the current calculation round. : .

[0064] S5. Based on the initial calculation results, the validity of the participating columns using hierarchical quantization control is determined, and a second-stage refinement reading is triggered for the target columns that do not meet the validity requirements.

[0065] S5.1: Based on the initial calculation results, output level, predicted value and quantized state sequence, the control circuit jointly analyzes and generates an effective state description that includes four types of indicators: boundary proximity, prediction consistency, neighborhood ranking consistency and perturbation stability.

[0066] Specifically, the control circuit calculates the initial result for the current column. Output level information corresponding to the current column The predicted output value of the current column And the quantization state sequence currently listed in the initial quantization process. Perform joint analysis to construct a validity status description for the current column; The quantization state sequence represents the discrete quantization state evolution trajectory of the current column during each comparison cycle in the analog-to-digital conversion process, and is defined as:

[0067] in, Indicates the current column is in the [position]. Candidate codeword states during successive comparisons or approximations. This represents the total number of state updates during the initial quantization process; The validity state description includes code domain boundary proximity information, prediction consistency information, neighborhood ranking consistency information, and perturbation stability information; The control circuit determines the output level information based on the current column. and initial quantization control parameter set Determine the set of quantized code segments corresponding to the current column. :

[0068] Each code segment Refers to the first The analog input interval corresponding to each quantized code segment Refers to the first The number of quantized code segments; Furthermore, the control circuit, based on the initial calculation results... Obtain the reconstructed value :

[0069] in, A digital-to-analog reconstruction mapping function that matches the current quantization mode; Calculate the reconstructed value To the corresponding code segment Minimum distance to the boundary :

[0070] If the distance does not exceed the preset boundary sensitive width Then set the boundary proximity status flag. ,otherwise ; The boundary sensitivity width is determined by the output level, quantization bit width, reference voltage range, and the boundary of the sensitivity interval. The control circuit is based on the predicted output result Historical output average Historical output variance Array state drift Based on the distortion range allowed by the current quantization model, a prediction confidence interval is constructed. :

[0071] At the same time, according to The reconstruction interval of the current column is obtained by reverse calculation. :

[0072] If satisfied If an anomaly in prediction consistency is detected, a prediction consistency status flag is set. ; It should be noted that, These are preset parameters, and their value range is usually set to [value range]. The prediction confidence interval can be determined through experimental statistics and interval overlap sensitivity analysis. Specifically, under various typical ReRAM in-memory computing workloads, a large number of initial quantization results of column outputs and their corresponding high-precision reference values ​​are collected to construct the prediction confidence interval. Reconstruction interval The overlapping distribution, for valid samples (i.e., high-precision results consistent with predictions), is the statistical interval overlap ratio. For outlier samples, the same proportion was calculated simultaneously. Experimental results show that the overlap ratio of most valid samples is significantly higher than that of outlier samples. Therefore, a dividing point that effectively distinguishes between reliable and unreliable predictions was selected in the low-overlap region of the two distributions as... Preferred The optimal value is determined by performing end-to-end simulations on a 1T1R ReRAM array using standard datasets of CIFAR-10 and SpeechCommands under various process angles, temperatures, and device aging conditions. It ensures that most effective columns are free from redundant refinement while accurately triggering most abnormal columns, achieving a good balance between energy efficiency and computational accuracy. Control circuit defines the current column The neighborhood is listed as :

[0073] in, The neighborhood radius; Based on the relative strength of columns obtained during the prediction phase, the predicted ranking sign is calculated. :

[0074] And calculate the actual sorting symbol based on the reconstructed value. :

[0075] If there exists any neighboring column If an anomaly is found in the neighborhood sorting consistency, a neighborhood sorting status flag is set. ; Control circuit analysis and quantization of state sequence Count the number of codeword transitions between adjacent time points. :

[0076] and the number of LSB flips at the final stage :

[0077] Simultaneously, a unique identifier for the sub-interval is generated based on the sub-interval attribution results. :

[0078] in, This represents the set of candidate sub-intervals corresponding to the current column; If satisfied If any of the following conditions are met, a perturbation stability anomaly is determined, and a perturbation stability state flag is set. If none of the three conditions are met, then set ; It should be noted that, and The preset anomaly detection thresholds have the following value ranges: It was determined by statistical analysis of the intermediate response characteristics of a large number of column outputs under various typical ReRAM computing workloads. The specific method is as follows: collect data on the corresponding values ​​of valid and abnormal columns. and The index distribution ensures that the vast majority of effective columns are free from redundant refinement, while guaranteeing high-sensitivity triggering for abnormal columns caused by device mismatch, readout noise, or severe crosstalk. End-to-end simulation verification on a 1T1R ReRAM array under various process angles, temperatures (−40°C to 125°C), and accelerated aging conditions demonstrates that the threshold range achieves a good balance between energy efficiency and computational robustness. Preferably, It can ensure that effective columns are free from redundant refinement calculations while accurately triggering the vast majority of abnormal columns, thus achieving a good balance between energy efficiency and computational robustness.

[0079] S5.2: Determine whether a column is valid based on the count of abnormal flags. For target columns that do not meet the validity requirements, dynamically configure a secondary refined reading strategy according to the abnormality type, and drive the analog-to-digital conversion circuit to perform high-precision rereading to obtain the refined reading result.

[0080] Specifically, based on four types of validity states, the control circuit calculates the anomaly trigger count for the current column. :

[0081] when When the current column does not meet the validity requirements, it is designated as the target column; when... When the current column is valid, retain the initial calculation result. constant; It should be noted that the exception trigger count The determination threshold is set to The empirically optimal value was determined by performing end-to-end simulations of typical workloads of CIFAR-10 and SpeechCommands under various process angles, temperatures, and device aging conditions, and statistically analyzing the joint distribution of multidimensional anomaly markers in the valid and abnormal columns. When the threshold is set to 2, it indicates that there are two or more independent abnormal features in the current column at the same time, and the reliability of the initial quantification results decreases significantly. Setting the threshold to 2 can ensure a high anomaly detection rate while keeping the false alarm rate at a small value, thus achieving the best balance between calculation accuracy and energy efficiency. Construct an exception type vector based on the exception trigger count of the current column. :

[0082] Generate target column set :

[0083] For columns marked as target columns, the control circuit indexes the columns. Output level information Initial quantization control parameter set, and exception type vector Write to the refinement queue register; The control circuit sequentially reads the target column index from the refinement queue register and then, based on the exception type vector... Dynamically generate matching secondary refinement read control parameter group The specific strategies are as follows: like This reduces the local quantization range of the reference voltage and improves the local comparison resolution; like This increases the quantization bit width and expands the number of comparison rounds; like Then, the adjacent columns are combined to perform synchronous refined reading; like If so, then perform a repeat check after switching the sampling phase, comparison order, or reference sub-interval; The analog-to-digital conversion circuit reads the control parameter set based on secondary refinement. Output signal to the array corresponding to the target column Re-execute the high-precision reading and analog-to-digital conversion operations to obtain refined reading results. : .

[0084] S6. Combine the target column results after secondary refinement reading with the column results that have not triggered secondary refinement reading to obtain the final result of this in-memory calculation, and calculate the result based on the actual distribution of column outputs, the triggering of secondary refinement reading, and the result error feedback information during this in-memory calculation process.

[0085] S6.1: The control circuit establishes a result source identifier for each participating column based on the target column set, and performs a selection operation on the output of each column based on the result source identifier function, generates the final output result of the current column, and generates the final result vector by combining the column indices.

[0086] Specifically, the control circuit is based on the target column set. Establish result source identifiers for all participating columns:

[0087] in, This indicates that the current column result comes from the result of the second refinement read. This indicates that the result in the current column comes from the initial calculation result; Based on the result source identifier function, the control circuit performs a selection operation on each column of output to generate the final output result of the current column. :

[0088] The control circuit combines the final output results of all participating columns in column index order to generate the final result vector of this in-memory calculation. :

[0089] Among them, the final result vector It includes both the target column results after secondary refinement and the column results that retain their original values ​​without triggering secondary refinement.

[0090] S6.2: Reconstruct the mapping based on the output level information to ensure cross-precision consistency, and write the aligned result to the output buffer or on-chip SRAM.

[0091] Specifically, to maintain consistency in accuracy across quantization levels, the control circuit can base its operation on the output level signal. The information is used to reconstruct the mapping for each column of results:

[0092] After completing the result combination and format alignment, the control circuit will output the final result vector. and reconstruction results Write to the output buffer or on-chip SRAM.

[0093] S6.3: The control circuit generates control strategy update parameters based on the actual distribution of column outputs in this in-memory calculation, the secondary refinement triggering situation, and the result error feedback. The updated parameters are then written into the relevant functional units to optimize the next round of in-memory calculation.

[0094] Specifically, the control circuit controls the final result vector. Perform column output statistics to generate actual column output distribution information. :

[0095] in, The output mean of the column. The variance of the output column, These refer to the percentage of columns for different output levels; The control circuit is based on the target column set Statistics on secondary refinement trigger information:

[0096] The control circuit will the first The final reconstruction result of the column With high-precision reference results Compare and calculate the absolute error :

[0097] Furthermore, error feedback of calculation results :

[0098] The control circuit will output the actual distribution information of the column. Secondary refinement triggering conditions Error feedback of results The common input strategy update unit generates the control strategy update quantity for the next calculation round; The control circuit writes the updated control parameters into the level determination unit, quantization mapping unit, validity determination unit, and ADC configuration register, so that the updated parameters take effect when the next in-memory calculation task is executed.

[0099] This embodiment also provides an energy efficiency improvement system for ReRAM in-memory computing chips, including: The input and array state loading module is used to load digital input vectors, conductance indices and column history states under clock synchronization control, and to package analog input excitations and array parameters. The output feature prediction and grade determination module is used to predict column output features based on reconstructed conductance, input vector and historical statistical information, calculate comprehensive score and generate three-level output grade information; The graded quantization control and initial reading module is used to configure ADC parameters according to the output level, perform differentiated analog-to-digital conversion, and generate an initial calculation result vector; The validity determination and secondary refinement reading module is used to perform validity checks on low-level columns based on error indicators and preset thresholds, and to trigger high-precision rereading for target columns that do not meet the requirements. The result fusion and adaptive strategy update module is used to fuse the initial and refined results to generate the final output, and dynamically optimize the control strategy for the next calculation round based on the actual distribution, refinement triggering conditions and error feedback.

[0100] In summary, this invention achieves adaptive hierarchical quantization by fusing input vectors, array conductance states, and historical output statistics to predict and classify the output characteristics of each column. This allows for high-precision quantization of high-contribution columns and low-power quantization of low-contribution columns, thereby reducing analog-to-digital conversion energy consumption while maintaining computational accuracy. Furthermore, a multi-dimensional validity determination mechanism based on code domain boundary proximity, prediction consistency, neighborhood sorting consistency, and perturbation stability is introduced. This mechanism can identify abnormal quantization results online and trigger secondary refinement reads for columns that do not meet validity requirements, improving the reliability of computation results while avoiding redundant high-precision overhead. In addition, by statistically analyzing column output distribution, refinement triggering, and error feedback, the quantization control strategy is dynamically updated to achieve closed-loop adaptive optimization. This invention significantly improves the energy efficiency of ReRAM in-memory computing chips while balancing accuracy and robustness.

[0101] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for improving energy efficiency in ReRAM memory chips, characterized in that, include: Obtain input vector information and array state information of the ReRAM storage array; Based on input vector information and array state information, output feature prediction is performed on the columns participating in in-memory computation, and the output level information corresponding to each participating column is obtained. Based on the output level information corresponding to each participating column, hierarchical quantization control is performed on the analog-to-digital conversion circuit; The input signal is applied to the ReRAM memory array by the input drive circuit to perform analog multiply-accumulate operation, and the array output results of each participating column are read and quantized according to the conversion strategy to obtain the initial calculation result; Based on the initial calculation results, the validity of the participating columns using hierarchical quantization control is determined, and a second-stage refinement reading is triggered for the target columns that do not meet the validity requirements. The target column results after secondary refinement reading are combined with the column results that did not trigger secondary refinement reading to obtain the final result of this in-memory calculation. The final result is then calculated based on the actual distribution of column outputs, the triggering status of secondary refinement reading, and the result error feedback information during this in-memory calculation process.

2. The energy efficiency improvement method for ReRAM memory chips as described in claim 1, characterized in that: The acquisition of input vector information and ReRAM array state information includes: The control circuit triggers the on-chip cache to read the digital input vector to be processed and converts it into an analog voltage through linear transformation. Simultaneously, the conductivity index vector and historical state information of the corresponding column are acquired in parallel, and the conductivity value of the array cell is reconstructed based on the conductivity index vector; After the analog input voltage stabilizes and is latched, an input vector is formed, and the input vector, conductance information, and state information are packaged together.

3. The energy efficiency improvement method for ReRAM memory chips as described in claim 2, characterized in that: The step of predicting the output features of columns participating in in-memory computation based on input vector information and array state information includes: The control circuit starts the output feature prediction module during the clock cycle, reconstructs the equivalent conductance based on the conductance index vector of the current column, and calculates the predicted output value of the current column by combining it with the stabilized analog input vector. The predicted value is Z-score normalized using the historical output mean and historical output variance of the current column to obtain the deviation index, and the amplitude is normalized to extract the normalized output features. The predicted output value and the normalized output features are fused into a column output state representation and written into the predicted feature buffer.

4. The energy efficiency improvement method for ReRAM memory chips as described in claim 3, characterized in that: The process of obtaining the output level information corresponding to each participating column includes: The control circuit integrates the deviation index of the current column and the secondary refinement flag to generate a comprehensive prediction score, and divides it into high output level, medium output level and low output level according to the preset threshold. After each column is judged, the output level information corresponding to all columns participating in the in-memory calculation is calculated and written into the column level register, and finally a complete column output level vector is generated.

5. The energy efficiency improvement method for ReRAM memory chips as described in claim 4, characterized in that: The step of performing hierarchical quantization control on the analog-to-digital conversion circuit based on the output level information corresponding to each participating column includes: The control circuit generates a preliminary quantization control parameter set corresponding to the output level for each participating column based on the column output level vector. It then performs coordinated correction of the parameter set by combining the adjacent column level status and ADC resource sharing to determine the initial quantization accuracy mode for each column. The driver analog-to-digital conversion circuit performs coarse quantization and dynamically triggers local fine quantization operations based on whether the quantization result falls within the sensitive range, thereby achieving adaptive hierarchical quantization control that is compatible with the output levels of each column, inter-column correlation, and sensitivity characteristics.

6. The energy efficiency improvement method for ReRAM memory chips as described in claim 5, characterized in that: The process involves applying an input signal to the ReRAM memory array via an input drive circuit, performing analog multiply-accumulate operations, and reading and quantizing the array output results of each participating column according to a conversion strategy to obtain the initial calculation results, including: The control circuit applies an input signal to the ReRAM memory array through the input drive circuit, triggering parallel analog multiply-accumulate operations to generate output currents for each column; After column-end conversion and latching, the output voltage is read in column index order, and analog-to-digital conversion of corresponding precision is performed according to the configured quantization control parameter group to obtain the initial calculation result of the current round. After all participating columns have completed analog multiplication and accumulation and hierarchical quantization, the initial calculation result vector of the current calculation round is generated.

7. The energy efficiency improvement method for ReRAM memory chips as described in claim 6, characterized in that: The process of determining the validity of participating columns using hierarchical quantization control based on initial calculation results, and triggering secondary refinement readings for target columns that do not meet validity requirements, includes: Based on the initial calculation results, output level, predicted value and quantized state sequence, the control circuit jointly analyzes and generates an effective state description that includes four types of indicators: boundary proximity, prediction consistency, neighborhood ranking consistency and perturbation stability. The validity of a column is determined by counting the anomaly flags. For target columns that do not meet the validity requirements, a secondary refined reading strategy is dynamically configured based on the anomaly type, and the analog-to-digital conversion circuit is driven to perform a high-precision reread to obtain the refined reading result.

8. The energy efficiency improvement method for ReRAM memory chips as described in claim 7, characterized in that: The process of combining the target column results after secondary refinement with the column results that did not trigger secondary refinement to obtain the final result of this in-memory calculation includes: The control circuit establishes a result source identifier for each participating column based on the target column set, and performs a selection operation on the output of each column based on the result source identifier function, generates the final output result of the current column, and generates the final result vector by combining the column indices; The mapping is reconstructed based on the output level information to ensure cross-precision consistency, and the aligned result is written to the output buffer or on-chip SRAM.

9. The energy efficiency improvement method for ReRAM memory chips as described in claim 8, characterized in that: The information provided, based on the actual distribution of column outputs during this in-memory calculation process, the triggering of secondary refinement reads, and the result error feedback, includes: The control circuit generates control strategy update parameters based on the actual distribution of column outputs in this in-memory calculation, the triggering of secondary refinement, and the feedback of result error. The updated parameters are then written into the relevant functional units to optimize the next round of in-memory calculation.

10. An energy efficiency improvement system for ReRAM in-memory computing chips, based on the energy efficiency improvement method for ReRAM in-memory computing chips according to any one of claims 1 to 9, characterized in that: include, The input and array state loading module is used to load digital input vectors, conductance indices and column history states under clock synchronization control, and to package analog input excitations and array parameters. The output feature prediction and grade determination module is used to predict column output features based on reconstructed conductance, input vector and historical statistical information, calculate comprehensive score and generate three-level output grade information; The graded quantization control and initial reading module is used to configure ADC parameters according to the output level, perform differentiated analog-to-digital conversion, and generate an initial calculation result vector; The validity determination and secondary refinement reading module is used to perform validity checks on low-level columns based on error indicators and preset thresholds, and to trigger high-precision rereading for target columns that do not meet the requirements. The result fusion and adaptive strategy update module is used to fuse the initial and refined results to generate the final output, and dynamically optimize the control strategy for the next calculation round based on the actual distribution, refinement triggering conditions and error feedback.

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