A CORDIC sine and cosine solving device and method based on hybrid angle encoding

Abstract

This invention discloses a scaling-free CORDIC sine and cosine solving device and method based on hybrid angle encoding, relating to the fields of digital signal processing and VLSI design. Addressing the problems of high iteration delay, the need for additional multipliers for scaling compensation in traditional CORDIC algorithms, and the complex control logic of existing scaling-free algorithms, this invention proposes a high-throughput segmented hybrid computing architecture. This scheme divides the input angle into three segments—high, middle, and low—based on the convergence characteristics of Taylor series: the high-order segment obtains the initial reference coordinates through a lookup table (LUT); the low-order segment uses canonical signed number (CSD) encoding to decouple the carry signal and performs fine-grained rotation based on the first-order Taylor approximation; the middle-order segment combines the previous carry and uses a customized three-bit encoding mechanism to perform rotation calculation based on the second-order Taylor approximation, generating a higher-order carry; finally, a compensation module performs global carry correction. This invention employs an innovative bottom-up carry correction mechanism to completely eliminate residual angle feedback paths. It achieves fully scale-free calculation by purely utilizing shift and addition operations, compressing system latency to 3 clock cycles. This significantly improves the accuracy of sine and cosine calculations while greatly reducing hardware resource overhead.

Description

Technical Field

[0001] This invention relates to the fields of digital signal processing and very large-scale integrated circuit design, specifically to an ultra-low latency, high-precision unscaled CORDIC sine and cosine solving device and method based on hybrid angle coding. Background Technology

[0002] High-precision and high-throughput trigonometric function calculations are crucial for digital signal processing and control systems on FPGAs. Traditional CORDIC algorithms, despite using only shift-add logic, suffer from high computational latency and high hardware resource consumption due to the need for numerous iterations to meet accuracy constraints. Look-up table (LUT)-based methods, while fast, experience exponential memory demands with increasing accuracy. High-radix CORDIC aims to reduce the number of iterations but typically requires complex prior logic to select micro-rotation directions, lengthening the critical path and increasing hardware complexity. Existing scaling-free CORDIC architectures attempt to eliminate the overhead of scaling multipliers, but these methods often introduce irregular control logic or still have residual scaling errors that need compensation, failing to achieve a completely multiplier-free data path without performance trade-offs. Hybrid algorithms partially based on Taylor series rely on truncated multipliers for final accuracy fine-tuning, violating the fundamental paradigm of multiplier-free CORDIC. Furthermore, some methods neglect higher-order terms during approximate expansion, creating systemic accuracy bottlenecks. Summary of the Invention

[0003] This invention aims to provide a high-throughput hybrid architecture that avoids the residual angle feedback and high iteration costs of traditional algorithms by using angle segmentation and hybrid encoding based on the convergence characteristics of Taylor series, thereby achieving high-precision sine and cosine calculations without scaling.

[0004] The technical solution adopted by the device of this invention is: a scaling-free CORDIC sine and cosine solver based on hybrid angle encoding, comprising: a coarse rotation lookup table module, a fine rotation module based on canonical signed number (CSD) encoding, a medium-order rotation module based on three-bit encoding, and a carry compensation module. The following description uses 16-bit fixed-point number format. (1 integer digit, 1 integer digit, 14 decimal places) Fixed-point number format is explained.

[0005] Coarse Rotation Lookup Table Module: Used to process high-order segments of target angles. The high-order segment It consists of the three decimal places and one integer place of the highest target angle (i.e.) This module contains two parallel lookup tables for sine and cosine respectively, directly... The 4-bit signal is used as the address to address within an address space containing 13 valid entries; the module outputs error-free sine and cosine initial coordinate values. and For subsequent fine rotation modules.

[0006] Fine rotation module: Used to process fractional segments of the target angle composed of the lower 8 bits. (Right now This module contains a canonical signed number (CSD) encoder and a shift-adder network; it re-encodes a standard binary input sequence into a three-bit set {-1, 0, 1}, and systematically separates boundary overflows as carry signals during the encoding process. It is passed to the next level; at the same time, this module extracts the equivalent local effective rotation angle. Based on the first-order Taylor approximation principle (i.e. and The first intermediate coordinate value is calculated using a single-step network consisting of a base-5 stored adder (CSA-5-2) and a regular adder. and .

[0007] Intermediate-order rotation module: Used to process median segments of the target angle. (i.e.) carry over from the previous level The accumulated input angle This module employs an optimized three-dimensional encoding scheme to map the input angle into a simplified local rotation angle. And convert the higher-order weights into carry signals. Output; based on the second-order Taylor approximation expansion (i.e. and The second intermediate coordinate value is calculated iteratively using a cascaded array of multiplexers (MUX) and a 5-2 carry-store adder. and .

[0008] Carry compensation module: As part of the global synchronization and angle compensation stage, it is used to uniformly collect discrete overflow carry signals excluded by the previous local rotation stage. When detected When the weight is non-zero, perform one weighting operation. The final rotation operation compensates for any unexecuted weights; this module reconstructs the coordinates through merged shift and addition / subtraction logic, outputting the final sine and cosine results of the target angle. and .

[0009] This invention discloses a scaling-free CORDIC sine and cosine solving method based on hybrid angle encoding, which... Target input angle in format The specific mathematical calculations and execution steps include:

[0010] (1) Based on the error convergence limit of the Taylor series expansion, the angle is decomposed into three parts ( , and To ensure that each segment maintains high precision while minimizing logical overhead in hardware implementation, this invention derives and defines two key segmentation thresholds based on precision constraints. and ,in This represents the floor function. Based on the above derivation, the target angle... The mathematical decomposition formula is:

[0011] ;

[0012] (2) Extracting high-order segments (Right now The corresponding initial reference coordinates are obtained directly by mapping in a read-only lookup table (LUT): .because exist The format consists of 1 integer bit. and 3 highest decimal places Composition, its mathematical representation is In the first quadrant Within a large angle region (where Its binary representation is These 4 signals constitute a valid address space containing 13 address bytes (from 0000 to 1100). The corresponding lookup table relationships are shown in Table 1:

[0013] Table 1: Initial Coordinate Mapping Table

[0014]

[0015] (3) For the low-order segments consisting of 8 decimal places (Right now This stage processes the 8-bit data in parallel in a single step. The binary mathematical expression is: To minimize the addition complexity in the hardware data path, this method performs a canonical signed number (CSD) encoding conversion on the input, re-encoding standard binary bits into a set of three bits. During the encoding process, the boundary overflow of the highest-order bit is systematically removed, logically decoupling it into a carry signal to be passed to the next level (intermediate order). and equivalent local effective rotation angle : After CSD encoding and decoupling, the maximum amplitude of the equivalent local rotation angle is strictly limited to... For such a small angle, a first-order Taylor approximation is directly used: and Specifically, this utilizes the inherent constraint in CSD encoding that adjacent bits cannot both be non-zero (i.e., ), 8-bit encoded sequence It is divided into four independent 2-bit data groups. This makes it possible to represent the approximate components of a sine wave. At this time, each of these four data groups contains at most one non-zero element, so the sum of the whole will produce at most four non-zero shift terms. During hardware execution, since the sine summation is transformed into the parallel accumulation of at most four non-zero selection terms, these four shift terms, along with one initial coordinate term (…), or This results in exactly 5 operands. Therefore, the hardware only needs one 5-to-2 CSA adder paired with one adder to complete the parallel iterative calculation of these 8 decimal places in a single step, greatly shortening the critical path. The iterative update of the coordinates in this stage is as follows: , .

[0016] (4) The median segment containing 3 data bits (Right now Add the carry-over from the previous stage Obtain the total intermediate-order input Although canonical signed number (CSD) encoding is used in the low-order segments, continuing to use CSD encoding in this intermediate rotation stage can easily lead to non-adjacent non-zero shift terms (e.g., To meet accuracy requirements at this stage, a second-order Taylor approximation must be used. These non-adjacent terms inevitably introduce complex cross-product terms during squaring, significantly increasing the complexity of hardware implementation. Furthermore, if the input is directly Taylor-expanded, in the worst case (e.g., input is binary 111), the sine and cosine functions will generate too many non-zero expansion terms, leading to an excessively deep adder tree path. To effectively address these issues, avoid complex cross-product terms, and reduce the number of expansion terms, this scheme employs a customized three-bit encoding mechanism to encode the input... Mapped to a simplified local rotation angle and carry-over to the next level Through this encoding scheme, high weights are effectively converted into carry signals. Output, the generated equivalent angle It contains at most two non-zero terms (usually reduced to a single sign term), maintaining a simple structure for approximate calculations. Based on this, a second-order Taylor approximation formula introducing a quadratic term (i.e., ...) is adopted. and Perform the iterative update for this phase: , The specific three-bit encoding logic mapping relationship is shown in Table 2:

[0017] Table 2: Three-digit coding table

[0018] (5) Determine the carry from the output of the previous step. Is it not equal to zero? If so, then define the compensation angle. And perform coordinate calculations with final error compensation: , If the carry-over is zero, then directly... As a final result return.

[0019] The present invention has the following beneficial effects:

[0020] (1) The invention adopts an innovative bottom-up carry correction mechanism. The carry generated by the lower-level bit calculation is directly propagated to the upper-level rotation, which completely eliminates the residual angle data feedback path, fundamentally maintains unity gain, and realizes a pure shift addition design without multipliers and without backward scaling.

[0021] (2) The three-level parallel segmented architecture proposed in this invention eliminates the strong data dependency between traditional iterations and is implemented as a full pipeline operation in 3 clock cycles, which can maintain the highest throughput and significantly reduce computational latency.

[0022] (3) The use of optimized hybrid coding (CSD and three-bit coding) greatly reduces the number of non-zero coefficients in the shift-add network, while reducing logic resources and register overhead. Attached Figure Description

[0023] Figure 1 This is a diagram of the overall pipeline architecture of the algorithm based on hybrid angle coding;

[0024] Figure 2 This is a schematic diagram of the CSD encoding structure and bit pair processing logic;

[0025] Figure 3 This is a hardware structure diagram for intermediate-order rotation and carry compensation iterative calculation;

[0026] Figure 4 Hardware structure diagram for carry compensation iterative calculation; Detailed Implementation Plan

[0027] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0028] This invention proposes a scaling-free CORDIC sine and cosine solver based on hybrid angle encoding. Its overall calculation process consists of four cascaded pipeline stages: coarse rotation, fine rotation, intermediate-order rotation, and global carry compensation. Target input angle. After preprocessing, it can be mapped to the first quadrant reference domain. Inside, after the calculation is completed, the circle is restored using the sign bit. Interval.

[0029] Based on the convergence error limits of the first-order and second-order Taylor expansions (i.e., the previously set piecewise threshold derivation formula), the following formula is derived. The angle is systematically decomposed into three sub-segments: high-order segment occupy Median segment occupy Low-level segments occupy .

[0030] The first stage directly processes the high-order segments. .because Taylor series converges slowly over a large angle range, so this device uses a lookup table method to directly extract the results. The 4-bit signal constitutes 13 effective address spaces (corresponding to angles from 0 to 1.5 radians). The initial reference coordinates are directly output by accessing parallel sine and cosine read-only memories. , This stage extracts absolutely accurate coordinate values ​​using a small-capacity memory, effectively avoiding the huge hardware overhead caused by using high-order polynomial fitting.

[0031] The second stage combines a fine-rotation module with CSD encoding; this stage processes the low-order segments consisting of 8 decimal places. (Right now It is then fed into a canonical signed number (CSD) encoder to convert the binary bit sequence into a set of three bits. Due to the encoding characteristics, the boundary overflow of the highest bit is stripped out as a carry signal. The remaining portion constitutes an equivalent local rotation angle and is then fed into the next stage. .

[0032] Because of the maximum effective value The second-order truncation error within this range (approximately) Since the precision is far below the 14-bit threshold, the first-order Taylor approximation is applied directly: In particular, the mathematical constraint in CSD encoding that adjacent bits cannot both be non-zero is utilized. This divides the 8-bit sequence into four independent 2-bit data groups. This makes the equivalent angle... When calculating the sine sum in hardware, at most four non-zero shift options are used. The matrix formula for coordinate update is derived as follows:

[0033] ;

[0034] ;

[0035] In terms of hardware circuit layout, the shift results of these four non-zero selection options, along with the initial coordinates, are fed into a 5-to-2 CSA adder combined with a conventional adder. Thus, the 8 bits of data that previously required serial iteration are compressed into a single clock cycle for absolutely parallel, fast computation.

[0036] The third stage combines a three-bit encoded intermediate-order rotation module; this stage receives the median segment. ) and carry over from the previous level The sum of these results constitutes the complete input for this stage. To meet Due to the high accuracy requirements, this stage must incorporate quadratic terms and employ the second-order Taylor approximation: , .

[0037] If CSD encoding is continued at this stage, non-adjacent terms will be generated (e.g., 2^{-4}-2^{-6}), which will cause problems when calculating the square operation. This can introduce difficult-to-handle cross-product terms, leading to a surge in hardware complexity. Therefore, this invention employs a customized three-bit encoding logic (encoding rules detailed in the aforementioned invention description) to accurately map it into a simplified equivalent rotation angle. And converts the unresolvable higher-order weights into global carry. Overflow. After this three-bit encoding, the equivalent angle... At most two non-zero components are retained. Subsequently, the following second-order iterative formula is executed through the data path consisting of a cascaded multiplexer (MUX) array and a 5-2 CSA:

[0038] ;

[0039] ;

[0040] Phase 4: The global carry compensation module serves as the synchronization and final error correction phase for the entire pipeline. This module collects carry signals extracted from the underlying layers. And perform global angle compensation. When When valid (i.e., non-zero), it means that the rotation weights that need to be compensated are constant. At this point, based on the target accuracy requirements, the hardware execution equation for the compensation calculation expands to:

[0041] ;

[0042] ;

[0043] like If the detection result is 0, then this stage is bypassed directly through the selector, and the circuit is run unchanged. Output the target sine and cosine values.

[0044] Example

[0045] This embodiment further illustrates the deployment performance of the above-described device in a real digital signal processing system. The fully scale-free CORDIC solver of this invention is designed using Verilog HDL for register-transfer level (RTL). In the deployment verification, the target platform uses a Xilinx Zynq UltraScale+ (xczu5ev) SoC device for logic synthesis, and the system's maximum operating frequency can reach 200MHz.

[0046] Thanks to the three-level segmentation, feedforward carry compensation strategy, and hybrid encoding architecture that eliminates the strong data dependency of traditional CORDIC proposed in this invention, this solving device achieves pure shift and addition operations, completely eliminating the hardware multiplier, and the entire processing pipeline requires only 3 clock cycles of ultra-low computational latency. In terms of logic resource overhead, this embodiment consumes only about 680 lookup tables (LUTs) and 109 registers, while maintaining the root mean square error (RMSE) of the sine and cosine operations at extremely low levels. and With its extremely low latency, compact resource footprint, and outstanding high-precision computing capabilities, this device is particularly suitable for seamless embedding into FPGA signal processing data streams that have stringent requirements for real-time data throughput, especially as the core computing unit for underlying hardware acceleration modules such as FFT processing algorithms and complex communication baseband demodulation.

Claims

1. A CORDIC sine and cosine solving device and method based on hybrid angle encoding, characterized in that, It includes a coarse rotation lookup table module, a fine rotation module, an intermediate-order rotation module, and a carry compensation module; the coarse rotation lookup table module is used to receive high-order segments of the target angle. Use this as an address to access the read-only lookup table and obtain the initial sine and cosine values. and And output it to the next-level module; the fine rotation module is used to output the low-order segment of the input angle. Perform standardized signed number encoding and extract system boundary overflow as the carry signal. And obtain the equivalent local rotation angle. ; The first intermediate coordinate value is calculated based on the first-order Taylor approximation and the data path. and ; The intermediate-order rotation module is used to receive median segments. and carry over to the previous level The sum is mapped to a simplified local rotation angle using a three-dimensional encoding mechanism. And output carry signal ; The second intermediate coordinate value was calculated based on the second-order Taylor approximation formula. and ; The carry compensation module is used to collect the carry signals that escape during the aforementioned local rotation phase. Perform the final compensation rotation of the global angle, and output the final sine and cosine results of the target angle. and .

2. The CORDIC sine and cosine solving device and method based on hybrid angle encoding as described in claim 1, characterized in that, The unscaled CORDIC sine and cosine solving method based on hybrid angle encoding includes the following calculation steps: Step 1: Angle Segmentation Preprocessing: Based on the convergence properties of Taylor series, the target input angle system is decomposed into three segments: high-order segment... Median segment and low-level segments ; Step 2: Coarse initialization by looking up the table: Extracting the high-order segment Using a lookup table Perform coarse initialization to obtain the corresponding initial reference coordinates. ; Step 3: Fine rotation of the standard signed number encoding: for the low-order segment The application standard uses signed number encoding, which decouples its logic into the transmission of carry. and equivalent local rotation angle ; Perform iterations based on first-order expansions: , ; Step 4: Combine the mid-order rotation of the three-dimensional encoding: transform the mid-order segment Add the carry-over from the previous stage And a simplified rotation angle is obtained by customizing it with three-dimensional encoding. and subsequent carry-over ; Coordinate updates are performed using a second-order approximation formula that introduces a quadratic term: ; Step 5, Global Carry Correction and Compensation: Determine the carry output in Step 4. Is it non-zero? If non-zero, then set the compensation angle. The final coordinates are obtained by performing a rotation calculation with final error compensation on the second intermediate coordinate using this compensation angle. If it is zero, then directly set the second intermediate coordinate. As the final output.

3. The scaling-free CORDIC sine and cosine solving method based on hybrid angle encoding as described in claim 2, characterized in that, In step one, for... The target angle is represented in the format (1 sign bit, 1 integer bit, m decimal places). To ensure that the truncation error of Taylor approximations of different orders in the corresponding interval is strictly less than the least significant bit of the system ( Specifically, to safely use the first-order approximation (omitting the second-order terms), the maximum truncation error must be minimized. This allows us to deduce the starting boundary of the lower-order segment. ; Similarly, to safely use the second-order approximation (omitting the third-order terms), the maximum error must be minimized. This leads to the derivation of the starting boundary of the median segment. ,in It represents rounding up.

4. The scaling-free CORDIC sine and cosine solving method based on hybrid angle encoding according to claim 2, characterized in that, In step three, due to the constraint that adjacent bits in the canonical signed number encoding cannot both be non-zero, the 8-bit encoding sequence is divided into four independent 2-bit data groups; this makes it possible to represent the sinusoidal approximate component. At most, it contains only 4 non-zero shift terms; the coordinate update operation is performed in parallel in a single step on the hardware by using a 5-2 base save adder in conjunction with a regular adder.

5. The scaling-free CORDIC sine and cosine solving method based on hybrid angle encoding according to claim 2, characterized in that, In step four, the specific expansion of the second-order Taylor approximation formula is as follows: .

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