Textual generation method of ladder diagram program, electronic device, and storage medium

Abstract

This application relates to the field of industrial automation control technology, and in particular to a method for generating text-based ladder diagram programs, an electronic device, and a storage medium. This application requires first obtaining the ladder diagram program to be converted; parsing and converting the ladder diagram program to obtain a corresponding directed graph data structure; wherein the directed graph data structure includes vertex elements and directed functional edge elements; based on the directed graph data structure, generating multiple logical expressions corresponding to each vertex element and each directed functional edge element; logically sorting each logical expression to construct a tree-shaped logic block; traversing the tree-shaped logic block to generate multiple instruction table program fragments; assembling each instruction table program fragment to obtain a complete instruction table program; and serializing the complete instruction table program to obtain a text-formatted data file. In this way, the core logical information of the program can be preserved while effectively filtering out graphical layout information irrelevant to the logic, thus obtaining high-quality training data.

Description

Technical Field

[0001] This application relates to the field of industrial automation control technology, and in particular to a method for generating textual ladder diagram programs, electronic devices, and storage media. Background Technology

[0002] In the field of industrial automation control, programmable logic controllers (PLCs) are the core control units of the system. Industrial control programming platforms serve as the software hub connecting engineers and PLCs, supporting development and debugging in various programming languages, including ladder logic. In recent years, with the development of artificial intelligence technology, converting ladder logic programs into text-format data files to build training datasets has become a technological approach for intelligent applications in the industrial control field.

[0003] In related technologies, the process of converting ladder diagrams into text format data files often employs a direct parsing and conversion method. This involves extracting each logical element and its connections from the ladder diagram, while retaining the graphical layout information of each element within the diagram, and then converting them all into text format for output. This approach results in the generated text format data file containing graphical layout data that has little relevance to the program logic. When used for subsequent training of large models, this graphical layout data may interfere with the model's understanding of the core control logic.

[0004] Therefore, how to retain the core logic information of the program while effectively filtering out irrelevant graphical layout information in order to obtain high-quality training data during the process of converting ladder diagrams into text format data files has become a technical problem that urgently needs to be solved in the industry. Summary of the Invention

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a text-based generation method, electronic device, and storage medium for ladder diagram programs, which can both retain the core logical information of the program and effectively filter out graphical layout information that is irrelevant to the logic, thereby obtaining high-quality training data.

[0006] A text-based generation method for a ladder diagram program according to a first aspect embodiment of this application includes: Obtain the ladder diagram to be converted; The trapezoidal graph program is parsed and transformed to obtain the corresponding directed graph data structure; wherein, the directed graph data structure includes vertex elements and directed functional edge elements; Based on the directed graph data structure, multiple logical expressions corresponding to each vertex element and each directed functional edge element are generated; The logical expressions are logically sorted to construct a tree-shaped logical block; Traverse the tree-shaped logic blocks to generate multiple instruction list program fragments; Assemble the program fragments of each instruction list to obtain the corresponding complete instruction list program; The complete program of the instruction table is serialized to obtain the corresponding text format data file.

[0007] According to some embodiments of this application, the step of parsing and converting the ladder diagram program to obtain the corresponding directed graph data structure includes: Functional element identification is performed on the ladder diagram program to determine multiple functional logic elements and connection endpoint information between each functional logic element; The vertex elements are constructed based on the connection endpoint information between each of the functional logic elements; The directed functional edge element is constructed according to the positional order of the multiple functional logic elements in the ladder diagram program. The directed graph data structure is formed based on the vertex elements and the directed functional edge elements.

[0008] According to some embodiments of this application, the directed functional edge element is configured with corresponding direction parameters and functional parameters, the logical expression includes vertex expressions and functional edge expressions, and the generation of multiple logical expressions corresponding to each vertex element and each directed functional edge element based on the directed graph data structure includes: Based on each of the aforementioned functional parameters, the functional edge expression is determined for each of the corresponding directed functional edge elements; Based on the direction parameters of each of the directed functional edge elements, the vertex arrangement order corresponding to each of the vertex elements is determined; According to the vertex arrangement order, the corresponding vertex expression is determined for each vertex element in turn.

[0009] According to some embodiments of this application, determining the corresponding vertex expression for each vertex element sequentially according to the vertex arrangement order includes: For each vertex element that does not have an associated incoming functional edge element, its corresponding vertex expression is assigned a preset truth value; wherein, the associated incoming functional edge element refers to the directed functional edge element that is upstream of the vertex element in the directed graph data structure; For each vertex element that has the associated incoming functional edge element, a logical combination operation is performed based on the functional edge expression corresponding to each vertex element to determine each vertex expression.

[0010] According to some embodiments of this application, the step of performing logical combination operations on each vertex element having the associated incoming functional edge element, based on the functional edge expression corresponding to each vertex element, to determine each vertex expression includes: For each vertex element that has the associated incoming functional edge element, the current vertex expression is initialized to a preset truth value; Traverse the associated incoming functional edge elements of each vertex element, and determine the operation form of each associated incoming functional edge element based on the corresponding functional parameters; wherein, each associated incoming functional edge element has a corresponding starting vertex element in the directed graph data structure, and the vertex expression of the starting vertex element is the starting vertex expression. Based on the operational form of each of the associated incoming functional edge elements, the corresponding starting vertex expression and the functional edge expression are processed to obtain the operational results of each branch; The results of each branch operation are integrated into the current vertex expression to determine the updated vertex expressions.

[0011] According to some embodiments of this application, determining the functional edge expression for each of the corresponding directed functional edge elements based on each of the functional parameters includes: For each directed functional edge element whose functional parameter is a normally open contact, the state value expression is determined based on the corresponding state variable, and used as the expression for each functional edge. For each directed functional edge element whose functional parameter is a normally closed contact, a logical inversion process is performed based on the corresponding state variable to obtain each logical inversion expression, which is used as the expression for each functional edge. For each directed functional edge element whose functional parameter is an edge contact, edge state detection is performed based on the corresponding state variable to obtain each edge detection expression, which is used as the expression for each functional edge. For each directed functional edge element whose functional parameter is a comparison instruction, numerical relationship operations are performed based on the corresponding comparison object to obtain each comparison operation expression, which is used as the expression of each functional edge. For each directed functional edge element whose functional parameter is an inversion instruction, the corresponding associated logical expression is logically inverted to serve as the functional edge expression. For each directed functional edge element whose functional parameter is a rising edge instruction, the corresponding associated logic expression is subjected to rising edge state detection to serve as the functional edge expression. For each directed functional edge element whose functional parameter is a falling edge instruction, the corresponding associated logic expression is subjected to falling edge state detection to serve as the functional edge expression. For each directed functional edge element whose functional parameter is of unknown instruction type, the expression of each functional edge is assigned a preset truth value.

[0012] According to some embodiments of this application, the step of logically sorting each of the logical expressions to construct a tree-shaped logical block includes: Extract each output endpoint expression from the multiple logical expressions; wherein, the output endpoint expression is the logical expression corresponding to each functional logical element at the output endpoint; Based on the position of the functional logic element corresponding to each output endpoint expression in the ladder diagram program, the output endpoint expressions are sorted to obtain a logic sequence list. The logical expressions are logically sorted based on the logical sequence list to construct the tree-shaped logical block.

[0013] According to some embodiments of this application, the step of logically sorting each of the logical expressions based on the logical sequence list to construct the tree-shaped logical block includes: The logical sequence list is subjected to common logic identification in order to divide the logical sequence list into multiple groups of common expressions with common logical conditions; The largest common logical subexpression is determined from the group of common expressions; Based on the maximum common logical expression, construct the tree branch nodes of the tree logic block; For each of the aforementioned common expression groups, the corresponding largest common logical expression is removed to form multiple branch expression groups; Each of the branch expression groups is used as the updated common expression group, and the largest common logical expression is re-determined from the common expression group; Based on the newly determined maximum common logical expression, construct the next-level tree branch node corresponding to the tree branch node; Remove the newly determined largest common logical expression from the updated common expression group to form multiple branch expression groups. Return to execution and use each branch expression group as the updated common expression group until the logical sequence list is traversed.

[0014] According to some embodiments of this application, the tree logic block includes multiple tree branch chains, each of the tree branch chains containing several levels of tree branch nodes and tree terminal nodes. Traversing the tree logic block to generate multiple instruction list program fragments includes: For each of the tree-shaped branch chains, traverse each of the tree-shaped branch nodes and the tree-shaped terminal node; During the traversal of the tree branch nodes and the tree terminal nodes, the logical expression associated with each tree branch node is determined as a branch logical expression, and the logical expression associated with each tree terminal node is determined as a port logical expression. According to each of the tree-shaped branch chains, the branch logic expression and the port logic expression are processed by instruction mapping to obtain each of the instruction table program fragments.

[0015] Secondly, embodiments of this application provide an electronic device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the textual generation method of the ladder diagram program as described in any one of the embodiments of the first aspect of this application.

[0016] Thirdly, embodiments of this application provide a computer-readable storage medium storing a program that is executed by a processor to implement the textual generation method of a ladder diagram program as described in any one of the embodiments of the first aspect of this application.

[0017] The text generation method, electronic device, and storage medium for ladder diagram programs according to embodiments of this application have at least the following beneficial effects: This application presents a method for text-based generation of ladder diagram programs. The method requires first obtaining the ladder diagram program to be converted; then parsing and converting the program to obtain a corresponding directed graph data structure, which includes vertex elements and directed functional edge elements; based on the directed graph data structure, generating multiple logical expressions corresponding to each vertex element and each directed functional edge element; logically sorting these logical expressions to construct tree-shaped logical blocks; traversing these tree-shaped logical blocks to generate multiple instruction table program fragments; assembling these instruction table program fragments to obtain the corresponding complete instruction table program; and finally, serializing the complete instruction table program to obtain the corresponding text-formatted data file. This approach preserves the core logical information of the program while effectively filtering out irrelevant graphical layout information, resulting in high-quality training data.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1A flowchart illustrating a text-based generation method for a ladder diagram program provided in an embodiment of this application; Figure 2 This is another flowchart illustrating the text generation method of the ladder diagram program according to an embodiment of this application; Figure 3 This is another flowchart illustrating the text generation method of the ladder diagram program according to an embodiment of this application; Figure 4 This is another flowchart illustrating the text generation method of the ladder diagram program according to an embodiment of this application; Figure 5 This is another flowchart illustrating the text generation method of the ladder diagram program according to an embodiment of this application; Figure 6 This is another flowchart illustrating the text generation method of the ladder diagram program according to an embodiment of this application; Figure 7 This is another flowchart illustrating the text generation method of the ladder diagram program according to an embodiment of this application; Figure 8 This is another flowchart illustrating the text generation method of the ladder diagram program according to an embodiment of this application; Figure 9 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0021] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0022] In the description of this application, it should be understood that the orientation descriptions, such as up, down, left, right, front, and back, are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0024] In the description of this application, it should be noted that, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly. Those skilled in the art can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution. Furthermore, the identification of specific steps in the following text does not imply a limitation on the order of steps or execution logic. The execution order and logic between each step should be understood and inferred from the content described in the embodiments.

[0025] Programmable Logic Controllers (PLCs) are the core computing units in industrial automation control systems. They execute logic operations, sequential control, timing and counting instructions through programmable memory, driving mechanical equipment or production processes via input / output interfaces. Among the various programming languages ​​supported by industrial control programming platforms, ladder diagrams, whose syntax directly borrows from traditional relay circuit diagrams, express logical relationships using graphical elements such as contacts, coils, and function blocks, forming ladders with horizontal wires. This high level of intuitiveness and engineering practicality makes ladder diagrams the most classic and widely used programming language in the industrial control field. Engineers can use ladder diagrams to describe switching control scenarios, such as motor start / stop and valve interlocking, in a manner consistent with electrical control practices. This has led to ladder diagrams' long-standing dominance in industrial settings.

[0026] However, using ladder diagrams to program programmable logic controllers places high demands on engineers' technical skills.

[0027] On the one hand, engineers need to be familiar with the working principles of electrical components such as relays, contactors, and sensors, understand the electrical control logic such as normally open contacts, normally closed contacts, and coil energization and de-energization, and master the correspondence between basic electrical symbols and ladder diagram symbols; On the other hand, engineers need to be able to break down complex control requirements into independent logic modules, be proficient in using Boolean algebra to design control logic, and transform electrical schematics into executable ladder diagram programs. When the control logic involves multi-layered nested conditional judgments or loop structures, the branch connections of the ladder diagram become intricate and complex. Troubleshooting becomes difficult when multiple coils affect the same output. Especially when implementing complex functions such as proportional-integral-differential algorithms or matrix operations, the ladder diagram connections become lengthy and difficult to trace, significantly reducing readability.

[0028] Despite the growing trend of AI-assisted programming, current large-scale model systems still struggle to automatically program ladder diagrams directly. Existing technologies can only generate ladder diagrams in text-based format. The shapes of components in these diagrams differ significantly from actual ladder diagrams, resulting in poor readability and making them unsuitable for direct import into industrial control programming platforms for compilation and debugging. Even with such generated results, engineers still need to manually reproduce them on the programming platform, failing to truly alleviate the programming burden. More importantly, directly converting ladder diagrams to structured text formats like JSON inevitably carries a large amount of graphical layout information unrelated to program logic, such as the row and column positions of functional blocks and the direction of connections within the ladder diagram. This information is meaningless for the program's logical execution, but when used as a training set for large language models in the industrial control field, it introduces noise, interfering with the model's understanding and learning of core control logic, leading to a decline in training data quality.

[0029] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a text-based generation method, electronic device, and storage medium for ladder diagram programs, which can both retain the core logical information of the program and effectively filter out graphical layout information that is irrelevant to the logic, thereby obtaining high-quality training data.

[0030] The following explanation is based on the accompanying drawings.

[0031] Reference Figure 1 The text-based generation method for ladder diagram programs according to embodiments of this application may include: Step S101: Obtain the ladder diagram program to be converted; Step S102: The ladder diagram program is parsed and transformed to obtain the corresponding directed graph data structure; wherein, the directed graph data structure contains vertex elements and directed functional edge elements; Step S103: Based on the directed graph data structure, generate multiple logical expressions corresponding to each vertex element and each directed functional edge element; Step S104: Logically sort each logical expression to construct a tree-shaped logical block; Step S105: Traverse the tree-structured logic blocks to generate multiple instruction list program fragments; Step S106: Assemble the program fragments of each instruction list to obtain the corresponding complete instruction list program; Step S107: Serialize the complete instruction list program to obtain the corresponding text format data file.

[0032] This application presents a method for text-based generation of ladder diagram programs. The method requires first obtaining the ladder diagram program to be converted; then parsing and converting the program to obtain a corresponding directed graph data structure, which includes vertex elements and directed functional edge elements; based on the directed graph data structure, generating multiple logical expressions corresponding to each vertex element and each directed functional edge element; logically sorting these logical expressions to construct tree-shaped logical blocks; traversing these tree-shaped logical blocks to generate multiple instruction table program fragments; assembling these instruction table program fragments to obtain the corresponding complete instruction table program; and finally, serializing the complete instruction table program to obtain the corresponding text-formatted data file. This approach preserves the core logical information of the program while effectively filtering out irrelevant graphical layout information, resulting in high-quality training data.

[0033] In some embodiments, step S101 involves obtaining the ladder diagram program to be converted. It's important to note that obtaining the ladder diagram program to be converted is crucial. A ladder diagram is a graphical industrial control programming language composed of graphical elements such as contacts, coils, and function blocks, along with horizontal and vertical wires connecting these elements. Each graphical element occupies a specific row and column position in the ladder diagram, and elements are connected in series or parallel via wires. Reading the original ladder diagram program data from the industrial control programming platform or storage medium provides the necessary information foundation for all subsequent processing. Without the original ladder diagram as input, subsequent abstraction, parsing, and conversion cannot be carried out; therefore, this step constitutes a prerequisite for the entire processing flow.

[0034] In step S102 of some embodiments, the ladder diagram program is parsed and transformed to obtain the corresponding directed graph data structure; wherein, the directed graph data structure includes vertex elements and directed functional edge elements; It's important to note that the obtained ladder diagram program is parsed and converted into a directed graph data structure. In this data structure, vertex elements represent the left and right connection endpoints of logic components, not the spatial location of the logic components themselves; directed functional edge elements represent the logic components themselves, such as normally open contacts, normally closed contacts, coils, timers, or function blocks. The direction of the edges is fixed from the left endpoint to the right endpoint, corresponding to the left-to-right energy flow direction in the ladder diagram. If multiple endpoints are connected by horizontal or vertical wires, these endpoints are merged into a single vertex in the directed graph, thus abstracting the physical connection of the wires into equipotential logical connection points. The purpose of this step is to transform the graphical ladder diagram into a mathematical topological structure, turning the graphical elements and their connections, which originally relied on visual presentation, into a set of nodes and edges that can be recognized and computed by a computer. This modeling method is used because the graphical row and column coordinates and the direction of the connections have no substantial impact on the execution of the program logic, while the topological dependencies between components are the essence of the control logic. By transforming the spatial layout into topological relationships, we can remove graphical information irrelevant to the logic while preserving the logical connections.

[0035] Reference Figure 2 According to some embodiments of this application, step S102, which parses and transforms the ladder diagram program to obtain the corresponding directed graph data structure, may include: Step S201: Identify functional elements for the ladder diagram program to determine multiple functional logic elements and the connection endpoint information between each functional logic element; Step S202: Construct vertex elements based on the connection endpoint information between each functional logic element; Step S203: Construct directed functional edge elements according to the position order of multiple functional logic elements in the ladder diagram program; Step S204: Based on vertex elements and directed functional edge elements, a directed graph data structure is formed.

[0036] In some embodiments, step S201 involves identifying functional elements in the ladder diagram program to determine multiple functional logic elements and connection endpoint information between each functional logic element. It's important to note that a preliminary semantic analysis is performed on the original ladder diagram program. A ladder diagram consists of various graphic symbols, such as normally open contacts, normally closed contacts, coils, timers, counters, and function blocks. These symbols are presented in specific graphic styles and occupy defined positions within the ladder diagram. Functional element identification refers to the computer program identifying the specific logical function type represented by each graphic symbol by parsing the graphical data or structured description of the ladder diagram. Simultaneously, it determines the connection endpoint information of each functional logic element, that is, the positions of the left and right endpoints of each element in the diagram, and which other elements these endpoints are connected to via wires. The purpose of this step is to transform the graphical visual information into structured data that the computer can understand, extracting the logical elements and their physical connections from the originally graphical representation into clear type identifiers and positional relationship data. This identification is necessary because the original ladder diagram is stored in a graphical format or proprietary data structure, which the computer cannot directly understand. The graphic symbols must first be converted into identifiable functional types and connection information to provide the necessary foundational data for subsequent mathematical abstraction processing.

[0037] In some embodiments, step S202 involves constructing vertex elements based on the connection endpoint information between functional logic elements. It should be noted that the identified connection endpoint information is converted into vertex elements in a graph data structure. In step S201, the positions of the left and right endpoints of each functional logic element and the wire connection relationships between the endpoints have been obtained. Now, it is necessary to define the vertices in the graph based on this information: if the endpoints of multiple functional logic elements are directly connected by horizontal and vertical wires, these endpoints are merged into the same vertex in the directed graph, because the wires themselves only serve as equipotential connections and do not perform any logical operations; if an endpoint connects only a single element, then that endpoint constitutes a vertex alone. The vertex elements constructed in this way represent logical connection points, not the functional elements themselves. The purpose of this step is to abstract the physical connection relationships into mathematical nodes, so that the originally scattered endpoint information is merged into connection nodes with topological significance, eliminating the interference of the complex geometric orientation of the wires in the ladder diagram on the logical relationships. The reason for such merging and abstraction is that the horizontal and vertical wires in the ladder diagram may present complex intersections and extensions in physical layout, but logically they only represent that some connection points have the same potential. By merging the connected endpoints into the same vertex, the geometric attributes of the wires can be eliminated, and only the pure logical connection relationships can be retained.

[0038] In step S203 of some embodiments, directed functional edge elements are constructed according to the positional order of multiple functional logic elements in the ladder diagram program; It should be noted that directed functional edge elements are constructed based on the positional order of multiple functional logic elements in the ladder diagram program. Positional order refers to the arrangement of functional logic elements in the ladder diagram, which can follow the execution rules from left to right and from top to bottom. Each functional logic element is modeled as a directed edge, starting from the vertex corresponding to its left endpoint and pointing to the vertex corresponding to its right endpoint. The direction of the edge is always fixed from left to right, consistent with the direction of energy flow from the left busbar to the right busbar in the ladder diagram. Through the positional order information, the relative positions of each edge in the diagram and the dependencies between edges can be determined. The purpose of this step is to transform the identified functional logic elements into directional edges, encapsulating the logical function of each element as a directed relationship connecting two vertices, thereby unifying the element's type and direction attributes in the edge definition. The reason for constructing directed edges based on positional order is that the execution of a ladder diagram has a clear directionality. Only by modeling elements as directional edges can the transmission path of energy flow in the circuit and the order in which logical calculations should be followed be accurately reflected.

[0039] In some embodiments, step S204 forms a directed graph data structure based on vertex elements and directed functional edge elements.

[0040] It's important to note that combining the previously constructed vertex elements and directed functional edge elements forms a complete directed graph data structure. Vertices represent connection points, directed functional edges represent functional elements, the direction of the edges indicates the energy flow direction, and the connections between vertices represent the series or parallel topology between elements. By associating vertices and edges according to their actual connections, a mathematical structure capable of fully describing the logical topology of the ladder diagram is formed. This step integrates the scattered vertex and edge elements into a unified data organization, allowing the logical relationships of the entire ladder diagram to be described holistically using graph theory. This data structure is necessary because only by organizing vertices and edges into a complete graph can graph theory algorithms be applied to systematically analyze and process the ladder diagram, providing a structured data foundation for subsequent logical calculations and program transformations based on the graph structure.

[0041] In some more specific embodiments, a standard start-stop circuit ladder diagram used in an industrial control programming platform for controlling motor start and stop is used as the basis for text generation. This ladder diagram starts from the left busbar and includes a normally open contact X0 corresponding to a start button and a normally open contact Y0 for self-locking. These two contacts are connected in parallel, with their upper ends connected to the left busbar via vertical wires and their lower ends converging at the same node via horizontal wires. A normally closed contact X1 corresponding to a stop button is connected in series after this converging point. Finally, an output coil Y0 is connected, with its right end connected to the right busbar.

[0042] In step S101, the ladder diagram program to be converted is obtained by reading the project file or storage medium of the industrial control programming platform. Specifically, the obtained content includes the type identifiers and status variable addresses of four functional logic elements, namely normally open contact X0, normally closed contact X1, output coil Y0, and self-locking normally open contact Y0, and the description information of the wire connection relationships between these elements is also obtained. The purpose of this step is to provide complete raw input data for subsequent parsing and conversion, enabling the computer to identify which logic elements are included in the ladder diagram and how these elements are connected on the diagram.

[0043] In step S102, the ladder diagram program obtained above is parsed and transformed to obtain the corresponding directed graph data structure. First, the ladder diagram is functionally identified to determine four functional logic elements and their respective connection endpoints. When constructing vertex elements, the rule that a vertex represents the left and right connection endpoints of a logic element is followed, and the endpoints of each functional logic element are taken as potential vertex objects. Among them, the left endpoint of normally open contact X0 and the left endpoint of self-locking normally open contact Y0 are both connected to the left busbar by vertical wires. Since there are horizontal and vertical wires connecting these two endpoints, they are merged into the same vertex V1 in the directed graph data structure. This vertex represents the common upper connection point of the parallel branches. The right endpoint of normally open contact X0, the right endpoint of self-locking normally open contact Y0, and the left endpoint of normally closed contact X1 are connected to each other by horizontal wires. There are also horizontal and vertical wires connecting these three endpoints, so they are merged into the same vertex V2, representing the middle connection point after the parallel branches merge. The right end of the normally closed contact X1 is directly connected to the left end of the output coil Y0 via a wire, forming vertex V3. The right end of the output coil Y0 is connected to the right busbar, forming vertex V4. Thus, the wire connection relationship in the ladder diagram is abstracted into four vertex elements.

[0044] When constructing directed functional edge elements, the rule is followed: each edge represents the logical element itself, and the direction of the edge is always from the left endpoint to the right endpoint. Each functional logic element is modeled as a directed functional edge. The normally open contact X0 is modeled as a directed functional edge from vertex V1 to vertex V2, with its direction parameter indicating that the energy flow is from the left endpoint to the right endpoint, and its functional parameter identifying it as a normally open contact. The self-locking normally open contact Y0 is modeled as another directed functional edge from vertex V1 to vertex V2, with the direction parameter also being from the left endpoint to the right endpoint, and its functional parameter being a normally open contact. The normally closed contact X1 is modeled as a directed functional edge from vertex V2 to vertex V3, with the direction parameter being from the left endpoint to the right endpoint, and its functional parameter being a normally closed contact. The output coil Y0 is modeled as a directed functional edge from vertex V3 to vertex V4, with the direction parameter being from the left endpoint to the right endpoint, and its functional parameter being an output coil. Based on the four vertex elements and four directed functional edge elements mentioned above, a directed graph data structure is finally formed that can completely describe the logical topology of the circuit.

[0045] In some embodiments, step S103 generates multiple logical expressions corresponding to each vertex element and each directed functional edge element based on the directed graph data structure. It should be noted that, based on the established directed graph data structure, multiple logical expressions corresponding to each vertex element and each directed functional edge element are generated. In this step, each vertex element is assigned a logical expression to describe the conditions that must be met for energy flow to occur at the connection endpoint; each directed functional edge element is also mapped to a logical expression to describe the logical operation or judgment condition represented by the logical element itself. For example, normally open contacts are mapped to the variable itself, normally closed contacts are mapped to logical NOT operations, and comparison instructions are mapped to arithmetic comparison relations. For vertices that serve as the logical starting point, their expressions are defined as truth constants; for other vertices, by traversing all their forward edges, the expressions of the predecessor vertices are logically combined with the expressions of the corresponding edges to obtain the complete logical expression of that vertex. The purpose of this step is to further transform the topological relationships in the graph structure into computable logical formulas, turning the connection relationships originally represented by nodes and edges into Boolean expressions or arithmetic expressions with explicit operational rules. The reason for this conversion is that although the graph structure expresses the connection order between components, it does not reveal the specific logical conditions that the signal needs to satisfy when it is transmitted at each node. Only by converting the graph structure into a logical expression can the control logic implemented by the ladder diagram be accurately described.

[0046] Reference Figure 3According to some embodiments of this application, directed functional edge elements are configured with corresponding direction parameters and functional parameters. The logical expressions include vertex expressions and functional edge expressions. Step S103, based on the directed graph data structure, generates multiple logical expressions corresponding to each vertex element and each directed functional edge element, which may include: Step S301: Based on each functional parameter, determine the functional edge expression for each corresponding directed functional edge element; Step S302: Determine the vertex arrangement order corresponding to each vertex element based on the direction parameter of each directed functional edge element; Step S303: Determine the corresponding vertex expression for each vertex element in turn according to the vertex arrangement order.

[0047] In some embodiments, step S301 involves determining a functional edge expression for each directed functional edge element based on each functional parameter. It should be noted that the functional parameters configured for directed functional edge elements describe the type and logical attributes of the functional logic element represented by the edge, such as whether the element is a normally open contact, normally closed contact, comparison instruction, or other functional block. Based on each functional parameter, a functional edge expression is determined for each corresponding directed functional edge element. This functional edge expression is the logical operation rule or judgment condition corresponding to the logic element itself. The purpose of this step is to transform the functional attributes of the edge into computable logical semantics, so that each directed functional edge not only represents the connection relationship between two vertices, but also carries specific logical operation meanings. The reason why it is necessary to determine the functional edge expression first is that when calculating the energy flow state of each connection point in the subsequent calculation, it is necessary to clarify what conditions need to be met when passing through each edge, and the functional edge expression is precisely the mathematical description of these conditions.

[0048] According to some embodiments of this application, determining the functional edge expression for each corresponding directed functional edge element based on each functional parameter may include: For each directed functional edge element whose functional parameter is a normally open contact, the expression for each state value is determined based on the corresponding state variable, and used as the expression for each functional edge. For each directed functional edge element whose functional parameter is a normally closed contact, a logical inversion process is performed based on the corresponding state variable to obtain each logical inversion expression, which is then used as the expression for each functional edge. For each directed functional edge element whose functional parameter is an edge contact, edge state detection is performed based on the corresponding state variable to obtain each edge detection expression, which is then used as the expression for each functional edge. For each directed functional edge element whose functional parameter is a comparison instruction, numerical relationship operations are performed based on the corresponding comparison object to obtain each comparison operation expression, which is then used as the expression for each functional edge. For each directed functional edge element whose functional parameter is a negation instruction, the corresponding associated logical expression is negated to serve as the functional edge expression. For each directed functional edge element whose functional parameter is a rising edge instruction, the corresponding associated logic expression is subjected to rising edge state detection to serve as the expression for each functional edge. For each directed functional edge element whose functional parameter is a falling edge instruction, the corresponding associated logic expression is subjected to falling edge state detection to serve as the expression for each functional edge. For each directed function edge element whose function parameter is an unknown instruction type, assign a preset truth value to each function edge expression.

[0049] Functional edge expressions are the core step in transforming various graphical symbols in a ladder diagram into computable logical conditions. Because the logic elements in a ladder diagram are diverse, and each element has different rules for controlling energy flow, it is necessary to establish differentiated expression mapping rules based on the element type identified by the functional parameters, so that each element corresponds to a clear mathematical or logical judgment condition.

[0050] For normally open contacts, the functional parameter indicates that the element is normally open. Taking the start button X0 as an example, when the button is not pressed, the contact is in the open state, and energy cannot flow; when the button is pressed, the contact closes, and energy flows. Therefore, its functional side expression directly takes the state variable X0 corresponding to the contact, and the expression is X0. When X0 is TRUE, the side is on; when it is FALSE, the side is off. For normally closed contacts, the functional parameter indicates that the element is normally closed. Taking the stop button X1 as an example, the button is in the closed state under normal conditions, and energy can flow; when the button is pressed, the contact opens, and energy flow is cut off. Therefore, its functional side expression needs to logically invert the state variable X1, and the expression is NOT X1. When X1 is FALSE, NOT X1 is TRUE, and the side is on; when X1 is TRUE, NOT X1 is FALSE, and the side is off.

[0051] For edge-triggered contacts, their functional parameters indicate the instantaneous transition of the state variable that the component needs to detect. Taking LDP M0 as an example, this component does not conduct while M0 is continuously TRUE, but only returns to TRUE at the instant M0 transitions from FALSE to TRUE, remaining FALSE at all other times. Therefore, its functional edge expression is P(M0), where P represents the rising edge detection function. This expression can accurately capture the transition edge of the signal, rather than a continuous level, and is suitable for control scenarios requiring single triggering or debouncing processing.

[0052] For comparison instructions, the function parameter indicates that the element needs to perform a relational operation on two values. Taking W<= D0D1 as an example, this instruction compares the values ​​in data registers D0 and D1. When the value in D0 is less than or equal to the value in D1, the comparison condition is true, the function expression D0<= D1 is TRUE, and power flows through the edge; otherwise, the expression is FALSE, and power flow is blocked. This expression directly transforms the numerical comparison relationship into a logical judgment condition, enabling ladder diagrams to handle complex control logic beyond simple switching quantities.

[0053] For NOT, rising-edge, and falling-edge instructions, the functional parameters of these components indicate that they do not directly act on the original state variables, but rather perform secondary processing on the upstream calculated logical expressions. Taking the NOT instruction INV as an example, if its upstream logical expression is a complex AND / OR combination, then the functional edge expression of this edge is to logically invert that result, i.e., NOT(upstream expression). Taking the rising-edge instruction MEP as an example, if the upstream logical expression is an intermediate result, then the functional edge expression of this edge is to perform rising-edge detection on that result, i.e., P(upstream expression), indicating that it only conducts at the instant the upstream result changes from FALSE to TRUE. Similarly, the functional edge expression of the falling-edge instruction MEF is F(upstream expression), indicating that it only conducts at the instant the upstream result changes from TRUE to FALSE. These processing methods enable ladder diagrams to achieve state inversion and edge capture at intermediate nodes of the logic chain, expanding the flexibility of the control logic.

[0054] For directed functional edge elements whose functional parameters are unidentifiable or belong to unknown instruction types, due to the lack of explicit logical operation rules, they cannot be mapped to specific Boolean expressions or numerical comparison relationships. In this case, the functional edge expression of the edge is assigned a preset truth value, meaning that the edge is always logically connected and does not obstruct or restrict the energy flow in any way. This approach ensures that the conversion process will not be interrupted by encountering undefined instruction types, while minimizing the impact of these unknown components on the overall logic, allowing subsequent calculations to continue.

[0055] In some embodiments, step S302 determines the vertex arrangement order corresponding to each vertex element based on the direction parameter of each directed functional edge element. It's important to note that the direction parameter configured for a directed functional edge element indicates the fixed direction of that edge in the graph, i.e., from the vertex corresponding to the left endpoint to the vertex corresponding to the right endpoint. Based on the direction parameters of all directed functional edge elements, the dependency directions between vertex elements can be analyzed, thereby determining the vertex arrangement order corresponding to each vertex element. This arrangement order requires that for any directed functional edge, its originating vertex is always located before the arriving vertex in the arrangement, essentially forming a linearized sequence from input to output according to the energy flow direction. The purpose of this step is to establish a reasonable computation sequence, ensuring that the subsequent determination of each vertex expression can be performed sequentially according to the logical dependencies. The reason for determining such an arrangement order is that the logical transmission in a ladder diagram has a clear directionality; only by clarifying the sequential dependencies between vertices can we avoid referencing undetermined results when calculating a certain vertex.

[0056] In some embodiments, step S303 involves determining the corresponding vertex expression for each vertex element in turn, according to the vertex arrangement order.

[0057] It should be noted that, following the vertex arrangement order determined in step S302, the corresponding vertex expression is determined sequentially for each vertex element. The vertex expression describes the logical conditions required for energy flow at that connection point. Since the arrangement order ensures that all upstream vertices of each vertex are listed first, when calculating a vertex, the expression of its predecessor vertex is already determined. Based on these determined expressions and the expressions of the functional edges connecting that vertex, the expression of the current vertex can be derived. This step further transforms the topological relationships in the graph structure into specific logical operation results at each connection point, enabling the abstract vertices to ultimately acquire clear logical semantics. The reason for determining these expressions sequentially is that the logical state of a vertex directly depends on its upstream input. Only by ensuring that the upstream input is completed first can the logical expression of the current vertex be correctly derived, thus guaranteeing the coherence of the entire logical derivation process and the correctness of the result.

[0058] Reference Figure 4 According to some embodiments of this application, step S303, which determines the corresponding vertex expression for each vertex element in the order of vertex arrangement, may include: Step S401: For each vertex element that does not have an associated incoming functional edge element, assign a preset truth value to its corresponding vertex expression; where an associated incoming functional edge element refers to a directed functional edge element that is upstream of the vertex element in the directed graph data structure. Step S402: For each vertex element with associated incoming functional edge elements, perform logical combination operations based on the functional edge expression corresponding to each vertex element to determine the expression of each vertex.

[0059] In step S401 of some embodiments, for each vertex element that does not have an associated incoming functional edge element, the corresponding vertex expression is assigned a preset truth value; wherein, the associated incoming functional edge element refers to the directed functional edge element that is upstream of the vertex element in the directed graph data structure. It should be noted that classifying vertices into those with and without upstream inputs during the process of determining the expressions of each vertex according to their arrangement is a necessary method to conform to the energy flow transmission rules of ladder diagrams. For vertices without associated incoming functional edges, that is, when no directed functional edge points to the vertex in the directed graph data structure, these vertices correspond to the left endpoint or left bus position of the leftmost input logic element in the ladder diagram. Since these positions are at the very front of the entire logic chain, with no other logic elements or connection points transmitting energy to them and no preceding logical conditions, the expressions of these vertices are assigned preset truth values. The purpose of this processing is to establish a unified starting point for the entire logic derivation, so that the expression calculations of all subsequent downstream vertices can be carried out based on a definite initial state. The reason for assigning these starting points to truth constants is that the execution logic of the ladder diagram assumes that the left bus always has energy flow conditions. Only when this is true can the subsequent operations of each logic element correctly reflect the actual conduction and cutoff states.

[0060] In step S402 of some embodiments, for each vertex element with associated incoming functional edge elements, a logical combination operation is performed based on the functional edge expression corresponding to each vertex element to determine the expression of each vertex.

[0061] It should be noted that for vertices with associated incoming functional edges—that is, vertices in a directed graph data structure where at least one directed functional edge points to them—these vertices correspond to connection points in a ladder diagram located to the right of an input element, to the left of an output element, or to the right of an output element. These vertices are located in the middle or at the end of a logic chain, and their energy flow state depends on the continuity of the upstream path. Determining the expression for such vertices requires performing logical combination operations based on the expressions of the functional edges pointing to them, as well as the already determined vertex expressions of the vertices originating from these edges.

[0062] Specifically, each incoming functional edge represents a path from an upstream vertex through a specific logic element to the current vertex. The conduction condition of this path is that the energy flow state of the upstream vertex and the functional condition of the logic element are simultaneously satisfied. Therefore, it is necessary to perform a logical AND operation between the expression of the starting vertex and the expression of the corresponding functional edge. If multiple incoming functional edges point to the same vertex, then multiple parallel branches in the corresponding ladder diagram converge at the same node. In this case, the vertex can obtain energy flow if any one branch is conducting. Therefore, it is necessary to perform a logical OR operation on the results of each path. The purpose of this process is to deduce the energy flow state of each downstream connection point step by step based on the determined starting point and upstream intermediate results, ensuring that the logical expression of each vertex can accurately reflect the comprehensive influence of all its upstream paths. The reason why this combination operation must be performed sequentially according to the vertex arrangement order is that the arrangement order itself ensures that when processing a certain vertex, the expressions of all its upstream starting vertices have been determined, so that these results can be directly referenced for combination, avoiding circular dependencies or uncertain results.

[0063] Reference Figure 5 According to some embodiments of this application, step S402, for each vertex element with associated incoming functional edge elements, performs a logical combination operation based on the functional edge expression corresponding to each vertex element to determine the expression of each vertex, and may include: Step S501: For each vertex element with associated incoming functional edge elements, initialize the current vertex expression to a preset truth value. Step S502: Traverse the associated incoming functional edge elements of each vertex element, and determine the operation form of each associated incoming functional edge element based on the corresponding functional parameters; wherein, each associated incoming functional edge element has a corresponding starting vertex element in the directed graph data structure, and the vertex expression of the starting vertex element is the starting vertex expression. Step S503: Based on the operation form of each associated incoming functional edge element, perform operation processing on the corresponding starting vertex expression and functional edge expression to obtain the operation results of each branch. Step S504: Integrate the results of each branch operation into the current vertex expression to determine the updated vertex expressions.

[0064] In some embodiments, step S501 initializes the current vertex expression to a preset truth value for each vertex element that has an associated incoming functional edge element. It's important to note that for vertices with incoming functional edges, the current vertex expression is initialized to a preset truth value before processing begins. This preset truth value serves as the starting point for logical operations, essentially preparing an initial container for receiving the results of subsequent branch operations. In ladder logic, a vertex may simultaneously receive power flows from multiple parallel branches, each requiring separate calculation before being aggregated back to the vertex. Without initializing a base value, subsequent branch results would lack a clear accumulation object. Setting the initial value to a preset truth value means that before any branch input, the vertex is in a known logical state. Each time an incoming edge is processed, the calculation result of that branch is logically operated on with this base value, gradually constructing the complete vertex expression. This approach ensures that even with multiple incoming edges, they can be processed sequentially according to a unified framework, avoiding result confusion.

[0065] In step S502 of some embodiments, the associated incoming functional edge elements of each vertex element are traversed, and the operation form of each associated incoming functional edge element is determined based on the corresponding functional parameters; wherein, each associated incoming functional edge element has a corresponding starting vertex element in the directed graph data structure, and the vertex expression of the starting vertex element is the starting vertex expression. It's important to note that after initialization, it's necessary to traverse all associated incoming functional edge elements of the current vertex. Each incoming functional edge corresponds to a logical path from an upstream vertex to the current vertex, and the functional parameter records the specific type of the functional logic element represented by the edge, such as a normally open contact, normally closed contact, invert instruction, or edge detection instruction. Based on this functional parameter, the operation form that each incoming edge should use in subsequent calculations can be determined. Simultaneously, each of these incoming edges has its own originating vertex element in the directed graph data structure. These originating vertex elements have been pre-calculated in the order they are arranged, yielding their respective vertex expressions, i.e., originating vertex expressions. The purpose of this step is to clarify the operation rules of each incoming path and the known logical state of the upstream endpoint of that path, ensuring that each incoming edge has a clear operation form and known upstream input conditions. The reason for determining the operation form first is that different types of logic elements process energy flow differently; only by identifying the edge type can the correct operation formula be selected.

[0066] In step S503 of some embodiments, based on the operation form of each associated incoming functional edge element, the corresponding starting vertex expression and functional edge expression are processed to obtain the operation results of each branch. It should be noted that, given that the operational form, starting vertex expression, and functional edge expression for each incoming edge are already clearly defined, these three are processed to obtain the results of each branch operation. The specific processing method depends on the determined operational form: If it is a normal functional logic element, the power flow state of the starting vertex and the functional condition of the edge need to be logically ANDed to indicate that the signal must simultaneously satisfy the upstream conduction and the current element condition to pass; If it is a negation instruction, then perform a logical NOT operation on the starting vertex expression; If it is an edge detection instruction, then the corresponding edge detection function is applied to the starting vertex expression.

[0067] It should be understood that the purpose of this step is to transform the abstract graph connections into concrete logical operation values, so that each incoming path produces a clear Boolean result. The reason for differentiated processing based on the operation form is that different components in the ladder diagram have fundamentally different control logics for energy flow. Only by using operation rules that match the component type can the continuity of the path be accurately reflected.

[0068] In some embodiments, step S504 integrates the results of each branch operation into the current vertex expression to determine the updated vertex expressions.

[0069] It's important to note that after obtaining the branch operation results for each incoming edge, these results need to be integrated into the expression of the current vertex to determine the updated final vertex expression. Since multiple incoming edges pointing to the same vertex represent multiple parallel branches in the ladder diagram converging at the same node, the conduction of any branch means that the node receives energy flow. Therefore, the results of each branch operation are aggregated using a logical OR relationship. This step aims to converge the scattered branch calculation results into a unified logical expression, fully representing the energy flow state of the vertex under the combined influence of all upstream paths. The reason for integrating the branch results into the current expression is that the final logical state of a vertex depends on the overall contribution of all incoming paths. Processing any single branch in isolation cannot fully describe the logical conditions of the node; only by aggregating the results of all branches can an accurate vertex expression be obtained.

[0070] It's important to clarify that in a directed graph data structure, in-degree is the number of edges pointing to a given vertex. If no edge points to a vertex, then that vertex has an in-degree of zero. In the graph constructed in this scheme, vertices represent the left and right endpoints of logic elements, and edges represent the logic elements themselves, with a fixed direction from left to right. Therefore, vertices with an in-degree of zero correspond to the left endpoints of the leftmost column of input elements in the ladder diagram, such as the left endpoints of normally open or normally closed contacts. These positions have no upstream connections from other elements and are the starting points for energy flow into the logic circuit. Since these vertices do not depend on any prior computation results, they are defined as truth constants in the logical expressions, serving as the baseline starting point for the entire logic derivation.

[0071] It's important to clarify that out-degree refers to the number of edges originating from a given vertex. If no edge extends outward from a vertex, then that vertex has an out-degree of zero. In the graph structure of this scheme, vertices with an out-degree of zero correspond to the right endpoints of the rightmost column of output elements in the ladder diagram, such as the right endpoints of coils, timers, or function blocks. These positions are the endpoints of power flow and do not connect to other logic elements further downstream. Since these vertices converge the logical results of all upstream paths, they carry the complete logical conditions driving the final output. They are placed last in the topological sorting and serve as the carrier of the final output expression in dynamic programming calculations.

[0072] It should be understood that in-degree and out-degree together describe the position and role of each vertex in the logical chain. Vertices with both in-degree and out-degree are intermediate connection points; they have inputs from upstream and outputs downstream, corresponding in a ladder diagram to intermediate nodes of a serial path or merging points of parallel branches. By calculating in-degree and out-degree, we can determine which link in the logical chain a vertex occupies: an in-degree of zero means it is the starting point, an out-degree of zero means it is the ending point, and both being non-zero means it is an intermediate node connecting upstream and downstream. This distinction directly determines the order of topological sorting and the computation path of dynamic programming, ensuring that the logical expression is derived step-by-step in the correct direction from input to output.

[0073] In some more specific embodiments, based on the directed graph data structure obtained by the aforementioned start-stop circuit, the structure includes vertices V1, V2, V3, V4 and directed functional edges E1, E2, E3, E4. The execution process of step S103 is as follows.

[0074] First, step S301 is executed to determine the functional edge expression for each directed functional edge element. Directed functional edge E1 corresponds to the normally open contact X0, and its functional parameter is identified as a normally open contact type. Based on this functional parameter, the corresponding state variable X0 is directly determined as the functional edge expression, i.e., the expression is X0. Directed functional edge E2 corresponds to the self-locking normally open contact Y0, and its functional parameter is also a normally open contact type; its functional edge expression is Y0. Directed functional edge E3 corresponds to the normally closed contact X1, and its functional parameter is identified as a normally closed contact type. Based on this functional parameter, the state variable X1 is logically inverted, resulting in the functional edge expression NOT(X1). Directed functional edge E4 corresponds to the output coil Y0, and its functional parameter is identified as an output coil type. According to the processing rules of other instructions, its functional edge expression is assigned the preset truth value TRUE. At this point, all four directed functional edges have expressions that can participate in subsequent logical operations. The purpose of this step is to transform the various graphic symbols in the ladder diagram into a unified logical semantic, so that the conduction conditions of each element are clearly defined in the form of mathematical expressions, providing directly callable edge conditions for the subsequent calculation of vertex expressions.

[0075] Then, step S302 is executed to determine the order of each vertex element. In this directed graph data structure, vertex V1 is formed by merging the left endpoints of normally open contact X0 and self-locking normally open contact Y0. No directed functional edges point to this vertex, meaning there are no associated incoming functional edge elements, and its in-degree is 0. This corresponds to the case where the left endpoint of all leftmost column input logic elements corresponds to a vertex with an in-degree of 0. Therefore, V1 is added to the order first. Vertex V4 is the right endpoint of output coil Y0. No directed functional edges originate from this vertex, and its out-degree is 0. This corresponds to the case where the right endpoint of all rightmost column output logic elements corresponds to a vertex with an out-degree of 0. Therefore, V4 is placed last. Vertices V2 and V3 are intermediate vertices, where the incoming edge of V2 comes from V1, and the incoming edge of V3 comes from V2. Based on this dependency, the vertex order is determined to be V1, V2, V3, V4. The purpose of this step is to establish a linear computation sequence that conforms to the energy flow direction, ensuring that the expression of the upstream starting vertex of each vertex has been determined when it is processed, thereby avoiding computational errors caused by reverse dependency.

[0076] Next, steps S303 are executed sequentially according to this arrangement to determine the vertex expression for each vertex. For vertex V1, since it has no associated incoming functional edge elements, it is a vertex with an in-degree of 0. According to the content of step S401, its vertex expression is assigned the preset truth value TRUE. This step corresponds to the processing of defining the logical expressions of all vertices with an in-degree of 0 as TRUE. Its purpose is to establish a unified starting point for the entire logical derivation, so that the expression calculation of all subsequent downstream vertices can be carried out based on a definite initial state.

[0077] For vertex V2, which has two associated incoming functional edges E1 and E2, and whose in-degree is not 0, logical combination operation is performed according to step S402. First, according to step S501, the vertex expression of V2 is initialized to a preset true value, serving as the starting container for receiving the results of each branch operation. Then, according to step S502, its two incoming functional edges are traversed: the functional parameter of E1 is a normally open contact, and its operation mode is determined to be a normal logical AND operation; the functional parameter of E2 is also a normally open contact, and its operation mode is also a normal logical AND operation. In step S503, for E1, its starting vertex is V1, the starting vertex expression is TRUE, and the functional edge expression is X0. The two are logically ANDed to obtain the branch operation result X0; for E2, its starting vertex is also V1, the starting vertex expression is TRUE, and the functional edge expression is Y0. The two are logically ANDed to obtain the branch operation result Y0. Finally, in step S504, the results of each branch operation are integrated into the current vertex expression. Since the two incoming edges correspond to two parallel branches in the ladder diagram that converge at the same node, the node can receive power flow if either branch is active. Therefore, the results of each branch are summarized using a logical OR relationship, resulting in the vertex expression of V2 as X0 OR Y0. This result accurately reflects the logical relationship in the parallel structure where the start button and the self-locking contact jointly drive the intermediate node.

[0078] For vertex V3, there is an associated incoming functional edge element E3. Following the processing flow in step S402, this incoming edge is traversed after initialization. The functional parameter of E3 is a normally closed contact, and its operation involves logical negation, corresponding to the normally closed contact functional edge expression NOT(X1). The originating vertex of this edge is V2, and its originating vertex expression is X0 OR Y0. Following step S503, the originating vertex expression and the functional edge expression are logically ANDed to obtain the branch operation result (X0 OR Y0) AND NOT(X1). Since V3 has only one incoming edge, after integration according to step S504, this result is the vertex expression of V3. This result accurately reflects the logical relationship in the series structure that the converging signal of parallel branches must pass through the normally closed contact of the stop button to be transmitted forward.

[0079] For vertex V4, there is an associated incoming functional edge element E4. After initialization, this edge is traversed. The functional parameter of E4 is the output coil. For other instruction types, its functional edge expression is the preset truth value TRUE. The starting vertex of this edge is V3, and the starting vertex expression is (X0 OR Y0) AND NOT(X1). Since performing a logical AND operation between TRUE and any expression does not change the logical result of the expression, the branch operation result obtained after the operation processing in step S503 is (X0 OR Y0) AND NOT(X1). In step S504, the current vertex expression is integrated, and the vertex expression of V4 is finally determined to be (X0 OR Y0) AND NOT(X1). This expression completely describes all the logical conditions that need to be satisfied to drive the output coil Y0, that is, the start button X0 is pressed or the self-locking contact Y0 is closed, and the stop button X1 is not pressed. This is completely consistent with the actual control logic of the start-stop circuit. Thus far, step S103 has completed the generation of logical expressions for each vertex and edge based on the directed graph data structure, providing a precise mathematical basis for the subsequent construction of tree-shaped logic blocks and instruction table programs.

[0080] In some embodiments, step S104 involves logically sorting each logical expression to construct a tree-shaped logical block. It should be noted that the logical expressions are logically sorted, and a tree-like logic block is constructed based on this. The logical sorting is based on the row coordinates of the logic elements corresponding to each output expression in the original ladder diagram, arranging the output expressions into an ordered list from top to bottom. On this basis, expressions with the same common prefix are grouped, their longest common prefix is ​​extracted as the common condition, and the remaining parts are branch outputs. Through recursive processing, the flat set of expressions is reconstructed into a tree structure with outputs as roots, common conditions as internal nodes, and branches as subtrees. The purpose of this step is to identify and restore the inherent parallel and series hierarchical relationships in the ladder diagram, and to explicitly represent the common input conditions that may be shared among multiple outputs as a tree-like branch structure. The reason for sorting and tree reconstruction is that the set of logical expressions obtained in the previous step is flat and fails to reflect the structural reuse relationship when multiple outputs share the same precondition. The actual logic of a ladder diagram often presents a tree pattern where a common condition is followed by multiple branch outputs. By reconstructing this hierarchical structure, a foundation can be laid for generating a compact instruction sequence later.

[0081] Reference Figure 6 According to some embodiments of this application, step S104, which performs logical sorting on each logical expression to construct a tree-shaped logical block, may include: Step S601: Extract each output endpoint expression from multiple logical expressions; wherein, the output endpoint expression is the logical expression corresponding to each functional logical element at the output endpoint. Step S602: Based on the position of the functional logic element corresponding to each output endpoint expression in the ladder diagram program, sort the output endpoint expressions to obtain a logic sequence list; Step S603: Logically sort each logical expression based on the logical sequence list to construct a tree-shaped logical block.

[0082] In step S601 of some embodiments, each output endpoint expression is extracted from multiple logical expressions; wherein, the output endpoint expression is the logical expression corresponding to each functional logic element at the output endpoint. It's important to note that from the previously generated logical expressions, those corresponding to the output endpoints are selected. In a ladder diagram, output endpoints can refer to the right-hand connection endpoints of functional logic elements such as coils, timers, and counters. These locations are the final convergence points of energy flow, directly determining the state of the programmable logic controller's output. Output endpoint expressions are the logical expressions corresponding to these output endpoints. They represent the complete logical conditions driving the output, integrating all logical operation results passed from the input through various series and parallel paths. Extracting these expressions clarifies which logical expressions are the final output results, distinguishing between expressions at intermediate connection points and the final output expressions, thus providing a foundation for organizing the output logic according to the original program structure. The reason for separately extracting output endpoint expressions is that a ladder diagram can contain multiple rungs, each potentially corresponding to one or more outputs. Only by identifying these final outputs can the multi-output structure of the original ladder diagram be organized in an orderly manner.

[0083] In step S602 of some embodiments, based on the position order of the functional logic elements corresponding to each output endpoint expression in the ladder diagram program, the output endpoint expressions are sorted to obtain a logic sequence list; It's important to note that after extracting the expressions for each output endpoint, the expressions are sorted according to the positional order of their corresponding functional logic elements in the original ladder diagram program. Positional order refers to the arrangement of functional logic elements in the ladder diagram, which can be represented by row coordinates from top to bottom. Sorting the output endpoint expressions according to this positional order yields a logic sequence list. This sorting restores the sequential order of multiple outputs in the original ladder diagram, arranging the output results, which were originally calculated separately in the diagram structure, into a table according to the reading order preferred by engineers. The reason for sorting based on positional order is that, as a graphical program, the ladder diagram's multiple rungs can be executed in a top-to-bottom order. Maintaining this order helps ensure consistency with the original program structure during subsequent processing, facilitating understanding and debugging.

[0084] In some embodiments, step S603 involves logically sorting each logical expression based on a logical sequence list to construct a tree-shaped logical block.

[0085] It should be noted that, based on the logical sequence list obtained in step S602, the logical expressions are logically ordered to construct a tree-shaped logical block. This logical ordering is not a simple linear arrangement, but rather organizes the flat set of expressions into a hierarchical tree structure based on the logical dependencies and shared common conditions between expressions. The logical sequence list provides the order in which each output is processed. Based on this, it analyzes whether there are shared common input conditions among the output expressions, grouping outputs with the same preconditions into the same branch, forming a tree-shaped organization with common conditions as internal nodes and each output as terminal leaves. The purpose of constructing the tree-shaped logical block is to make the common preconditions that may exist between multiple outputs explicit, giving the originally scattered set of expressions a clear hierarchical structure. This tree structure is necessary because multiple outputs in a ladder diagram often share some input conditions. By identifying and reconstructing the hierarchical relationship between these common conditions and branch outputs, a foundation can be laid for generating a compact instruction sequence, avoiding the repeated calculation of the same common conditions.

[0086] Reference Figure 7 According to some embodiments of this application, step S603, which logically sorts each logical expression based on a logical sequence list to construct a tree-shaped logical block, may include: Step S701: Perform common logic identification on the logical sequence list to divide the logical sequence list into multiple groups of common expressions with common logical conditions; Step S702: Determine the largest common logical subexpression from the group of common expressions; Step S703: Construct the tree branch nodes of the tree logic block based on the largest common logical expression; Step S704: Remove the corresponding largest common logical subexpression from each common expression group to form multiple branch expression groups; Step S705: Each branch expression group is taken as the updated common expression group, and the largest common logical expression is re-determined from the common expression group. Step S706: Based on the newly determined maximum common logical expression, construct the next-level tree branch node corresponding to the tree branch node; Step S707: Remove the newly determined largest common logical expression from the updated common expression group to form multiple branch expression groups. Return to execution and use each branch expression group as an updated common expression group until the logical sequence list is traversed.

[0087] In some embodiments, step S701 involves identifying common logic in the logical sequence list to divide the logical sequence list into multiple groups of common expressions with common logical conditions. It should be noted that although the multiple output endpoint expressions in the logic sequence list are arranged according to the positional order of the original ladder diagram, they may share structural relationships. The purpose of common logic identification for this list is to discover which output expressions share the same preconditions and group these expressions with common conditions into the same common expression group. This identification is based on comparing the logical structures of the expressions to find their common prefixes.

[0088] In ladder diagrams, multiple output coils are often driven in parallel by the same set of pre-contacts before being branched off. This parallel structure is reflected at the expression level as multiple output expressions sharing the same pre-contact logic conditions. By dividing the logic sequence list into multiple common expression groups, the originally linear expression sequence can be reorganized according to logical affinity, providing a grouping basis for subsequently constructing a hierarchical tree structure.

[0089] In some embodiments, step S702 involves determining the largest common logical subexpression from the group of common expressions; It's important to further determine the largest common logical precondition shared by all expressions in the group. The largest common logical precondition is the longest logical prefix contained in every expression within the group that cannot be extended further outwards. It represents the most complete common precondition driving all outputs in the group. For example, if multiple output expressions in the group begin with the same combination of serial contacts, then this combination is the largest common logical precondition. Determining this precondition helps to precisely identify the shared logical core of the group's outputs, clearly distinguishing it from the branch conditions specific to each subsequent output.

[0090] In some embodiments, step S703 involves constructing tree branch nodes of the tree logic block based on the maximum common logic expression. It should be noted that, based on the determined largest common logical expression, the tree branch nodes of the tree logic block are constructed. This node is located upstream of all outputs in the tree structure, serving as the common ancestor node that governs subsequent branches. This node itself does not correspond to a specific output, but rather to the preconditions that a group of outputs commonly depend on. It plays a bridging role in the tree structure: its upstream connects to more basic input conditions, and its downstream branches into multiple child nodes, each corresponding to a different output path.

[0091] In some embodiments, step S704 involves removing the corresponding largest common logical subexpression from each common expression group to form multiple branch expression groups. It should be noted that after the common conditions are extracted and constructed as nodes, the largest common logical expression is removed from each group of common expressions to form multiple groups of branch expressions. The removal operation involves eliminating the extracted common prefix from the logical structure of each expression within the group; the remaining part represents the unique logical conditions that the output must satisfy after the common conditions are met. These remaining expressions constitute the groups of branch expressions, representing the independent paths branching off from the common nodes.

[0092] In step S705 of some embodiments, each branch expression group is used as an updated common expression group, and the largest common logical expression is re-determined from the common expression group. It should be noted that, since the branch expression group may still contain multiple expressions, and these expressions may continue to have deeper levels of common logical conditions, step S705 treats these branch expression groups as updated common expression groups and re-determines the largest common logical expression from them. The purpose of this recursive processing is to uncover multi-level common conditions in the logical structure, because the parallel structures in the ladder diagram may be nested, that is, large parallel structures may contain smaller parallel structures.

[0093] In some embodiments, step S706 involves constructing a tree branch node corresponding to the next level of the tree branch node based on the newly determined maximum common logical expression. It should be noted that, based on the newly determined largest common logical expression, corresponding second-level tree branch nodes are constructed. These second-level nodes are located downstream of the aforementioned common branch nodes, representing more detailed common preconditions. Through this layer-by-layer construction, the tree structure gradually expands downwards from the root node, with each level of nodes corresponding to a certain level of common logical conditions.

[0094] In some embodiments, step S707 involves removing the newly determined largest common logical expression from the updated common expression group to form multiple branch expression groups, and then returning to execute each branch expression group as an updated common expression group until the logical sequence list is traversed completely.

[0095] It should be noted that, after removing the newly determined largest common logical expression from the updated common expression group, a new branch expression group is formed, and the process returns to process each branch expression group as an updated common expression group. This process is repeated until each branch is reduced to a single expression, from which no more common expressions can be extracted. At this point, the entire logical sequence list has been traversed. This recursive descent approach gradually decomposes the originally flat multiple output expressions into multi-level combinations of common conditions and branch outputs, ultimately forming a tree-like logical block that fully reflects the parallel and series hierarchical relationships in the ladder diagram.

[0096] In some specific embodiments, a ladder diagram program contains two ladder levels. The first line, from top to bottom, consists of normally open contacts X0, X1, and X2 connected in series, ultimately driving the output coil Y0; the second line, from top to bottom, consists of normally open contacts X0, X1, and X3 connected in series, ultimately driving the output coil Y1. In the aforementioned steps, after performing dynamic programming calculations based on the directed graph data structure, the complete logical expression for driving the output coil Y0 is obtained as X0 AND X1 AND X2, and the complete logical expression for driving the output coil Y1 is X0 AND X1 AND X3.

[0097] In step S104, step S601 can be executed first to extract the output endpoint expressions from the multiple logical expressions mentioned above. Here, the expressions for driving output coil Y0 (X0 AND X1 AND X2) and driving output coil Y1 (X0 AND X1 AND X3) are extracted. These two expressions are the output endpoint expressions, corresponding to the logical expressions calculated from all output vertices. The purpose of this extraction operation is to distinguish the final output result from the expressions of intermediate connection points, clarifying which expressions need to be further organized into a tree structure of output logic.

[0098] Then, step S602 is executed, sorting the output endpoint expressions based on the positional order of the corresponding functional logic elements in the ladder diagram program. Output coil Y0 is located in the first row of the ladder diagram, and output coil Y1 is located in the second row. Following the top-to-bottom row coordinate order, the two output endpoint expressions are arranged into a logical sequence list, in the order X0AND X1 AND X2, X0 AND X1 AND X3. This sorting process generates an ordered list by using the row coordinates of the corresponding logic elements in the ladder diagram as a reference, from top to bottom. Its purpose is to restore the sequential order of multiple outputs in the original ladder diagram, ensuring that subsequent processing remains consistent with the original program structure.

[0099] Next, step S603 is executed to construct a tree-shaped logic block based on the logic sequence list. In step S701, common logic is identified in the logic sequence list. The logical structures of the two expressions X0 AND X1 AND X2 and X0 AND X1 AND X3 are analyzed, and it is found that they have the same common prefix expression X0 AND X1. Therefore, these two expressions are divided into the same common expression group. This operation corresponds to grouping expressions with the same common prefix expression into the same subgroup for an ordered list of logical expressions. In step S702, the largest common logical expression, X0 AND X1, is determined from the common expression group as the common condition. The largest common prefix expression is then calculated as the common condition. In step S703, based on the largest common logical expression X0 AND X1, the tree branch node of the tree-shaped logic block is constructed. This node serves as the root node of the tree structure, representing the common precondition shared by the two outputs. In step S704, the corresponding largest common logical subexpression X0 AND X1 is removed from the group of common expressions. The common prefix is ​​subtracted from the expressions X0 AND X1 AND X2 to obtain the remaining expression X2, and subtracted from the expressions X0 AND X1 AND X3 to obtain the remaining expression X3. This forms a group of branch expressions containing X2 and X3. This removal operation corresponds to subtracting this common subexpression from all expressions in this group, and the resulting set of remaining expressions is the branch output.

[0100] In step S705, since the branch expression group contains two expressions, X2 and X3, and the number is greater than 1, each branch expression group is used as the updated common expression group, from which the largest common logical expression is re-determined. Common logical identification is performed on X2 and X3, and it is found that there are no non-trivial common prefixes between them; therefore, their respective largest common logical expressions are themselves. This recursive process corresponds to the branch output; if it contains more than 1 expressions, the grouping and common prefix extraction operations are repeated for this branch output. In step S706, based on the re-determined results, the tree branch node is constructed to correspond to the next level of the tree branch node. Since X2 and X3 are independent, they are directly used as the tree terminal nodes. In step S707, after removing the determined parts, each branch expression has converged to a single expression, and it is impossible to continue extracting common expressions. The logical sequence list is traversed, and the algorithm converges. The resulting tree-shaped logic block takes X0 AND X1 as the root node and branches down into two terminal branches, X2 and X3, which correspond to the final driving conditions of the output coils Y0 and Y1, respectively. This completely restores the parallel and series hierarchical structure of the two outputs in the ladder diagram, which share the front contacts X0 and X1 and are then driven by independent contacts X2 and X3 respectively.

[0101] In some embodiments, step S105 involves traversing the tree logic blocks to generate multiple instruction list program fragments. It should be noted that the constructed tree-like logic blocks are traversed to generate multiple instruction list program fragments. During the traversal, for common condition nodes in the tree-like logic blocks, corresponding load-type instructions and operation instructions are generated; for branch output nodes, corresponding branch instruction sequences are generated. After traversal, each tree-like logic block forms an instruction list program fragment containing only logical instructions, variable names, and opcodes. These fragments do not carry any graphical layout information of the original ladder diagram. The purpose of this step is to transform the hierarchical logical expression into a low-level text instruction sequence standard in the industrial control field, making the pure logic structure closer to an executable text program form. The instruction list was chosen as the generation target because it is a compact textual representation; its instructions themselves only express logical operations and program control, naturally lacking graphical attributes, and can serve as an effective carrier of pure logical data.

[0102] Reference Figure 8 According to some embodiments of this application, the tree logic block includes multiple tree branch chains, each tree branch chain containing several levels of tree branch nodes and tree terminal nodes. Step S105 traverses the tree logic block to generate multiple instruction list program fragments, which may include: Step S801: For each tree branch chain, traverse each tree branch node and the tree terminal node; Step S802: During the traversal of tree branch nodes and tree terminal nodes, the logical expression associated with each tree branch node is determined as a branch logical expression, and the logical expression associated with each tree terminal node is determined as a port logical expression. Step S803: According to each tree branch chain, perform instruction mapping processing on the branch logic expression and port logic expression to obtain each instruction table program fragment.

[0103] It's important to clarify that a tree-structured logic block is composed of multiple tree-branch chains. Each chain contains several levels of tree branch nodes and one tree terminal node. The tree branch nodes correspond to the common logic conditions identified in the ladder diagram; they are located at the middle levels of the chain and are responsible for carrying the pre-processing logic shared by multiple downstream paths. The tree terminal node is located at the very end of each chain, corresponding to a specific output port and carrying the complete logic conditions driving that output. This hierarchical structure organizes the originally flat multiple output expressions according to the relationship between common conditions and branch outputs, making the logical dependencies present a clear tree-like structure.

[0104] In some embodiments, step S801 involves traversing each tree branch node and the tree terminal node for each tree branch chain. It's important to note that for each tree-like branch chain, each branch node and the final node are traversed sequentially. The purpose of this traversal is to systematically access the logical information carried by each node according to the hierarchical relationship of the tree structure, ensuring that the complete logical path from the root node to the final node is covered. Since there are clear upstream and downstream dependencies between nodes in the tree-like branch chain, the logical conditions of upstream nodes must be processed before those of downstream nodes. Therefore, the traversal process follows the direction from common conditions to the branch's final node, delving deeper layer by layer until the final node is reached. This traversal provides an ordered processing path for subsequently converting the logical expression of each node into a sequence of instructions.

[0105] In step S802 of some embodiments, during the traversal of tree branch nodes and tree terminal nodes, the logical expression associated with each tree branch node is determined as a branch logical expression, and the logical expression associated with each tree terminal node is determined as a port logical expression. It's important to clarify that the logical expressions associated with each branch node in the tree structure are defined as branch logical expressions, while the logical expressions associated with the terminal nodes are defined as port logical expressions. Branch logical expressions correspond to the logical content carried by common condition nodes, representing a set of shared preconditions for downstream outputs. Port logical expressions correspond to the logical content carried by terminal nodes, representing the complete driving logic for a specific output port. This distinction is necessary during traversal because branch nodes and terminal nodes have fundamental differences in logical function: the former are the branching or converging points of the logical path, and their expressions need to be shared or reused by multiple downstream nodes; the latter are the endpoints of the logical path, and their expressions directly determine the final state of a particular output port. Clearly distinguishing between these two types of expressions allows for the adoption of appropriate processing strategies based on the node type when generating instructions.

[0106] In step S803 of some embodiments, the branch logic expression and port logic expression are processed by instruction mapping according to each tree branch chain to obtain each instruction table program fragment.

[0107] It should be noted that, according to each tree branch chain, the aforementioned branch logic expressions and port logic expressions undergo instruction mapping processing to obtain each instruction table program fragment. Instruction mapping processing refers to converting purely logical expressions into specific instruction sequences in the instruction table of the industrial control field. For example, mapping logical AND operations to AND instructions, logical OR operations to OR instructions, and variable loading to load instructions, etc. Since each tree branch chain corresponds to a complete logical path from the common condition to the final output, after mapping the expressions of all nodes in the chain, the resulting instruction sequence naturally constitutes a logically coherent program fragment. The purpose of this step is to transform the abstract logic tree structure into an executable set of text instructions, turning purely mathematical logical expressions into a standard low-level programming language form in the industrial control field. The reason for mapping according to the tree branch chains is that each chain represents an independent output logic path, and processing them separately ensures the logical integrity of each output and avoids instruction confusion between different output paths.

[0108] In some embodiments, step S106 involves assembling the instruction table program fragments to obtain the corresponding complete instruction table program. It should be noted that assembling the various instruction list program fragments into a complete instruction list program is necessary. Since each tree logic block corresponds to the logic of one or more output coils, the generated program fragments are scattered. They need to be connected into a coherent, complete program using predefined connection instructions, according to the logical dependencies and variable passing relationships between the fragments. The purpose of this step is to integrate the scattered logic block fragments into a complete instruction list program with a unified execution order, ensuring that the connection relationships and variable sharing between the output logic are handled correctly. Assembly is necessary because although each tree logic block expresses independent output logic, a complete ladder diagram program contains multiple outputs. These outputs may share variables or have execution order requirements. Only by assembling the fragments in an orderly manner can the complete control flow expressed by the original ladder diagram be restored.

[0109] In some more specific embodiments, if a ladder diagram program contains three ladder levels, each row has the same pre-connection conditions. The first row, from top to bottom, consists of normally open contacts X0, X1, and X2 connected in series, ultimately driving the output coil Y0; the second row consists of normally open contacts X0, X1, and X3 connected in series, ultimately driving the output coil Y1; the third row consists of normally open contacts X0, X1, and X4 connected in series, ultimately driving the output coil Y2.

[0110] In the aforementioned steps, based on dynamic programming calculation and branch strategy algorithm, the tree logic block corresponding to the ladder diagram is obtained: its common condition is X0 AND X1, and the branch output set contains three branches, namely X2 driving Y0, X3 driving Y1, and X4 driving Y2.

[0111] During the generation of the instruction list program fragment, for the common condition X0 AND X1, which has an AND operator at the top, according to the processing rules, the program corresponding to the first sub-expression X0 is generated first. Since X0 is a single logical element, i.e., a normally open contact, its corresponding functional parameter is mapped to a load instruction, generating LD X0. Then, the program corresponding to the second sub-expression X1 is generated. Since X1 is also a single logical element, i.e., a normally open contact, and is the second sub-expression of the AND operator, the optimization rules apply, directly generating the AND operation instruction AND X1, without needing to add an ANDB instruction. Thus, the instruction list program fragment corresponding to the common condition is LDX0 followed by AND X1. For the branch output set, since the number of branches is 3, which is greater than 2, according to the processing rules, an MPP instruction is added before generating the first branch program, an MRD instruction is added before generating the second branch program, and an MPS instruction is added before generating the last branch program.

[0112] The first branch corresponds to X2 driving Y0, and its program fragment is LD X2 followed by OUT Y0; The second branch corresponds to X3 driving Y1, and its program fragment is LD X3 followed by OUT Y1; The third branch corresponds to X4 driving Y2, and its program fragment is LD X4 followed by OUT Y2.

[0113] After combining the linker instructions with each branch program, the three branch segments are MPP, LD X2, OUT Y0, MRD, LD X3, OUT Y1, and MPS, LD X4, OUT Y2.

[0114] In step S106, the above instruction list program fragments are assembled into the corresponding complete instruction list program. The assembly process follows the order of common condition first, followed by each branch, sequentially connecting the common condition fragment with each branch program fragment. Specifically, the common condition fragment composed of LD X0 and AND X1 is placed at the beginning position, and then the first branch fragment MPP, LD X2, OUT Y0, the second branch fragment MRD, LD X3, OUT Y1, and the third branch fragment MPS, LD X4, OUT Y2 are sequentially concatenated to form the complete instruction list program: LD X0; AND X1; MPP; LD X2; OUT Y0; MRD; LD X3; OUT Y1; MPS; LD X4; OUT Y2.

[0115] It should be understood that the purpose of assembling instruction list program segments is to integrate the scattered calculation of common conditions and the output logic of each branch into a coherent and sequentially executable instruction sequence, so that the originally separately generated program segments form a logical closed loop, ensuring that common conditions are correctly saved, reused and released between multiple branches through stack instructions, thereby completely restoring the control logic of multiple outputs in the ladder diagram that share preconditions and are driven independently.

[0116] In some embodiments, step S107 involves serializing the complete instruction list program to obtain a corresponding text format data file.

[0117] It's important to note that the complete instruction list program undergoes serialization to obtain a corresponding text-formatted data file. Serialization is the process of encoding and outputting the structured data of the instruction list program according to specific text format rules. It can be represented as structured text containing data fields such as instruction opcodes, operands, and variable information. The purpose of this step is to generate a final text-formatted file that can be stored, transmitted, or used as training data. Serialization is necessary because although the instruction list program is already a collection of text instructions, it still needs to be converted into a standardized data file format before it can be read, parsed, and processed in batches by external systems, thus completing the full conversion from graphical ladder diagrams to plain text data.

[0118] In some more specific embodiments, if the complete program of the instruction table obtained by the aforementioned assembly process includes the following instruction sequence: load normally open contact X0, AND normally open contact X1, pop and restore stack, load normally open contact X2, output to coil Y0, read and restore stack, load normally open contact X3, output to coil Y1, push stack, load normally open contact X4, output to coil Y2.

[0119] In step S107, the complete instruction table program is serialized to generate a corresponding text-formatted data file. Specifically, a JSON data structure is defined, which contains an instruction array. Each element in the array corresponds to an instruction in the instruction table, and the opcode and operand of the instruction are recorded in key-value pairs. For example, the instruction to load normally open contact X0 is serialized into a JSON object containing the opcode field LD and the variable parameter field X0; the instruction to AND normally open contact X1 is serialized into a JSON object containing the opcode field AND and the variable parameter field X1; the stack pop instruction MPP is serialized into a JSON object containing the opcode field MPP; and the instruction to output to coil Y0 is serialized into a JSON object containing the opcode field OUT and the variable parameter field Y0. Following the same rules, the stack read restoration instruction MRD, load normally open contact X3, output to coil Y1, stack push instruction MPS, load normally open contact X4, and output to coil Y2 are sequentially serialized into corresponding JSON objects. Finally, all JSON objects are organized into a structured instruction array and encapsulated in the top-level JSON object to form a complete text format data file.

[0120] It should be understood that serialization processing corresponds to serializing the complete IL instruction list program to generate a JSON file. During this process, the generated text-formatted data file only contains opcode and variable information converted from the instruction list program, such as opcodes like LD, AND, MPP, MRD, MPS, and OUT, and addressing status variables like X0, X1, X2, X3, X4, Y0, Y1, and Y2. The file does not contain any data fields recording the original ladder diagram's graphical layout, such as the row and column coordinates of each logic element in the ladder diagram, the direction of geometric connections between elements, or visual attributes like the size or color of contacts and coils. This content structure completely eliminates any graphical layout information from the original ladder diagram, ensuring that the final output text-formatted data file retains only the program's logical control semantics, providing a high-quality data foundation purely based on logical instructions for the subsequent training of large-scale language models in the industrial control field.

[0121] Reference Figure 9 , Figure 9 This illustration shows the hardware structure of an electronic device according to another embodiment. The electronic device may include: The processor 901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 902 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902, and the processor 901 calls and executes the text generation method of the ladder diagram program in the embodiments of this application. The input / output interface 903 is used to implement information input and output; The communication interface 904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 905 transmits information between various components of the device (e.g., processor 901, memory 902, input / output interface 903, and communication interface 904); The processor 901, memory 902, input / output interface 903, and communication interface 904 are connected to each other within the device via bus 905.

[0122] This application also provides a computer program product, which includes a computer program. A processor of a computer device reads and executes the computer program, causing the computer device to perform the text-based generation method for the ladder diagram program described above.

[0123] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “including,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0124] It should be understood that in this disclosure, "at least one item" means one or more, and "more than one" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0125] It should be understood that in the description of the embodiments of this application, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0126] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0127] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0129] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this disclosure. The aforementioned storage medium may include: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code.

[0130] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different technical effects.

[0131] The above is a detailed description of the embodiments of this disclosure. However, this disclosure is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this disclosure. All such equivalent modifications or substitutions are included within the scope defined by the claims of this disclosure.

Claims

1. A method for generating text-based ladder diagram programs, characterized in that, include: Obtain the ladder diagram to be converted; The ladder diagram program is parsed and transformed to obtain the corresponding directed graph data structure; wherein, the directed graph data structure includes vertex elements and directed functional edge elements, and the directed functional edge elements are configured with corresponding direction parameters and function parameters; Based on the directed graph data structure, multiple logical expressions corresponding to each vertex element and each directed functional edge element are generated, the logical expressions including vertex expressions and functional edge expressions; wherein, generating multiple logical expressions corresponding to each vertex element and each directed functional edge element based on the directed graph data structure includes: For each directed functional edge element whose functional parameter is a normally open contact, the state value expression is determined based on the corresponding state variable, and used as the expression for each functional edge. For each directed functional edge element whose functional parameter is a normally closed contact, a logical inversion process is performed based on the corresponding state variable to obtain each logical inversion expression, which is used as the expression for each functional edge. For each directed functional edge element whose functional parameter is an edge contact, edge state detection is performed based on the corresponding state variable to obtain each edge detection expression, which is used as the expression for each functional edge. For each directed functional edge element whose functional parameter is a comparison instruction, numerical relationship operations are performed based on the corresponding comparison object to obtain each comparison operation expression, which is used as the expression of each functional edge. For each directed functional edge element whose functional parameter is an inversion instruction, the corresponding associated logical expression is logically inverted to serve as the functional edge expression. For each directed functional edge element whose functional parameter is a rising edge instruction, the corresponding associated logic expression is subjected to rising edge state detection to serve as the functional edge expression. For each directed functional edge element whose functional parameter is a falling edge instruction, the corresponding associated logic expression is subjected to falling edge state detection to serve as the functional edge expression. For each directed functional edge element whose functional parameter is of unknown instruction type, the expression of each functional edge is assigned a preset truth value; Based on the direction parameters of each of the directed functional edge elements, the vertex arrangement order corresponding to each of the vertex elements is determined; For each vertex element that does not have an associated incoming functional edge element, its corresponding vertex expression is assigned a preset truth value; wherein, the associated incoming functional edge element refers to the directed functional edge element that is upstream of the vertex element in the directed graph data structure; For each vertex element that has the associated incoming functional edge element, a logical combination operation is performed based on the functional edge expression corresponding to each vertex element to determine each vertex expression; The logical expressions are logically sorted to construct a tree-shaped logical block; Traverse the tree-shaped logic blocks to generate multiple instruction list program fragments; Assemble the program fragments of each instruction list to obtain the corresponding complete instruction list program; The complete program of the instruction table is serialized to obtain the corresponding text format data file.

2. The method according to claim 1, characterized in that, The step of parsing and converting the ladder diagram program to obtain the corresponding directed graph data structure includes: Functional element identification is performed on the ladder diagram program to determine multiple functional logic elements and connection endpoint information between each functional logic element; The vertex elements are constructed based on the connection endpoint information between each of the functional logic elements; The directed functional edge element is constructed according to the positional order of the multiple functional logic elements in the ladder diagram program. The directed graph data structure is formed based on the vertex elements and the directed functional edge elements.

3. The method according to claim 2, characterized in that, The step of logically sorting each of the logical expressions to construct a tree-shaped logical block includes: Extract each output endpoint expression from the multiple logical expressions; wherein, the output endpoint expression is the logical expression corresponding to each functional logical element at the output endpoint; Based on the position of the functional logic element corresponding to each output endpoint expression in the ladder diagram program, the output endpoint expressions are sorted to obtain a logic sequence list. The logical expressions are logically sorted based on the logical sequence list to construct the tree-shaped logical block.

4. The method according to claim 3, characterized in that, The step of logically sorting each of the logical expressions based on the logical sequence list to construct the tree-shaped logical block includes: The logical sequence list is subjected to common logic identification in order to divide the logical sequence list into multiple groups of common expressions with common logical conditions; The largest common logical subexpression is determined from the group of common expressions; Based on the maximum common logical expression, construct the tree branch nodes of the tree logic block; For each of the aforementioned common expression groups, the corresponding largest common logical expression is removed to form multiple branch expression groups; Each of the branch expression groups is used as the updated common expression group, and the largest common logical expression is re-determined from the common expression group; Based on the newly determined maximum common logical expression, construct the next-level tree branch node corresponding to the tree branch node; Remove the newly determined largest common logical expression from the updated common expression group to form multiple branch expression groups. Return to execution and use each branch expression group as the updated common expression group until the logical sequence list is traversed.

5. The method according to claim 4, characterized in that, The tree-structured logic block includes multiple tree-structured branch chains, each of which contains several levels of tree-structured branch nodes and tree-structured terminal nodes. Traversing the tree-structured logic block to generate multiple instruction list program fragments includes: For each of the tree-shaped branch chains, traverse each of the tree-shaped branch nodes and the tree-shaped terminal node; During the traversal of the tree branch nodes and the tree terminal nodes, the logical expression associated with each tree branch node is determined as a branch logical expression, and the logical expression associated with each tree terminal node is determined as a port logical expression. According to each of the tree-shaped branch chains, the branch logic expression and the port logic expression are processed by instruction mapping to obtain each of the instruction table program fragments.

6. An electronic device, characterized in that, include: The system includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the textual generation method for ladder diagram programs as described in any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that, The storage medium stores a program that is executed by a processor to implement the textual generation method of the ladder diagram program as described in any one of claims 1 to 5.

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