External DDR-free ZYNQ chip online upgrading method and system

Abstract

The application discloses a ZYNQ chip online upgrading method and system without external DDR, and belongs to the technical field of embedded system online upgrading. The method comprises the following steps: a ZYNQ chip is not connected with an external DDR memory, and a program runs in an OCM inside the chip. After power-on, BootRom loads FSBL to AXI_SRAM for execution, FSBL loads BootLoader to AHB_SRAM and jumps; after BootLoader is started, whether an upgrade file is received is detected, if the upgrade file is received, the upgrade file is written into an EMMC temporary storage area and restarted, otherwise, whether there is to-be-upgraded PL / PS data in the EMMC is detected, if the to-be-upgraded PL / PS data exists, the to-be-upgraded PL / PS data is transported to a corresponding area of a QSPI FLASH; finally, a PL end program is loaded to the PL end, and a PS end program is loaded to AXI_SRAM and jumps for execution. The application further provides a system for implementing the above method. The application realizes reliable online upgrading without external DDR, supports automatic recovery in the case of abnormal power-off, and saves FLASH storage space.

Description

Technical Field

[0001] This invention relates to the field of embedded system online upgrade technology, and more specifically, to an online upgrade method and system for ZYNQ chips without external DDR. Background Technology

[0002] The ZYNQ series chips are System-on-Chip (SoCs), integrating an ARM core (PS, Processing System) and programmable logic (PL, Programmable Logic) within the chip. With the development of domestically produced chips, China has also launched its own ZYNQ chips (such as the FMQL series). Currently, ZYNQ chips are widely used in industrial control, communications, and military fields.

[0003] The online upgrade solutions based on ZYNQ chips mainly include the following: 1) JTAG emulator method, which burns the program into FLASH through the JTAG port; 2) SD card upgrade method, which copies the file to the SD card for updating, but requires manual insertion and removal of the SD card; 3) Receiving upgrade data through network and serial port, caching it in DDR (Double Data Rate) memory and then writing it into FLASH.

[0004] All of the above solutions rely on external DDR as cache space. For systems requiring low cost or with limited space, introducing DDR chips will significantly increase material costs and PCB layout complexity. More importantly, in some low-cost application scenarios, ZYNQ system designs directly forgo external DDR, with programs running directly in OCM (On-Chip Memory). Under this architecture, existing online upgrade solutions are unsuitable due to the lack of DDR.

[0005] In addition, existing online upgrade solutions are prone to system failure due to abnormal power outages during the upgrade process. How to reliably achieve online upgrades without DDR is an urgent problem to be solved in this field. Summary of the Invention

[0006] This invention breaks through the conventional design concept in the field that "ZYNQ online upgrades must rely on external DDR". Existing technologies and chip manufacturers' reference designs all consider external DDR as a necessary component for ZYNQ chip online upgrades. It is generally believed in the art that during remote online upgrades, the PS-side application must run on external DDR, and the upgrade data also requires DDR as temporary storage space. This invention adopts a two-stage upgrade process of "EMMC temporary storage + reset relocation": In the first stage, during normal application operation, upgrade data is received through the LVDS interface and directly written to the EMMC, while the application itself runs on the chip's internal AXI_SRAM; in the second stage, after system reset, the BootLoader reads the upgrade data from the EMMC, writes it to the QSPI FLASH, and completes program loading, while the BootLoader itself runs on the chip's internal AHB_SRAM. Therefore, this invention achieves complete online upgrades without relying on external DDR, solving the problem that existing ZYNQ chip online upgrade solutions rely on external DDR memory as cache or running space, resulting in the inability to complete online upgrades without an external DDR architecture, and the risk of system "bricking" due to abnormal power outages during the upgrade process.

[0007] In response, this invention provides a method and system for online upgrade of ZYNQ chips without external DDR.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: In a first aspect, this application provides an online upgrade method for a ZYNQ chip without external DDR, which is applied to an embedded system including a ZYNQ chip, a QSPI FLASH memory and an EMMC memory. The ZYNQ chip is not connected to an external DDR memory, and the program runs in the chip's internal on-chip memory OCM, which includes AHB_SRAM and AXI_SRAM. The method includes the following steps: Step S1: After the chip is powered on, the BootROM reads the FSBL from the bootloader loading area of ​​the QSPI FLASH and loads it into the AXI_SRAM for execution; the FSBL loads the BootLoader from the QSPI FLASH into the AHB_SRAM and jumps to the BootLoader entry point for execution; Step S2: After the BootLoader starts, it checks whether upgrade file data has been received from the external host computer; if upgrade file data is received, it writes the upgrade file data to the temporary storage area of ​​the EMMC and then performs a restart operation; if upgrade file data is not received within the preset waiting time, it proceeds to step S3. Step S3: The BootLoader checks whether there is PL-side program data and / or PS-side program data to be upgraded in the EMMC temporary storage area; if there is PL-side program data to be upgraded, the data is read from the EMMC and written to the FPGA data area of ​​the QSPI FLASH; if there is PS-side program data to be upgraded, the data is read from the EMMC and written to the ARM data area of ​​the QSPI FLASH. Step S4: The BootLoader loads the PL-side program from the FPGA data area of ​​the QSPI FLASH into the PL-side of the ZYNQ chip, and loads the PS-side program from the ARM data area of ​​the QSPI FLASH into the AXI_SRAM, then jumps to execute the PS-side program.

[0009] Furthermore, in step S2, the preset waiting time after the BootLoader starts is 15-40 seconds.

[0010] Furthermore, in step S2, the upgrade file data is partitioned according to data type and written to the temporary storage area of ​​EMMC; This includes a flag area, which stores upgrade flags, file block count, and the number of valid bytes in the last frame; a PS upgrade data temporary storage area, which stores PS-side upgrade data; and a PL upgrade data temporary storage area, which stores PL-side upgrade data. The flag area, PS upgrade data temporary storage area, and PL upgrade data temporary storage area are allocated storage blocks in the EMMC; the storage blocks are allocated according to the size required by the corresponding data.

[0011] Furthermore, in step S3, when reading the upgrade data from the PL or PS end from the EMMC and writing it into the QSPI FLASH, the overwrite method is used to directly write it into the preset fixed address space. Before writing, the corresponding area is erased, and a read verification is performed after each page is written.

[0012] Further, in step S4, loading the PL program onto the PL terminal of the ZYNQ chip specifically includes: initializing the PCAP interface, configuring it to write mode, and resetting the PL terminal; setting the CSU DMA to bit stream download mode, configuring the DMA source address, source length, destination address, and destination length; and configuring the PCAP to idle mode after waiting for the DONE signal of the PL terminal to go high.

[0013] Furthermore, during the normal operation of the PS-side program, if an online upgrade command is received from an external host computer, the upgrade file data is received through the external communication interface. During the reception process, the SLIP protocol is used for data packetization, and CRC check is used to ensure data correctness. After the upgrade data is received, it is written to the EMMC temporary storage area, and then a restart operation is performed.

[0014] Furthermore, the external communication interface is an LVDS interface, which uses a serial communication protocol.

[0015] This invention also provides an online upgrade system for ZYNQ chips without external DDR, comprising: a ZYNQ main control chip, wherein the ZYNQ chip is not connected to external DDR memory and integrates an on-chip memory OCM containing AHB_SRAM and AXI_SRAM; a QSPI FLASH memory for storing FSBL, BIT files, BootLoader, and stored PL and PS side applications; an EMMC memory for temporarily storing application files to be upgraded sent by an external host computer; and an LVDS external communication interface for establishing a data transmission channel between the external host computer and the ZYNQ chip; the storage space of the QSPI FLASH memory is divided into: a bootloader area for storing the combined file of FSBL, BIT files, and BootLoader; an ARM data area for storing PS side applications; and an FPGA data area for storing PL side applications.

[0016] Furthermore, the EMMC memory is divided into: a flag area for storing upgrade flags and file verification information; a PS upgrade data temporary storage area; and a PL upgrade data temporary storage area. The upgrade data is first written to the EMMC temporary storage area and then transferred by the BootLoader to the corresponding hardened area of ​​the QSPI FLASH during the next startup.

[0017] Furthermore, both the BootLoader and the normally operating PS-side application have the function of receiving upgrade file data and writing it to the EMMC temporary storage area through the external communication interface; when the reception of any stage is completed, a restart operation is performed, and the BootLoader uniformly completes the data transfer and program loading from the EMMC temporary storage area to the QSPI FLASH; when an abnormal power failure occurs during the process of writing upgrade data to the QSPI FLASH, the BootLoader can still detect the upgrade data in the EMMC temporary storage area and complete the transfer after the system is powered on and restarted, thereby realizing automatic recovery after an abnormal power failure.

[0018] The beneficial effects of this invention are as follows: This invention utilizes the chip's built-in OCM (AHB_SRAM and AXI_SRAM) as the program execution space, completely eliminating the dependence on external DDR, and is suitable for cost-sensitive or space-constrained embedded systems.

[0019] This invention enables independent upgrades for the PL and PS ends by using the upgrade data type identifier in the EMMC. It also supports receiving upgrade files during application operation or in the BootLoader, effectively preventing abnormal power outages during the upgrade process from bricking the device.

[0020] This invention uses an LVDS interface for data transmission, supporting long-distance, high-speed data communication, and is suitable for complex environments such as industrial sites.

[0021] This invention uses EMMC as the upgrade data temporary storage area, combined with the BootLoader's overwrite mechanism, which significantly saves FLASH storage space compared to the dual-zone backup solution.

[0022] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the QSPI FLASH partitioning of the present invention.

[0025] Figure 2 This is a schematic diagram of the EMMC partitioning of the present invention.

[0026] Figure 3 This is a flowchart of the program startup process of this invention.

[0027] Figure 4 This is a flowchart of the BootLoader program of this invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0029] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] In the description of this invention, "A-side" generally refers to the first side of the package substrate core, and "B-side" generally refers to the second side of the package substrate core. "BGA" refers to the solder ball array in a ball grid array package structure.

[0031] Terminology Explanation ZYNQ: Programmable System on Chip, which integrates an ARM processor core (PS side) and programmable logic (PL side). DDR: Double Data Rate Memory, External Dynamic Random Access Memory; OCM: On-Chip Memory, integrated inside the ZYNQ chip, including AHB_SRAM and AXI_SRAM; AHB_SRAM: Advanced High-performance Bus Static Random Access Memory. AXI_SRAM: Advanced eXtensible Interface Static Random Access Memory. QSPI FLASH: Quad Serial Peripheral Interface Flash. EMMC: Embedded Multi Media Card; FSBL: First Stage Boot Loader; BootLoader: The second-level boot loader; BootROM: The read-only memory containing the startup code embedded inside the chip; PL: Programmable Logic. PS end: Processing System; PCAP: Processor Configuration Access Port. CSU DMA: Configuration Security Unit Direct Memory Access. LVDS: Low Voltage Differential Signaling; SLIP: Serial Line Internet Protocol. CRC: Cyclic Redundancy Check.

[0032] Example 1: This embodiment provides an online upgrade method for a ZYNQ chip without external DDR memory, applicable to an embedded system comprising a ZYNQ chip, QSPI FLASH memory, and eMMC memory. The ZYNQ chip is not connected to external DDR memory; the program runs in the chip's internal on-chip memory (OCM), which includes AHB_SRAM and AXI_SRAM.

[0033] In this embodiment, the main control chip is the FMQL45T900 chip (ZYNQ architecture). This chip integrates an ARM processor core (PS side) and a programmable logic unit (PL side), and has built-in AHB_SRAM (address range 0xE1FE_0000~0xE1FF_FFFF, total 128KB) and AXI_SRAM (starting address 0x0002_0000) as on-chip memory, providing program running space without the need for external DDR.

[0034] External memory chips include: QSPI FLASH memory: 16MB capacity, used to store the FSBL, BIT file, BootLoader, and final application program. Its address allocation space is set according to actual needs and is not specifically limited here. In this embodiment, the address space allocation is as follows: the starting address 0x0000_0000 stores the BIN file composed of FSBL, BIT, and BootLoader, with a storage space allocation of 6.5MB; the starting address for the PS application's firmware is 0x0068_0000, with a storage space allocation of 512KB; (e.g., ...) Figure 1As shown, the PL application's fixed starting address is 0x0070_0000, and the allocated storage space is 6.5MB.

[0035] EMMC memory: 8GB capacity, used to temporarily store application files to be upgraded from an external host computer. Its storage block allocation is as follows: block 0 stores the upgrade flag, number of file blocks, and number of valid bytes in the last frame; blocks 1~1000 store the PS-side application data to be upgraded; blocks 1001~41960 store the PL-side application data to be upgraded, such as... Figure 2 As shown.

[0036] The external data communication interface uses LVDS (Low Voltage Differential Signaling) lines to establish a data transmission channel between the external host computer and the ZYNQ chip. In this embodiment, a baud rate of 3125000 is used for transmission, and the application layer uses the SLIP protocol to assemble packets and adds CRC check.

[0037] During the production phase, the FSBL, BIT file, and BootLoader are first written to address 0 of the external QSPI FLASH using a JTAG emulator. Specifically, the BIT file is compressed using third-party software (such as PROCISE), and then the three files are combined into a single BIN file using PROCISE before being written. The PS-side application and PL-side application are then converted to BIN files and written to addresses 0x0068_0000 and 0x0070_0000 respectively.

[0038] Set the boot mode of the ZYNQ chip to boot from QSPI FLASH. For example... Figure 3 As shown, after the device is powered on, perform the following steps: Step S1: The BootROM reads the FSBL from the QSPI FLASH bootloader area and loads it into the AXI_SRAM for execution.

[0039] like Figure 4 As shown, FSBL performs the following operations: Initialize the basic peripherals on the PS side, including the clock, QSPI controller, and EMMC controller; Load the BIT file into the PL terminal; Load the BootLoader into the chip's internal AHB_SRAM (address range 0xE1FE_0000~0xE1FF_FFFF, total 128KB); Jump to the BootLoader entry address of AHB_SRAM and start executing the BootLoader.

[0040] This embodiment utilizes the BootROM to load the FSBL into the AXI_SRAM for execution, and then the FSBL loads the BootLoader into the AHB_SRAM, realizing a two-level boot mechanism in the absence of external DDR. It fully leverages the respective advantages of the two OCMs (AHB_SRAM and AXI_SRAM) within the ZYNQ chip: AHB_SRAM is used to run the BootLoader (smaller size, less demanding on real-time performance), while AXI_SRAM is used to finally run the PS-side application (requiring more space and higher bandwidth).

[0041] Step S2: After the BootLoader starts, it waits for a preset time and checks whether upgrade file data has been received from the external host computer. The preset waiting time is 15-40 seconds.

[0042] If upgrade file data is received, the data type partition of the upgrade file data is written to the temporary storage area of ​​EMMC; This includes a flag area, which stores upgrade flags, file block count, and the number of valid bytes in the last frame; a PS upgrade data temporary storage area, which stores PS-side upgrade data; and a PL upgrade data temporary storage area, which stores PL-side upgrade data. The flag area, PS upgrade data temporary storage area, and PL upgrade data temporary storage area are allocated storage blocks in the EMMC; the storage blocks are allocated according to the size required by the corresponding data.

[0043] Specifically, in this embodiment, the temporary storage area of ​​the EMMC can be written in the following manner: block 0 of the EMMC stores the upgrade flag, the number of file blocks, and the number of valid bytes of the last frame; blocks 1 to 1000 store the PS end upgrade data; blocks 1001 to 41960 store the PL end upgrade data; and a restart operation is performed after the writing is completed.

[0044] If the upgrade file data is not received within 20 seconds, proceed to step S3.

[0045] Step S2 sets a preset waiting time (e.g., 20 seconds) after the BootLoader starts, and detects and receives upgrade file data from the external host computer within this window period. After temporarily storing the data in the EMMC, the system restarts immediately. This embodiment places the time-consuming and easily interfered-with upgrade file transmission process in the EMMC temporary storage stage, avoiding the risk of FLASH data corruption due to communication interruption or abnormality when directly operating QSPIFLASH during transmission. Moreover, the waiting window when the BootLoader starts provides the system with a "safe upgrade mode". Even if the application crashes or the application in the FLASH is corrupted, the system can still receive the upgrade file and complete the recovery through this window, effectively preventing the system from becoming "bricked". At the same time, the temporary storage and subsequent processing of upgrade data in this embodiment are completed without DDR. The EMMC replaces the caching function of DDR in the traditional solution, making online upgrades possible under the DDR-free architecture.

[0046] Step S3: The BootLoader checks whether the PL-side program data and / or PS-side program data to be upgraded exist in the EMMC temporary storage area. If PL program data to be upgraded exists, it is read from the EMMC and written to the FPGA data area of ​​the QSPI FLASH (starting address 0x0070_0000). Before writing, the area is erased, and the data is written directly to the preset fixed address space using an overwrite method. After each page is written, a read verification is performed. After writing is complete, the PL upgrade flag in block 0 of the EMMC is cleared.

[0047] If PS-side program data to be upgraded exists, it is read from the EMMC and written to the ARM data area of ​​the QSPI FLASH (starting address 0x0068_0000). Before writing, the area is erased, and the data is written directly to the preset fixed address space using an overwrite method. After each page is written, a read verification is performed. After writing is complete, the PS upgrade flag in block 0 of the EMMC is cleared.

[0048] Step S4: The BootLoader loads the PL-side program from the FPGA data area of ​​the QSPI FLASH into the PL-side of the ZYNQ chip, and loads the PS-side program from the ARM data area of ​​the QSPI FLASH into the AXI_SRAM, then jumps to execute the PS-side program.

[0049] Specifically, loading the PL program into the ZYNQ chip's PL terminal includes: Initialize the PCAP interface, configure it to write mode, and reset the PL terminal; Set CSU DMA to bit stream download mode, and configure the DMA source address as 0xE870_0000, source length, destination address as 0xFFFF_FFFF, and destination length; After the DONE signal on the PL side goes high, configure the PCAP to idle mode.

[0050] The PS-side application is loaded into the entry address (0x0002_0000) of AXI_SRAM. Before jumping, the MMU and cache are disabled, and then execution is performed.

[0051] This step loads the PL-side program via the PCAP interface, a hardware configuration method that does not rely on external DDR. Loading the PS-side program into AXI_SRAM and jumping to it fully utilizes the high bandwidth of AXI_SRAM, ensuring the running performance of the application. Furthermore, after the upgrade, there is no need to reset again or rely on other bootloaders. The same BootLoader performs program transfer, verification, and loading all at once, making the process simple and reliable.

[0052] In this invention, step S2 receives upgrade data and restarts, step S3 completes the FLASH update, and step S4 loads the new program. The entire upgrade process, whether triggered by the application or the BootLoader, ultimately converges on the waiting window of step S2 and the data transfer and update in step S3, ensuring the atomicity and recoverability of the upgrade process. Even if a power outage occurs during the FLASH writing process in step S3, the system can still enter the waiting window of step S2 after power is restored, detect the existing upgrade data in the EMMC, and re-execute steps S3 and S4, completely avoiding the risk of the system becoming bricked.

[0053] During normal operation of the PS-side program, if an online upgrade command is received from an external host computer, the upgrade file data is received via the LVDS interface. During reception, the SLIP protocol is used for data packet assembly, and CRC checksums are used to ensure data integrity. Specifically: the external host computer sends the upgrade file data via the LVDS interface. The data is received via the serial port built on the PL side and stored in a FIFO. The PS side reads the data via the AXI bus and stores it in a circular buffer. The data is then cyclically unpacked according to the SLIP protocol, and a CRC check is performed after each unpacked packet. If the check is successful, the received upgrade data is written to the corresponding partition of the EMMC temporary storage area, and an ACK frame is sent back. If the check fails, an error is recorded, and the loading result is sent back after transmission. After the upgrade data is received, it is written to the EMMC temporary storage area, and then a restart operation is performed. After restarting, steps S2-S4 are executed to complete the upgrade.

[0054] This embodiment includes the following exception handling mechanism: If an abnormal power outage occurs during the upgrade process, after the system powers on and restarts and enters the BootLoader, a 20-second upgrade time is reserved. If the upgrade file data is received within 20 seconds, the system can still complete the normal upgrade process.

[0055] Both the BootLoader and the normally running PS-side application have the function of receiving upgrade file data and writing it to the EMMC temporary storage area. After either stage of reception is completed, a restart operation is performed, with the BootLoader uniformly handling the data transfer from the EMMC temporary storage area to the QSPI FLASH and loading the program. If an abnormal power outage occurs during the upgrade data writing process to the QSPI FLASH, the BootLoader can still detect the upgrade data in the EMMC temporary storage area and complete the transfer after the system powers on and restarts, thus achieving automatic recovery after an abnormal power outage.

[0056] Example 2: This embodiment provides an online upgrade system for ZYNQ chips without external DDR, which is used to implement the method described in Embodiment 1. The system includes: The ZYNQ main control chip uses the FMQL45T900 chip. This chip does not connect to external DDR memory; it integrates an on-chip memory (OCM) containing AHB_SRAM (128KB, address range 0xE1FE_0000~0xE1FF_FFFF) and AXI_SRAM (starting address 0x0002_0000). The chip also integrates an ARM processor core (PS side) and a programmable logic unit (PL side).

[0057] QSPI FLASH memory: It has a capacity of 16MB and is used to store FSBL, BIT files, BootLoader, and stored PL and PS applications.

[0058] The storage space of the QSPI FLASH memory is divided into: Bootloader area (starting address 0x0000_0000, 6.5MB): used to store the combined files of FSBL, BIT files and BootLoader; ARM data area (starting address 0x0068_0000, 512KB): used to embed PS-side applications; FPGA data area (starting address 0x0070_0000, 6.5MB): used to embed PL-side applications.

[0059] EMMC storage: It has a capacity of 8GB and is used to temporarily store application files to be upgraded sent by an external host computer.

[0060] The EMMC memory is divided into: Flag area (block0): Used to store file verification information such as upgrade flags, number of file blocks, and number of valid bytes in the last frame; PS upgrade data temporary storage area (block1~block1000): Used to store PS client program data to be upgraded; PL upgrade data temporary storage area (block1001~block41960): Used to store the PL end program data to be upgraded.

[0061] The upgrade data is first written to the EMMC temporary storage area, and then the BootLoader moves it to the corresponding hardened area of ​​the QSPI FLASH during the next startup.

[0062] LVDS External Communication Interface: Employing a Low Voltage Differential Signaling (LVDS) interface, this interface establishes a data transmission channel between the external host computer and the ZYNQ chip. It uses a serial communication protocol with a baud rate of 3125000. The application layer uses the SLIP protocol for data packet assembly and employs CRC checksums to ensure data integrity.

[0063] The program loading and upgrade module includes the FSBL module, the BootLoader module, and the online application upgrade module; FSBL module: embedded in the QSPI FLASH bootloader area, used to initialize basic peripherals on the PS side, load the BIT file to the PL side, load the BootLoader to AHB_SRAM and jump to execute.

[0064] BootLoader module: embedded in the QSPI FLASH bootloader area, used to perform 20-second wait detection, receive upgrade files and write them to EMMC, detect upgrade data in EMMC and transfer it to QSPI FLASH, load the PL-side program through the PCAP interface, load the PS-side program into AXI_SRAM and jump.

[0065] Online application upgrade module: During the normal operation of the application on the PS side, upgrade file data is received through the LVDS interface. SLIP+CRC verification is used. After the correct upgrade data is written to the EMMC temporary storage area, the system is restarted.

[0066] Both the BootLoader and the normally operating PS-side application have the function of receiving upgrade file data through the LVDS interface and writing it to the EMMC temporary storage area. After either stage of reception is completed, a restart operation is performed, with the BootLoader uniformly handling the data transfer from the EMMC temporary storage area to the QSPI FLASH and loading the program. In the event of an abnormal power outage during the upgrade data writing process to the QSPI FLASH, the BootLoader can still detect the upgrade data in the EMMC temporary storage area and complete the transfer after the system powers on and restarts, thus achieving automatic recovery after an abnormal power outage.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0068] It should be noted that the specific manner in which each module performs its operation in the apparatus described in the above embodiments has been described in detail in the embodiments of the method, and will not be elaborated here.

[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0070] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for online upgrade of a ZYNQ chip without external DDR, applied to an embedded system comprising a ZYNQ chip, QSPI FLASH memory, and eMMC memory, characterized in that, The ZYNQ chip is not connected to an external DDR memory; the program runs in the chip's internal on-chip memory OCM, which includes AHB_SRAM and AXI_SRAM. The method includes the following steps: Step S1: After the chip is powered on, the BootROM reads the FSBL from the bootloader loading area of ​​the QSPI FLASH and loads it into the AXI_SRAM for execution; the FSBL loads the BootLoader from the QSPI FLASH into the AHB_SRAM and jumps to the BootLoader entry point for execution; Step S2: After the BootLoader starts, it checks whether it has received upgrade file data from an external host computer; If upgrade file data is received, the upgrade file data is written to the temporary storage area of ​​the EMMC, and then a restart operation is performed; If the upgrade file data is not received within the preset waiting time, proceed to step S3; Step S3: The BootLoader checks whether there is PL-side program data and / or PS-side program data to be upgraded in the EMMC temporary storage area; If there is PL-side program data to be upgraded, then read the data from the EMMC and write it into the FPGA data area of ​​the QSPI FLASH; If there is PS-side program data to be upgraded, then read the data from the EMMC and write it to the ARM data area of ​​the QSPI FLASH; Step S4: The BootLoader loads the PL-side program from the FPGA data area of ​​the QSPI FLASH into the PL-side of the ZYNQ chip, and loads the PS-side program from the ARM data area of ​​the QSPI FLASH into the AXI_SRAM, then jumps to execute the PS-side program.

2. The online upgrade method for a ZYNQ chip without external DDR according to claim 1, characterized in that, In step S2, the preset waiting time after the BootLoader starts is 15-40 seconds.

3. The online upgrade method for a ZYNQ chip without external DDR according to claim 1, characterized in that, In step S2, the upgrade file data is partitioned according to data type and written to the temporary storage area of ​​EMMC; This includes the flag area, storage upgrade flag, number of file blocks, and number of valid bytes in the last frame; PS upgrade data temporary storage area, which stores upgrade data on the PS side; PL upgrade data temporary storage area, which stores upgrade data from the PL side; The flag area, PS upgrade data temporary storage area, and PL upgrade data temporary storage area are storage blocks allocated in the EMMC.

4. The online upgrade method for a ZYNQ chip without external DDR according to claim 3, characterized in that, In step S3, when reading the upgrade data from the PL or PS end from the EMMC and writing it into the QSPI FLASH, the overwrite method is used to directly write it into the preset fixed address space. Before writing, the corresponding area is erased, and a read verification is performed after each page is written.

5. The online upgrade method for a ZYNQ chip without external DDR according to claim 1, characterized in that, In step S4, loading the PL-side program into the PL-side of the ZYNQ chip specifically includes: Initialize the PCAP interface, configure it to write mode, and reset the PL terminal; Configure CSU DMA to bitstream download mode, and configure the DMA source address, source length, destination address, and destination length; After the DONE signal on the PL side goes high, configure the PCAP to idle mode.

6. The online upgrade method for a ZYNQ chip without external DDR according to claim 1, characterized in that, During normal operation of the PS program, if an online upgrade command is received from an external host computer, the upgrade file data is received through the external communication interface. During the reception process, the SLIP protocol is used to assemble the data packets, and CRC check is used to ensure the correctness of the data. After the upgrade data is received, it is written to the EMMC temporary storage area, and then a restart operation is performed.

7. The online upgrade method for a ZYNQ chip without external DDR according to claim 6, characterized in that, The external communication interface is an LVDS interface, which uses a serial communication protocol.

8. An online upgrade system for ZYNQ chips without external DDR, characterized in that, The system for implementing the online upgrade method for ZYNQ chips without external DDR as described in any one of claims 1-7 includes: The ZYNQ main control chip is not connected to an external DDR memory, but integrates an on-chip memory OCM containing AHB_SRAM and AXI_SRAM. QSPI FLASH memory is used to store FSBL, BIT files, BootLoader, and stored PL and PS applications. The EMMC memory is used to temporarily store application files to be upgraded, which are sent from an external host computer. The LVDS external communication interface is used to establish a data transmission channel between an external host computer and the ZYNQ chip; The QSPI FLASH memory is divided into: a bootloader area for storing the combined files of FSBL, BIT, and BootLoader; an ARM data area for embedding the PS-side application; and an FPGA data area for embedding the PL-side application.

9. A ZYNQ chip online upgrade system without external DDR according to claim 8, characterized in that, The EMMC memory is divided into: a flag area for storing upgrade flags and file verification information; a PS upgrade data temporary storage area; and a PL upgrade data temporary storage area. Upgrade data is first written to the EMMC temporary storage area and then transferred by the BootLoader to the corresponding hardened area of ​​the QSPI FLASH during the next startup.

10. A ZYNQ chip online upgrade system without external DDR according to claim 8, characterized in that, Both the BootLoader and the normally operating PS-side application have the function of receiving upgrade file data and writing it to the EMMC temporary storage area through the external communication interface. After the reception of any stage is completed, a restart operation is performed, and the BootLoader uniformly completes the data transfer and program loading from the EMMC temporary storage area to the QSPI FLASH. If an abnormal power failure occurs during the process of writing upgrade data to the QSPI FLASH, the BootLoader can still detect the upgrade data in the EMMC temporary storage area and complete the transfer after the system is powered on and restarted, thereby realizing automatic recovery after an abnormal power failure.

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