Automation Method and Apparatus for Extended Instruction Design Based on Operator Semantics

Abstract

This application relates to the field of extended instruction design technology, providing an automated method and apparatus for extended instruction design based on operator semantics. This invention generates and constructs an operator feature library through static program structure, dynamic analysis logs, and architecture configuration files, forming an operator semantic understanding that can guide design and providing a semantic knowledge foundation for downstream searches. By dividing the system into multiple fusion groups, redundant exploration of individual operator instances is avoided; by dynamically prioritizing the fusion groups, frequent and computationally intensive operator combinations are placed in priority processing positions. A fixed order reflects actual mutual constraints, significantly narrowing the feasible space, improving search efficiency, and shortening the design cycle; simultaneously, expansion, filtering, and selection operations are performed at each level of decision-making, achieving automatic semantic mining of extended instructions within hardware capacity boundaries. A dual-track generation mechanism and a five-level verification architecture are used to verify the correctness of instruction configurations, ensuring that the generated instruction configurations are deployable and error-free.

Description

Technical Field

[0001] This application relates to the field of extended instruction design technology, and in particular to an automated method and apparatus for extended instruction design based on operator semantics. Background Technology

[0002] Edge AI processors need to ensure high computing throughput under stringent power consumption and cost constraints, and custom instruction set architecture (ISA) extensions are a core technology for improving their computing efficiency. Compared to coarse-grained hardware accelerators, tightly coupled ISA extensions offer both flexibility and cost advantages, with their core reliance on the matching degree between extended instructions and the semantics of high-level AI operators.

[0003] Current ISA extension technologies suffer from several inherent limitations. Traditional manual design methods are costly and time-consuming, and design experience is difficult to generalize and adapt to diverse edge AI workloads. Mainstream automated design relies on data flow graph subgraph mining, which breaks down high-level AI operators into fine-grained instruction fragments, fragmenting the complete operator semantics and failing to achieve instruction-level semantic compression of complete operators, thus limiting optimization effectiveness. Industrial ASIP toolchains only support automated implementation of instruction sets and lack the ability to automatically mine extended instructions from workload semantics.

[0004] Existing LLM-assisted design solutions are not adapted to the hierarchical and strongly coupled characteristics of the ISA design space, and flat search strategies struggle to handle complex dependency decisions. Furthermore, existing technologies lack built-in correctness verification mechanisms, instruction semantics lack formal definition, verification is delayed, and the generated instructions cannot be guaranteed to be deployable and error-free, severely hindering the automated and high-precision optimization of edge AI ISA extensions. Summary of the Invention

[0005] Therefore, it is necessary to provide an automated method and apparatus for designing extended instructions based on operator semantics to address the aforementioned technical problems.

[0006] An automated method for designing extended instructions based on operator semantics, the method comprising the following steps: S1. Generate a unified structured operator descriptor based on the static program structure, dynamic analysis logs and architecture configuration file of the input target AI program, and build an operator feature library; S2. Based on the execution topology order and fusion candidate relationship in the operator feature library, the static program structure of the target AI program is divided into multiple fusion groups, and the fusion groups are sorted according to dynamic priority. S3. For each high-priority fusion group, make decisions layer by layer in multiple coupled design dimensions according to a preset order, generate a complete instruction configuration, and perform expansion, filtering and selection operations at each layer of decision-making. S4. Use a lightweight cost model to evaluate the utility of the generated instruction configuration. If the utility value is greater than the preset threshold, proceed to S5; otherwise, discard the current instruction configuration. S5. Generate an executable ISA-IR corresponding to the instruction configuration. Based on the ISA-IR, generate two sets of entities: a high-fidelity reference simulator and integration code. Based on the two generated entities, perform static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks on the instruction configuration in sequence. Store the verified instruction configuration into the extended instruction set and feed the verification results back to the operator feature library.

[0007] In one embodiment, a unified structured operator descriptor is generated based on the static program structure, dynamic profiling logs, and architecture configuration file of the input target AI program, and an operator feature library is constructed, including: Input the static program structure, dynamic analysis logs, and architecture configuration file of the target AI program, and parse them to obtain the corresponding structured information; The structured information corresponding to the static program structure, dynamic profiling logs, and architecture configuration files is encapsulated into a canonical text context containing defined tags and input into the LLM; LLM generates a unified structured operator descriptor based on the input canonical text context, and constructs an operator feature library.

[0008] In one embodiment, the static program structure, dynamic profiling logs, and architecture configuration file of the target AI program are input and parsed to obtain the corresponding structured information, including: The high-level computation graph of the static program structure is analyzed, the operator category of each node is identified, the data dependency relationship between nodes is analyzed, the execution topology sorting is recorded, and operator pairs with stable producer-consumer relationships are identified as potential fusion candidates. Dynamic behavior data of each operator is obtained based on dynamic analysis logs; Based on the architecture configuration file, extract the hard constraint parameters that are directly related to the design space.

[0009] In one embodiment, for each high-priority fusion group, decisions are made layer by layer across multiple coupled design dimensions in a preset order to generate a complete instruction configuration. At each layer of decision-making, expansion, filtering, and selection operations are performed, including: For each high-priority fusion group, an empty instruction configuration is initialized, and decisions are made layer by layer in the design dimensions of granularity, operator fusion, data type, boundary behavior and operand organization according to a preset order to generate a complete instruction configuration. Perform expansion, filtering, and selection operations at each level of decision-making.

[0010] In one embodiment, expansion, filtering, and selection operations are performed at each level of decision-making, including: At each level of decision-making, LLM infers semantically reasonable and technically feasible candidate options based on the current design state. The candidate options are filtered using architectural constraints as hard rules to obtain the legal candidate options; Legally valid candidate options are selected and included in the current configuration based on heuristic principles.

[0011] In one embodiment, a lightweight cost model is used to evaluate the utility of the generated instruction configuration, including: The estimated system-level speedup, percentage increase relative to total processor area, and percentage increase in dynamic power consumption resulting from the instruction configuration calculated using a lightweight cost model are as follows: ; in, This is a utility assessment value; For the estimated system-level acceleration; This represents the percentage increase relative to the total processor area. This represents the percentage increase in dynamic power consumption. , , These are the weighting coefficients.

[0012] In one embodiment, the instruction configuration is subjected to static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks sequentially based on the two generated sets of entities, including: The high-fidelity reference simulator is used for static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks; the integration code is used for integration checks.

[0013] In one embodiment, the elements of ISA-IR include binary encoding, operand structure, state transition function, and read / write resource set.

[0014] In one embodiment, the LLM generates a unified structured operator descriptor based on the input canonical text context, from three levels: interpreting static semantics, evaluating dynamic bottlenecks, and combining architectural constraints.

[0015] An automated device for designing extended instructions based on operator semantics, the device comprising: The operator feature library construction module is used to generate unified structured operator descriptors and build the operator feature library based on the static program structure, dynamic analysis logs and architecture configuration files of the input target AI program. The fusion group partitioning module is used to divide the static program structure of the target AI program into multiple fusion groups based on the execution topology order and fusion candidate relationship in the operator feature library, and sort the fusion groups according to dynamic priority. The instruction configuration generation module is used to make decisions layer by layer on multiple coupled design dimensions for each high-priority fusion group in a preset order, generate complete instruction configurations, and perform expansion, filtering and selection operations at each layer of decision-making. The utility evaluation module is used to evaluate the utility of the generated instruction configuration using a lightweight cost model. If the utility value is greater than the preset threshold, it will be transferred to the five-level verification module; otherwise, the current instruction configuration will be discarded. The five-level verification module is used to generate executable ISA-IRs corresponding to instruction configurations. Based on the ISA-IRs, two sets of entities are generated: a high-fidelity reference simulator and integration code. Based on the two generated entities, the instruction configurations are subjected to static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks in sequence. The verified instruction configurations are stored in the extended instruction set, and the verification results are fed back to the operator feature library.

[0016] The aforementioned automated method and apparatus for designing extended instructions based on operator semantics generates an operator feature library from the static program structure, dynamic analysis logs, and architecture configuration files of the target AI program. This constitutes an operator semantic understanding that can guide design, providing a semantic knowledge foundation for downstream search. By dividing the static program structure of the target AI program into multiple fusion groups, redundant exploration of individual operator instances is avoided, supporting instruction reuse across instances. Dynamic priorities are used to sort the fusion groups, placing frequent and computationally intensive operator combinations in a priority position. By making decisions layer by layer in a fixed order across multiple coupled design dimensions, the actual mutual constraints are reflected in this fixed order, significantly narrowing the feasible space, improving search efficiency, and shortening the design cycle. Simultaneously, expansion, filtering, and selection operations are performed at each layer of decision-making, achieving automatic semantic mining of extended instructions within hardware capacity boundaries. The utility evaluation of the generated instruction configuration is only performed after the decision using a lightweight cost model, effectively avoiding the introduction of inaccurate intermediate signals that could interfere with the design direction. The generated instruction configuration is verified for correctness through the ISA-IR dual-track generation mechanism and a five-level verification architecture, thereby ensuring that the generated instruction configuration is deployable and error-free. The verification results are also fed back to the operator feature library to optimize subsequent generation.

[0017] This invention achieves efficient and controllable search within a vast coupled design space through an architecture of semantic inference, architectural constraint filtering, and cost model final selection.

[0018] This invention enables constrained automatic search in tightly coupled design dimensions such as granularity, fusion range, data type, boundary behavior, and operand organization. It can also complete static checks, resource analysis, dynamic execution verification, deterministic checks, and integration consistency verification before instructions enter architecture simulation or subsequent deployment, avoiding the problem of disconnect between generation and verification. This ensures that candidate instructions have clear semantic basis and correctness guarantee in the design stage. Attached Figure Description

[0019] Figure 1 A flowchart illustrating an automated method for designing extended instructions based on operator semantics in one embodiment; Figure 2 A schematic diagram illustrating the framework of an automated method for designing extended instructions based on operator semantics in one embodiment; Figure 3 This is a schematic diagram illustrating the construction process of an operator feature library in one embodiment; Figure 4 This is a flowchart illustrating the ISA-IR homologous dual-track generation mechanism and five-level verification architecture in one embodiment; Figure 5 A block diagram of an automation device designed based on operator semantics for one embodiment. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] In one embodiment, such as Figure 1 , Figure 2 As shown, an automated method for designing extended instructions based on operator semantics is provided. The method includes the following steps: S1. Generate a unified structured operator descriptor based on the static program structure, dynamic analysis logs, and architecture configuration file of the input target AI program, and build an operator feature library.

[0022] It should be noted that the static program structure includes operator types, operational primitives, data dependencies, and execution topology order, used to identify operator categories and identify potential fusion relationships; the dynamic profiling log is dynamic runtime profiling data, including execution time percentage, dynamic instruction count, arithmetic strength, etc., used to quantify the performance criticality of operators; the architecture configuration file contains the architecture parameters of the target processor, including vector register width, number of registers, data type support, etc., used as hard constraints for all subsequent design decisions.

[0023] S2. Based on the execution topology order and fusion candidate relationship in the operator feature library, the static program structure of the target AI program is divided into multiple fusion groups, and the fusion groups are sorted according to dynamic priority.

[0024] The fusion groups are sorted according to dynamic priority. Specifically, the fusion groups are sorted using a workload-aware priority function, which is as follows: ; in, For workload-aware values; for The number of times it appears; for Arithmetic strength; For the first A fusion group. By merging the groups according to... The patterns are sorted in descending order, prioritizing those that are both frequent and computationally intensive.

[0025] It should be noted that a fusion group represents a recurring operator collaboration pattern with a stable producer-consumer relationship, such as the three-stage structure of "convolution-batch normalization-nonlinear activation".

[0026] S3. For each high-priority fusion group, make decisions layer by layer across multiple coupled design dimensions in a preset order to generate a complete instruction configuration, and perform expansion, filtering and selection operations at each layer of decision-making.

[0027] S4. Use a lightweight cost model to evaluate the utility of the generated instruction configuration. If the utility value is greater than the preset threshold, proceed to S5; otherwise, discard the current instruction configuration.

[0028] S5. Generate an executable ISA-IR corresponding to the instruction configuration. Based on the ISA-IR, generate two sets of entities: a high-fidelity reference simulator and integration code. Based on the two generated entities, perform static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks on the instruction configuration in sequence. Store the verified instruction configuration into the extended instruction set and feed the verification results back to the operator feature library.

[0029] The aforementioned automated method for designing extended instructions based on operator semantics generates an operator feature library from the static program structure, dynamic profiling logs, and architecture configuration files of the target AI program. This constitutes an operator semantic understanding that can guide design, providing a semantic knowledge foundation for downstream searches. By dividing the static program structure of the target AI program into multiple fusion groups, redundant exploration of individual operator instances is avoided, supporting instruction reuse across instances. Dynamic priorities are used to sort the fusion groups, placing frequent and computationally intensive operator combinations in a priority position. By making decisions layer by layer in a fixed order across multiple coupled design dimensions, the actual mutual constraints are reflected in this fixed order, significantly narrowing the feasible space, improving search efficiency, and shortening the design cycle. Simultaneously, expansion, filtering, and selection operations are performed at each layer of decision-making, achieving automatic semantic mining of extended instructions within hardware capacity boundaries. Only after the decision is made is the utility evaluation of the generated instruction configuration performed using a lightweight cost model, effectively avoiding the introduction of inaccurate intermediate signals that could interfere with the design direction. The generated instruction configuration is verified for correctness through the ISA-IR dual-track generation mechanism and a five-level verification architecture, thereby ensuring that the generated instruction configuration is deployable and error-free. The verification results are also fed back to the operator feature library to optimize subsequent generation.

[0030] In one embodiment, reference Figure 3 Based on the static program structure, dynamic analysis logs, and architecture configuration files of the input target AI program, a unified structured operator descriptor is generated, and an operator feature library is constructed, including: Input the static program structure, dynamic analysis logs, and architecture configuration file of the target AI program, and parse them to obtain the corresponding structured information; The structured information corresponding to the static program structure, dynamic profiling logs, and architecture configuration files is encapsulated into a canonical text context containing defined tags and input into the LLM; LLM generates a unified structured operator descriptor based on the input canonical text context, and constructs an operator feature library.

[0031] Specifically, the structured information corresponding to the static program structure, dynamic profiling logs, and architecture configuration files is encapsulated into a specification text context containing tags such as "<static structure>", "<dynamic profiling>", and "<architecture configuration>".

[0032] In this embodiment, an LLM (Limited Language Management) engine is used as the semantic analysis engine. For each identified operator instance, structured information is encapsulated into a canonical text context containing defined labels, and this context is input into the LLM as part of a prompt. The LLM then generates a unified structured operator descriptor, constructing an operator feature library. By utilizing static program structure, dynamic profiling logs, and architecture configuration files, a semantic understanding of operators that can guide design is formed.

[0033] In one embodiment, the static program structure, dynamic profiling logs, and architecture configuration file of the target AI program are input and parsed to obtain the corresponding structured information, including: The high-level computation graph of the static program structure is analyzed, the operator category of each node is identified, the data dependency relationship between nodes is analyzed, the execution topology sorting is recorded, and operator pairs with stable producer-consumer relationships are identified as potential fusion candidates. Dynamic behavior data of each operator is obtained based on dynamic analysis logs; Based on the architecture configuration file, extract the hard constraint parameters that are directly related to the design space.

[0034] Specifically, operator categories include Generalized Matrix Multiplication (GEMM), Two-Dimensional Convolution (Conv2D), and Leaky Integral Delivery (LIF) neurons. By analyzing the static program structure, the nature of the computation is clarified. Dynamic behavior data for each operator includes the proportion of its execution time to the total program execution time, the number of dynamic instructions required to run the operator under the benchmark ISA, the average cycle per instruction (CPI), and arithmetic intensity. For loads with extremely low arithmetic intensity, close to zero, branch density can be used as a substitute signal. By analyzing the dynamic profiling logs, the importance of the computation can be quantified. Hard constraint parameters directly related to the design space include, but are not limited to: the bit width of vector registers, the total number of architecture registers, register file read / write port limits, and supported arithmetic precision formats. By analyzing the architecture configuration file, the location and physical boundaries of the computation are clarified.

[0035] In one embodiment, the LLM generates a unified structured operator descriptor based on the input canonical text context, from three levels: interpreting static semantics, evaluating dynamic bottlenecks, and combining architectural constraints.

[0036] Understandably, LLM reasoning proceeds from three levels: interpreting static semantics, assessing dynamic bottlenecks, and incorporating architectural constraints (i.e., what the operator "is" (static semantics), how important it is (dynamic behavior), and what it "runs on" (architectural constraints)). This process generates a unified structured operator descriptor. Specifically, interpreting static semantics involves understanding the operator's core operational primitives, data flow patterns, and potential fusion logic with preceding and following operators. Assessing dynamic bottlenecks involves determining whether the operator is computationally or memory-constrained based on execution ratio and arithmetic strength, and evaluating the urgency and value of its optimization. Incorporating architectural constraints involves reasoning about feasible parallelism and storage schemes under current physical limitations such as the number of registers and data path width. LLM integrates all analysis results and outputs a unified structured operator descriptor.

[0037] The generated structured operator descriptors contain fields including operator category, fusionable candidate producer-consumer, parallelism type (scalar / SIMD / tensor slice), memory access mode, execution percentage, and arithmetic strength. All descriptors are compiled into an operator feature library, which becomes the semantic knowledge foundation for downstream search.

[0038] In one embodiment, for each high-priority fusion group, decisions are made layer by layer across multiple coupled design dimensions in a preset order to generate a complete instruction configuration. At each layer of decision-making, expansion, filtering, and selection operations are performed, including: For each high-priority fusion group, an empty instruction configuration is initialized, and decisions are made layer by layer in the design dimensions of granularity, operator fusion, data type, boundary behavior and operand organization according to a preset order to generate a complete instruction configuration. Perform expansion, filtering, and selection operations at each level of decision-making.

[0039] For the five design dimensions of granularity, operator fusion, data type, boundary behavior, and operand organization, specifically, granularity is used to determine the processing width of the operation, with options including scalar, single instruction multiple data stream, and tensor slicing; operator fusion is used to determine which consecutive operators in the fusion group are fused into a single instruction within the granularity limits; data type is used to determine the data precision of input, intermediate computation, and output; boundary behavior is used to define how to handle the remaining "tail block" when a dimension of the input data is not an integer multiple of the current operation granularity; and operand organization is used to allocate source registers, destination registers, and determine the addressing mode.

[0040] In this embodiment, a decision tree is constructed using five design dimensions: granularity, operator fusion, data type, boundary behavior, and operand organization. The actual mutual constraints are reflected in a fixed dimensional order, thereby significantly narrowing the subsequent feasible space by selecting the previous dimension, shortening the design cycle, and reducing the consumption of computing resources.

[0041] In one embodiment, expansion, filtering, and selection operations are performed at each level of decision-making, including: At each level of decision-making, LLM infers semantically reasonable and technically feasible candidate options based on the current design state. The candidate options are filtered using architectural constraints as hard rules to obtain the legal candidate options; Legally valid candidate options are selected and included in the current configuration based on heuristic principles.

[0042] Specifically, during the expansion process, the current partial configuration, current decision dimension, feature descriptors of the target operator group, and architectural constraints are input to the LLM as the design state. The LLM, acting as a semantic branch generator, analyzes the current design state and infers several semantically reasonable and technically feasible candidate options for that dimension. For example, in the granularity dimension, the LLM might propose "SIMD" and "tensor slice," while excluding the "scalar" option because it cannot meet the performance requirements of this computationally intensive operator. During the filtering process, architectural constraints are used as hard rules to screen candidate options. For example, if the total number of simultaneous input / output registers required by the "tensor slice" option exceeds the number of physical registers in the target processor, or if the data path width required for its computation exceeds hardware support, it is eliminated. During the selection process, a valid candidate option is chosen heuristically and incorporated into the current configuration. Options that result in higher computational density and leave more room for choice in subsequent dimensions are prioritized.

[0043] In one embodiment, a lightweight cost model is used to evaluate the utility of the generated instruction configuration, including: The estimated system-level speedup, percentage increase relative to total processor area, and percentage increase in dynamic power consumption resulting from the instruction configuration calculated using a lightweight cost model are as follows: ; in, This is a utility assessment value; For the estimated system-level acceleration; This represents the percentage increase relative to the total processor area. This represents the percentage increase in dynamic power consumption. , , These are the weighting coefficients.

[0044] In one embodiment, the elements of ISA-IR include binary encoding, operand structure, state transition function, and read / write resource set.

[0045] Specifically, ISA-IR (ISA Intermediate Representation) is the authoritative definition of the semantics of each candidate instruction, including binary encoding, operand structure, state transition function, and read / write resource set. Binary encoding: The binary representation of the instruction in machine code, including the opcode and operand fields. Operand structure: Clearly defines the type, number, and location of the source and destination operands. State transition function: This is a pure function of the form: new machine state = function(copy of old machine state, immediate value); it completely and unambiguously defines the execution behavior of the instruction, i.e., how to modify the processor's architectural state. Read / write resource set: Explicitly declares all registers that the instruction will read and write at the architectural level.

[0046] In one embodiment, the instruction configuration is subjected to static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks sequentially based on the two generated sets of entities, including: The high-fidelity reference simulator is used for static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks; the integration code is used for integration checks.

[0047] Specifically, refer to Figure 4 Starting from the same ISA-IR source file, two sets of entities are automatically generated: one is a reference simulator implemented in a high-level language, serving as the "semantic gold standard"; the other is C++ integrated code for a target-cycle precise architecture simulator (such as the gem5 analysis model).

[0048] Static checking: Parsing the ISA-IR source file to check for syntactic correctness and semantic consistency; specifically, this includes verifying the legality of binary encoding (e.g., whether fields overlap or are missing), whether operand type declarations match actual usage, and whether there are any undeclared but referenced resources. This stage can quickly eliminate formal errors.

[0049] Resource analysis: By symbolically traversing the logic of state transition functions, all architectural resources actually read and written within the function are statically deduced; the deduced resource set is compared with the read and write resource set explicitly declared in the instruction description; if a resource written by the function but declared as read-only, or a resource declared but never used is found, it is determined to be a resource conflict error, which can prevent data hazards and compiler scheduling errors.

[0050] Dynamic execution verification: The candidate instruction is loaded into the reference simulator and run; the system generates a large number of random input stimuli covering the normal and boundary domains for the instruction; during execution, the monitor detects any illegal memory access, arithmetic exceptions or other runtime errors; this stage verifies the functional robustness of the instruction in dynamic scenarios.

[0051] Deterministic check: Select several sets of inputs and execute the instructions multiple times on the same set of inputs; compare the final results of the machine state after each execution, and ensure that all architecturally visible state bits are consistent bit by bit; this stage aims to eliminate any uncertain behavior caused by uninitialized variables or reliance on global state.

[0052] Integration check: This is the final and most critical consistency verification. The system maintains a random but fixed set of test sequences; these test sequences are run simultaneously in two environments: one is on the reference simulator of the "semantic gold standard" invoking the instruction, and the other is on the target architecture simulator executing the integration code automatically generated by ISA-IR; after execution, the final processor states in the two environments are compared; any deviation, even a single inconsistent flag bit, indicates an error introduced in the translation process from semantic definition to architectural implementation, and the instruction will be deemed unqualified.

[0053] Understandably, only instruction configurations that pass all five levels of verification—static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks—will be recognized as valid extension instructions that are semantically correct, behaviorally deterministic, and equivalent to the target architecture implementation.

[0054] This invention elevates the starting point of ISA extension design from traditional low-level instruction fragments to high-level operator semantics, enabling the system to identify the complete computational intent in edge AI loads such as attention mechanisms, normalization, and spiking neuron updates, thereby discovering semantic compression opportunities that are difficult to capture by traditional DFG subgraph mining methods.

[0055] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0056] In one embodiment, refer to Figure 5 An automated device for designing extended instructions based on operator semantics is provided, the device comprising: The operator feature library construction module 901 is used to generate a unified structured operator descriptor based on the static program structure, dynamic analysis logs and architecture configuration file of the input target AI program, and to build the operator feature library.

[0057] The fusion group division module 902 is used to divide the static program structure of the target AI program into multiple fusion groups based on the execution topology order and fusion candidate relationship in the operator feature library, and sort the fusion groups according to dynamic priority.

[0058] The instruction configuration generation module 903 is used to make decisions layer by layer on multiple coupled design dimensions for each high-priority fusion group in a preset order, generate a complete instruction configuration, and perform expansion, filtering and selection operations at each layer of decision.

[0059] The utility evaluation module 904 is used to evaluate the utility of the generated instruction configuration using a lightweight cost model. If the utility value is greater than the preset threshold, it will be transferred to the five-level verification module; otherwise, the current instruction configuration will be discarded.

[0060] The five-level verification module 905 is used to generate executable ISA-IRs corresponding to instruction configurations. Based on the ISA-IRs, two sets of entities are generated: a high-fidelity reference simulator and integration code. Based on the two sets of entities generated, static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks are performed on the instruction configurations in sequence. The verified instruction configurations are stored in the extended instruction set, and the verification results are fed back to the operator feature library.

[0061] Specific limitations regarding the automated device for designing extended instructions based on operator semantics can be found in the limitations of the automated method for designing extended instructions based on operator semantics mentioned above, and will not be repeated here. Each module in the aforementioned automated device for designing extended instructions based on operator semantics can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0062] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An automated method for designing extended instructions based on operator semantics, characterized in that, The method includes the following steps: S1. Generate a unified structured operator descriptor based on the static program structure, dynamic analysis logs and architecture configuration file of the input target AI program, and build an operator feature library; S2. Based on the execution topology order and fusion candidate relationship in the operator feature library, the static program structure of the target AI program is divided into multiple fusion groups, and the fusion groups are sorted according to dynamic priority. S3. For each high-priority fusion group, make decisions layer by layer in multiple coupled design dimensions according to a preset order, generate a complete instruction configuration, and perform expansion, filtering and selection operations at each layer of decision-making. S4. Use a lightweight cost model to evaluate the utility of the generated instruction configuration. If the utility value is greater than the preset threshold, proceed to S5; otherwise, discard the current instruction configuration. S5. Generate an executable ISA-IR corresponding to the instruction configuration. Based on the ISA-IR, generate two sets of entities: a high-fidelity reference simulator and integration code. Based on the two generated entities, perform static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks on the instruction configuration in sequence. Store the verified instruction configuration into the extended instruction set and feed the verification results back to the operator feature library.

2. The automated method for designing extended instructions based on operator semantics according to claim 1, characterized in that, Based on the static program structure, dynamic profiling logs, and architecture configuration files of the input target AI program, a unified structured operator descriptor is generated, and an operator feature library is constructed, including: Input the static program structure, dynamic analysis logs, and architecture configuration file of the target AI program, and parse them to obtain the corresponding structured information; The structured information corresponding to the static program structure, dynamic profiling logs, and architecture configuration files is encapsulated into a canonical text context containing defined tags and input into the LLM; LLM generates a unified structured operator descriptor based on the input canonical text context, and constructs an operator feature library.

3. The automated method for designing extended instructions based on operator semantics according to claim 2, characterized in that, The system takes the target AI program's static program structure, dynamic profiling logs, and architecture configuration file as input, parses them, and obtains the corresponding structured information, including: The high-level computation graph of the static program structure is analyzed, the operator category of each node is identified, the data dependency relationship between nodes is analyzed, the execution topology sorting is recorded, and operator pairs with stable producer-consumer relationships are identified as potential fusion candidates. Dynamic behavior data of each operator is obtained based on dynamic analysis logs; Based on the architecture configuration file, extract the hard constraint parameters that are directly related to the design space.

4. The automated method for designing extended instructions based on operator semantics according to claim 1, characterized in that, For each high-priority fusion group, decisions are made layer by layer across multiple coupled design dimensions in a preset order to generate a complete instruction configuration. At each decision level, expansion, filtering, and selection operations are performed, including: For each high-priority fusion group, an empty instruction configuration is initialized, and decisions are made layer by layer in the design dimensions of granularity, operator fusion, data type, boundary behavior and operand organization according to a preset order to generate a complete instruction configuration. Perform expansion, filtering, and selection operations at each level of decision-making.

5. The automated method for designing extended instructions based on operator semantics according to claim 4, characterized in that, Perform expansion, filtering, and selection operations at each level of decision-making, including: At each level of decision-making, LLM infers semantically reasonable and technically feasible candidate options based on the current design state. The candidate options are filtered using architectural constraints as hard rules to obtain the legal candidate options; Legally valid candidate options are selected and included in the current configuration based on heuristic principles.

6. The automated method for designing extended instructions based on operator semantics according to claim 1, characterized in that, A lightweight cost model is used to evaluate the utility of the generated instruction configuration, including: The estimated system-level speedup, percentage increase relative to total processor area, and percentage increase in dynamic power consumption resulting from the instruction configuration calculated using a lightweight cost model are as follows: ； in, This is a utility assessment value; For the estimated system-level acceleration; This represents the percentage increase relative to the total processor area. This represents the percentage increase in dynamic power consumption. , , These are the weighting coefficients.

7. The automated method for designing extended instructions based on operator semantics according to claim 1, characterized in that, Based on the two generated entities, the instruction configuration is sequentially subjected to static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks, including: The high-fidelity reference simulator is used for static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks; the integration code is used for integration checks.

8. The automated method for designing extended instructions based on operator semantics according to claim 1, characterized in that, The elements of ISA-IR include binary encoding, operand structure, state transition functions, and read / write resource set.

9. The automated method for designing extended instructions based on operator semantics according to claim 2, characterized in that, LLM generates a unified structured operator descriptor based on the context of the input canonical text, from three levels: interpreting static semantics, evaluating dynamic bottlenecks, and combining architectural constraints.

10. An automated device for designing extended instructions based on operator semantics, characterized in that, The device includes: The operator feature library construction module is used to generate unified structured operator descriptors and build the operator feature library based on the static program structure, dynamic analysis logs and architecture configuration files of the input target AI program. The fusion group partitioning module is used to divide the static program structure of the target AI program into multiple fusion groups based on the execution topology order and fusion candidate relationship in the operator feature library, and sort the fusion groups according to dynamic priority. The instruction configuration generation module is used to make decisions layer by layer on multiple coupled design dimensions for each high-priority fusion group in a preset order, generate complete instruction configurations, and perform expansion, filtering and selection operations at each layer of decision-making. The utility evaluation module is used to evaluate the utility of the generated instruction configuration using a lightweight cost model. If the utility value is greater than the preset threshold, it will be transferred to the five-level verification module; otherwise, the current instruction configuration will be discarded. The five-level verification module is used to generate executable ISA-IRs corresponding to instruction configurations. Based on the ISA-IRs, two sets of entities are generated: a high-fidelity reference simulator and integration code. Based on the two generated entities, the instruction configurations are subjected to static checks, resource analysis, dynamic execution verification, deterministic checks, and integration checks in sequence. The verified instruction configurations are stored in the extended instruction set, and the verification results are fed back to the operator feature library.

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