A method for entry creation in a branch predictor, a processor and an electronic device

Abstract

This specification relates to the field of computer technology, and more particularly to a method, processor, and electronic device for creating entries in a branch predictor. The method includes: detecting that a prediction table for a first target level has failed to predict a branch instruction; searching for a prediction fit value corresponding to a prediction table for a candidate level based on the instruction information of the branch instruction; wherein the candidate level is higher than the first target level; determining a prediction table for a second target level from the prediction table of the candidate level based on the prediction fit value; and creating an initial prediction entry for predicting the branch instruction within the range of prediction tables from the second target level to the highest level. This significantly improves the efficiency of the processor pipeline and the effective utilization of the overall storage hardware of the TAGE predictor.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and more particularly to a method, processor, and electronic device for creating entries in a branch predictor. Background Technology

[0002] In the field of modern high-performance processor architecture design, especially in processor systems that employ out-of-order execution technology, maximizing instruction throughput while maintaining efficient utilization of computing resources has become one of the core challenges in processor performance optimization.

[0003] During processor pipeline execution, branch instructions (such as if-else statements and loop structures) that are widespread in program code can lead to uncertainty in control flow. If this uncertainty is not handled effectively, it will inevitably cause pipeline stalls, resulting in idle computing resources and performance loss.

[0004] Currently, most mainstream high-performance branch prediction solutions in the industry adopt a prediction mechanism based on the TAGE (TAgged GEometric history length) architecture.

[0005] The core innovation of the TAGE predictor lies in its dynamically adaptive history management mechanism. This architecture employs a multi-level memory structure, with each memory bank equipped with an independent history length and tag identifier. It can select the optimal history window length for prediction decisions based on the local characteristics and global behavior patterns of branch instructions. The TAGE architecture effectively solves the accuracy bottleneck problem of traditional branch predictors when handling branch patterns at different time scales. This multi-level, adaptive prediction framework significantly improves the prediction accuracy of processors when facing complex program flows, providing key technical support for modern high-performance processors to achieve continuous instruction pipelining and efficient resource utilization.

[0006] However, the TAGE branch predictor uses a linear allocation mechanism that attempts step-by-step from lower-level tables to higher-level tables when creating prediction entries for new branch instructions.

[0007] In this scenario, for branches requiring long correlation distances, prediction capability is only available on high-level tables (e.g., the 10th table). To eventually allocate an entry to the required table, the branch needs to experience at least 9 mispredictions. After each misprediction, a new entry is allocated on tables 1 through 9, and finally, an entry is allocated on table 10 to avoid mispredictions. This leads to two problems: 1) A single branch instruction generates multiple mispredictions, causing multiple pipeline flushes. 2) Requesting an entry in multiple low-level tables results in wasted capacity. Summary of the Invention

[0008] To address the problems in the prior art, embodiments of this specification provide a method, apparatus, and electronic device for creating entries in a branch predictor. This significantly improves the efficiency of the processor pipeline and the effective utilization of the overall storage hardware of the TAGE predictor.

[0009] The specific technical solutions of the embodiments in this specification are as follows: On one hand, embodiments of this specification provide a method for creating entries in a branch predictor, the method comprising: If the prediction table for the first target level fails to predict the branch instruction, the prediction adaptation value corresponding to the prediction table for the candidate level is found based on the instruction information of the branch instruction; wherein, the candidate level is higher than the first target level. Based on the predicted fit value, a prediction table for the second target level is determined from the prediction table of the candidate levels; Within the range of the prediction table from the second target level to the highest level, initial prediction entries are created for predicting the branch instructions.

[0010] Further, based on the predicted fit value, determining the prediction table for the second target level from the prediction table of the candidate levels includes: From the prediction table of the candidate levels, select the prediction table with the largest prediction fit value as the prediction table of the second target level.

[0011] Furthermore, the method also includes: If multiple candidate level prediction tables have the same maximum prediction fit value, select the prediction table with the lowest level from the multiple candidate level prediction tables with the same maximum prediction fit value as the prediction table for the second target level.

[0012] Further, within the range of the prediction table from the second target level to the highest level, initial prediction entries for predicting the branch instructions are created, including: Within the range of the prediction table from the second target level to the highest level, in ascending order of level, find the items to be replaced that meet the preset conditions for effectiveness information and use them as target replacement items. The initial prediction entry is created to overwrite the target replacement entry.

[0013] Furthermore, the validity information satisfying a preset condition indicates that the validity information is 0.

[0014] Furthermore, after creating initial prediction entries for predicting the branch instructions, the method further includes: The prediction adaptation value, identified by the first index information, corresponding to the prediction table where the initial prediction entry is located, is reduced by a first preset value; wherein, the first index information is generated based on the instruction information of the branch instruction.

[0015] Furthermore, each level of prediction table corresponds to a set of saturation counters, and the prediction adaptation value is stored in the saturation counters corresponding to each level of prediction table.

[0016] Further, based on the instruction information of the branch instruction, the prediction adaptation value corresponding to the prediction table of the candidate level is looked up, including: Generate first index information based on the preset bits of the address of the branch instruction; Based on the first index information, the corresponding saturation counter value is found from the saturation counter group corresponding to each candidate level prediction table as the prediction adaptation value.

[0017] Furthermore, the method also includes updating the prediction fit values ​​corresponding to each level prediction table in the following manner: For retired branch instructions, determine the prediction table containing the prediction entries that provide prediction results for the retired branch instructions during the prediction phase; If the prediction direction of the prediction entry is correct and its effectiveness information meets the preset conditions, a reward is given to the prediction adaptation value identified by the second index information corresponding to the prediction table where the prediction entry is located; wherein, the second index information is generated based on the instruction information of the retired branch instruction.

[0018] Furthermore, it also includes: If the prediction direction of the prediction entry is incorrect, a penalty is imposed on the prediction adaptation value identified by the second index information corresponding to the prediction table where the prediction entry is located.

[0019] On the other hand, embodiments of this specification also provide an apparatus for creating entries in a branch predictor, the apparatus comprising: The lookup module is used to detect that the prediction table of the first target level fails to predict the branch instruction, and to look up the prediction adaptation value corresponding to the prediction table of the candidate level according to the instruction information of the branch instruction; wherein the candidate level is higher than the first target level. A determination module is used to determine a prediction table for a second target level from the prediction table of the candidate levels based on the prediction adaptation value; A creation module is used to create initial prediction entries for predicting the branch instructions within the range of the prediction table from the second target level to the highest level.

[0020] On the other hand, embodiments of this specification also provide a branch predictor, including multiple sets of saturation counters; the branch predictor is configured with multi-level prediction tables; each set of saturation counters is associated with a level of prediction table, wherein each saturation counter is used to store a count value characterizing the prediction fit value between the branch instruction and the prediction table of that level; the branch predictor is configured to perform any of the methods described above.

[0021] On the other hand, embodiments of this specification also provide a processor including any of the multi-level branch predictors described above.

[0022] On the other hand, embodiments of this specification also provide a computer device, including a memory and a computer program stored in the memory and executable on a processor, including any of the processors described above.

[0023] On the other hand, embodiments of this specification also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements any of the methods described above.

[0024] On the other hand, embodiments of this specification also provide a computer program product, including at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement any of the methods described above.

[0025] By employing the entry creation method in the branch predictor provided in the embodiments of this specification, and querying in real time based on dynamically learned prediction adaptation values, the most likely target level can be directly determined, and an entry can be created in the table at that level or a higher level. This means that, ideally, the branch instruction only needs to undergo one misprediction and pipeline flushing from its first prediction failure to achieving correct prediction capability. This reduces the number of additional mispredictions caused by the entry creation process to a theoretical minimum, greatly reducing the performance overhead caused by the branch predictor's own learning mechanism and significantly improving the efficiency of the processor pipeline.

[0026] Furthermore, the traditional step-by-step allocation process creates useless temporary entries for branch instructions in multiple lower-level tables. These entries, due to mismatched historical lengths, cannot provide accurate predictions for branch instructions, yet they occupy valuable storage space for extended periods, crowding out prediction resources for other lower-level table branches that might benefit from them, resulting in significant capacity waste. In the embodiments described in this specification, intelligent bootstrapping allows new entries to be created in one step at the target level with the highest fit or its nearest parent table, avoiding the creation of invalid entries in incompatible lower-level tables. This ensures that every storage unit in the prediction table can be used to store entries with actual predictive value, thereby significantly improving the overall effective utilization of the TAGE predictor's storage hardware. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 The diagram shown is a schematic of a multi-level branch predictor structure in related technologies; Figure 2 The diagram shown is a flowchart illustrating a method for creating entries in a branch predictor according to an embodiment of this specification. Figure 3 The diagram shown is a schematic of a multi-level branch predictor structure provided in an embodiment of this specification. Figure 4 The diagram shown is a flowchart illustrating an initial prediction entry provided in an embodiment of this specification. Figure 5 The diagram shown is a flowchart illustrating an embodiment of this specification for updating predicted adaptation values. Figure 6 The diagram shown is a structural schematic of an entry creation device in a branch predictor provided in an embodiment of this specification. Figure 7 The diagram shown is a structural schematic of a computer device provided in an embodiment of this specification.

[0029] Explanation of symbols in the attached drawings: 601. Search module; 602. Determine the module; 603. Create a module; 702. Computer equipment; 704, Processor; 706. Memory; 708. Drive mechanism; 710. Input / Output Module; 712. Input devices; 714. Output devices; 716. Presentation equipment; 718. Graphical User Interface; 720. Network interface; 722. Communication link; 724. Communication bus. Detailed Implementation

[0030] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0031] It should be noted that the terms "first," "second," etc., used in this specification, claims, and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0032] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the acquisition, storage, use, and processing of data in the technical solutions described in the embodiments of this application all comply with relevant regulations.

[0033] It should be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solutions of the embodiments of this specification. However, it does not mean that the applicant has used or necessarily used such solutions.

[0034] TAGE (TAgged GEometric) is a high-performance branch prediction algorithm commonly used in modern processor branch prediction. TAGE significantly improves branch prediction accuracy by using multi-level history lookup tables, each using a global history of varying lengths. Its basic idea is to capture branching behavior in a program using global histories of different lengths and dynamically select the most suitable history table for prediction. If more than one history lookup table is matched simultaneously, the prediction result from the lookup table with the longer global history is usually chosen.

[0035] Figure 1The basic structure of the TAGE branch predictor is shown. T0 is a branch predictor based on instruction address index (PC, program counter), i.e. Figure 1 The base predictor is shown. T1 to T4 are predictors based on PC and global branch history information (ghist, i.e., global hist). The higher the level of the table, the more global branch history information is input (the i-th TAGE table uses ghist[0:L(i)], the larger i is, the larger L(i) is), and the longer the related branch distance of the predicted branch is. Each TAGE table contains multiple entries, and each entry contains three types of information: label information (tag), prediction direction information (pred), and validity information (u). Figure 1 The "=?" indicates whether the hash result is a match, and the final output is the prediction result.

[0036] During prediction, TAGE uses global historical information and the program counter (PC) to generate an index address and tag information for each TAGE table (i.e., the TAGE table for each level) through a hash function. Then, it queries each TAGE table. Finally, during prediction, TAGE prioritizes the prediction results of higher-level tables. If a higher-level table is not matched, the prediction results of lower-level tables are used.

[0037] If the prediction provided by the i-th table fails, a replacement entry with a validity information (u) of 0 will be searched in the (i+1)-th table. Then, a new entry will be created for the current instruction information to replace it. The tag of the new entry is generated based on the PC and ghist of this branch instruction (the length of ghist is adapted to the (i+1)-th table), and the validity information (u) will be initialized to 0.

[0038] As can be seen, during the program's execution, it requests entries from higher-level tables in TAGE level by level until the branch association distance that the TAGE table can cover is greater than or equal to the branch association distance required by the program's branch instructions.

[0039] As the size of the TAGE increases, the length of the ghist also grows, leading to a continuous increase in the number of tables within the TAGE. For branches requiring longer join distances, multiple allocation processes are needed to secure a suitable table, wasting TAGE capacity and causing more pipeline flushes.

[0040] To address the aforementioned technical issues, this specification provides a method for creating entries in a branch predictor.

[0041] In this scheme, a saturation counter is added to each TAGE table. The value of the saturation counter represents the prediction fit between the instruction information of the current branch and the TAGE table at that level. When requesting a TAGE entry, the new entry is preferentially placed in the TAGE table with the larger saturation counter value, thereby requesting the branch to the appropriate TAGE table at once, reducing the space occupied by the TAGE table, reducing the number of pipeline flushes, and improving program performance.

[0042] See details Figure 2 This specification provides a method for creating entries in a branch predictor, as illustrated in the embodiments thereof. The method includes: 201: If the prediction table for the first target level fails to predict the branch instruction, the prediction adaptation value corresponding to the prediction table of the candidate level is found according to the instruction information of the branch instruction; wherein, the candidate level is higher than the first target level.

[0043] In the embodiments described in this specification, a set of saturation counters is added to the prediction table for each level to record the prediction fit value.

[0044] The index of the saturation counter can be determined by the instruction information of the branch instruction. In one embodiment, first index information is generated based on preset bits of the address of the branch instruction; based on the first index information, the corresponding saturation counter value is searched from the saturation counter group corresponding to each candidate level prediction table as the prediction adaptation value.

[0045] As an example, see Figure 3 , Figure 3 The prediction tables for four levels, T1-T4, are shown. For each level, four saturation counters are added, with indices idx=0, idx=1, idx=2, and idx=3, respectively. The index is generated using the instruction information of the branch instructions. For example, it is obtained by XORing the lower 6 bits of the instruction address (PC), i.e., idx=PC[0:1]^PC[2:3]^PC[4:5].

[0046] It should be noted that the embodiments in this specification do not limit the number of saturated counters in each saturated counter group or the method of generating the index through instruction information; the above is merely an illustrative example.

[0047] also, Figure 3 In this context, Counters_T1, Counters_T2, Counters_T3, and Counters_T4 represent the saturation counter groups corresponding to the four prediction tables from T1 to T4, respectively. They can also be understood as tables that record the values ​​of each saturation counter. Figure 1The "=?" indicates whether the hash result is a match, and the final output is the prediction result.

[0048] For the current branch instruction, if the prediction result of the prediction table of the first target level is used and the prediction fails, an index is generated based on the instruction information of the branch instruction. The corresponding prediction fit can be determined by querying each prediction table above the first target level based on the generated index.

[0049] As an example, if the highest level is 10 and the first target level is 4, then the prediction fit can be determined for the prediction tables for the six levels from 5 to 10.

[0050] For example, when determining the prediction fit for the prediction table of the nth level, the value of idx can be calculated according to idx=PC[0:1]^PC[2:3]^PC[4:5]. The value of idx in the index information is used to locate a specific counter in the saturation counter group corresponding to the nth level prediction table, so as to query the prediction fit.

[0051] 202: Based on the predicted fit value, determine the prediction table of the second target level from the prediction table of the candidate levels.

[0052] In some embodiments of this specification, the prediction table with the largest prediction fit value is selected as the prediction table for the second target level from the prediction table of candidate levels. Specifically, if there exists a prediction table with the largest prediction fit value, the corresponding level is determined as the second target level.

[0053] In some embodiments of this specification, if multiple candidate level prediction tables have the same maximum prediction fit value, the prediction table with the lowest level among the multiple candidate level prediction tables with the same maximum prediction fit value is selected as the prediction table for the second target level.

[0054] Specifically, the level with the highest prediction fit indicates that the past behavior pattern of this branch instruction (formed through counter training) best matches the historical length of that level. Therefore, creating a new entry at that level or its higher levels is prioritized. If multiple candidate levels have the same maximum prediction fit value, the one with the lowest value is selected to conserve resources in the higher-level prediction table.

[0055] 203: Within the range of the prediction table from the second target level to the highest level, create initial prediction entries for predicting the branch instructions.

[0056] In one embodiment, after determining the second target level, initial prediction entries are first created for branch instructions within the prediction table of the second target level. The tag of the created initial prediction entry is generated based on the instruction information of the branch instruction and the corresponding length of ghist, and the validity information (u) is initialized to 0.

[0057] By employing the entry creation method in the branch predictor provided in the embodiments of this specification, and querying in real time based on dynamically learned prediction adaptation values, the most likely target level can be directly determined, and an entry can be created in the table at that level or a higher level. This means that, ideally, the branch instruction only needs to undergo one misprediction and pipeline flushing from its first prediction failure to achieving correct prediction capability. This reduces the number of additional mispredictions caused by the entry creation process to a theoretical minimum, greatly reducing the performance overhead caused by the branch predictor's own learning mechanism and significantly improving the efficiency of the processor pipeline.

[0058] Furthermore, the traditional step-by-step allocation process creates useless temporary entries for branch instructions in multiple lower-level tables. These entries, due to mismatched historical lengths, cannot provide accurate predictions for branch instructions, yet they occupy valuable storage space for extended periods, crowding out prediction resources for other lower-level table branches that might benefit from them, resulting in significant capacity waste. In the embodiments described in this specification, intelligent bootstrapping allows new entries to be created in one step at the target level with the highest fit or its nearest parent table, avoiding the creation of invalid entries in incompatible lower-level tables. This ensures that every storage unit in the prediction table can be used to store entries with actual predictive value, thereby significantly improving the overall effective utilization of the TAGE predictor's storage hardware.

[0059] In one embodiment, see Figure 4 Within the range of the prediction table from the second target level to the highest level, initial prediction entries for predicting the branch instructions are created, including: 401: Within the range of the prediction table from the second target level to the highest level, in ascending order of level, find the replacement entries whose validity information meets the preset conditions and use them as target replacement entries; 402: Create the initial prediction entry to overwrite the target replacement entry.

[0060] To increase the chances of success, find suitable vacant or replaceable entries within the range of the second target level to the highest level to create the initial prediction entry.

[0061] Among these, the validity information is the key basis for determining whether an entry can be replaced. It is typically 1 bit, used to represent the usefulness of the historical prediction results for that entry. For example, u=0 indicates that the entry was not correctly predicted, its prediction value is low, and it has the highest priority for replacement. u=1 indicates that the entry has been verified as correctly predicted, and its prediction value is high.

[0062] Assuming the branch predictor has n levels of prediction tables (T1, T2, ..., Tn), the second target level is determined to be z, and the branch instruction address corresponding to the initial prediction entry to be created is PC. The steps for finding and replacing the target entry can include: Step 1: Set the current search rank variable k=z. Start searching from the candidate table Tz with the lowest rank and proceed to the tables with higher ranks in sequence.

[0063] Step 2: Find the item to be replaced in the current level prediction table Tk.

[0064] In the prediction table Tk, the entries to be replaced in the prediction table for the current level k are first determined.

[0065] In one embodiment, a set of candidate entries is located using hash calculation based on the current branch instruction PC and the global history length used for the corresponding level. Among these candidate entries, the entry most deserving replacement is determined using a replacement algorithm within the predictor, and this entry is selected as the replacement entry in the current level k prediction table. For example, the replacement algorithm could be an LRU (least recently used) algorithm.

[0066] Step 3: Determine whether the validity information of the item to be replaced meets the preset conditions.

[0067] Check the validity information of the current level k to be replaced as determined in step 2. If the condition is met (e.g., u=0), the search is successful and the entry is determined as the final target replacement entry.

[0068] If the condition is not met, it means that no ideal replacement item can be found at the current level k, and a higher level needs to be tried. In this case, the current search level k is incremented by 1, and step 1 is returned to be executed again.

[0069] Step 4: If all levels from Tz to Tn have been traversed and no target replacement entry has been found, then a forced case operation is performed.

[0070] In one embodiment, the validity information of all items to be replaced, determined by the replacement algorithm, across all levels from Tz to Tn, is forcibly set to 0. This operation does not delete the items, but rather changes their status flags. After the clearing operation is complete, the search for the target replacement item restarts from level Tz, proceeding in ascending order of level. Because the validity information of all relevant items to be replaced is set to 0, the target replacement item can be found quickly.

[0071] Once the target replacement entry is found, an overwrite operation is performed. First, a label for the new entry is generated based on the current branch instruction PC and the global history length used at the corresponding level (let's say Tm). The predicted direction of the new entry is initialized to the actual direction of execution of that branch instruction. The validity information u of the new entry is initialized to 0.

[0072] The prepared new entry data (label, prediction direction, u=0) is completely written to the storage location of the determined target replacement entry, replacing all the information of the original entry and making it a brand new initial prediction entry for the current branch instruction.

[0073] As can be seen, in the embodiments of this specification, priority is given to replacing entries that have the least impact on the predictor's performance. These entries have low predictive value or have not yet been verified, and replacing them has the least impact on the overall accuracy of the predictor. This minimizes the interference of the valuable prediction table storage space reclamation and reallocation process with the established and effective prediction knowledge base.

[0074] In some embodiments of this specification, after creating an initial prediction entry for predicting branch instructions, the method includes: reducing the prediction adaptation value identified by first index information corresponding to the prediction table where the initial prediction entry is located by a first preset value; wherein the first index information is generated based on the instruction information of the branch instruction.

[0075] After successfully creating the initial prediction entries, this invention introduces a key negative feedback adjustment mechanism to dynamically optimize the prediction fit value, enabling the system to adaptively balance resource allocation.

[0076] The core operation is to perform a reduction operation on the specific prediction adaptation value associated with the specific prediction table carrying the new entry. Specifically, this includes: recording the prediction table level that was just successfully created as Tm; generating first index information using a preset hash function based on the program counter address of the branch instruction that triggered this creation process; for example, taking the lower 6 bits of the address (PC[5:0]) and calculating PC[0:1] ^ PC[2:3] ^ PC[4:5] to obtain a 2-bit index value; this index information is used to locate a specific counter in the saturation counter group corresponding to each level of prediction table; assuming that the specific saturation counter identified by the first index information is located in the saturation counter group associated with prediction table Tm, then subtracting a first preset value from the count value (i.e., the prediction adaptation value) stored in the saturation counter. In a preferred embodiment, the first preset value is 1, i.e., performing a "decrease by 1" operation.

[0077] In the embodiments described in this specification, considering that the prediction table is a valuable and limited resource of storage space, its prediction fit value is reduced each time the resource is used (creating a new entry). This ensures that even if a prediction table performs exceptionally well for a certain type of branch instruction history, its fit value will decrease due to multiple reduction operations after creating multiple entries for it, thereby reducing the probability of it being selected by subsequent similar branch instructions. This effectively prevents a certain type of branch instruction from monopolizing high-level table resources.

[0078] The following explains the update method for the prediction fit values ​​corresponding to each level of the prediction table. (See also...) Figure 5 A flowchart illustrating the process of updating predicted fit values, including: 501: For retired branch instructions, determine the prediction table containing the prediction entries that provide prediction results for the retired branch instructions during the prediction phase.

[0079] The scheme described in this application not only includes negative feedback adjustment of the predicted fit value when creating an entry, but also includes a dynamic learning and reward mechanism activated after the branch instruction is executed. This mechanism is responsible for updating the predicted fit value based on the actual utility of the prediction result, thereby completing a full closed loop of system adaptation.

[0080] This dynamic learning and reward mechanism is triggered during the branch instruction retirement phase of the processor pipeline. At this point, the actual execution direction of the branch instruction has been finalized.

[0081] For currently retired branch instructions, backtrack the forecast information during the forecasting phase to determine which specific forecast entry provided the final forecast direction for that branch instruction. Record the forecast table level where that forecast entry belongs.

[0082] 502: If the prediction direction of the prediction entry is correct and its effectiveness information meets the preset conditions, a reward is given to the prediction adaptation value identified by the second index information corresponding to the prediction table where the prediction entry is located; wherein, the second index information is generated based on the instruction information of the retired branch instruction.

[0083] The system determines whether the prediction direction stored in the prediction entry is consistent with the actual execution direction of the branch instruction. If they are consistent, the first condition is met. Then, it determines whether the validity information of the prediction entry meets a preset condition. In a preferred embodiment, the preset condition is that the validity information equals 0, indicating that the entry is an unverified entry. If u=0, a reward is given to the prediction adaptation value identified by the second index information corresponding to the prediction table where the prediction entry is located.

[0084] For example, based on the program counter address of the retired branch instruction, a second index is generated using a preset hash function. The generation method can be the same as that of the first index (e.g., XORing the low bits of PC[5:0]) to ensure index consistency, thereby locating the counter shared by the same group of branch instructions.

[0085] Locate the specific saturation counter identified by the second index information within the saturation counter group associated with the level Tk of the predicted entry. Increase the prediction fit value stored in this counter by a preset reward amount. In a preferred embodiment, this reward amount is 2. Choosing a reward amount greater than 1 (relative to the penalty amount of 1 when creating the entry) embodies a strategy of reinforcing successful experiences, so that a successful prediction made by a newly created, unverified entry can significantly improve the fit of its corresponding prediction table level, thereby guiding subsequent similar branches to create prediction tables at the corresponding level.

[0086] In one embodiment, if the prediction direction of the prediction entry is incorrect, a penalty is imposed on the prediction adaptation value identified by the second index information corresponding to the prediction table where the prediction entry is located.

[0087] To construct a more complete and robust adaptive learning system, in the embodiments of this specification, a prediction error penalty mechanism can be further introduced on the basis of the reward mechanism for newly created entries. This mechanism, as a symmetrical supplement to the reward mechanism, ensures that the prediction fit value can more comprehensively and sensitively reflect the true fit relationship between the prediction table and the branch instructions.

[0088] The aforementioned error penalty mechanism is also triggered based on branch instruction retirement. The only difference is that when it is determined that the prediction direction of a prediction entry is incorrect, the prediction fit value stored in the saturation counter is reduced by a preset penalty amount. The penalty amount can be a fixed value (e.g., 1) or a value dynamically calculated based on the severity of the error (e.g., the cost of pipeline flushing caused by incorrect prediction).

[0089] During program execution, different phases occur, and branching behavior patterns may abruptly change. When a phase transition occurs, the high prediction fitness values ​​trained based on the old model may become misleading. A penalty mechanism can proactively correct these erroneous overestimations. Whenever a prediction table from the old model makes an incorrect prediction under the new model, its fitness value is reduced, making room for other prediction tables adapted to the new model (whose fitness values ​​may initially be lower). This shortens the predictor's performance recovery time after a phase transition and improves the processor's overall robustness.

[0090] Based on the method for creating entries in a branch predictor described above, embodiments of this specification also provide an apparatus for creating entries in a branch predictor. The apparatus may include a system (including a distributed system), software (application), module, component, server, client, etc., using the method described in the embodiments of this specification, combined with necessary hardware implementation. Based on the same innovative concept, the apparatuses in one or more embodiments provided in this specification are as described in the following embodiments. Since the implementation schemes and methods for solving the problem by the apparatus are similar, the implementation of the specific apparatus in the embodiments of this specification can refer to the implementation of the aforementioned method, and repeated details will not be repeated. As used below, the terms "unit" or "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0091] Specifically, refer to Figure 6 As shown in the embodiments of this specification, an apparatus for creating entries in a branch predictor includes: The lookup module 601 is used to detect that the prediction table of the first target level fails to predict the branch instruction, and to look up the prediction adaptation value corresponding to the prediction table of the candidate level according to the instruction information of the branch instruction; wherein the candidate level is higher than the first target level. The determining module 602 is used to determine the prediction table of the second target level from the prediction table of the candidate levels based on the prediction adaptation value; The creation module 603 is used to create initial prediction entries for predicting the branch instructions within the range of the prediction table from the second target level to the highest level.

[0092] The beneficial effects obtained by the apparatus provided in the embodiments of this specification are consistent with the beneficial effects obtained by the methods described above, and will not be repeated here.

[0093] This specification also provides a branch predictor, including multiple sets of saturation counters; the branch predictor is configured with multi-level prediction tables; each set of saturation counters is associated with a level of prediction table, wherein each saturation counter is used to store a count value characterizing the prediction fit value between the branch instruction and the prediction table at that level; the branch predictor is configured to perform the entry creation method in any of the above-described branch predictors.

[0094] Reference Figure 7 As shown, based on the method for creating entries in a branch predictor described above, one embodiment of this specification also provides a computer device 702, wherein the above method runs on the computer device 702. The processor included in the computer device can configure the branch predictor mentioned in this embodiment.

[0095] The computer device 702 may include one or more processors 704, such as one or more central processing units (CPUs), each of which may implement one or more hardware threads. The computer device 702 may also include any memory 706 for storing information of any kind, such as code, settings, data, etc. Non-limitingly, for example, memory 706 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Furthermore, any memory may provide volatile or non-volatile retention of information. Furthermore, any memory may represent a fixed or removable component of the computer device 702. In one case, when processor 704 executes associated instructions stored in any memory or combination of memories, the computer device 702 may perform any operation of the associated instructions. The computer device 702 also includes one or more drive mechanisms 708 for interacting with any memory, such as hard disk drive mechanisms, optical disk drive mechanisms, etc.

[0096] Computer device 702 may also include an input / output module 710 (I / O) for receiving various inputs (via input device 712) and providing various outputs (via output device 714). A specific output mechanism may include a presentation device 716 and an associated graphical user interface (GUI) 718. In other embodiments, the input / output module 710 (I / O), input device 712, and output device 714 may be omitted, and the device may function solely as a computer device within a network. Computer device 702 may also include one or more network interfaces 720 for exchanging data with other devices via one or more communication links 722. One or more communication buses 724 couple the components described above together.

[0097] Communication link 722 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 722 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0098] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the above-described method.

[0099] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the steps of the above-described method.

[0100] This specification also provides a computer program product, including at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the steps of the above method.

[0101] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0102] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.

[0103] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0104] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0105] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0106] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0107] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0108] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0109] This specification uses specific embodiments to illustrate the principles and implementation methods of this specification. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this specification. Therefore, the content of this specification should not be construed as a limitation of this specification.

Claims

1. A method of entry creation in a branch predictor, characterized by, The method includes: If the prediction table for the first target level fails to predict the branch instruction, the prediction adaptation value corresponding to the prediction table for the candidate level is found based on the instruction information of the branch instruction; wherein, the candidate level is higher than the first target level. Based on the predicted fit value, a prediction table for the second target level is determined from the prediction table of the candidate levels; Within the range of the prediction table from the second target level to the highest level, initial prediction entries are created for predicting the branch instructions.

2. The method of claim 1, wherein, Based on the predicted fit value, determining the prediction table for the second target level from the prediction table of the candidate levels includes: From the prediction table of the candidate levels, select the prediction table with the largest prediction fit value as the prediction table of the second target level.

3. The method of claim 2, wherein, The method further includes: If multiple candidate level prediction tables have the same maximum prediction fit value, select the prediction table with the lowest level from the multiple candidate level prediction tables with the same maximum prediction fit value as the prediction table for the second target level.

4. The method according to any one of claims 1 to 3, characterized in that, Within the range of the prediction table from the second target level to the highest level, initial prediction entries are created for predicting the branch instructions, including: Within the range of the prediction table from the second target level to the highest level, in ascending order of level, find the items to be replaced that meet the preset conditions for effectiveness information and use them as target replacement items. The initial prediction entry is created to overwrite the target replacement entry.

5. The method according to claim 4, characterized in that, The validity information meeting the preset conditions indicates that the validity information is 0.

6. The method of claim 1, wherein, After creating initial prediction entries for predicting the branch instructions, the method further includes: The prediction adaptation value, identified by the first index information, corresponding to the prediction table where the initial prediction entry is located, is reduced by a first preset value; wherein, the first index information is generated based on the instruction information of the branch instruction.

7. The method of claim 1, wherein, Each level of prediction table corresponds to a set of saturation counters, and the prediction fit values ​​are stored in the saturation counters corresponding to each level of prediction table.

8. The method of claim 7, wherein, Based on the instruction information of the branch instruction, the prediction fit value corresponding to the prediction table of the candidate level is found, including: Generate first index information based on the preset bits of the address of the branch instruction; Based on the first index information, the corresponding saturation counter value is found from the saturation counter group corresponding to each candidate level prediction table as the prediction adaptation value.

9. The method of claim 1, wherein, The method further includes updating the prediction fit values ​​corresponding to each level of the prediction table in the following manner: For retired branch instructions, determine the prediction table containing the prediction entries that provide prediction results for the retired branch instructions during the prediction phase; If the prediction direction of the prediction entry is correct and its effectiveness information meets the preset conditions, a reward is given to the prediction adaptation value identified by the second index information corresponding to the prediction table where the prediction entry is located; wherein, the second index information is generated based on the instruction information of the retired branch instruction.

10. The method of claim 9, wherein, Also includes: If the prediction direction of the prediction entry is incorrect, a penalty is imposed on the prediction adaptation value identified by the second index information corresponding to the prediction table where the prediction entry is located.

11. An apparatus for entry creation in a branch predictor, the apparatus comprising: The device includes: The lookup module is used to detect that the prediction table of the first target level fails to predict the branch instruction, and to look up the prediction adaptation value corresponding to the prediction table of the candidate level according to the instruction information of the branch instruction; wherein the candidate level is higher than the first target level. A determination module is used to determine a prediction table for a second target level from the prediction table of the candidate levels based on the prediction adaptation value; A creation module is used to create initial prediction entries for predicting the branch instructions within the range of the prediction table from the second target level to the highest level.

12. A branch predictor, characterized by It includes multiple sets of saturation counters; the branch predictor is configured with multi-level prediction tables; each set of saturation counters is associated with a level of prediction table, wherein each saturation counter is used to store a count value that represents the prediction fit value between the branch instruction and the prediction table of that level. The branch predictor is configured to perform the method as described in any one of claims 1 to 10.

13. A processor, characterized in that, Includes the branch predictor as described in claim 12 above.

14. A computer device comprising a memory, a computer program stored on the memory and executable on a processor, characterized in that, Includes the processor as described in claim 13 above.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 10.

16. A computer program product, characterized in that, It includes at least one instruction or at least one program segment, said at least one instruction or said at least one program segment being loaded and executed by a processor to implement the method as claimed in any one of claims 1 to 10.

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