A data transmission method and device, electronic equipment, and storage medium

Abstract

This invention relates to the field of data processing technology, and in particular to a data transmission method, apparatus, electronic device, and storage medium. The invention adds a temporary destination register to cross-type instructions, establishes data dependencies during the renaming phase, and splits the instruction into two micro-operations. It utilizes the processor's existing bypass network to transmit the result of the first micro-operation to the second micro-operation as the source operand, eliminating the need for dedicated data paths, additional register read / write ports, or temporary buffers, thus avoiding wasted hardware resources and chip area overhead. The continuous issue mechanism ensures data transmission is completed within the effective window of the bypass network, making instruction execution latency comparable to ordinary instructions and maintaining high performance. Simultaneously, it eliminates timing issues caused by long-distance data transmission, helping the processor maintain a high clock frequency. Furthermore, adding cross-type operations only requires modification of the microcode control logic, without altering the register file hardware, significantly enhancing design scalability and flexibility.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a data transmission method, apparatus, electronic device, and storage medium. Background Technology

[0002] Modern high-performance out-of-order execution processors typically contain register files of various types, including integer, floating-point, and vector registers. These register files are physically located close to their respective execution units to enable proximity access. In the processor microarchitecture, there exists a class of instructions that manipulate registers across different types, such as the integer-to-floating-point (i2f) instruction, which reads data from an integer register, converts it, and then writes it to a floating-point register.

[0003] For this type of instruction, existing technologies mainly employ two implementation methods. One method involves establishing a dedicated data path, adding an extra read / write port between the integer register file and the floating-point execution unit to achieve direct data transmission. The other method executes the instruction in two steps: first, data is read from the integer register and temporarily stored in a temporary buffer, and then the temporarily stored data is read and converted. This requires the addition of a temporary buffer and control logic.

[0004] However, existing solutions have significant drawbacks. First, cross-type instructions typically account for less than 1% of actual workloads, and the aforementioned methods of adding dedicated data paths and register read / write ports result in low hardware resource utilization, consuming a large amount of chip area and power. Second, the physical separation of different types of register files increases signal latency and power consumption due to long data paths, potentially causing timing constraints and forcing the processor to reduce its clock frequency. Furthermore, the discrete execution approach requires additional temporary buffers, further increasing hardware costs and introducing additional latency cycles. As instruction sets expand, each additional cross-type operation in existing solutions requires corresponding hardware support, leading to a linear increase in design complexity. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a data transmission method, apparatus, electronic device, and storage medium to achieve efficient data transmission across register types without adding dedicated hardware resources for cross-type register operation instructions, thereby reducing chip area and power consumption overhead, maintaining high-performance processor execution, and enhancing design scalability.

[0006] In a first aspect, embodiments of the present invention provide a data transmission method, the method comprising: Identify cross-type register operation instructions; A temporary destination register is added to the cross-type register operation instruction, and the temporary destination register is designated as the destination register of the first micro-operation. The original destination register of the cross-type register operation instruction is designated as the destination register of the second micro-operation. The first micro-operation is a micro-operation used to perform source register read operation after splitting the cross-type register operation instruction, and the second micro-operation is a micro-operation used to perform data type conversion and destination register write operation after splitting the cross-type register operation instruction. By using a renaming mechanism, the same physical register identifier is assigned to the destination register of the first micro-operation and the source operand register of the second micro-operation, so as to establish the data dependency relationship between the second micro-operation and the first micro-operation. Cross-type register operation instructions are split into a first micro-operation and a second micro-operation, and the split first micro-operation and second micro-operation inherit the data dependency relationship. In response to data dependencies, the first and second micro-operations are successively issued to the execution unit; The execution result of the first micro-operation is transmitted to the second micro-operation through the processor's bypass network, serving as the source operand of the second micro-operation.

[0007] In conjunction with the first aspect, a temporary destination register is added for cross-type register operation instructions, including: Allocate a temporary destination register for cross-type register operation instructions. The type of the temporary destination register is the same as the type of the source register of the cross-type register operation instructions. Use the source operand register of the cross-type register operation instruction as the source operand register of the first micro-operation, and use the temporary destination register as the destination register of the first micro-operation. Use the temporary destination register as the source operand register for the second micro-operation, and use the original destination register of the cross-type register operation instruction as the destination register for the second micro-operation.

[0008] In conjunction with the first aspect, the step of assigning the same physical register identifier to the destination register of the first micro-operation and the source operand register of the second micro-operation to establish a data dependency of the second micro-operation on the first micro-operation includes: Assign a first physical register identifier to the destination register of the first micro-operation; When renaming the source operand register of the second micro-operation, the source operand register of the second micro-operation is mapped to the first physical register identifier so that the first micro-operation and the second micro-operation share the same physical register identifier.

[0009] In conjunction with the first aspect, the step of sequentially issuing the first micro-operation and the second micro-operation to the execution unit in response to data dependencies includes: The first micro-operation is issued to the first type of execution unit corresponding to the source register type, and the second micro-operation is issued to the second type of execution unit corresponding to the target register type; The scheduler in the launch queue sets the priority for the second micro-operation, so that the second micro-operation is launched within one or more clock cycles after the launch of the first micro-operation, and the launch interval between the first micro-operation and the second micro-operation does not exceed the effective transmission window of the bypass network.

[0010] In conjunction with the first aspect, the step of transmitting the execution result of the first micro-operation to the second micro-operation via the processor's bypass network as the source operand of the second micro-operation includes: The execution result of the first micro-operation after execution in the first type of execution unit is driven to the data bus of the bypass network; The bypass network broadcasts the execution results to the second type of execution unit; The second micro-operation captures the execution result from the bypass network as the source operand when the second type of execution unit is issued.

[0011] In conjunction with the first aspect, the first micro-operation only performs a register read operation in the first execution unit corresponding to the source register type.

[0012] In conjunction with the first aspect, after the second micro-operation captures the execution result from the bypass network as the source operand, it also includes: Perform data type conversion calculations and obtain the conversion results; Write the conversion calculation results to the register file corresponding to the target register type.

[0013] Secondly, this application provides a data transmission apparatus for performing the method described above; the apparatus includes: The decoding module is used to identify cross-type register operation instructions; The temporary register allocation module is used to add a temporary destination register for cross-type register operation instructions, and designate the temporary destination register as the destination register of the first micro-operation, and designate the original destination register of the cross-type register operation instructions as the destination register of the second micro-operation; wherein, the first micro-operation is a micro-operation used to perform source register read operation after splitting the cross-type register operation instructions, and the second micro-operation is a micro-operation used to perform data type conversion and target register write operation after splitting the cross-type register operation instructions; The dependency establishment module is used to assign the same physical register identifier to the destination register of the first micro-operation and the source operand register of the second micro-operation through a renaming mechanism, so as to establish the data dependency relationship between the second micro-operation and the first micro-operation. The instruction splitting module is used to split cross-type register operation instructions into a first micro-operation and a second micro-operation. The split first micro-operation and the second micro-operation inherit the data dependency relationship. The launch control module is used to continuously launch the first micro-operation and the second micro-operation to the execution unit in response to data dependencies; The bypass transmission module is used to transmit the execution result of the first micro-operation to the second micro-operation through the processor's bypass network, as the source operand of the second micro-operation.

[0014] Thirdly, this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor runs the computer program to cause the electronic device to perform the above-described method.

[0015] Fourthly, this application provides a readable storage medium storing computer program instructions, which are read and executed by a processor to perform the above-described method.

[0016] The embodiments of the present invention bring the following beneficial effects: The present application provides a data transmission method, apparatus, electronic device, and storage medium. The method includes: identifying cross-type register operation instructions; adding a temporary destination register to the cross-type register operation instructions and designating the temporary destination register as the destination register of a first micro-operation, and designating the original destination register of the cross-type register operation instructions as the destination register of a second micro-operation; wherein, the first micro-operation is a micro-operation used to perform a source register read operation after splitting the cross-type register operation instructions, and the second micro-operation is a micro-operation used to perform a data type conversion and a target register write operation after splitting the cross-type register operation instructions; through a renaming mechanism, assigning the same physical register identifier to the destination register of the first micro-operation and the source operand register of the second micro-operation to establish a data dependency relationship between the second micro-operation and the first micro-operation; splitting the cross-type register operation instructions into the first micro-operation and the second micro-operation, the split first micro-operation and the second micro-operation inheriting the data dependency relationship; responding to the data dependency relationship, continuously issuing the first micro-operation and the second micro-operation to the execution unit; the execution result after the first micro-operation is executed is transmitted to the second micro-operation through the processor's bypass network as the source operand of the second micro-operation.

[0017] This invention adds a temporary destination register to cross-type instructions, establishes data dependencies during the renaming phase, and splits the instruction into two micro-operations. It utilizes the processor's existing bypass network to transmit the result of the first micro-operation to the second micro-operation as the source operand. Compared to existing technologies, this invention eliminates the need for dedicated data paths, additional register read / write ports, or temporary buffers, avoiding wasted hardware resources and chip area overhead. The continuous issue mechanism ensures data transmission is completed within the effective window of the bypass network, making instruction execution latency comparable to ordinary instructions and maintaining high performance. Simultaneously, it eliminates timing issues caused by long-distance data transmission, helping the processor maintain a high clock frequency. Furthermore, adding cross-type operations only requires modification of the microcode control logic, without altering the register file hardware, significantly enhancing design scalability and flexibility.

[0018] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 A flowchart illustrating the data transmission method provided in an embodiment of the present invention; Figure 2 A schematic diagram of a data transmission device provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the electronic device structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the principle of the data transmission method provided in an embodiment of the present invention.

[0022] Figure label: 1-Decoding module; 2-Renaming module; 3-Instruction dispatch module; 4-Integer issue queue; 5-Integer register file; 6-Integer execution unit; 7-Floating-point issue queue; 8-Floating-point register file; 9-Floating-point execution unit; 10-Bypass network; 100 - Identification module, 200 - Temporary register allocation module, 300 - Dependency establishment module, 400 - Instruction splitting module, 500 - Launch control module, 600 - Bypass transmission module; 130 - Processor, 131 - Memory, 132 - Bus, 133 - Communication interface. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] To facilitate understanding of this embodiment, the technical terms used in this application will be briefly introduced below.

[0025] Cross-type register operation instructions refer to instructions that read data from a register of one type (such as an integer register), convert the data format, and write it to a register of another type (such as a floating-point register). Examples include integer-to-floating-point (i2f), floating-point-to-integer (f2i), integer-to-variable, and vector-to-floating-point instructions. These instructions account for a small percentage of actual workloads, typically less than 1%.

[0026] A temporary destination register is a temporary register allocated during the decoding stage for instructions that perform cross-type register operations. Its type is the same as the source register, and it is used to establish a data dependency between the first and second micro-operations. For example, for the i2f instruction (source register is integer x2, destination register is floating-point f5), the decoding stage adds an integer temporary destination register temp, making the destination register of the first micro-operation temp, and the source operand register of the second micro-operation also temp, thus establishing a data dependency.

[0027] A micro-operation (mop) is a basic execution unit after the processor has broken down instructions; it represents the smallest granularity for the actual scheduling and execution of execution units. In this application, cross-type instructions are broken down into two micro-operations: the first micro-operation is responsible for reading data from the execution unit corresponding to the source register type; the second micro-operation is responsible for performing data type conversion and write operations in the execution unit corresponding to the destination register type.

[0028] Data dependency refers to a situation where the execution of a second micro-operation must wait for the result of the first micro-operation; that is, the source operand of the second micro-operation depends on the destination register of the first micro-operation. This application establishes this dependency by assigning the same physical register identifier to both micro-operations through a renaming mechanism, ensuring that the two micro-operations are executed in the correct order.

[0029] Continuous transmission refers to the sequential transmission of two micro-operations within adjacent clock cycles, ensuring that the time interval between the first and second micro-operations does not exceed the effective transmission window of the bypass network (typically 1-2 clock cycles). This application achieves continuous transmission by setting the second micro-operation with the highest priority through a scheduler in the transmission queue.

[0030] A bypass network is a hardware pathway in a processor used to directly forward execution results between execution units. It typically consists of a multiplexer, a data bus, and control logic. This application reuses this network to achieve cross-type data transmission: the execution result of the first micro-operation is written to the bypass network and then broadcast to all execution units; the second micro-operation directly captures this result from the bypass network as its source operand.

[0031] The first type of execution unit refers to the execution unit corresponding to the source register type, such as the integer execution unit; the second type of execution unit refers to the execution unit corresponding to the destination register type, such as the floating-point execution unit. The two execution units are usually physically separated, located close to their respective register files.

[0032] A register file is a physical storage structure used to store the state of processor architecture registers. It includes integer register files, floating-point register files, vector register files, etc. Different types of register files are physically located close to their corresponding execution units for easy access.

[0033] After introducing the technical terms used in this application, the application scenarios and design concepts of the embodiments of this application will be briefly described below.

[0034] Modern high-performance processors contain multiple register files, including integer and floating-point registers, and have cross-type operation instructions (such as i2f). Existing technologies achieve data transmission by adding dedicated data paths or executing them separately, but this results in problems such as wasted hardware resources, high timing pressure, and poor scalability.

[0035] Based on this, embodiments of this application provide a data transmission method, apparatus, electronic device, and storage medium.

[0036] Example 1 This application provides a data transmission method, combined with Figure 1As shown, the method includes: S110 identifies cross-type register operation instructions.

[0037] S120, add a temporary destination register for the cross-type register operation instruction, and designate the temporary destination register as the destination register of the first micro-operation, and designate the original destination register of the cross-type register operation instruction as the destination register of the second micro-operation; wherein, the first micro-operation is a micro-operation used to perform source register read operation after splitting the cross-type register operation instruction, and the second micro-operation is a micro-operation used to perform data type conversion and destination register write operation after splitting the cross-type register operation instruction.

[0038] S130, through a renaming mechanism, assigns the same physical register identifier to the destination register of the first micro-operation and the source operand register of the second micro-operation, so as to establish the data dependency relationship between the second micro-operation and the first micro-operation.

[0039] S140 splits cross-type register operation instructions into a first micro-operation and a second micro-operation, with the split first micro-operation and second micro-operation inheriting data dependencies.

[0040] S150, in response to data dependencies, continuously sends the first micro-operation and the second micro-operation to the execution unit.

[0041] S160, the execution result of the first micro-operation is transmitted to the second micro-operation through the processor's bypass network as the source operand of the second micro-operation.

[0042] This invention adds a temporary destination register to cross-type instructions, establishes data dependencies during the renaming phase, and splits the instruction into two micro-operations. It utilizes the processor's existing bypass network to transmit the result of the first micro-operation to the second micro-operation as the source operand, eliminating the need for dedicated data paths, additional register read / write ports, or temporary buffers, thus avoiding wasted hardware resources and chip area overhead. The continuous issue mechanism ensures data transmission is completed within the effective window of the bypass network, making instruction execution latency comparable to ordinary instructions and maintaining high performance. Simultaneously, it eliminates timing issues caused by long-distance data transmission, helping the processor maintain a high clock frequency. Furthermore, adding cross-type operations only requires modification of the microcode control logic, without altering the register file hardware, significantly enhancing the scalability and flexibility of the processor design.

[0043] For ease of understanding, in the following description, the first type of execution unit refers to the execution unit corresponding to the source register type (e.g., ...). Figure 4 Integer execution unit 6), the second type of execution unit refers to the execution unit corresponding to the target register type (such as...). Figure 4(Floating-point execution unit 9 in the example). The order of the method steps described in the following embodiments is the logical order, which is intended to clearly demonstrate the technical concept of the present invention. In the processor hardware pipeline, the timing of some operations (such as renaming, register mapping) may be earlier than or parallel to other operations, but this does not affect the scope of protection of the present invention. Those skilled in the art should understand that as long as the present invention implements the addition of temporary destination registers for cross-type instructions, the establishment of data dependencies, and the use of bypass networks to transmit data, it should fall within the scope of protection of the present invention.

[0044] In step S110, cross-type register operation instructions refer to instructions that need to read data from a register of one type, convert it, and then write it to a register of another type, such as integer to floating point instructions (i2f), floating point to integer instructions (f2i), integer to variable instructions, vector to floating point instructions, etc.

[0045] Combination Figure 4 As shown, the decoding module 1 at the processor front end decodes the fetched instruction and identifies whether it is a cross-type register operation instruction by checking the instruction opcode. Decoding module 1 internally stores an opcode mapping table for cross-type instructions. When the instruction opcode matches an entry in the mapping table, it is identified as a cross-type instruction. Taking the i2f instruction as an example, assuming the source operand is an integer register x2 and the destination operand is a floating-point register f5, after decoding module 1 identifies the instruction as a cross-type instruction, it triggers the temporary destination register allocation mechanism.

[0046] In step S120, the decoding module 1 allocates a temporary destination register temp for the instruction. The type of the temporary destination register is the same as that of the source register (i.e., integer). After the temporary destination register allocation is completed, the register information of the instruction is as follows: the source operand register is x2 (integer), and the destination registers are temp (integer, temporary) and f5 (floating-point, original destination). The temporary destination register temp will serve as the destination register for the first micro-operation and simultaneously as the source operand register for the second micro-operation; the original destination register f5 will serve as the destination register for the second micro-operation.

[0047] In step S130, the renaming module 2 renames and maps the logical registers in the instruction. Specifically: it assigns a physical register identifier iptag15 to the source operand register x2; it assigns a physical register identifier iptag21 to the temporary destination register temp; and it assigns a physical register identifier fptag3 to the original destination register f5. Since the source operand register (temp) of the second micro-operation and the destination register (temp) of the first micro-operation are the same logical register, the renaming module 2 maps them to the same physical register identifier iptag21, thereby establishing a data dependency relationship between the second micro-operation and the first micro-operation at the hardware level.

[0048] In step S140, the instruction dispatch module 3 splits the cross-type instruction into two micro-operations: the first micro-operation is set to a "read-only" opcode, with the source operand being iptag15 and the destination register being iptag21, and is issued to the integer issue queue 4; the second micro-operation is set to a "conversion and write" opcode, with the source operand being iptag21 and the destination register being fptag3, and is issued to the floating-point issue queue 7. The two split micro-operations inherit the data dependencies established in the renaming phase.

[0049] In conjunction with the first aspect, step S120 adds a temporary destination register for cross-type register operation instructions, including: S121 allocates a temporary destination register for a cross-type register operation instruction. The type of the temporary destination register is the same as the type of the source register of the cross-type register operation instruction.

[0050] After decoding module 1 identifies a cross-type register operation instruction, it immediately allocates a temporary destination register `temp` for that instruction. The type of this temporary destination register is consistent with the type of the source register to ensure that no type mismatch issues occur during subsequent data transfer. For example, for the `i2f` instruction, if the source register is an integer register `x2`, then the allocated temporary destination register `temp` will also be an integer register; for the `f2i` instruction, if the source register is a floating-point register, then the temporary destination register `temp` will also be a floating-point register.

[0051] The temporary destination register `temp` logically serves as the output location for the first micro-operation and the input location for the second micro-operation, acting as a data bridge connecting the two micro-operations. By introducing the temporary destination register, the originally single cross-type instruction is split into two micro-operations that are related at the register level, laying the foundation for establishing data dependencies later.

[0052] S122, the source operand register of the cross-type register operation instruction is used as the source operand register of the first micro-operation, and the temporary destination register is used as the destination register of the first micro-operation.

[0053] The first micro-operation is responsible for reading the raw data from the register file corresponding to the source register type. Therefore, setting the source operand register of the cross-type instruction (such as x2) as the source operand register of the first micro-operation indicates that the first micro-operation needs to read data from this register; setting the temporary destination register temp as the destination register of the first micro-operation indicates that the data read by the first micro-operation will be written to temp.

[0054] Taking the i2f instruction as an example, the configuration of the first micro-operation is: source operand register = x2, destination register = temp. This means that the first micro-operation reads data from the integer register x2 and writes the read result to the temporary destination register temp.

[0055] S123, use the temporary destination register as the source operand register of the second micro-operation, and use the original destination register of the cross-type register operation instruction as the destination register of the second micro-operation.

[0056] The second micro-operation is responsible for performing data type conversion and writing the result to the destination register. Therefore, setting the temporary destination register temp as the source operand register of the second micro-operation indicates that the second micro-operation needs to read data from temp as input for the conversion; setting the original destination register of the cross-type instruction (such as f5) as the destination register of the second micro-operation indicates that the conversion result is ultimately written to this register.

[0057] Taking the i2f instruction as an example, the configuration of the second micro-operation is: source operand register = temp, destination register = f5. This means that the second micro-operation reads integer data from the temporary destination register temp, performs an integer-to-floating conversion, and writes the conversion result to the floating-point register f5.

[0058] Through steps S121 to S123, the following key configurations were completed during the decoding stage: The source operand register of the first micro-operation = the source operand register of the instruction (e.g., x2); The destination register for the first micro-operation is the temporary destination register (temp). The source operand register of the second micro-operation = the temporary destination register (temp). The destination register for the second micro-operation is the original destination register of the instruction (e.g., f5).

[0059] Since the destination register of the first micro-operation and the source operand register of the second micro-operation are both temp, a data flow relationship between the two micro-operations is established at the logical level: the source operand required by the second micro-operation comes from the execution result of the first micro-operation.

[0060] In conjunction with the first aspect, step S130 includes: S131, assign the first physical register identifier to the destination register of the first micro-operation.

[0061] During the renaming phase, the renaming module 2 performs physical register mapping on the logical registers in the instruction. The destination register of the first micro-operation is a temporary destination register temp (as configured in S120), and the renaming module 2 allocates an available physical register identifier (PTAG) for this temporary destination register, denoted as the first physical register identifier.

[0062] Taking the i2f instruction as an example, assuming the temporary destination register is temp, the renaming module 2 assigns it a physical register identifier iptag21. Simultaneously, the source operand register of the first micro-operation (e.g., x2) is also assigned a physical register identifier, such as iptag15. These two allocation operations are completed in parallel during the renaming phase, mapping the logical registers to their specific storage locations in the physical register file.

[0063] S132, when renaming the source operand register of the second micro-operation, the source operand register of the second micro-operation is mapped to the first physical register identifier so that the first micro-operation and the second micro-operation share the same physical register identifier.

[0064] During the renaming phase, renaming module 2 continues to process the source operand register of the second micro-operation. According to the configuration in S120, the source operand register of the second micro-operation is the temporary destination register temp. Renaming module 2 queries the register mapping table and finds that temp has been assigned the physical register identifier iptag21 (i.e., the first physical register identifier assigned in S131).

[0065] Therefore, renaming module 2 does not allocate a new physical register for temp, but instead directly maps the source operand register of the second micro-operation to the existing iptag21. At the same time, the destination register of the second micro-operation (the original destination register, such as f5) is assigned a new physical register identifier, such as fptag3.

[0066] Through the coordinated operation of steps S131 and S132, the destination register (temp) of the first micro-operation and the source operand register (temp) of the second micro-operation share the same physical register identifier iptag21. This means: After the first micro-operation is completed, its result will be written to the physical register iptag21; When the second micro-operation is executed, its source operand will be read from the physical register iptag21.

[0067] This establishes a real data dependency at the hardware level: the second micro-operation can only be executed after the first micro-operation is completed and written to iptag21. This dependency will be recognized by the scheduler in the launch queue to control the launch order and ensure data correctness.

[0068] In conjunction with the first aspect, step S150 includes: S151, the first micro-operation is issued to the first type execution unit corresponding to the source register type, and the second micro-operation is issued to the second type execution unit corresponding to the target register type.

[0069] According to the S120 configuration, the first micro-operation is assigned to integer launch queue 4, and the second micro-operation is assigned to floating-point launch queue 7. The scheduler in integer launch queue 4 is responsible for the launch control of the first micro-operation, and the scheduler in floating-point launch queue 7 is responsible for the launch control of the second micro-operation. The two launch queues operate independently, coordinating launch timing through a dependency tracking mechanism.

[0070] S152, the scheduler in the transmission queue sets the priority for the second micro-operation, so that the second micro-operation is transmitted within one or more clock cycles after the first micro-operation is transmitted, and the transmission interval between the first micro-operation and the second micro-operation does not exceed the effective transmission window of the bypass network.

[0071] Schedulers are installed in integer launch queue 4 and floating-point launch queue 7 respectively to continuously monitor the data dependency status of each micro-operation. Since a data dependency relationship has been established in S130 (the source operand of the second micro-operation depends on the execution result of the first micro-operation), the scheduler can identify this dependency relationship.

[0072] After the first micro-operation is launched from integer launch queue 4, the scheduler in floating-point launch queue 7 detects that among all the dependencies of the second micro-operation, only the result of the first micro-operation is awaited, and all other resources are ready. Therefore, it raises the launch priority of the second micro-operation to the highest level, ensuring it is selected for launch in the next clock cycle. Normally, the first micro-operation is launched in clock cycle T, and the second micro-operation is launched in clock cycle T+1, achieving continuous launch in adjacent clock cycles.

[0073] If the first micro-operation is delayed due to resource conflicts (such as busy execution units, missing data cache, etc.), the scheduler will correspondingly delay the launch of the second micro-operation to ensure that the two micro-operations always maintain a sequential launch relationship. The scheduler uses a priority mechanism and dependency tracking to control the launch interval of the two micro-operations within the effective transmission window of the bypass network 10 (usually 1-2 clock cycles).

[0074] If an abnormal situation (such as a branch prediction error or an abnormal interruption) causes the launch interval to exceed the effective window, the scheduler will trigger a data retention mechanism to temporarily store the result of the first micro-operation in the bypass network buffer, or notify the second micro-operation to read from the register file again. However, such situations are rarely triggered under normal execution paths.

[0075] Taking the i2f instruction as an example, assume that the effective transmission window of the bypass network is 2 clock cycles: Normal situation: During clock cycle T, the first micro-operation is issued and executed in the integer execution unit 6, and the execution result is written to the bypass network 10; During clock cycle T+1, the scheduler of the floating point issuance queue 7 detects that the result of the first micro-operation is ready and issues the second micro-operation to the floating point execution unit 9. The second micro-operation captures data from the bypass network 10. The time interval is 1 clock cycle, which is much smaller than the effective window.

[0076] Resource conflict situation: If the first micro-operation is delayed by 1 clock cycle due to the busy integer execution unit 6, the first micro-operation is not launched in clock cycle T, and the scheduler does not schedule the second micro-operation for the time being; the first micro-operation is launched and executed in clock cycle T+1; the second micro-operation is launched in clock cycle T+2. At this time, the result of the first micro-operation is still within the effective window of the bypass network and the data can still be obtained correctly.

[0077] Through steps S151 and S152, the priority control mechanism of the schedulers in integer launch queue 4 and floating-point launch queue 7 enables the continuous launch of two micro-operations, ensuring that the launch interval does not exceed the effective transmission window of bypass network 10. This mechanism allows cross-type data transmission to be completed within the validity period of the bypass network, avoiding the need for additional dedicated hardware, maintaining high-performance execution, and enhancing the system's adaptability to resource conflicts.

[0078] In conjunction with the first aspect, step S160 includes: S161, drive the execution result of the first micro-operation after execution in the first type of execution unit to the data bus of the bypass network.

[0079] The first micro-operation is issued to the first type of execution unit (such as...). Figure 4 After the integer execution unit 6 in the micro-operation, the execution unit retrieves the corresponding register from the register file (e.g., ...) based on the source register address in the micro-operation. Figure 4 5) Read data from the integer register file. After reading, the execution unit does not write the result back to the register file, but directly drives the data to the data bus of the bypass network 10 through its output port.

[0080] Taking the i2f instruction as an example, after the integer execution unit 6 reads the integer data from the integer register file 5, the execution unit directly outputs the data to the data bus of the bypass network 10. The control logic of the integer execution unit 6 skips all calculation steps according to the "read-only" opcode, and the micro-operation is completed within a single clock cycle. When the control logic of the bypass network 10 detects the completion of the first micro-operation, it latches the result data into a temporary buffer and sets the corresponding physical register identifier (such as iptag21) data ready flag.

[0081] By directly driving the result to the bypass network via S161, the extra delay of writing back to the register file and then reading it is avoided. This facilitates the rapid acquisition of data in the second micro-operation, while reducing the number of register file read and write operations and lowering power consumption.

[0082] S162, the bypass network broadcasts the execution result to the second type of execution unit.

[0083] The bypass network 10 is a hardware pathway in the processor used to directly forward execution results between execution units, and typically consists of a multiplexer, a data bus, and control logic. Upon receiving the execution result of the first micro-operation, the bypass network 10 routes the result data simultaneously to the bypass input ports of all execution units through its internal data distribution logic.

[0084] During the broadcast process, the control logic of the bypass network 10 sets the corresponding data tag based on the physical register identifier (e.g., iptag21) corresponding to the result data, so that each execution unit can identify whether the required data is ready. Second type of execution unit (e.g., Figure 4 The bypass input port of the floating-point execution unit 9 in the middle continuously listens for data broadcasts, and when it detects the arrival of data identified by the required physical register, it is ready to capture the data.

[0085] Based on the example above, the bypass network 10 broadcasts integer data to all execution units, including the floating-point execution unit 9, while simultaneously transmitting the corresponding physical register identifier iptag21. The bypass input port of the floating-point execution unit 9 continuously monitors to identify whether the data corresponding to iptag21 has arrived. The broadcast mechanism of S162 enables the bypass network to provide data to all execution units simultaneously, eliminating the need to establish dedicated paths for cross-type data transmission, fully utilizing existing hardware resources, and achieving efficient data distribution.

[0086] S163, the second micro-operation captures the execution result from the bypass network as the source operand when the second type of execution unit is issued.

[0087] The bypass network 10 is a hardware pathway in the processor used to directly forward execution results between execution units, and typically consists of a multiplexer, a data bus, and control logic. Upon receiving the execution result of the first micro-operation, the bypass network 10 routes the result data simultaneously to the bypass input ports of all execution units through its internal data distribution logic.

[0088] During the broadcast process, the control logic of the bypass network 10 sets the corresponding data tag based on the physical register identifier (e.g., iptag21) corresponding to the result data, so that each execution unit can identify whether the required data is ready. Second type of execution unit (e.g., Figure 4The bypass input port of the floating-point execution unit 9 in the middle continuously listens for data broadcasts, and when it detects the arrival of data identified by the required physical register, it is ready to capture the data.

[0089] Based on the example above, the bypass network 10 broadcasts integer data to all execution units, including the floating-point execution unit 9, while simultaneously transmitting the corresponding physical register identifier iptag21. The bypass input port of the floating-point execution unit 9 continuously monitors to identify whether the data corresponding to iptag21 has arrived. The broadcast mechanism of S162 enables the bypass network to provide data to all execution units simultaneously, eliminating the need to establish dedicated paths for cross-type data transmission, fully utilizing existing hardware resources, and achieving efficient data distribution.

[0090] Through steps S161 to S163, the processor's existing bypass network 10 is reused to achieve data transfer between register types without the need for additional read / write ports, dedicated data paths, or temporary buffers for register files, thus avoiding waste of hardware resources and chip area overhead. At the same time, the physical path of the bypass network 10 is typically short and optimized, eliminating timing issues caused by long-distance data transfer and helping the processor maintain a high clock frequency.

[0091] In conjunction with the first aspect, the first micro-operation only performs a register read operation in the first execution unit corresponding to the source register type.

[0092] The first micro-operation is the first micro-operation generated after splitting the cross-type register operation instruction. It is responsible for reading the original data from the register file corresponding to the source register type. The execution unit matching the source register type is the first execution unit, such as integer execution unit 6 corresponding to an integer register. This execution unit has the ability to access the register file of the corresponding type (e.g., ...). Figure 4 The dedicated read / write port for the integer register file (5).

[0093] During the instruction dispatch phase, instruction dispatch module 3 generates a first micro-operation and sets a "read-only" opcode for it. This opcode instructs the first type of execution unit to activate only the register read path and not the computation path when executing the micro-operation.

[0094] The specific execution process is as follows: The first micro-operation is issued to the first type of execution unit (such as...). Figure 4 Medium integer execution unit 6); The first type of execution unit, based on the source register address in the micro-operation, retrieves the corresponding first register file (e.g., ...). Figure 4 5) Read data from the integer register file; After reading, the execution unit outputs the data directly to the bypass network 10 without passing through the arithmetic logic unit (ALU) or floating-point unit (FPU) inside the execution unit. The control logic of the first type of execution unit skips all computation steps based on the "read-only" opcode, and the micro-operation is completed within a single clock cycle.

[0095] Taking the i2f instruction as an example, the specific execution process of the first micro-operation is as follows: Integer execution unit 6 receives the first micro-operation, whose source operand is specified as integer register R1; Integer execution unit 6 reads the integer data (e.g., the value 0x0000FFFF) stored in R1 through the read port of integer register file 5. After the reading is complete, the integer data is directly output to the bypass network 10, and the ALU inside the integer execution unit 6 does not participate in any calculation; The entire process takes only one clock cycle, and the execution unit can receive new micro-operations in the next clock cycle.

[0096] In traditional solutions, cross-type operations often involve data transfer after computation is completed in the source execution unit, or require additional temporary storage logic. This solution separates reading from computation, making the first micro-operation a lightweight data transfer operation responsible only for retrieving data from the register file and sending it out via a bypass network. Since the first micro-operation does not perform computation, its output is the raw data read directly from the register file. This data is directly transmitted to the second micro-operation via the bypass network 10 without any intermediate processing. This achieves cross-type data transfer while minimizing the computational resource consumption of the execution unit, thus reusing existing resources and avoiding hardware redundancy.

[0097] In conjunction with the first aspect, after step S160, the following also includes: S170, perform data type conversion calculation and obtain the conversion calculation result.

[0098] S180 writes the conversion calculation result to the register file corresponding to the target register type.

[0099] In step S170, when the second micro-operation is emitted by the second type of execution unit, the execution unit captures the execution result of the first micro-operation from the bypass network 10 as the source operand. Subsequently, the execution unit activates the corresponding data type conversion circuit according to the opcode type of the second micro-operation to perform conversion calculations on the source operand.

[0100] The specific execution process is as follows: When the second micro-operation is launched, the execution result data of the first micro-operation is captured from the bypass network 10 through the bypass input port; The opcode of the second micro-operation carries conversion type information (such as i2f, f2i, v2f, etc.), and the execution unit selects the corresponding conversion path according to this information; The conversion circuit inside the execution unit performs data format conversion on the source operands: i2f: Converts the binary representation of integer data into the IEEE 754 standard floating-point format; f2i: Converts floating-point numbers to integer data, including rounding mode processing; v2f: Extracts elements from a vector register and converts them to floating-point numbers; After the conversion is completed, the calculation result is temporarily stored in the output register inside the execution unit, waiting to be written to the register file.

[0101] Taking the i2f instruction as an example, the specific execution process of the second micro-operation is as follows: Floating-point execution unit 9 captures integer data 0x0000FFFF (decimal 65535) from bypass network 10. The execution unit recognizes the opcode as i2f and activates the integer-to-float conversion circuit. The conversion circuit converts the integer 65535 to the IEEE 754 single-precision floating-point representation 0x477FFF00 (i.e., 65535.0). The conversion result is temporarily stored in the output register of floating-point execution unit 9.

[0102] After the data type conversion is completed in step S170, the execution unit writes the conversion result to the register file of the target register type through the write port. The specific execution flow is as follows: Write address determination: The destination register address of the second micro-operation has been mapped to the physical register identifier (PTAG) during the renaming phase, which specifies the specific write location in the target register file; Result writing: The execution unit writes the conversion calculation result to the physical register entry corresponding to the target register file through its write port; Readiness status update: After the write is completed, the rename table updates the readiness status of the physical register so that other instructions that depend on the result can obtain the data; Commit complete: When the second micro-operation is committed, the physical register is mapped to the architecture register, and the conversion result officially becomes part of the processor architecture state.

[0103] In this embodiment, taking the i2f instruction as an example, the writing process of the second micro-operation is as follows: The floating-point execution unit 9 writes the conversion result 65535.0 (floating-point representation 0x477FFF00) to the floating-point register file 8 through the write port; Write to the physical register PTAG_456 corresponding to the second micro-operation destination register F1; After the write is complete, rename the table marker PTAG_456 to indicate that the data is ready; When an instruction is submitted, PTAG_456 is mapped to the architecture floating-point register F1, and the conversion result is visible to subsequent instructions.

[0104] Through the complete process of steps S110 to S180, this invention achieves cross-register type data transfer without the need for dedicated hardware. S170 is performed by the execution unit corresponding to the target type (e.g., ...). Figure 4 The floating-point execution unit (9) in the processor performs the conversion calculation, enabling the conversion operation to utilize specialized circuitry to ensure conversion efficiency and accuracy. S180 writes the result to the target register file, completing persistent data storage and supporting correct access to subsequent instructions. The entire process fully utilizes the processor's existing bypass network (10), floating-point execution unit (9), and floating-point register file (8) resources, avoiding the need for additional dedicated data paths, extra read / write ports, or temporary buffers to process a small number of cross-type instructions. This achieves optimized utilization of hardware resources while maintaining high performance.

[0105] In conjunction with the first aspect, cross-type register operation instructions include at least one of the following: integer to floating-point instructions, floating-point to integer instructions, integer to variable instructions, or vector to floating-point instructions.

[0106] Cross-type register manipulation instructions are those that read data from a register of one type, convert the data format, and then write it to a register of another type. These instructions are used in processor instruction set architectures to support conversion operations between different data types and are an indispensable category of instructions in high-performance processors.

[0107] The Integer-to-Floating-Point (i2f) instruction converts integer data in an integer register to a floating-point number and writes it to a floating-point register. It is used in scientific computing, graphics processing, physics engines, and other scenarios that require converting integer coordinates or count values ​​to floating-point numbers for precise calculations. For example, if the integer register R1 stores the integer value 65535, executing the i2f instruction will return the corresponding single-precision floating-point number 65535.0 in the floating-point register F1.

[0108] The floating-point to integer conversion instruction (f2i) converts floating-point data in a floating-point register to an integer format and writes it to an integer register. It is typically used in scenarios requiring the conversion of floating-point results to integers, such as data index calculations, loop counter updates, and fixed-point number processing. For example, if floating-point register F1 stores the floating-point number 3.14159, executing the f2i instruction will return the integer 3 in integer register R1 (this may vary depending on the rounding mode).

[0109] The integer to vector instruction expands or copies data from an integer register to multiple elements of a vector register. It is used in SIMD parallel computing scenarios where a scalar value needs to be broadcast to all channels of a vector, such as setting a uniform color value in image processing or setting a constant vector in matrix calculations. For example, if the integer register R1 stores the integer value 255, after executing the integer to vector instruction, each element of the vector register V1 (e.g., 16 8-bit integers) will receive 255.

[0110] The vector-to-floating-point instruction extracts data from a specified element of a vector register, converts it to a floating-point number, and writes it to a floating-point register. This is used for extracting vector calculation results and performing further floating-point operations, such as extracting the intensity value of a pixel in image processing for subsequent calculations, or extracting vector components in scientific computing. For example, vector register V1 stores four single-precision floating-point numbers (1.0, 2.0, 3.0, 4.0). After executing the vector-to-floating-point instruction and selecting the third element, floating-point register F1 returns 3.0.

[0111] The diversity of instructions for cross-type register operations is the foundation for the widespread application value of the technical solution in this application. The method in this application does not rely on specific instruction types, but rather establishes a general processing framework capable of covering any combination of register types, including integer, floating-point, and vector registers. This characteristic enables the solution to adapt to the continuous evolution of instruction set architectures, providing a scalable solution for future novel cross-type operations.

[0112] like Figure 4 As shown, the data transmission method provided in this embodiment of the invention involves the following core modules: decoding module 1, renaming module 2, instruction dispatch module 3, integer issue queue 4, integer register file 5, integer execution unit 6, floating-point issue queue 7, floating-point register file 8, floating-point execution unit 9, and bypass network 10. These modules work together to achieve efficient transmission of data across register types.

[0113] During the decoding stage: Instruction identification and temporary destination register allocation. Decoding module 1 retrieves the instruction from the instruction cache and decodes it. By identifying the instruction opcode, it determines whether the current instruction is a cross-type register operation instruction (such as the integer-to-floating-point instruction i2f). When a cross-type instruction is identified, decoding module 1 allocates a temporary destination register temp for the instruction, whose type is the same as the source register type (such as integer). Taking the i2f instruction as an example, assuming the source operand is an integer register x2 and the destination operand is a floating-point register f5, decoding module 1 adds an integer temporary destination register temp for this instruction.

[0114] During the renaming phase: Physical register identifiers and data dependencies are established. After the temporary destination register allocation is completed, the instruction enters renaming module 2. Renaming module 2 renames and maps the logical registers in the instruction: it assigns physical register identifier iptag15 to the source operand register x2; it assigns physical register identifier iptag21 to the temporary destination register temp; and it assigns physical register identifier fptag3 to the original destination register f5. Since the source operand register (temp) of the second micro-operation and the destination register (temp) of the first micro-operation are the same logical register, renaming module 2 maps them to the same physical register identifier iptag21, thereby establishing a data dependency at the hardware level.

[0115] During the dispatch phase: Instructions are split and dependencies are inherited. After renaming, the instruction enters instruction dispatch module 3. Instruction dispatch module 3 splits the cross-type instruction into two micro-operations: The first micro-operation is set to "read-only" semantics, with the source operand being iptag15 and the destination register being iptag21. It is responsible for reading the raw data from the register file corresponding to the source register type and dispatching it to integer issue queue 4. The second micro-operation is set to "conversion and write" semantics, with the source operand being iptag21 and the destination register being fptag3. It is responsible for performing data type conversion and writing the result to the register file of the destination register type, and dispatching it to floating-point issue queue 7. The two split micro-operations inherit the data dependencies established during the renaming phase.

[0116] During the launch phase: continuous launch control. Schedulers are installed in integer launch queue 4 and floating-point launch queue 7 respectively to monitor the data dependency status of micro-operations and control the launch timing. Since the renaming module 2 has established data dependencies, the scheduler recognizes that the second micro-operation depends on the execution result of the first micro-operation. Therefore, it sets the highest priority for the second micro-operation, ensuring that it is launched continuously within one or more clock cycles after the launch of the first micro-operation, and the launch interval does not exceed the effective transmission window of the bypass network 10 (usually 1-2 clock cycles). Under normal circumstances, the first micro-operation is launched in clock cycle T, and the second micro-operation is launched in clock cycle T+1, achieving continuous launch of adjacent clock cycles.

[0117] During execution and bypass transmission, data reading and forwarding are performed. After receiving the first micro-operation, the integer execution unit 6 activates only the register read path according to its "read-only" opcode: it reads the data of the specified register (such as the data corresponding to iptag15) from the integer register file 5, and then directly drives the read result to the data bus of the bypass network 10 without any calculation by the arithmetic logic unit (ALU). This operation is completed within a single clock cycle.

[0118] Bypass network 10 is a hardware pathway in the processor used to directly forward execution results between execution units. Upon receiving data driven by integer execution unit 6, bypass network 10 simultaneously broadcasts the data and its corresponding physical register identifier iptag21 to the bypass input ports of all execution units, including floating-point execution unit 9.

[0119] During the conversion and writing process, data type conversion and result storage are performed. After receiving the second micro-operation, the floating-point execution unit 9 captures data matching the physical register identifier iptag21 from the data bus of the bypass network 10 through its bypass input port as the source operand. Since the data is already ready in the bypass network, the floating-point execution unit 9 can obtain the source operand without accessing the floating-point register file 8. Subsequently, the floating-point execution unit 9 activates the corresponding data type conversion circuit according to the opcode (such as i2f) of the second micro-operation, performs data format conversion (such as converting integer data to IEEE 754 single-precision floating-point numbers), and writes the conversion result to the corresponding physical register entry fptag3 in the floating-point register file 8 through the write port, completing the cross-type data transmission.

[0120] Furthermore, during the second micro-operation submission, the physical register fptag3 is mapped to the architecture floating-point register f5, and the conversion result officially becomes part of the processor architecture state, visible to subsequent instructions.

[0121] Through the coordinated operation of the aforementioned modules, this invention utilizes the processor's existing bypass network 10 to achieve cross-register type data transmission. In the entire process, the decoding module 1 is responsible for allocating temporary destination registers, the renaming module 2 is responsible for establishing data dependencies, the instruction dispatch module 3 is responsible for splitting and distributing micro-operations, the issue queue is responsible for continuous issue control, the execution unit is responsible for data reading, conversion, and writing, and the bypass network is responsible for data forwarding. This solution eliminates the need for additional read / write ports or dedicated data paths for cross-type instructions, maintaining high-performance processor execution while avoiding waste of hardware resources.

[0122] Secondly, embodiments of this application provide a data transmission apparatus for performing the method described above; in conjunction with Figure 2 As shown, the device includes: an identification module 100, a temporary register allocation module 200, a dependency establishment module 300, an instruction splitting module 400, a launch control module 500, and a bypass transmission module 600.

[0123] The identification module 100 is used to identify cross-type register operation instructions.

[0124] The temporary register allocation module 200 is used to add a temporary destination register for cross-type register operation instructions and designate the temporary destination register as the destination register of the first micro-operation, and designate the original destination register of the cross-type register operation instructions as the destination register of the second micro-operation; wherein, the first micro-operation is a micro-operation used to perform source register read operation after splitting the cross-type register operation instructions, and the second micro-operation is a micro-operation used to perform data type conversion and target register write operation after splitting the cross-type register operation instructions.

[0125] The dependency establishment module 300 is used to establish a data dependency relationship between the second micro-operation and the first micro-operation by assigning the same physical register identifier to the destination register of the first micro-operation and the source operand register of the second micro-operation through a renaming mechanism.

[0126] The instruction splitting module 400 is used to split cross-type register operation instructions into a first micro-operation and a second micro-operation, and the split first micro-operation and second micro-operation inherit the data dependency relationship.

[0127] The launch control module 500 is used to launch the first micro-operation and the second micro-operation to the execution unit in response to data dependencies.

[0128] The bypass transmission module 600 is used to transmit the execution result of the first micro-operation to the second micro-operation through the processor's bypass network, as the source operand of the second micro-operation.

[0129] Thirdly, embodiments of this application provide an electronic device, combined with Figure 3 As shown, the electronic device includes a memory 131 and a processor 130. The memory 131 stores a computer program, and the processor 130 runs the computer program to make the electronic device perform the above-described method.

[0130] Furthermore, combined Figure 3 The electronic device shown also includes a bus 132 and a communication interface 133, with the processor 130, the communication interface 133 and the memory 131 connected via the bus 132.

[0131] The memory 131 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 133 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 132 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 3 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0132] Processor 130 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 130 or by instructions in software form. Processor 130 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 131, and processor 130 reads the information in memory 131 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0133] Fourthly, embodiments of this application provide a readable storage medium storing computer program instructions, which are read and executed by a processor to perform the above-described method.

[0134] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0135] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0136] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0137] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0138] Finally, it should be noted that the above embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A data transmission method, characterized in that, The method includes: Identify cross-type register operation instructions; A temporary destination register is added to the cross-type register operation instruction, and the temporary destination register is designated as the destination register of the first micro-operation. The original destination register of the cross-type register operation instruction is designated as the destination register of the second micro-operation. The first micro-operation is a micro-operation used to perform a source register read operation after splitting the cross-type register operation instruction, and the second micro-operation is a micro-operation used to perform a data type conversion and a target register write operation after splitting the cross-type register operation instruction. By using a renaming mechanism, the same physical register identifier is assigned to the destination register of the first micro-operation and the source operand register of the second micro-operation, so as to establish the data dependency relationship between the second micro-operation and the first micro-operation. The cross-type register operation instruction is split into a first micro-operation and a second micro-operation, and the split first micro-operation and second micro-operation inherit the data dependency relationship; In response to the data dependency, the first micro-operation and the second micro-operation are successively sent to the execution unit; The execution result of the first micro-operation is transmitted to the second micro-operation through the processor's bypass network, serving as the source operand of the second micro-operation.

2. The method according to claim 1, characterized in that, Adding a temporary destination register to the cross-type register operation instruction includes: Allocate a temporary destination register for the cross-type register operation instruction, wherein the type of the temporary destination register is the same as the type of the source register of the cross-type register operation instruction; The source operand register of the cross-type register operation instruction is used as the source operand register of the first micro-operation, and the temporary destination register is used as the destination register of the first micro-operation. The temporary destination register is used as the source operand register of the second micro-operation, and the original destination register of the cross-type register operation instruction is used as the destination register of the second micro-operation.

3. The method according to claim 1, characterized in that, The step of assigning the same physical register identifier to the destination register of the first micro-operation and the source operand register of the second micro-operation to establish the data dependency of the second micro-operation on the first micro-operation includes: Assign a first physical register identifier to the destination register of the first micro-operation; When renaming the source operand register of the second micro-operation, the source operand register of the second micro-operation is mapped to the first physical register identifier so that the first micro-operation and the second micro-operation share the same physical register identifier.

4. The method according to claim 1, characterized in that, The step of sequentially sending the first micro-operation and the second micro-operation to the execution unit in response to the data dependency includes: The first micro-operation is sent to the first type of execution unit corresponding to the source register type, and the second micro-operation is sent to the second type of execution unit corresponding to the target register type; The scheduler in the launch queue sets the priority for the second micro-operation, so that the second micro-operation is launched within one or more clock cycles after the launch of the first micro-operation, and the launch interval between the first micro-operation and the second micro-operation does not exceed the effective transmission window of the bypass network.

5. The method according to claim 4, characterized in that, The step of transmitting the execution result of the first micro-operation to the second micro-operation via the processor's bypass network as the source operand of the second micro-operation includes: The execution result of the first micro-operation after it is executed in the first type of execution unit is driven to the data bus of the bypass network; The bypass network broadcasts the execution result to the second type of execution unit; When the second micro-operation is issued by the second type of execution unit, the execution result is captured from the bypass network as the source operand.

6. The method according to claim 1, characterized in that, The first micro-operation performs only a register read operation in the first execution unit corresponding to the source register type.

7. The method according to claim 1, characterized in that, After the second micro-operation captures the execution result as the source operand from the bypass network, it further includes: Perform data type conversion calculations and obtain the conversion results; The conversion calculation result is written into the register file corresponding to the target register type.

8. A data transmission device, characterized in that, The apparatus is used to perform the method as described in any one of claims 1-7; the apparatus comprises: The identification module is used to identify cross-type register operation instructions; A temporary register allocation module is used to add a temporary destination register for the cross-type register operation instruction, and designate the temporary destination register as the destination register of the first micro-operation, and designate the original destination register of the cross-type register operation instruction as the destination register of the second micro-operation; wherein, the first micro-operation is a micro-operation for performing a source register read operation after splitting the cross-type register operation instruction, and the second micro-operation is a micro-operation for performing a data type conversion and a target register write operation after splitting the cross-type register operation instruction; The dependency establishment module is used to assign the same physical register identifier to the destination register of the first micro-operation and the source operand register of the second micro-operation through a renaming mechanism, so as to establish the data dependency relationship between the second micro-operation and the first micro-operation. The instruction splitting module is used to split the cross-type register operation instruction into a first micro-operation and a second micro-operation, wherein the split first micro-operation and the second micro-operation inherit the data dependency relationship; A launch control module is used to continuously launch the first micro-operation and the second micro-operation to the execution unit in response to the data dependency relationship; The bypass transmission module is used to transmit the execution result of the first micro-operation to the second micro-operation through the processor's bypass network, as the source operand of the second micro-operation.

9. An electronic device, characterized in that, include: A processor and a memory, the memory being used to store computer program instructions; the processor, when executing the computer program instructions, implements the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 7.

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