A multi-layer logic circuit CPU architecture and single-time sequence closed-loop global calculation method

Abstract

This invention discloses a multi-layer logic circuit CPU architecture and a single-time timing closed-loop global computation method, belonging to the field of processor architecture and digital circuit technology. The architecture includes a global clock, multi-layer logic circuits, independent microcores, aggregated large-core scheduling, path pre-deployment, and a hierarchical reset module. This invention relies on multi-layer circuits to adapt to instruction operation levels, adopts a multi-core collaborative mode of microcore control and large-core coordination, switches timing operation modes, and combines path pre-deployment and timing linkage to achieve single-time closed-loop computation. The solution addresses the problems of redundant execution processes, poor hierarchical adaptation, fixed multi-core modes, and weak operational stability in existing processors, and is applicable to general-purpose processors, embedded chips, and parallel computing hardware design scenarios.

Description

Technical Field

[0001] This invention relates to the fields of processor hardware architecture, digital logic circuit design, multi-core scheduling and data processing technology, specifically to a processor architecture and processing method with multi-layer logic circuit structure, dynamic timing control and multi-core collaborative scheduling. Background Technology

[0002] Currently, conventional processors generally adopt a segmented execution mode, where data reading, computation, and result storage are carried out in separate steps, resulting in waiting intervals and resource scheduling losses during the operation. Conventional processors employ a single-layer planar structure for computation. When faced with multi-layered nested and multi-associative complex operations, they cannot directly match the computational level with hardware. Instead, they need to use software to break down the computational steps and process them iteratively layer by layer, resulting in a cumbersome execution process. Existing multi-core processors have fixed timing operation modes, and can only choose to run synchronously across the entire domain or to run asynchronously independently on each core. The two modes cannot be flexibly switched, making it difficult to adapt to both fragmented multi-task processing and large-scale collaborative computing scenarios. During equipment operation, most adopt a unified reset method after the task is completed. Long-term continuous operation can easily lead to the retention of circuit state and the accumulation of register data, which affects the stability of operation. Regular computing tasks are broken down and completed gradually over multiple clock cycles, resulting in a large number of execution links and a fragmented process. In summary, existing processors have limitations in terms of timing scheduling flexibility, hardware computing matching capabilities, and multi-core collaborative adaptation. Summary of the Invention

[0003] Purpose of the invention This invention aims to overcome the shortcomings of existing processors, such as step-by-step execution, single computational level, fixed multi-core operating mode, unreasonable state reset method, and dispersed task execution process. It provides a multi-layer logic circuit CPU architecture and a single-time time-closed-loop global calculation method, optimizes hardware structure and timing scheduling logic, simplifies the computation execution process, and improves device adaptability and stability. Technical solution 1. Overall Architecture A multi-layer logic circuit CPU architecture includes a global reference clock module, a multi-layer progressive logic circuit module, several independent micro-core arithmetic units, an aggregated large core scheduling module, a path pre-deployment module, and a hierarchical state reset module. The global reference clock module is used to provide a unified time reference across the entire domain and to uniformly manage the timing adjustment, phase matching, and task scheduling boundaries of each computing unit. The multi-layer progressive logic circuit module is configured with multiple layers of hardware logic circuits. The circuit level corresponds to the instruction nesting operation level, which is used to match the hardware level with the compound nested operation logic to realize layered parallel operation processing. The independent microcore computing unit is the smallest independent computing unit. Each microcore is configured with an independent computing path and logical resources, and manages a single computing process independently. Several independent microcores can be combined into a unified logical big core through the aggregation big core scheduling module, which can coordinate the nested relationships of operations and the order of execution to complete the overall task logic arrangement. The path pre-deployment module is used to pre-match and lock the hardware computing circuit and data transmission path corresponding to this task during the instruction parsing stage. The hierarchical state reset module is used to distinguish between whole-machine initialization reset and task-specific reset, thereby achieving hierarchical state cleanup and control. 2. Hierarchical dynamic timing control mechanism This architecture employs a global reference clock anchoring and hierarchical dynamic adaptation timing control method: In typical multitasking scenarios, each independent microcore adaptively adjusts its own computation timing within the constraints of the global reference clock, and each microcore independently adapts to the running rhythm of the corresponding computation task, working asynchronously and independently. In large-scale parallel collaborative computing scenarios, phase locking instructions can be issued through a global reference clock to uniformly lock the running phase of all micro-cores within the aggregated big core, enabling all computing units within the aggregated big core to synchronize timing and execution. The timing mode switching process is uniformly controlled by the global reference clock. Before the switch, the current task data snapshot and path status lock are completed to ensure data integrity and continuous operation during the timing switching process. 3. Single-time closed-loop global computation mechanism This invention adopts a single-time closed-loop operation method. The single-time closed-loop is not limited to a fixed single clock cycle. The complete operation task relies on pre-deployed paths, multi-layer parallel circuits, and timing-coupled execution mechanisms to complete all operations, data processing, and result output in a single step within a unified task timing closed loop, without the need to split steps and process in segments. The data transmission process and the computation process are coupled and synchronized in time, eliminating the waiting redundancy caused by step-by-step execution, and completing the entire process of data loading, multi-level parallel computation, and synchronous output of results within a single task time loop. A single complex instruction corresponds to a unique operational logic deployment scheme, which is compatible with any level of nested structure, and the hardware circuit logic layout is completed synchronously by instruction invocation. 4. Layered State Reset Mechanism The architecture is configured with a two-level reset mode: Full-domain reset: This function is only executed when the device is powered on and initialized, the entire system is reset, or all tasks have ended. It clears all registers, arithmetic circuits, and cache states, restoring the hardware to its initial stable state. Partial task reset: During normal continuous operation of the equipment, only the status of completed independent sub-task blocks is reset and cleaned up, while the intermediate calculation data and hierarchical calculation status of unfinished tasks are retained to ensure the data integrity of continuous calculation. 5. Pathway pre-deployment mechanism During the instruction parsing phase, the path pre-deployment module matches and locks the corresponding multi-layer logic operation circuits, data transmission paths, and hardware computing resources in one go, based on the current task instruction logic. For routine computation tasks, the main path is locked throughout, with no secondary dynamic scheduling. For complex computation tasks with multiple branches, the main path remains locked while the branch paths are reserved for dynamic allocation to adapt to variable instruction logic. 6. Multi-layered progressive hardware computing mechanism The multi-layered progressive logic circuit module sets up multiple independent hardware operation levels, with each circuit level matched with operation instructions of different nesting depths. The multi-layer circuit is deduced synchronously and in parallel, and the solution is obtained step by step according to the nested instruction logic. The hardware level and the operation logic level correspond one-to-one, and there is no need for software to disassemble the nested operation steps. Each circuit level sets up a data interaction protocol and read / write priority mechanism to standardize multi-level operation data calls, result overwriting, and hierarchical linkage logic. 7. Multi-core aggregation and synergy mechanism Each independent microcore has its own dedicated computing circuitry and timing resources, eliminating task slicing and frequent context switching. Multiple independent microcores can be dynamically aggregated into a logical aggregated large core, and the timing of aggregated large cores at the same level is isolated from each other; the phase alignment and timing coordination of upper and lower level aggregated units are uniformly controlled by a global reference clock. Attached Figure Description Figure 1 is an overall block diagram of the multi-layer progressive multi-core computing architecture with hierarchical dynamic timing coordinated by the reference clock of the present invention. The diagram clearly illustrates the core role of the global reference clock module in timing coordination, the hierarchical operation structure of the multi-layered progressive computing logic circuit, the multi-core aggregation relationship between independent microcores and aggregated large cores, and the linkage logic of the three major functional modules: path pre-deployment, hierarchical state reset, and cross-base operation adaptation. The arrows indicate the flow of timing control, instruction scheduling, data operation, and reset control, respectively, fully reflecting the core architecture mechanism of hierarchical dynamic timing, multi-layered parallel operation, and multi-core collaborative scheduling. Beneficial effects Compared with the prior art, the present invention has the following technical effects: It adopts a multi-layered progressive hardware logic circuit structure, which can directly match the nested compound operation level, reducing the number of software splitting operation steps and achieving a higher degree of compatibility in operation logic. It supports flexible switching between two operating modes: microkernel autonomous timing adjustment and overall phase locking, which can adapt to a variety of task scenarios and has stronger applicability to timing scheduling. Distinguishing between whole-machine reset and partial task reset modes can avoid the problem of residual states caused by long-term operation and ensure that valid calculation data is not lost. It adopts a single-time closed-loop single-step operation mode, which eliminates the unnecessary steps of step-by-step processing, effectively reduces the operation time, and simplifies the execution process. Hardware pathways are locked before the task runs, reducing dynamic resource allocation during operation and minimizing scheduling overhead. The multi-core division of labor is clear, the single-path operation is independently managed, the overall operation logic is uniformly arranged, and the task processing is well-organized.

Claims

1. A multi-layer logic circuit CPU architecture, characterized by, It includes a global reference clock module, a multi-layer progressive logic circuit module, several independent micro-core arithmetic units, an aggregated large core scheduling module, a path pre-deployment module, and a hierarchical state reset module; The global reference clock module is used to provide a unified time reference across the entire domain and to control the timing adjustment and phase matching of each computing unit. The multi-layer progressive logic circuit module is configured with multi-layer hardware logic circuits to match instruction nesting levels and realize layered parallel operation; The independent microcore computing unit is the smallest independent computing unit. Each microcore is configured with an independent computing path and is responsible for single-path computing control. Several independent microcores can be aggregated into a unified logical big core through the aggregated big core scheduling module to coordinate the overall computing logic arrangement. The path pre-deployment module is used to pre-lock the hardware computing path and resources corresponding to the task during the instruction parsing stage; The hierarchical state reset module is used to achieve hierarchical control of system-wide reset and task-specific reset.

2. The CPU architecture of claim 1, wherein, The global reference clock module implements hierarchical dynamic timing control; In multi-tasking scenarios, each independent microcore adaptively adjusts its own operation timing within the reference clock range and runs asynchronously and independently; In parallel collaboration scenarios, the global reference clock issues a phase locking command to uniformly lock the operating phase of all micro-cores within the aggregated big core; The timing mode switching process is uniformly controlled by the global reference clock, and data snapshots and path status locking are completed synchronously.

3. The CPU architecture of claim 1, wherein, The hierarchical state reset module includes two levels of reset logic; When the device is powered on, the system is completely reset, or all tasks are completed, a full-domain reset is performed to clear the entire hardware state. During normal operation of the equipment, a partial reset is performed on completed sub-tasks, while the intermediate calculation data and hierarchical status of unfinished tasks are retained.

4. The CPU architecture of claim 1, wherein, The path pre-deployment module locks the hardware computing circuit and data transmission path once during the instruction parsing stage; For routine tasks, the path is statically locked throughout, while for complex tasks with multiple branches, the path is dynamically allocated by reserving branches.

5. The CPU architecture of claim 1, wherein, The architecture adopts a single-time closed-loop operation method. The complete operation task is completed in one step within a unified task time closed loop, including data loading, multi-level operation and result output, without the need for step-by-step processing. Data transmission and computation processing are coupled and executed synchronously, with each instruction corresponding to a unique computational logic deployment structure.

6. The CPU architecture of claim 1, wherein, The multi-layered progressive logic circuit module has a one-to-one correspondence between the multi-layered circuit levels and the instruction nesting operation levels, and the multi-layered circuits solve the problem synchronously and in parallel. Configure data interaction protocols and read / write priority queues at each circuit level.

7. The CPU architecture of claim 1, wherein, Each independent microcore has its own dedicated computing circuitry and timing resources; Multiple microcores can be dynamically aggregated into a large aggregate core. The timing of large aggregate cores at the same level is isolated from each other, and the phase of upper and lower level aggregate units is uniformly controlled by a global reference clock.

8. A single-cycle closed-loop global computing method of a multi-layer logic circuit CPU, applied to the CPU architecture of any one of claims 1 to 7, characterized in that, Includes the following steps: After the S1 device is powered on, it performs a full-domain reset and initializes the global reference clock for the global time base. S2 receives external computing instructions, and the path pre-deployment module pre-matches and locks the hardware computing path according to the instruction logic; The S3 global reference clock matches the timing operation mode according to the current task type. Ordinary tasks use micro-core adaptive asynchronous timing, while parallel collaborative tasks use large core phase synchronization timing. S4 relies on multi-layered progressive logic circuit modules to complete layered parallel operations, with data transmission and operation processing being coupled and proceeding synchronously in sequence. S5 completes all computations and outputs results in a single step within the time loop of a single task, and performs local state reset on completed subtasks. S6 continuously receives and processes subsequent instructions, and performs a system reset after all tasks are completed.

Images