A heterogeneous reconfigurable chip mapping method and program product

Abstract

This application provides a heterogeneous reconfigurable chip mapping method and program product. The method includes: acquiring a power-aware resource graph model; the resource graph model includes nodes and edges abstracted from hardware resources in the reconfigurable chip, the nodes and edges being configured with weights to characterize power consumption; establishing mapping relationships between each operating node and multiple candidate hardware resources to obtain a candidate solution set; in the resource graph model, determining target hardware resources that meet type compatibility requirements for each operating node from the candidate solution set based on accumulated power consumption costs, and establishing communication paths via the nodes and edges between operating nodes with data dependencies. This method can systematically explore the global low-power solution space, reduce chip interconnect power consumption and computational power consumption, and improve the mapping success rate under complex heterogeneous architectures.

Description

Technical Field

[0001] This application relates to the field of CGRA resource allocation technology, and more specifically, to a heterogeneous reconfigurable chip mapping method and program product. Background Technology

[0002] With the continuous development of integrated circuit technology, the number of processing units integrated on a single chip continues to increase, and multi-core processing chips have become the mainstream architecture for high-performance computing. To further improve energy efficiency, a design trend of heterogeneous multi-core processing chips has emerged in recent years—that is, integrating multiple types of processing cores on a single chip, each core optimized for a specific type of computing task. These chips are called heterogeneous reconfigurable architecture chips, with coarse-grained reconfigurable arrays (CGRAs) being a typical example. Unlike traditional homogeneous multi-core processors, heterogeneous CGRA chips typically have the following structural characteristics and advantages: (1) Structural features: The heterogeneous CGRA chip integrates multiple heterogeneous processing units (PEs) on a single chip. These PEs are not simple copies of the CPU core, but contain hardware units designed for specific operations, such as Fast Fourier Transform (FFT) units, Coordinate Rotating Digital Computer (CORDIC) units, complex multipliers, Finite Impulse Response (FIR) filters, etc. These heterogeneous PEs are connected through efficient on-chip interconnect networks (such as Crossbar, multilayer switching networks, or on-chip networks NoC) to form a reconfigurable computing array. Each PE can be dynamically configured at the cycle level, and the interconnect network can also establish data paths as needed.

[0003] (2) Advantages Analysis: By employing dedicated hardware units oriented towards specific computing modes, the overhead of instruction fetching and decoding in traditional processors can be completely eliminated, achieving extremely high computing density while significantly reducing power consumption per unit operation. Research shows that heterogeneous CGRA can achieve several times the energy efficiency improvement compared to homogeneous multi-core processors. Compared to application-specific integrated circuits (ASICs), heterogeneous CGRA chips can still change their functions and interconnections after tape-out, adapting to changes in computing modes in different application scenarios, combining the energy efficiency of ASICs with the flexibility of FPGAs. Heterogeneous CGRA adopts a modular design, which can flexibly adapt to the computing needs of different application fields by increasing the size of the PE array or integrating more types of dedicated units.

[0004] (3) Challenges: Its application deployment still faces challenges: how to efficiently map applications to heterogeneous CGRA. This mapping process requires selecting a compatible PE type for each operation in the algorithm, determining its physical location in the array, and establishing a data routing path in the interconnect network, while satisfying resource constraints. Due to the heterogeneity of PE types and the complexity of interconnect topologies, the search space of the mapping problem grows exponentially, making it a recognized NP-hard problem. The mapping result directly affects the chip's performance and power consumption—low-quality mapping may lead to a longer critical path, reduced resource utilization, and a surge in interconnect power consumption, severely weakening the energy efficiency advantages of heterogeneous CGRA.

[0005] Therefore, designing efficient mapping algorithms that can generate high-quality mapping schemes for heterogeneous CGRA chips within an acceptable timeframe is a current challenge in the field of heterogeneous reconfigurable computing. Summary of the Invention

[0006] The purpose of this application is to provide a heterogeneous reconfigurable chip mapping method and program product, so as to achieve the technical effect of global low power consumption and high success rate heterogeneous reconfigurable chip mapping.

[0007] A first aspect of this application provides a heterogeneous reconfigurable chip mapping method, the method comprising: A power consumption-aware resource graph model is obtained; the resource graph model includes nodes and edges obtained based on hardware resource abstraction in a reconfigurable chip, and the nodes and edges are configured with weights to characterize power consumption; Establish a mapping relationship between each operation node and multiple candidate hardware resources to obtain a candidate solution set; In the resource graph model, target hardware resources that meet type compatibility requirements are determined for each operating node from the candidate solution set based on the accumulated power consumption cost, and communication paths are established between operating nodes with data dependencies via the nodes and the edges.

[0008] In the above implementation process, power quantization is incorporated into the search space by constructing a resource graph model with embedded power weights; multiple candidate hardware resources are maintained for each operating node, avoiding the local optimum trap of traditional greedy strategies; and the accumulated power cost guides the node allocation and path establishment process, completing global mapping under heterogeneous type compatibility and data dependency routing constraints. Thus, the global low-power solution space can be systematically explored, reducing chip interconnect power consumption and computational power consumption, while improving the mapping success rate under complex heterogeneous architectures.

[0009] Furthermore, before acquiring the power-aware resource graph model, the following is also included: The switching network units in the reconfigurable chip are modeled as first-type nodes, and the computing units in the reconfigurable chip are modeled as second-type nodes. The resource graph model is obtained by configuring a first weight to characterize the power consumption of the switching network unit for the first type of nodes, a second weight to characterize the power consumption of the computing unit for the second type of nodes, and a third weight to characterize the power consumption of data transmission for the edges between the nodes.

[0010] In the above implementation process, by explicitly modeling the switching network unit as a node, the limitation of the router function being implicitly contained in the edge in the traditional MRRG is overcome, and the accurate quantification of routing power consumption is achieved. By configuring power consumption weights for computing unit nodes, router nodes and interconnection edges respectively, the system power consumption of CGRA (including computing power consumption, routing power consumption and transmission power consumption) is completely encoded into the graph model, and a power consumption embedded search space is constructed, so that subsequent mapping search can be guided by quantified power consumption values, thus solving the defect that low-power mapping cannot be achieved due to the lack of accurate power consumption modeling.

[0011] Furthermore, establishing the mapping relationship between each operating node and multiple candidate hardware resources includes: The search starting point is determined from the data flow graph of the algorithm to be mapped, and the search starting point is mapped to the starting hardware resource in the resource graph model; Add the predecessor operation node of the search starting point to the search queue; Candidate hardware resources are selected from the search queue based on the cumulative power consumption cost and determined as resources to be verified; the cumulative power consumption cost is the sum of the weights of the nodes and edges traversed from the starting hardware resource to the selected candidate hardware resource.

[0012] In the above implementation process, by determining the search starting point from the data flow graph and mapping it to the resource graph model, an initial anchor point is established for the mapping search; by adding the predecessor operation node to the search queue, the search range is progressively expanded, avoiding the problem of falling into local optima due to early local decision-making errors.

[0013] Furthermore, the method also includes: If the resource to be verified is determined to be a computing unit node and the resource to be verified passes the function type verification, data dependency verification, and route legality verification, the resource to be verified is determined as a candidate hardware resource of the operation node and added to the mapping relationship.

[0014] In the above implementation process, function type verification ensures type compatibility under heterogeneous architecture, data dependency verification implements efficient pruning to eliminate invalid branches, and route validity verification uses the maximum flow algorithm to verify the coexistence feasibility of multiple communication requirements. Only after all the above verifications pass is the resource to be verified identified as a candidate hardware resource of the operation node and added to the mapping relationship. This achieves the reduction of invalid search branches through progressive pruning while ensuring heterogeneous type matching and no routing conflicts. At the same time, through the accumulation of one-to-many mapping relationships, a diverse candidate solution space is preserved for non-greedy progressive search.

[0015] Furthermore, the function type verification includes determining whether the computation type of the resource to be verified matches the computation type of the operation node; the data dependency verification includes determining whether all successor nodes of the operation node have at least one candidate hardware resource in the mapping relationship; the route validity verification includes the following steps: constructing a subgraph including the resource to be verified and the occupied hardware resources; extracting operation node pairs with data dependencies in the mapping algorithm; verifying whether there exists a conflict-free communication path in the subgraph that simultaneously satisfies the communication requirements of all operation node pairs.

[0016] In the above implementation process, under the constraints of heterogeneous type and interconnection resources, effective candidate resources are efficiently screened by progressive pruning from simple to complex. At the same time, the feasibility of global routing is ensured by graph theory verification, avoiding later routing congestion failures caused by early decisions, and providing a guarantee for obtaining a complete, conflict-free, and low-power mapping scheme.

[0017] Furthermore, the method also includes: If the resource to be verified passes the function type verification, data dependency verification, and route validity verification, then the predecessor operation node of the operation node is added to the search queue.

[0018] In the above implementation process, the progressive search is extended by adding the predecessor operation node of the operation node that has passed the three-layer verification to the search queue.

[0019] Furthermore, the method also includes: Hardware resources that are deemed unusable during the verification process will be stored in a spare set. When the number of occupied hardware resources reaches a preset threshold, the hardware resources in the spare set are added back to the search range. After all operation nodes of the algorithm to be mapped have been processed, the remaining hardware resources in the spare set are added back to the search range.

[0020] The above implementation process can correct early decision-making errors, avoid discarding potential hardware resources due to the limitations of local resource views, and enhance the robustness of the search process.

[0021] Furthermore, the method also includes: Once all operation nodes of the mapping algorithm have determined the target hardware resources, a mapping scheme is selected from the candidate solution set as the mapping result based on the total power consumption cost. The total power consumption cost is the sum of the node weights and edge weights corresponding to all determined target hardware resources and the communication paths between the target hardware resources.

[0022] In the above implementation process, the previously constructed power-aware resource graph model (node ​​weights and edge weights), the multi-candidate solution set established by non-greedy progressive search, and the feasible mapping scheme ensured by progressive verification are integrated. The scheme with the best global power consumption is selected as the final output in the complete mapping solution space. This realizes a closed loop from power embedded modeling to power-driven search and then to the best power consumption output, ensuring that the final generated chip configuration scheme has the lowest system power consumption while meeting the requirements of heterogeneous type compatibility and routing conflict-free operation.

[0023] Furthermore, the mapping result is the mapping scheme with the minimum total power consumption cost.

[0024] In the above implementation process, under the premise of ensuring heterogeneous type compatibility and routing conflict-free operation, a chip configuration scheme with the lowest system power consumption is output to fully unleash the hardware potential of heterogeneous reconfigurable chips in terms of energy efficiency.

[0025] A second aspect of this application provides a computer program product, the computer program product including a computer program, which, when executed by a processor, implements any of the methods described in the first aspect. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A flowchart illustrating a heterogeneous reconfigurable chip mapping method provided in an embodiment of this application; Figure 2 This application provides a schematic diagram of power consumption and linear regression fitting for an 8×8 Crossbar under different active connection numbers. Figure 3A schematic diagram of an extended MRRG with power integration provided in an embodiment of this application; Figure 4 This is a schematic diagram of route verification corresponding to two node mapping schemes provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0029] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] In related technologies, CGRA chip mapping methods can be mainly divided into the following categories: (1) Metaheuristic methods: such as simulated annealing (SA) and DRESC. This method searches for feasible solutions through random perturbation and iterative optimization. Although it can handle large-scale spaces, it has slow convergence, lacks power consumption optimization, and is prone to getting trapped in local optima.

[0031] (2) Mathematical optimization methods: such as integer linear programming (ILP), which can obtain the theoretical optimal solution, but the computational complexity increases exponentially with the problem size, and cannot solve slightly larger DFG problems in an acceptable time.

[0032] (3) Greedy and local search methods: Hycube uses Dijkstra's shortest path greedy mapping, which is fast but has a low success rate and is prone to high power consumption due to local optima. PathSeeker introduces a three-level local recovery mechanism to make local adjustments when it fails, but its vision is limited to the neighborhood of the failed node and it cannot correct early global decision errors.

[0033] (4) Backtracking method: For example, GraphMinor uses a backtracking strategy when the mapping fails, but the backtracking order is based on the node mapping order, which may backtrack to a node that is not the root cause of the problem, resulting in a large number of invalid backtrackings and a surge in compilation time.

[0034] In summary, the relevant technologies either lack power-oriented approaches during the search process (such as SA and PathSeeker), get stuck in local optima due to greed or locality (such as Hycube and PathSeeker), or have low backtracking efficiency (such as GraphMinor), making it difficult to stably obtain a globally low-power mapping scheme under complex heterogeneous constraints.

[0035] Specifically, the relevant mapping methods have the following main technical drawbacks when processing heterogeneous CGRA chips: 1. Lack of accurate power consumption modeling; the search process is not power consumption-oriented: Most related technologies prioritize routing feasibility or resource utilization for optimization, neglecting interconnect power consumption as a core metric. Since circuit-switched networks dominate chip system power consumption, a lack of power-oriented search makes it difficult to find truly low-power mapping solutions.

[0036] 2. Greedy strategies are prone to getting trapped in local optima and cannot guarantee low global power consumption. Greedy methods select the current optimal local path each time, and the decision is irreversible. Once a node is poorly chosen, it is difficult to make up for it later, and in the end, only a local optimal solution can be obtained, which often results in high power consumption.

[0037] 3. The backtracking mechanism is inefficient and cannot correct early global decision-making errors: Related backtracking methods (such as GraphMinor) backtrack in the order of node mapping, which may repeatedly try invalid branches, greatly increasing compilation time. Although PathSeeker's local recovery is more intelligent than blind backtracking, it has a narrow field of view and is powerless to deal with routing congestion caused by early decisions.

[0038] To address any of the aforementioned issues, this application proposes to quantify power consumption as a search cost by constructing a power-aware extended MRRG model; to adopt a non-greedy progressive search method, maintain a set of multiple candidate solutions, and guide the search direction with a power-driven priority queue to avoid getting trapped in local optima; and to introduce a parameterized active backtracking mechanism to re-evaluate shelved candidate resources in a controlled manner, thereby enhancing the robustness of the search.

[0039] This application quantifies interconnect power consumption as a search cost using a power-aware MRRG model. Combined with a non-greedy progressive search, it can systematically find a global low-power mapping scheme. Simultaneously, the non-greedy strategy retains multiple candidate solutions, and the proactive backtracking mechanism promptly corrects early decision errors, significantly improving the mapping success rate for complex heterogeneous architectures. Progressive three-layer verification quickly prunes invalid branches, parameterized backtracking control overhead, and fast compilation time outperform other heuristic algorithms. The backtracking period parameter is adjustable, allowing users to balance compilation speed and mapping quality according to their needs, adapting to different application scenarios.

[0040] Based on this, embodiments of this application provide a heterogeneous reconfigurable chip mapping method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating a heterogeneous reconfigurable chip mapping method provided in an embodiment of this application.

[0041] In this embodiment, the method includes: Step S10: Obtain a power-aware resource graph model; the resource graph model includes nodes and edges obtained based on hardware resource abstraction in the reconfigurable chip, and the nodes and edges are configured with weights to characterize power consumption; It's important to note that the power-aware resource graph model refers to the extended modular resource graph (MRRG) model. Unlike traditional MRRGs, this model explicitly models routers (crossbars) in reconfigurable chips as a type of node, forming a complete node set together with compute unit nodes. By abstracting interconnect paths as edges, a directed graph structure is formed to describe the chip's topology and resource constraints. To support power-driven mapping searches, this model assigns computational power weights to compute unit nodes, router operating power weights to router nodes, and data transmission power weights to interconnect edges. This allows the total system power consumption of any mapping scheme to be quantified as the sum of the weights of the occupied nodes and edges. Thus, this resource graph model constructs a search space that embeds power information within the graph model, laying the foundation for subsequent power-driven mapping searches.

[0042] Hardware resource abstraction of nodes and edges: The computing units (PE) and switching network units (Crossbar) in the reconfigurable chip are abstracted as nodes, and the interconnection paths are abstracted as edges, forming a directed graph structure to describe the topology and resource constraints of the chip.

[0043] Step S20: Establish the mapping relationship between each operation node and multiple candidate hardware resources to obtain the candidate solution set; It should be noted that each operation node refers to every computational operation node in the data flow graph (DFG) of the algorithm to be mapped.

[0044] Multiple candidate hardware resources: Each DFG node does not have a fixed and unique hardware location, but maintains multiple possible mapping options (one-to-many mapping dictionary) to avoid making decisions too early and getting trapped in local optima.

[0045] Candidate solution set: The set of all mapping relationships, that is, the set of feasible partial solutions or complete solutions accumulated during the search process.

[0046] Step S30: In the resource graph model, based on the accumulated power consumption cost, target hardware resources that meet the type compatibility requirements are determined for each operation node from the candidate solution set, and communication paths are established between operation nodes with data dependencies via the nodes and the edges.

[0047] It should be noted that the accumulated power cost is the sum of the weights of the nodes and edges traversed from the search starting point to the current candidate resource. This accumulated cost is managed by a priority queue in ascending order to ensure that the search process always prioritizes exploring paths with lower power consumption, thereby achieving power-oriented incremental expansion.

[0048] Type compatibility is a core constraint for heterogeneous reconfigurable chips. Because heterogeneous chips integrate various types of dedicated computing units (such as Fast Fourier Transform units, coordinate rotation digital computer units, complex multipliers, etc.), the operation nodes in the algorithm to be mapped must be mapped to hardware units that support their operation types. Function type verification is designed specifically for this purpose, ensuring that the operation nodes and hardware resources match in terms of computation type.

[0049] The target hardware resource refers to the hardware location ultimately determined for each operating node. In the candidate solution set, each operating node may correspond to multiple candidate hardware resources. Based on power consumption costs and verification results, a unique target hardware resource can be selected for each operating node from the candidate solution set to complete the node allocation.

[0050] In a data flow graph, data dependencies refer to pairs of nodes connected by directed edges. These dependencies define the direction of data flow: source nodes generate data, target nodes consume data, and data must be transmitted from the source node to the target node. These node pairs constitute the basic units for establishing communication paths during the mapping process.

[0051] Establishing a communication path via the nodes and edges refers to finding a conflict-free routing path for pairs of operational nodes with data dependencies in the resource graph model. This process involves occupying router nodes and interconnecting edges.

[0052] In this embodiment, a resource graph model with embedded power consumption weights is constructed to integrate power consumption quantization into the search space. By maintaining multiple candidate hardware resources for each operating node, the local optimum trap of traditional greedy strategies is avoided. The accumulated power consumption cost guides the node allocation and path establishment process, and global mapping is completed under the constraints of heterogeneous type compatibility and data dependency routing. As a result, the global low-power solution space can be systematically explored, reducing chip interconnect power consumption and computational power consumption, while improving the mapping success rate under complex heterogeneous architectures.

[0053] Based on any of the above embodiments, before obtaining the power-aware resource graph model, the method further includes: The switching network units in the reconfigurable chip are modeled as first-type nodes, and the computing units in the reconfigurable chip are modeled as second-type nodes. The resource graph model is obtained by configuring a first weight to characterize the power consumption of the switching network unit for the first type of nodes, a second weight to characterize the power consumption of the computing unit for the second type of nodes, and a third weight to characterize the power consumption of data transmission for the edges between the nodes.

[0054] It should be noted that the switching network unit refers to the interconnect structure in a reconfigurable chip, typically implemented as a crossbar, multilayer switching network, or on-chip network (NoC). In a circuit-switched network, the switching network unit is responsible for establishing physical connections between inputs and outputs, and its power consumption accounts for the majority of the system's power consumption.

[0055] The computing unit refers to the processing unit (PE) in a reconfigurable chip, which includes hardware units designed for specific operations, such as fast Fourier transform units, coordinate rotation digital computer units, complex multipliers, finite impulse response filters, etc.

[0056] Modeling as Type I and Type II nodes: In traditional modular resource graphs, the functionality of a router is implicitly embedded in the edge connections. This embodiment extends this by explicitly modeling the switching network unit as a type I node in the graph, which, together with the computing unit nodes, forms a complete node set. This explicit modeling approach allows the router's power consumption to be quantified and incorporated into the search cost.

[0057] The first weight (power consumption of the switching network unit) characterizes the power consumption of a router (such as a crossbar) during operation. This power consumption can be simplified to a linear expression: ;in, This indicates the base power consumption when the Crossbar is in operation. Represents the number of concurrently active connections. This represents the dynamic power consumption weight of a pair of connected links. The specific value is obtained through comprehensive netlist simulation and linear regression fitting.

[0058] The second weight (computing unit power consumption): characterizes the dynamic power consumption generated by various computing units when performing operations. Given a fixed operating frequency, this power consumption can be considered a fixed value and can be obtained through power estimation tools or measurement.

[0059] The third weight (data transmission power consumption) characterizes the power consumption generated during data transmission along the interconnect path. Its expression is: Where α is the switching activity factor, C is the product of line length and unit length capacitance, V is the voltage, f is the operating frequency, and W is the data bit width. In synchronous, near full-bandwidth data transmission scenarios, α can be considered a constant of 1.

[0060] Specifically, after completing the above modeling and weight configuration, a complete power-aware extended MRRG model is formed. This model constructs a search space that embeds power information within a graph structure, providing a quantitative basis for subsequent power-driven mapping searches.

[0061] In this embodiment, by explicitly modeling the switching network unit as a node, the limitation of router functions being implicitly contained in the edges in the traditional MRRG is overcome, and accurate quantification of routing power consumption is achieved. By configuring power consumption weights for computing unit nodes, router nodes, and interconnection edges respectively, the system power consumption of CGRA (including computing power consumption, routing power consumption, and transmission power consumption) is completely encoded into the graph model, constructing a power-embedded search space. This allows subsequent mapping searches to be guided by quantified power consumption values, solving the defect that low-power mapping cannot be achieved due to the lack of accurate power consumption modeling.

[0062] Based on any of the above embodiments, establishing the mapping relationship between each operating node and multiple candidate hardware resources includes: The search starting point is determined from the data flow graph of the algorithm to be mapped, and the search starting point is mapped to the starting hardware resource in the resource graph model; Add the predecessor operation node of the search starting point to the search queue; Candidate hardware resources are selected from the search queue based on the cumulative power consumption cost and determined as resources to be verified; the cumulative power consumption cost is the sum of the weights of the nodes and edges traversed from the starting hardware resource to the selected candidate hardware resource.

[0063] It should be noted that the data flow graph of the algorithm to be mapped refers to a graphical representation of the algorithm, generally defined as a directed acyclic graph (DFG), where nodes represent computational operations and edges represent data dependencies between operations. The data flow graph is the input to the mapping algorithm.

[0064] The search starting point refers to a node in the data flow graph that has no predecessor, usually an input node or the starting operation of an algorithm.

[0065] Starting hardware resource: The hardware location in the resource graph model corresponding to the starting point of the search. The starting hardware resource is the anchor point of the mapping process, from which the search is gradually expanded.

[0066] A predecessor node is a node in the data flow graph that has a data dependency relationship with the current node and is located upstream of it. Specifically, if there exists a directed edge from node u to node v, then u is the predecessor node of v.

[0067] The search queue is a data structure used to manage candidate hardware resources that are yet to be processed.

[0068] The cumulative power consumption cost refers to the sum of the weights of all nodes and edges traversed from the search starting point (i.e. the initial hardware resource) to the current candidate hardware resource.

[0069] For example, the algorithm enters the main loop, and in each iteration, selects a candidate hardware resource from the queue as the resource to be verified. Optionally, the queue is sorted in ascending order of cumulative power consumption cost, and the selection rule is: take the head of the queue, i.e., the candidate hardware resource with the smallest current cumulative power consumption cost. However, the selection based on cumulative power consumption cost described in this embodiment is not limited to selecting the minimum value. In some implementations, selection can also be made sequentially in ascending order of cumulative power consumption cost, or randomly within a certain threshold range. As long as the selection rule is related to the cumulative power consumption cost, a power-oriented search effect can be achieved.

[0070] In this embodiment, an initial anchor point is established for the mapping search by determining the search starting point from the data flow graph and mapping it to the resource graph model; by adding the predecessor operation node to the search queue, the search range is progressively expanded, avoiding the problem of getting trapped in local optima due to early local decision-making errors.

[0071] Based on any of the above embodiments, the method further includes: If the resource to be verified is determined to be a computing unit node and the resource to be verified passes the function type verification, data dependency verification, and route legality verification, the resource to be verified is determined as a candidate hardware resource of the operation node and added to the mapping relationship.

[0072] It should be noted that a compute unit node refers to a node representing a compute unit (PE) in the resource graph model, which is distinct from a router node. Router nodes have no type constraints and can be directly included in occupied resources, while compute unit nodes require a complete three-layer verification: function type verification, data dependency verification, and route validity verification.

[0073] Function type verification checks whether the resource to be verified supports the computation type (such as FFT, CORDIC, complex multiplication, etc.) of the currently mapped operation node. Data dependency verification confirms whether all successor nodes of the current operation node have at least one candidate hardware resource in the mapping dictionary. Data dependency verification can significantly reduce invalid searches. Route validity verification constructs an MRRG subgraph containing the current candidate nodes and occupied resources to verify the existence of a valid communication path.

[0074] It should be understood that recording the verified candidate resources into the mapping dictionary (i.e., the mapping relationship) achieves the accumulation of one-to-many mapping relationships.

[0075] In this embodiment, function type verification ensures type compatibility under heterogeneous architecture, data dependency verification implements efficient pruning to eliminate invalid branches, and route validity verification uses the maximum flow algorithm to verify the coexistence feasibility of multiple communication requirements. Only after all the above verifications pass is the resource to be verified determined as a candidate hardware resource of the operation node and added to the mapping relationship. This achieves the reduction of invalid search branches through progressive pruning while ensuring heterogeneous type matching and no routing conflicts. At the same time, through the accumulation of one-to-many mapping relationships, a diverse candidate solution space is preserved for non-greedy progressive search.

[0076] Based on any of the above embodiments, the function type verification includes determining whether the computation type of the resource to be verified matches the computation type of the operation node; the data dependency verification includes determining whether all successor nodes of the operation node have at least one candidate hardware resource in the mapping relationship; the route validity verification includes the following steps: constructing a subgraph including the resource to be verified and the occupied hardware resources; extracting operation node pairs with data dependencies in the mapping algorithm; verifying whether there exists a conflict-free communication path in the subgraph that simultaneously satisfies the communication requirements of all operation node pairs.

[0077] It should be noted that the computation type of the resource to be verified refers to the computational function supported by the hardware resource, such as a Fast Fourier Transform (FFT) unit, a Coordinate Rotating Digital Computer (CORDIC) unit, a complex multiplier, a Finite Impulse Response (FIR) filter, etc. The computation type of the operation node refers to the type of computation performed by the operation node in the data flow graph of the algorithm to be mapped, such as FFT operation, CORDIC operation, complex multiplication, etc. Matching the computation type of the resource to be verified with the computation type of the operation node means that the computation type of the operation node is consistent with the computation type of the hardware resource, i.e., the hardware resource can perform the operation. The reason for setting up function type verification is that different types of operations must be executed by dedicated hardware units that support that type.

[0078] A successor node is a node in the data flow graph that has a data dependency relationship with the current operation node and is located downstream of it. If there exists a directed edge from node v to node u, then u is the successor node of v.

[0079] The existence of at least one candidate hardware resource means that the successor node already has one or more feasible hardware mapping options in the mapping relationship. If a successor node does not yet have any candidate resources, the current path may not be able to complete the mapping in the end, and it should be pruned in advance. By checking the mapping feasibility of successor nodes, candidate resources that may cause subsequent mapping failures can be eliminated in advance, reducing invalid search branches.

[0080] Subgraph: A local subgraph extracted from the resource graph model, consisting of resources to be verified and occupied hardware resources.

[0081] Occupied hardware resources: In a defined mapping scheme, hardware resources (including compute unit nodes, router nodes, and occupied interconnect edges) that have been allocated to other operating nodes.

[0082] Operation node pairs with data dependencies: Operation node pairs directly connected by directed edges in a data flow graph indicate that data must be transferred from the source node to the target node.

[0083] Conflict-free communication path: The physical path (via router nodes and interconnection edges) allocated to each operating node pair does not conflict on shared resources, that is, different node pairs will not occupy the same interconnection edge or the same router port at the same time.

[0084] Understandably, the route validity check uses the maximum flow algorithm to verify whether multiple sets of data dependencies can simultaneously establish conflict-free communication paths in a subgraph containing both the resource to be checked and the already occupied resources.

[0085] In this embodiment, under the constraints of heterogeneous type and interconnection resources, a progressive pruning method from simple to complex is used to efficiently screen effective candidate resources. At the same time, graph theory verification is used to ensure the feasibility of global routing, avoiding later routing congestion failures caused by early decisions, and providing a guarantee for obtaining a complete, conflict-free, and low-power mapping scheme.

[0086] Based on any of the above embodiments, the method further includes: If the resource to be verified passes the function type verification, data dependency verification, and route validity verification, then the predecessor operation node of the operation node is added to the search queue.

[0087] Specifically, candidate hardware resources corresponding to the predecessor operation node (i.e., possible mapping positions of the predecessor node) are added to the search queue, thereby gradually expanding the search scope and covering more operation nodes in the data flow graph.

[0088] In the specific implementation, after the current operating node determines the candidate hardware resources, its predecessor node is included in the queue and waits for subsequent exploration. At the same time, the current node itself is not removed from the queue, preserving the possibility of further exploring other candidates. This achieves the gradual expansion of the search range while ensuring power consumption guidance. By retaining the multiple candidate states of the current node, the irreversible decision problem of the traditional greedy strategy, where the selection is fixed, is avoided.

[0089] In this embodiment, the progressive search is extended by adding the predecessor operation node of the operation node that has passed the three-layer verification to the search queue.

[0090] Based on any of the above embodiments, the method further includes: Hardware resources that are deemed unusable during the verification process will be stored in a spare set. When the number of occupied hardware resources reaches a preset threshold, the hardware resources in the spare set are added back to the search range. After all operation nodes of the algorithm to be mapped have been processed, the remaining hardware resources in the spare set are added back to the search range.

[0091] It should be noted that hardware resources deemed unusable during the verification process refer to candidate hardware resources that failed in function type verification, data dependency verification, or route validity verification. These resources are not permanently unusable, but rather inapplicable in the local resource view at the current search moment. As mapping progresses (the occupied resource set expands), these previously rejected nodes may become feasible due to matching the type of subsequent nodes or providing a lower-power path.

[0092] The number of occupied hardware resources represents the number of hardware resources successfully mapped and allocated to the operating node, i.e., the size of the occupied resource set. The preset threshold can be defined as the threshold for the number of times the occupied resource set can be expanded. The value of the preset threshold should consider search efficiency and mapping quality: a value that is too small will cause frequent backtracking, increasing compilation overhead; a value that is too large will result in sparse backtracking, potentially leading to a suboptimal power consumption scheme. This embodiment does not limit the specific value of the preset threshold.

[0093] Re-add to search scope: Add all nodes in the standby set back to the search queue (i.e., priority queue) so that they can participate in a new round of candidate evaluation.

[0094] All operation nodes of the mapping algorithm have been processed: the main loop ends, that is, all DFG nodes have completed the mapping process.

[0095] Remaining hardware resources in the standby set: Hardware resources in the standby set that have not been reactivated after periodic backtracking. These resources may have been excluded during the main loop due to resource constraints, but may become optimization options in the final state.

[0096] This embodiment ensures that potential high-quality solutions are not missed due to period settings by using final backtracking, and supplements and optimizes the obtained mapping schemes.

[0097] In this embodiment, early decision-making errors can be corrected, potential hardware resources can be discarded due to the limitations of the local resource view, and the robustness of the search process can be enhanced.

[0098] Based on any of the above embodiments, the method further includes: Once all operation nodes of the mapping algorithm have determined the target hardware resources, a mapping scheme is selected from the candidate solution set as the mapping result based on the total power consumption cost. The total power consumption cost is the sum of the node weights and edge weights corresponding to all determined target hardware resources and the communication paths between the target hardware resources.

[0099] It should be noted that all operation nodes of the algorithm to be mapped refer to all computational operation nodes in the data flow graph of the algorithm to be mapped.

[0100] The determination of target hardware resources by all operational nodes means that each operational node has selected the final target hardware resource from the candidate solution set. This signifies that the main part of the mapping process, namely node allocation and route establishment, has been completed, and all operational nodes have completed verification and recorded in the mapping relationship.

[0101] Total power consumption cost: The total power consumption of a complete mapping scheme, which can be quantified as the sum of all node weights and edge weights occupied by the mapping scheme.

[0102] Specifically, the selected scheme is determined as the final mapping output, which is used to configure the hardware resources of the heterogeneous reconfigurable chip (including PE function configuration and interconnect network routing configuration).

[0103] All identified target hardware resources: all hardware resource nodes occupied in the mapping scheme, including computing unit nodes and router nodes. The weight (first weight or second weight) corresponding to each node is included in the total power consumption.

[0104] The communication paths between the target hardware resources are data communication paths established between operational nodes that have data dependencies, and these paths are composed of interconnecting edges.

[0105] The sum of node weights and edge weights: The total system power consumption of the mapping scheme is obtained by adding the weights of all occupied nodes (computing unit nodes and router nodes) to the weights of all occupied edges (communication paths). This quantification method allows for objective power consumption comparisons between different mapping schemes.

[0106] In this embodiment, the previously constructed power-aware resource graph model (node ​​weights and edge weights), the multi-candidate solution set established by non-greedy progressive search, and the feasible mapping scheme ensured by progressive verification are integrated. The scheme with the optimal global power consumption is selected as the final output in the complete mapping solution space. This realizes a closed loop from power embedded modeling to power-driven search and then to the optimal power consumption output, ensuring that the final generated chip configuration scheme has the lowest system power consumption while meeting the requirements of heterogeneous type compatibility and routing conflict-free operation.

[0107] Based on any of the above embodiments, the mapping result is the mapping scheme with the minimum total power consumption cost.

[0108] It should be noted that the mapping scheme with the lowest total power consumption cost refers to the scheme with the lowest numerical total power consumption cost among all feasible complete mapping schemes. For the constructed power-aware extended MRRG model, the total power consumption cost of the mapping scheme is quantified as the sum of the weights of the occupied computing unit nodes, router nodes, and interconnection edges. Node weights represent computational and routing power consumption, while edge weights represent data transmission power consumption. A non-greedy progressive search mechanism maintains multiple candidate hardware resources for each operating node during the search process, forming a candidate solution set. A progressive three-layer verification (functional type verification, data dependency verification, and route validity verification) ensures that candidate schemes meet heterogeneous type compatibility and route conflict-free constraints. A parameterized proactive backtracking mechanism corrects early decision errors, further enriching the feasible solution space. Based on this, the mapping scheme with the lowest total power consumption cost is selected from the candidate solution set, i.e., the configuration with the lowest total system power consumption is selected from all feasible schemes that meet the hardware constraints.

[0109] The reason for selecting the mapping scheme with the lowest total power consumption cost is that the system power consumption of heterogeneous reconfigurable chips mainly consists of three parts: computational power consumption, routing power consumption, and data transmission power consumption. Among these, routing power consumption and data transmission power consumption (i.e., interconnect-related power consumption) dominate in circuit-switched networks. Most related mapping methods optimize routing feasibility or resource utilization, lacking accurate power consumption modeling and power-oriented search mechanisms. This often results in mapping schemes with high interconnect power consumption, severely weakening the energy efficiency advantages of heterogeneous CGRA. This application constructs a power-aware resource graph model, embedding power consumption information into the search space; it systematically explores the global low-power solution space through a non-greedy progressive search; and it ensures the feasibility and completeness of the mapping scheme through progressive verification and active backtracking. Based on this, selecting the mapping scheme with the lowest total power consumption cost can minimize the dynamic power consumption of the chip during operation, especially the dominant interconnect power consumption, thereby fully releasing the hardware potential of heterogeneous reconfigurable chips in terms of energy efficiency.

[0110] In this embodiment, under the premise of ensuring heterogeneous type compatibility and routing conflict-free operation, a chip configuration scheme with the lowest system power consumption is output to fully unleash the hardware potential of heterogeneous reconfigurable chips in terms of energy efficiency.

[0111] Furthermore, based on the same concept as the above-mentioned heterogeneous reconfigurable chip mapping method, this application embodiment also provides a non-greedy progressive mapping search and backtracking method for heterogeneous reconfigurable architecture processing chips, which is used to realize the search and backtracking of global low-power mapping.

[0112] In this embodiment, the non-greedy incremental mapping search and backtracking method for heterogeneous reconfigurable architecture processing chips explicitly models the router as an MRRG node and assigns precise power consumption weights to compute nodes, router nodes, and interconnect edges, enabling the search process to be quantified by power consumption and laying the foundation for low-power mapping. By maintaining a "one-to-many" mapping dictionary and a power-driven priority queue, the search path is expanded by addition rather than replacement, avoiding getting trapped in local optima and systematically exploring global low-power solutions. A backup set and backtracking period parameters are set to periodically re-evaluate temporarily shelved candidate resources, enhancing the robustness of the search in a controlled opportunistic manner and preventing early decisions from missing high-quality solutions.

[0113] Specifically, 1. For the extended power-aware MRRG model: Accurate power consumption modeling is a prerequisite for achieving low-power mapping. Traditional Modular Resource Graphs (MRRGs) abstract hardware as a directed graph G=(V,E), where nodes V represent functional units and edges E represent interconnections. This embodiment makes two key extensions to the traditional MRRG: First, at the hardware resource abstraction level, this embodiment explicitly models the router (Crossbar) as a type of node in MRRG. , and computing nodes Together they form a complete set of nodes. Traditional MRRGs typically embed the router's functionality within the edge connections.

[0114] Secondly, at the power consumption integration level, this embodiment encodes the system power consumption of CGRA into the MRRG model, and achieves quantitative expression of power consumption through node weights and edge weights. The system power consumption of CGRA can be divided into three main parts: basic circuit power consumption... Calculate power consumption and routing power consumption . This refers to the power consumption required for the CGRA circuit to maintain basic operation when there is no data transmission, including the power consumption generated by clock tree distribution, physical connections, and basic logic circuits. This part of the power consumption is relatively fixed and accounts for a small proportion, so it has a limited impact on the optimization selection of the mapping scheme. It is the dynamic power consumption generated when various computing units perform operations, which can be regarded as a fixed value when the operating frequency is determined.

[0115] Operating power consumption including Crossbar And the power consumption of data transmission on the bus. The static mapping method used in this embodiment configures the Crossbar in a 1-to-1 transmission mode, avoiding arbitration and broadcast overhead while maintaining near-full bandwidth utilization. Therefore, the power consumption model of the Crossbar can be simplified to a linear expression: ; in, This indicates the base power consumption when the Crossbar is in operation. Represents the number of concurrently active connections. This represents the dynamic power consumption weight of a pair of connected links. To verify this model, a star topology experiment was conducted using an 8×8 AXIS Crossbar as an example (e.g., Figure 2 (As shown). Based on a real comprehensive netlist file, simulations of different... The operating waveform was obtained, and the corresponding power consumption data was obtained using the PrimePower tool. Then, a linear regression method was used to fit the waveform. and Experimental results show that the model's coefficient of determination R0 2 = 0.9778, indicating that the linear model has high accuracy.

[0116] After completing the physical design, the line length is extracted. and capacitance per unit length The estimation is expressed as follows: ; in, Here, V is the switching activity factor, V is the voltage, and f is the operating frequency. This refers to the data bit width. In synchronous, near-full bandwidth data transmission scenarios... It can be considered as a constant 1.

[0117] Based on the above analysis, a complete power consumption model is established in MRRG: (1) Compute nodes The weights are defined as ; (2) Router node The weight is defined as ; (3) Side The weight is defined as .

[0118] like Figure 3 As shown, Figure 3 An extended MRRG instance is presented, which, compared to traditional representation methods, establishes a reliable quantization foundation for power-optimized mapping search while maintaining clear visualization of complex networks.

[0119] Based on this extended model, the total system power consumption of any mapping scheme m can be quantified as: ; 2. For non-greedy incremental search methods: Traditional greedy strategies, due to irreversible decision-making, are prone to getting trapped in local optima and struggle to obtain globally low-power solutions under complex constraints. This embodiment proposes a non-greedy, incremental search method. Its core idea is to follow a low-power path and dynamically maintain a diverse set of candidate solutions to avoid premature convergence of the search process, thereby systematically exploring better mapping schemes.

[0120] This method abandons the traditional paradigm of "choice equals fixation" and introduces a mapping dictionary. The algorithm dynamically maintains multiple candidate hardware locations for each DFG node. Through a one-to-many mapping mechanism, the algorithm continuously accumulates feasible solutions during the search process, rather than prematurely fixing the selection. Simultaneously, the search process is guided by quantified power consumption metrics, ensuring that the solution space is progressively expanded along a low-power path. Finally, the algorithm selects the globally power-optimal mapping scheme from the constructed complete candidate solution space.

[0121] The SAR imaging algorithm data flow graph to be mapped is defined as a directed acyclic graph. Where N represents the set of computation operation nodes and D represents the set of data dependency edges. The above incremental search algorithm illustrates the incremental search process. The algorithm maintains the following key data structures: : The queue of DFG nodes to be mapped.

[0122] : A dictionary recording all possible mappings from DFG nodes to MRRG nodes, with the following structure: This indicates that a DFG node has multiple possibilities for mapping to an MRRG node, reflecting the non-greedy nature of the algorithm.

[0123] , : Records the sets of MRRG nodes and edges that have been used in the search, and has the attributes of proximity anchor and low power consumption.

[0124] A cumulative power consumption cost starting from the search point. A minimum priority queue sorted by the sum of the weights of nodes and edges along the path. The queue is the core of the progressive search, ensuring that the algorithm always prioritizes exploring the path with the lowest current power consumption.

[0125] Some variables and functions are defined as follows: As the starting point for the search in DFG, This serves as the starting point for the search within MRRG; To obtain all predecessor nodes of a node in the graph; To obtain all forward edges of a node in the graph; To determine if the calculation type of v is compatible with n; To obtain all direct edges in G consisting of nodes in V; To determine whether there exists a conflict-free mapping scheme in G that includes all edges in E.

[0126] Specifically, the data flow graph of the algorithm to be mapped is defined as a directed acyclic graph, where nodes represent computational operations and edges represent data dependencies. The main flow of the algorithm is as follows: (a) Initialization phase: First, the search starting point is determined from the data flow graph of the algorithm to be mapped, and this search starting point is mapped to the starting hardware resource in the resource graph model. The search starting point is usually a node without a predecessor in the data flow graph, that is, an input node or the starting operation of the algorithm.

[0127] Then, construct the following key data structures: The mapping dictionary is used to record all possible mapping relationships between data flow graph nodes and resource graph model nodes. Its structure is "operation node → candidate hardware resource list", which reflects the non-greedy nature of the algorithm. The set of occupied resources records the graph model nodes and edges of the resources that have been occupied by the mapped schemes; The priority queue is used to manage candidate hardware resources to be searched. The queue is sorted in ascending order according to the cumulative power consumption cost from the search start point to the current candidate resource, ensuring that the path with lower power consumption is always explored first.

[0128] Subsequently, the direct predecessor operation node of the search starting point is added to the set of nodes to be mapped, and the candidate hardware resources corresponding to these predecessor nodes are filled into the priority queue according to their cumulative power consumption cost, thus completing the initialization.

[0129] (II) Main Cycle Phase: The algorithm enters the main loop. In each iteration, the candidate hardware resource with the lowest current cumulative power consumption cost is taken from the priority queue as the resource to be verified, and different processing is performed according to its node type: Scenario 1: The resource to be verified is a router node: Since router nodes have no computation type constraints, the algorithm directly includes them in the set of occupied nodes and adds all their forward edges to the set of occupied edges.

[0130] Scenario 2: The resource to be verified is a computing unit node: If the resource to be verified is a computing unit node, then a three-level progressive verification is performed sequentially. This process follows a simple-to-complex order, constituting an efficient pruning process. ① Function Type Verification: Determines whether the computation type of the resource to be verified matches the computation type of the current operation node to be mapped. This is a necessary adaptation check for heterogeneous architectures, ensuring that the operation node is mapped to a hardware unit that supports its computation type.

[0131] ② Data dependency verification: Determine whether all successor nodes of the current operating node have at least one candidate hardware resource in the mapping dictionary. This mechanism, as a forward-looking pruning strategy, can significantly reduce invalid search branches.

[0132] ③ Route validity verification: Construct a subgraph containing the currently verified resources and the occupied hardware resources. Extract the pairs of operation nodes with data dependencies in the algorithm to be mapped. Use the maximum flow algorithm to verify whether there exists a conflict-free communication path in the subgraph that simultaneously satisfies the communication requirements of all operation node pairs. This step verifies whether the path set formed by multiple source node and target node pairs can be established simultaneously on shared resources without conflict.

[0133] like Figure 4 As shown, Figure 4 Using two mapping schemes as examples, the scenarios of route collisions and no collisions are illustrated. In the MAP1 scheme, The corresponding MRRG path is It can be accessed through Implementation. However, when considering all nodes that need to be mapped, another edge MRRG path... It also needs to occupy Path. Due to With only one edge, the MAP1 scheme cannot achieve conflict-free global routing. In contrast, the MAP2 scheme... Mapped to another MRRG path This can avoid contact with The route contention is resolved. Therefore, the MAP2 scheme passes route verification.

[0134] If all three layers of verification pass, the mapping relationship is stored in the mapping dictionary, and the set of occupied nodes and the set of occupied edges are updated. Then, the predecessor node of the current operating node is added as a new node to be searched, and its cumulative power consumption cost is added to the priority queue. The current node will not be removed from the priority queue, which reflects the non-greedy nature of the algorithm—the same operating node can maintain multiple candidate mapping options, rather than fixing a single choice.

[0135] (III) Proactive backtracking mechanism: During the search process, hardware resources deemed unusable are stored in a spare set instead of being permanently discarded. The algorithm sets a backtracking period parameter, defined as a threshold for the number of times the occupied node set is expanded. Whenever the cumulative number of new nodes added to the occupied node set reaches this threshold, a backtracking operation is triggered, adding all nodes in the spare set back to the search scope so that they can participate in a new round of candidate evaluation.

[0136] (iv) Output stage: After all operation nodes of the mapping algorithm have completed the mapping process, the algorithm selects the complete mapping scheme with the minimum total power consumption cost from the candidate solution set constructed by the mapping dictionary as the final output. The total power consumption cost is the sum of the node weights and edge weights corresponding to all determined target hardware resources and the communication paths between the target hardware resources.

[0137] In addition, after the main loop ends, the algorithm forces a final backtracking to use the remaining hardware resources in the spare set to supplement and verify the obtained mapping scheme, ensuring that potential high-quality solutions are not missed due to the period setting.

[0138] 3. For parameterized active backtracking methods: In progressive search, items are removed due to type or route validation failures. The MRRG node only indicates that it is not applicable in the local resource view at the current search moment. As mapping progresses ( (Expansion), with the addition of new DFG nodes, these previously removed nodes may become feasible due to matching the type of subsequent nodes or providing a lower-power path. If they are permanently discarded, the search process may miss the global optimum due to limitations in early decisions.

[0139] This embodiment introduces a parameterized active backtracking method. It treats temporarily failed MRRG nodes as "to be activated" resources, rather than "permanently discarded" resources, and reinstates them through a controlled periodic mechanism. Specifically, the algorithm maintains a backup set. Used to store all from The MRRG nodes are removed from the list. Simultaneously, a backtracking period parameter is defined. Defined as The threshold for the number of expansion attempts. Each time... The cumulative number of newly added nodes has reached At that time, a backtracking operation is triggered, and All nodes rejoined This will enable it to participate in a new round of candidate evaluation.

[0140] The value of has a significant impact on search efficiency and mapping quality: if the value is too small (e.g., 1), it will trigger frequent backtracking, causing a large number of nodes to be repeatedly verified, significantly increasing compilation overhead. Conversely, if the value is too large, the backtracking will be too sparse, causing valuable candidates to remain in the queue for a long time. The consequence is that in the mid-term, due to the limited number of available candidates, the algorithm is forced to explore distant resources with higher communication costs, resulting in a suboptimal power consumption scheme, or even mapping failure in extreme cases. Therefore, this embodiment uses a moderate value that has been experimentally optimized. The value is adjusted to balance the frequency of backtracking with the scope of the search.

[0141] Furthermore, to ensure that no potential high-quality solutions are missed due to the periodic setting, a final backtracking is forcibly performed after the main loop ends (i.e., after all DFG nodes have been mapped), utilizing... The remaining nodes perform supplementary checks on the obtained mapping scheme.

[0142] This design allows for a controlled, opportunistic re-evaluation and utilization of hardware resources temporarily shelved in earlier searches. This enhances the robustness of obtaining a global low-power mapping scheme, while also improving the parameter... The adjustments ensured that compilation efficiency remained within an acceptable range.

[0143] In this embodiment, a power-aware extended MRRG model is constructed to quantify power consumption as a search cost; a non-greedy progressive search method is adopted to maintain a set of multiple candidate solutions, and a power-driven priority queue guides the search direction to avoid getting trapped in local optima; a parameterized active backtracking mechanism is introduced to re-evaluate shelved candidate resources in a controlled manner, thereby enhancing the robustness of the search.

[0144] Based on the methods described in any of the above embodiments, this application also provides a computer program product, which includes one or more computer programs or instructions. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. When executed by a processor, the computer program implements the methods described in any of the above embodiments.

[0145] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0146] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0147] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0148] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0149] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0150] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for mapping heterogeneous reconfigurable chips, characterized in that, The method includes: A power consumption-aware resource graph model is obtained; the resource graph model includes nodes and edges obtained based on hardware resource abstraction in a reconfigurable chip, and the nodes and edges are configured with weights to characterize power consumption; Establish a mapping relationship between each operation node and multiple candidate hardware resources to obtain a candidate solution set; In the resource graph model, target hardware resources that meet type compatibility requirements are determined for each operating node from the candidate solution set based on the accumulated power consumption cost, and communication paths are established between operating nodes with data dependencies via the nodes and the edges.

2. The method according to claim 1, characterized in that, Before acquiring the power-aware resource graph model, the following is also included: The switching network units in the reconfigurable chip are modeled as first-type nodes, and the computing units in the reconfigurable chip are modeled as second-type nodes. The resource graph model is obtained by configuring a first weight to characterize the power consumption of the switching network unit for the first type of nodes, a second weight to characterize the power consumption of the computing unit for the second type of nodes, and a third weight to characterize the power consumption of data transmission for the edges between the nodes.

3. The method according to claim 1, characterized in that, The process of establishing the mapping relationship between each operating node and multiple candidate hardware resources includes: The search starting point is determined from the data flow graph of the algorithm to be mapped, and the search starting point is mapped to the starting hardware resource in the resource graph model; Add the predecessor operation node of the search starting point to the search queue; Candidate hardware resources are selected from the search queue based on the cumulative power consumption cost and determined as the resources to be verified; the cumulative power consumption cost is the sum of the weights of the nodes and edges traversed from the starting hardware resource to the selected candidate hardware resource.

4. The method according to claim 3, characterized in that, The method further includes: If the resource to be verified is determined to be a computing unit node and the resource to be verified passes the function type verification, data dependency verification, and route legality verification, the resource to be verified is determined as a candidate hardware resource of the operation node and added to the mapping relationship.

5. The method according to claim 4, characterized in that, The function type verification includes determining whether the computation type of the resource to be verified matches the computation type of the operation node; the data dependency verification includes determining whether all successor nodes of the operation node have at least one candidate hardware resource in the mapping relationship; the route validity verification includes the following steps: constructing a subgraph including the resource to be verified and the occupied hardware resources; extracting operation node pairs with data dependencies in the mapping algorithm; verifying whether there exists a conflict-free communication path in the subgraph that simultaneously satisfies the communication requirements of all operation node pairs.

6. The method according to claim 4, characterized in that, The method further includes: If the resource to be verified passes the function type verification, data dependency verification, and route validity verification, then the predecessor operation node of the operation node is added to the search queue.

7. The method according to claim 1, characterized in that, The method further includes: Hardware resources that are deemed unusable during the verification process will be stored in a spare set. When the number of occupied hardware resources reaches a preset threshold, the hardware resources in the spare set are added back to the search range. After all operation nodes of the algorithm to be mapped have been processed, the remaining hardware resources in the spare set are added back to the search range.

8. The method according to claim 1, characterized in that, The method further includes: Once all operation nodes of the mapping algorithm have determined the target hardware resources, a mapping scheme is selected from the candidate solution set as the mapping result based on the total power consumption cost. The total power consumption cost is the sum of the node weights and edge weights corresponding to all determined target hardware resources and the communication paths between the target hardware resources.

9. The method according to claim 8, characterized in that, The mapping result is the mapping scheme with the minimum total power consumption cost.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-9.

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